Vehicle electronic control unit

Abstract

To provide an electronic control device for a vehicle, which ensures that the reset of a monitoring microcomputer is reliably released before a control microcomputer is activated and after its operation is stopped.SOLUTION: In an electronic control device 1 for a vehicle, a monitoring microcomputer 3 monitors the operation of a control microcomputer 2. First and second level setting circuits 17 and 18 set levels of reset terminals of the control microcomputer 2 and the monitoring microcomputer 3, respectively, by ON / OFF of first and second switches 7 and 10. At the time when a reset signal output from a power supply IC 4 changes to a high level, since the first switch 7 is ON, the control microcomputer 2 is maintained in a reset state and the reset state of the monitoring microcomputer 3 is cancelled. At the time when the reset signal changes to a low level, since the second switch 10 is ON, the control microcomputer 2 is in the reset state and the monitoring microcomputer 3 is maintained in a reset-cancelled state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic control device for a vehicle in which the operation of a control microcomputer is monitored by a monitoring microcomputer. [Background technology]

[0002] Conventionally, a watchdog timer (WDT) has been used when a monitoring microcomputer monitors the operation of a control microcomputer. That is, if the control microcomputer is operating normally, the WDT in the monitoring microcomputer is reset at predetermined intervals by a watchdog signal continuously input from the control microcomputer. If the input of the watchdog signal stops, the WDT overflows, and an abnormality in the control microcomputer is detected. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-166549 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above configuration, differences in hardware and software can cause discrepancies in the timing at which each microcomputer starts up and stops operating. This can lead to cases where the control microcomputer starts up before the monitoring microcomputer, or the control microcomputer stops operating after the monitoring microcomputer stops operating. This can result in periods when the monitoring microcomputer cannot monitor the control microcomputer, which can cause the electronic control device to malfunction.

[0005] The present invention has been made in consideration of the above circumstances, and its purpose is to provide an electronic control device for a vehicle that ensures that the reset of the monitoring microcomputer is reliably released before the control microcomputer is started and after its operation stops. [Means for solving the problem]

[0006] According to the vehicle electronic control device of claim 1, the monitoring microcomputer monitors the operation of the control microcomputer. The first and second level setting circuits set the levels of the reset terminals of the control microcomputer and the monitoring microcomputer by turning on and off the first and second switches, respectively. The first and second level setting circuits are configured so that when the reset signal output from the reset circuit changes to an inactive level, the first switch is turned on, thereby maintaining the control microcomputer in a reset state and releasing the monitoring microcomputer from the reset state. Furthermore, when the reset signal changes to an active level, the second switch is turned on, thereby resetting the control microcomputer and maintaining the monitoring microcomputer in a released reset state.

[0007] With this configuration, when the reset signal changes from an active level, which resets both the control and monitoring microcomputers, to an inactive level, the monitoring microcomputer is released from its reset state first. Also, when the reset signal changes from an active level, which resets both the control and monitoring microcomputers and both are operating, the control microcomputer is released from its reset state first. Therefore, since the monitoring microcomputer is reliably operating while the control microcomputer is operating, the monitoring microcomputer can thoroughly monitor the operation of the control microcomputer.

[0008] According to the vehicle electronic control device of claim 2, the first level setting circuit is composed of a series circuit of a first switch and a resistor element connected between the reset terminal of the control microcomputer and a first potential point that applies a potential of the reset valid level, and the second level setting circuit is composed of a series circuit of a second switch and a resistor element connected between the reset terminal of the monitoring microcomputer and a second potential point that applies a potential of the reset invalid level.

[0009] The first control terminal of the monitoring microcomputer is connected via a resistive element to a potential point that turns the first switch ON, and the second control terminal of the control microcomputer is connected via a resistive element to a potential point that turns the second switch OFF. When the reset state is released, the monitoring microcomputer releases the reset state of the control microcomputer by turning the first switch OFF, and when the reset state is released, the control microcomputer turns the second switch ON.

[0010] With this configuration, immediately after the operating power supply is turned on, when both the control and monitoring microcomputers are in a reset state, the first switch is ON and the second switch is OFF. This causes the reset terminal of the control microcomputer to be phase-locked at an active level. Then, as the reset signal changes to an inactive level, the reset state of the monitoring microcomputer is released, but because the first switch is ON, the reset terminal of the control microcomputer remains at the active reset level, and the reset state is maintained.

[0011] After that, when the monitoring microcontroller is released from the reset state, it turns the first switch OFF to release the reset state of the control microcontroller, making it possible to release the reset state of the monitoring microcontroller first. Then, when the reset state is released, the control microcontroller turns the second switch ON, so the reset terminal of the monitoring microcontroller is phase-locked to the disabled level. Therefore, the control microcontroller goes into the reset state as the reset signal changes from the disabled level to the enabled level, but the monitoring microcontroller remains in the reset-released state. When the control microcontroller is reset, the output of the signal that turns the second switch ON is stopped, so the second switch turns OFF and the monitoring microcontroller is reset. This makes it possible to put the control microcontroller into the reset state first. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a functional block diagram illustrating a configuration of an electronic control device according to a first embodiment. [Figure 2] Timing chart showing startup operation [Figure 3] A diagram showing the signal flow corresponding to Figure 2. [Figure 4] Timing chart showing the operation at the end [Figure 5] A diagram showing the signal flow corresponding to Figure 4. [Figure 6] FIG. 10 is a timing chart illustrating the operation of the second embodiment when a power supply abnormality occurs. [Figure 7] Timing chart for explaining determination of power supply abnormality in the power supply monitoring unit [Figure 8] 10 is a timing chart showing the operation of the third embodiment when the WDC signal output of the control microcomputer is abnormal and the output of the control signal of the second switch continues. [Figure 9] Timing chart explaining how the monitoring microcontroller determines whether the WDC signal output of the control microcontroller is abnormal [Figure 10] A diagram showing the signal flow corresponding to Figure 8. [Figure 11] 10 is a timing chart showing the operation of the fourth embodiment when the WDC signal output of the control microcomputer is abnormal and the output of the control signal of the second switch is stopped. [Figure 12] A diagram showing the signal flow corresponding to Figure 11. [Figure 13] 10 is a timing chart showing the operation of the fifth embodiment when the WDC signal output of the monitoring microcomputer is abnormal and the output of the control signal of the first switch continues. [Figure 14] Timing chart explaining how the power supply IC determines whether the WDC signal output of the monitoring microcontroller is abnormal [Figure 15] 10 is a timing chart showing the operation of the sixth embodiment when the WDC signal output of the monitoring microcomputer is abnormal and the output of the control signal of the first switch is stopped. [Figure 16] A diagram showing the signal flow corresponding to Figure 15. [Figure 17] FIG. 13 is a functional block diagram illustrating the configuration of an electronic control device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] (First embodiment) As shown in FIG. 1, the electronic control device 1 is mounted on a vehicle and includes a control microcomputer (microcomputer 2), a monitoring microcomputer 3, and a power supply IC 4. The power supply IC 4 receives BATT power from a vehicle battery (not shown) and generates control power supplies VC, VREF, VCAN, etc. to be supplied to the control microcomputer 2 and the monitoring microcomputer 3. The power supply VREF is a power supply for an A / D converter (not shown), and the power supply VCAN is a power supply for CAN (registered trademark) communication, which is a type of in-vehicle LAN. An IG signal, which is an ON / OFF signal for the vehicle's ignition switch, is input to the control microcomputer 2, the monitoring microcomputer 3, and the power supply IC 4. In addition, although not shown, the electronic control device 1 also includes an A / D converter and an interface for CAN communication.

[0014] The power supply IC 4 incorporates a voltage monitoring unit 20. The voltage monitoring unit 20 monitors the voltages of the power supplies VC, VREF, and VCAN, and outputs a reset signal to the control microcomputer 2 and the monitoring microcomputer 3 when any of these voltages falls below a threshold. The power supply IC 4 also functions as a reset circuit. The reset signal is output to the control microcomputer 2 and the monitoring microcomputer 3 via diodes 5 and 6, whose anodes are connected in common. The diodes 5 and 6 correspond to a reset signal branching circuit.

[0015] A series circuit of a first switch 7 and a resistor element 8 is connected between the cathode of the diode 5 and ground, and the ON / OFF of the first switch 7 is controlled by the monitoring microcomputer 3. A first control terminal, from which the monitoring microcomputer 3 outputs a signal to control the first switch 7, is pulled up to a power supply VC via a resistor element 9. In addition, with regard to the reset signal, the ground level corresponds to the effective level of the reset signal, and the ground corresponds to the first potential point.

[0016] A series circuit of a second switch 10 and a resistor element 11 is connected between the cathode of the diode 6 and the power supply VC, and the ON / OFF of the second switch 10 is controlled by the control microcomputer 2. A second control terminal, from which the control microcomputer 2 outputs a signal to control the second switch 10, is pulled down to ground via a resistor element 12. The first switches 7 and 10 are turned ON when the control signal is at a high level and turned OFF when it is at a low level. Therefore, if the monitoring microcomputer 3 and the control microcomputer are not outputting control signals while the power supply VC is supplied, the first switch 7 is ON and the second switch 10 is OFF. With regard to the reset signal, the voltage of the power supply VC corresponds to the invalid level of the reset signal, and the power supply VC corresponds to the second potential point.

[0017] The monitoring microcomputer 3 has a built-in watchdog timer (not shown), and the control microcomputer 2 periodically outputs a signal to reset the watchdog timer as a WDC (Watch Dog Clock) signal, allowing the monitoring microcomputer 3 to monitor the operation of the control microcomputer 2. The terminal that outputs the WDC signal is pulled up to the power supply VC via a resistor element 13.

[0018] Similarly, the power supply IC 4 also has a built-in watchdog timer, and the monitoring microcontroller 3 periodically outputs a signal to reset the watchdog timer as a WDC signal, allowing the power supply IC 4 to monitor the operation of the monitoring microcontroller 3. The terminal that outputs the WDC signal is pulled up to the power supply VC via a resistor element 14.

[0019] When the control microcomputer 2 and the monitoring microcomputer 3 are released from reset and start up, they output HOLD signals to the power supply IC 4 to maintain the voltage of the power supply VC at an operable level until the IG signal turns OFF. These HOLD signals are input to the power supply IC 4 via diodes 15 and 16, whose cathodes are connected in common. The series circuit of the first switch 7 and resistor 8 constitutes a first level setting circuit 17, and the series circuit of the second switch 10 and resistor 11 constitutes a second level setting circuit 18. The diodes 5, 6, 15, and 16 and the level setting circuits 17 and 18 may be configured to be included in the power supply IC 4.

[0020] Next, the operation of this embodiment will be described. Note that in the following, circled numbers in the figures will be written as numbers in parentheses. Also, in Figure 2, the first and second switches 7 and 10 are designated SW1 and SW2, respectively.

[0021] <Microcontroller startup sequence> 2 and 3, when the IG signal goes high, the power supply IC 4 starts supplying the power supplies VC, VREF, and VCAN. At this point, the first switch 7 is turned ON, so the reset terminal of the control microcomputer 2 is pulled down.

[0022] The power supply IC 4 then sets the reset signal to high level, which is the release level (1). In response, the reset terminal of the monitoring microcontroller 3 goes high level (2), which releases the reset of the monitoring microcontroller 3 and causes the monitoring microcontroller 3 to start up first. The monitoring microcontroller 3 then turns off the first switch 7 (3). This releases the reset of the control microcontroller 2 and causes the control microcontroller 2 to start up (4). The monitoring microcontroller 3 also sets the HOLD signal to high level, which is the active level, and starts outputting the WDC signal. When the control microcomputer 2 is started up, it turns on the second switch 10 (5), sets the HOLD signal to high level, and starts outputting the WDC signal.

[0023] <Sequence when microcomputer operation ends> As shown in Figures 4 and 5, when the IG signal goes low, the control microcomputer 2 and the monitoring microcomputer 3 set the HOLD signal to low. In response, the power supply IC 4 sets the reset signal to low (1). Because the second switch 10 is ON, the reset terminal of the monitoring microcomputer 3 is pulled up, and only the control microcomputer 2 is reset (2). This stops the output of the WDC signal from the control microcomputer 2, and the output of the control signal from the second switch 10 stops, turning the second switch 10 OFF (3). This releases the pull-up state of the reset terminal of the monitoring microcomputer 3, resetting the monitoring microcomputer 3 (4). This stops the output of the WDC signal, and stops the output of the control signal from the first switch 7, turning the first switch 7 ON (5). After that, when the power supply IC 4 stops supplying the power supplies VC, VREF, and VCAN, the first switch 7 turns OFF.

[0024] As described above, according to this embodiment, in the vehicle electronic control device 1, the monitoring microcomputer 3 monitors the operation of the control microcomputer 2. The first and second level setting circuits 17 and 18 set the levels of the reset terminals of the control microcomputer 2 and the monitoring microcomputer 3 by turning on and off the first and second switches 7 and 10, respectively. When the reset signal output from the power supply IC 4 changes to a high level, the first switch 7 is turned on, thereby maintaining the control microcomputer 2 in a reset state and releasing the monitoring microcomputer 3 from the reset state. When the reset signal changes to a low level, the second switch 10 is turned on, thereby placing the control microcomputer 2 in a reset state and maintaining the monitoring microcomputer 3 in a released reset state.

[0025] With this configuration, when the reset signal changes from a state in which both microcomputers 2 and 3 are reset due to the reset signal being at low level to a high level, the monitoring microcomputer 3 is released from the reset state first. Also, when the reset signal changes to a low level from a state in which both microcomputers 2 and 3 are released from reset and both are operating, the control microcomputer 2 is reset first. Therefore, while the control microcomputer 2 is operating, the monitoring microcomputer 3 is reliably operating, and the monitoring microcomputer 3 can monitor the operation of the control microcomputer 2 without omission.

[0026] Specifically, the first level setting circuit 17 is configured as a series circuit of a first switch 7 and a resistor element 8 connected between the reset terminal of the control microcomputer 2 and ground, and the second level setting circuit 18 is configured as a series circuit of a second switch 10 and a resistor element 11 connected between the reset terminal of the monitoring microcomputer 3 and a power supply VC. The first control terminal of the monitoring microcomputer 3 is connected to the power supply VC via the resistor element 9, and the second control terminal of the control microcomputer 2 is connected to ground via the resistor element 12. When the reset state is released, the monitoring microcomputer 3 turns off the first switch 7 to release the reset state of the control microcomputer 2, and when the reset state is released, the control microcomputer 2 turns on the second switch 10.

[0027] This makes it possible for the monitoring microcomputer 3 to be released from the reset state before the control microcomputer 2 when the power-on reset is released. Also, when the reset signal changes to low level, it makes it possible for the control microcomputer 2 to be put into the reset state before the monitoring microcomputer 3.

[0028] (Second embodiment) Hereinafter, the same parts as those in the first embodiment will be denoted by the same reference numerals and explanations thereof will be omitted, and only the different parts will be explained. <Sequence when power supply fails> As shown in Figure 6, when the control microcomputer 2 and monitoring microcomputer 3 are operating normally, the voltage of the power supply VC is normal. However, if the voltages of the power supplies VREF and VCAN drop, the power supply monitoring unit 20 detects this and sets the reset signal to low level (1). Accordingly, the control microcomputer enters a reset state (2). As a result, the output of the signal that turns the second switch 10 ON from the second control terminal is stopped, so the second switch 10 turns OFF (3). This resets the monitoring microcomputer 3 (4). As a result, the output of the signal that turns the first switch 7 OFF from the first control terminal is stopped, so the first switch 7 turns ON (5). The signal flow shown in the block diagram is the same as that in Figure 5 of the first embodiment.

[0029] 7, the power supply monitoring unit 20 determines that the power supply voltage generated by the power supply IC 4 is "normal" if it is equal to or greater than the threshold Voff_th_L and equal to or less than the threshold Voff_th_H. When the power is turned on, the power supply IC 4 changes the reset signal from low to high after a specified recovery time has elapsed since the power supply voltage reached the threshold Von_th_L.

[0030] The abnormality determination threshold Voff_th_L is set lower than the threshold Von_th_L, and the abnormality determination threshold Voff_th_H is set higher than the threshold Von_th_H. When the power supply voltage falls below the abnormality determination threshold Voff_th_L or exceeds the abnormality determination threshold Voff_th_H, it is determined to be "abnormal" and the reset signal is changed from high level to low level. In this way, hysteresis is provided between the normal and abnormal thresholds.

[0031] Note that the timing of the reset signal shown in Fig. 6 includes a delay time within the power supply IC 4 from the time an abnormality occurs, but in Fig. 7, the delay time is not included in the timing in order to explain the principle. Also, in Fig. 6, the reset signal goes low after the abnormality occurs, and as shown in Fig. 7, the power supply voltage returns to a normal state and changes to high after the recovery time has elapsed, but this change is not shown. In other words, Fig. 7 shows the recovery time as shortened. The same applies to the following embodiments.

[0032] As described above, according to the second embodiment, even if an abnormality occurs in the power supplies VREF and VCAN while the control microcontroller 2 and monitoring microcontroller 3 are operating normally, the control microcontroller 2 can be reset before the monitoring microcontroller 3.

[0033] (Third embodiment) <Sequence when control microcomputer 2's WDC signal is abnormal: SW2 control signal output continues> 8 and 9, when the WDC signal input from the control microcomputer 2 stops and the watchdog timer inside the monitoring microcomputer 3 continues counting up and reaches the abnormality determination threshold, the monitoring microcomputer 3 detects an abnormality. The abnormality detection time is the time from when the watchdog timer is reset by the falling edge of the last input WDC signal until it continues counting up and reaches the abnormality determination threshold. However, in the third embodiment, it is assumed that even if the output of the WDC signal stops, the output of the control signal that turns on the second switch 10 continues from the second control terminal of the control microcomputer 2.

[0034] When the monitoring microcomputer 3 detects an abnormality, it turns on the first switch 7 (1), as shown in Figures 8 and 10. This causes the reset terminal of the control microcomputer 2 to go low, causing the control microcomputer 2 to enter a reset state (2). This then stops the output of the signal that turns on the second switch 10 from the second control terminal, causing the second switch 10 to go off (3). However, because the power supply IC 4 keeps the reset signal high, the monitoring microcomputer 3 is not reset and continues to operate.

[0035] As described above, according to the third embodiment, when the WDC signal input from the control microcontroller 2 stops and the monitoring microcontroller 3 detects an abnormality in the control microcontroller 2, the first switch 7 is turned ON to reset the control microcontroller 2.

[0036] (Fourth embodiment) <Sequence when control microcomputer 2's WDC signal is abnormal: SW2 control signal output stops> As in the third embodiment, the fourth embodiment assumes a case where the WDC signal input from the control microcomputer 2 stops, but where the output of the control signal that turns the second switch 10 ON from the second control terminal stops. As shown in Figures 11 and 12, when the WDC signal input from the control microcomputer 2 stops and the output of the control signal stops, the second switch 10 turns OFF (1). When the watchdog timer continues counting up and reaches the abnormality determination threshold, the monitoring microcomputer 3 detects an abnormality.

[0037] When the monitoring microcomputer 3 detects an abnormality, it turns on the first switch 7 (2), causing the control microcomputer 2 to enter a reset state (3). As a result, the only difference compared to the third embodiment is that the timing at which the second switch 10 is turned off is earlier.

[0038] (Fifth embodiment) <Sequence when WDC signal of monitoring microcomputer 3 is abnormal; SW1 control signal output continues> 13 and 14, when the WDC signal input from the monitoring microcomputer 3 stops and the watchdog timer inside the power supply IC 4 continues counting up until the abnormality detection time has elapsed, the power supply IC 4 detects the abnormality and sets the reset signal to low level (1). Accordingly, the control microcomputer 2 enters a reset state (2). In the fifth embodiment, it is assumed that even if the output of the WDC signal stops, the output of the control signal that turns off the first switch 7 continues from the first control terminal of the monitoring microcomputer 3.

[0039] When the control microcomputer 2 enters the reset state, the second switch 10 turns OFF (3). However, the power supply IC 4 keeps the reset signal at a low level, so the monitoring microcomputer 3 is reset (4). Then, the output of the signal that keeps the first switch 7 OFF stops, and the first switch 7 turns ON (5).

[0040] As described above, according to the fifth embodiment, when the WDC signal input from the monitoring microcontroller 3 is stopped and the power supply IC 4 detects an abnormality in the monitoring microcontroller 3, the monitoring microcontroller 3 can be put into a reset state even if the monitoring microcontroller 3 continues to output a control signal that turns off the first switch 7.

[0041] (Sixth embodiment) <Sequence when WDC signal of monitoring microcomputer 3 is abnormal: SW1 control signal output stops> The sixth embodiment, like the fifth embodiment, assumes that the WDC signal input from the monitoring microcontroller 3 stops, but that the output of the control signal that turns off the first switch 7 from the first control terminal stops.

[0042] 15 and 16, when the WDC signal input from the monitoring microcomputer 3 stops and an abnormality occurs, the monitoring microcomputer 3 stops outputting the control signal that is turning the first switch 7 OFF, and the first switch 7 turns ON (1). This causes the reset signal of the control microcomputer 2 to go low, resetting the control microcomputer 2 (2), and turning the second switch 10 OFF (3). The watchdog timer inside the power supply IC 4 continues counting up, and when the abnormality detection time has elapsed, the power supply IC 4 detects the abnormality and sets the reset signal to low (4). This causes the monitoring microcomputer 3 to go into a reset state (5).

[0043] As described above, according to the sixth embodiment, when the WDC signal input from the monitoring microcontroller 3 is stopped and the power supply IC 4 detects an abnormality in the monitoring microcontroller 3, the control microcontroller 2 can be put into a reset state even if the monitoring microcontroller 3 stops outputting the control signal that turns off the first switch 7.

[0044] (Seventh embodiment) In an electronic control device 1A of the seventh embodiment shown in FIG. 17, the voltage for pull-up is obtained by dividing the voltage of the BATT power supply by a resistor, instead of the control power supply VC.

[0045] (Other embodiments) The high / low relationship between the effective and ineffective levels of the signal may be reversed. The configuration of the first and second level setting circuits is not limited to that shown in the figure. Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0046] In the drawings, 1 indicates an electronic control device, 2 indicates a control microcomputer, 3 indicates a monitoring microcomputer, 4 indicates a power supply IC, 5 and 6 indicate diodes, 7 indicates a first switch, 8 indicates a resistive element, 10 indicates a second switch, 1 indicates a resistive element, 15 and 16 indicate diodes, 17 indicates a first level setting circuit, 18 indicates a second level setting circuit, and 20 indicates a voltage monitoring unit.

Claims

1. A control microcomputer (2), A monitoring microcomputer (3) that monitors the operation of the control microcomputer; a first level setting circuit (17) that sets the level of the reset terminal of the control microcomputer by turning on / off a first switch (7); a second level setting circuit (18) that sets the level of the reset terminal of the monitoring microcomputer by turning on / off a second switch (10); a reset circuit (4) that outputs a reset signal to the control microcomputer and the monitoring microcomputer; When the reset signal changes to an invalid level, the first and second level setting circuits maintain the control microcomputer in a reset state by turning on the first switch, and release the reset state of the monitoring microcomputer; An electronic control device for a vehicle is configured such that, when the reset signal changes to an active level, the second switch is turned ON, thereby putting the control microcomputer into a reset state and maintaining the reset of the monitoring microcomputer in an unlocked state.

2. the first level setting circuit is connected between a reset terminal of the control microcomputer and a first potential point that applies a potential of a reset valid level, and is composed of a series circuit of the first switch and a resistor element (8); the second level setting circuit is connected between a reset terminal of the monitoring microcomputer and a second potential point that applies a potential of a reset invalid level, and is composed of a series circuit of the second switch and a resistor element (11); The first switch is turned on and off by the monitoring microcomputer. a first control terminal to which the monitoring microcomputer outputs a signal for controlling the first switch is connected via a resistance element to a potential point that turns on the first switch; The second switch is turned on and off by the control microcomputer. a second control terminal to which the control microcomputer outputs a signal for controlling the second switch is connected via a resistance element to a potential point that turns off the second switch; When the reset state is released, the monitoring microcomputer turns off the first switch to release the reset state of the control microcomputer, 2. The electronic control device for a vehicle according to claim 1, wherein the control microcomputer turns on the second switch when the reset state is released.

3. 3. The electronic control device for a vehicle according to claim 2, wherein the monitoring microcomputer controls the first switch to reset the control microcomputer when the monitoring microcomputer detects that an abnormality has occurred in the control microcomputer.

4. 4. The electronic control unit for a vehicle according to claim 3, wherein the occurrence of the abnormality is detected using a watchdog timer.

5. 5. The electronic control device for a vehicle according to claim 1, wherein the reset circuit sets the reset signal to an active level when detecting that an abnormality has occurred in the monitoring microcomputer.

6. 6. The vehicle electronic control device according to claim 5, further comprising a reset signal branch circuit consisting of two diodes (5, 6) having a common anode connected to the reset signal output terminal of the reset circuit and two cathodes connected to the reset terminals of the control and monitoring microcomputer, respectively.

7. A voltage monitoring circuit (20) is provided to monitor the power supply voltage, 5. The electronic control device for a vehicle according to claim 1, wherein the voltage monitoring circuit sets the reset signal to an active level when it detects that the power supply voltage has become abnormal.

8. A voltage monitoring circuit (20) is provided to monitor the power supply voltage, 7. The electronic control unit for a vehicle according to claim 6, wherein the voltage monitoring circuit sets the reset signal to an active level when it detects that the power supply voltage has become abnormal.

9. 9. The electronic control unit for a vehicle according to claim 8, wherein the reset circuit, the voltage monitoring circuit, the first and second level setting circuits, and the reset signal branch circuit are configured as a single IC.

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