Drivers, electro-optical devices and electronic devices

Abstract

To provide a driver and the like that can compensate for excess or deficiency of electric charges occurring when a data line is connected in capacity drive by redistributing electric charges.SOLUTION: A driver 100 includes: a data voltage output terminal TVQ that is electrically connected with a data line via a data line switch of an electro-optical panel 200; a capacitor driving circuit 20 that outputs first to n-th capacitor driving voltages corresponding to gradation data to first to n-th nodes for driving capacitors; a capacitor circuit 10 that has first to n-th capacitors provided between an output node NVQ and the first to n-th nodes for driving capacitors; a processing circuit 42 that calculates the amount of excess or deficiency of electric charges in the output node NVQ when the data line switch is turned on; and an electric charge compensation circuit 90 that injects compensation electric charges based on the amount of excess or deficiency of electric charges calculated by the processing circuit 42 to the output node NVQ or discharges the electric charges from the output node NVQ by using an electric charge compensation capacitor circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a driver that includes a capacitive driving circuit and an amplifier circuit and drives an electro-optical panel. After the capacitive driving circuit starts capacitive driving of the electro-optical panel, the amplifier circuit performs voltage driving to output a data voltage corresponding to grayscale data to a data voltage output terminal. As a result, the amplifier circuit compensates for the drop in source line voltage after the source line switch of the electro-optical panel changes from off to on, thereby suppressing a decrease in accuracy of the data voltage during capacitive driving. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-80807 Summary of the Invention [Problem to be solved by the invention]

[0004] Before supplying grayscale voltages to pixel nodes and data lines connected to the pixel nodes, a precharge voltage is supplied to the pixel nodes and data lines. After the precharge voltage is supplied, a signal supply line, to which a voltage close to the target grayscale voltage is supplied by capacitive driving, is connected to the data line via a data line switch. Therefore, every time the signal supply line and data line are connected by the data line switch, charge supplied by capacitive driving flows to the data line, resulting in a charge surplus or deficiency. Patent Document 1 compensates for this charge surplus or deficiency using an amplifier circuit. However, when pixel drive time is shortened to accommodate higher pixel counts or higher frame rates, the responsiveness of the amplifier circuit poses a problem: the supply of the target grayscale voltage is delayed. Alternatively, increasing the responsiveness of the amplifier circuit increases power consumption or circuit area. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a driver including: a data voltage output terminal electrically connected to a data line via a data line switch of an electro-optical panel; a capacitor drive circuit that outputs first to n-th capacitor drive voltages (n is an integer of 2 or greater) corresponding to grayscale data to first to n-th capacitor drive nodes; an output node that is a node of the data voltage output terminal; a capacitor circuit having first to n-th capacitors provided between the first to n-th capacitor drive nodes; a processing circuit that calculates an excess or deficiency charge amount that is a deficiency or excess charge amount of the output node when the data line switch is turned on; and a charge compensation circuit that has a charge compensation capacitor circuit and uses the charge compensation capacitor circuit to inject or discharge compensation charge into or from the output node based on the excess or deficiency charge amount calculated by the processing circuit.

[0006] Another aspect of the present disclosure relates to an electro-optical device including the driver and the electro-optical panel.

[0007] Yet another aspect of the present disclosure relates to an electronic device including the driver described above. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows an example of the configuration of an electro-optical device. [Figure 2] First detailed configuration example of the driver. [Figure 3] FIG. 4 is a diagram illustrating the relationship between grayscale data and data voltage. [Figure 4] 10A and 10B show examples of detailed configurations of a capacitor circuit and a capacitor drive circuit, and examples of capacitance on the electro-optical panel side. [Figure 5] 10 shows an example of a signal waveform when the charge compensation circuit of the present embodiment is not used. [Figure 6] 10 is a first signal waveform example when the charge compensation circuit of the present embodiment is used. [Figure 7] 10 shows a second signal waveform example when the charge compensation circuit of the present embodiment is used. [Figure 8] 10 shows a first detailed configuration example of a charge compensation circuit. [Figure 9] 10 shows a first detailed configuration example of a processing circuit. [Figure 10] Example of capacitance value of capacitively driven capacitor. [Figure 11] 10 is a table illustrating a calculation formula for excess and deficiency tone values. [Figure 12] Calculation example for drive orders 1 to 4 in the horizontal scanning period. [Figure 13] Second detailed configuration example of the driver. [Figure 14] 10 shows a second detailed configuration example of a charge compensation circuit. [Figure 15] 10 shows an example of the signal waveform of a control signal output from a processing circuit to a charge compensation circuit in the second embodiment. [Figure 16] 10 shows a second detailed configuration example of a processing circuit. [Figure 17] FIG. 10 is a diagram illustrating a gradation value for calculating a compensation charge amount. [Figure 18] 10 is a table explaining the calculation formula for the capacity setting value. [Figure 19] Calculation example for drive orders 1 to 4 in the horizontal scanning period. [Figure 20] 10 shows a second detailed configuration example of a charge compensation circuit. [Figure 21]11 shows a first signal waveform example of a control signal output from a processing circuit to a charge compensation circuit in the third embodiment. [Figure 22] 11 shows a second signal waveform example of the control signal output from the processing circuit to the charge compensation circuit in the third embodiment. [Figure 23] 10 shows a third detailed configuration example of a processing circuit. [Figure 24] 1 is a table explaining the calculation formulas for the amount of charge injected and the amount of charge discharged. [Figure 25] Calculation example for drive orders 1 to 4 in the horizontal scanning period. [Figure 26] An example of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0010] 1. Electro-optical devices 1 shows an example of the configuration of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. In the following, the electro-optical device 400 will be described using a phase expansion driving method as an example, but is not limited to this. For example, the electro-optical device 400 may also use a demultiplex driving method.

[0011] The driver 100 drives the electro-optical panel 200 by outputting a data voltage to the signal supply lines of the electro-optical panel 200. A scanning line driving circuit that drives the scanning lines of the electro-optical panel 200 may be included in the driver 100, or may be provided external to the driver 100. The driver 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The driver 100 includes a control circuit 40 and first to k-th data line driving circuits DD1 to DDk, where k is an integer equal to or greater than 2. Note that the following description will be given taking the case where k=8 as an example.

[0012] The control circuit 40 outputs corresponding grayscale data to each of the data line driving circuits DD1 to DD8. The control circuit 40 also outputs a control signal ENBX to the electro-optical panel 200 to control the data line switches.

[0013] The data line driving circuits DD1 to DD8 convert the grayscale data into data voltages, and output the data voltages to the signal supply lines DL1 to DL8 of the electro-optical panel 200 as output voltages VQ1 to VQ8.

[0014] The electro-optical panel 200 includes first to eighth signal supply lines DL1 to DL8, first to 1280th data line switches SWEP1 to SWEP1280, and first to 1280th data lines SL1 to SL1280. There may be k×t data lines, where t is an integer equal to or greater than 2. Here, WXGA is used as an example, and t=160.

[0015] Of the data line switches SWEP1 to SWEP1280, one end of the data line switches SWEP((j-1)×k+1) to SWEP(j×k) is connected to the signal supply lines DL1 to DL8. j is an integer equal to or less than 160. For example, when j=1, the data line switches are SWEP1 to SWEP8.

[0016] Each of the data line switches SWEP1 to SWEP1280 is configured, for example, with a TFT or the like and is controlled based on a control signal ENBX. TFT stands for Thin Film Transistor. For example, the electro-optical panel 200 includes a switch control circuit (not shown), which controls the data line switches SWEP1 to SWEP1280 to turn on or off based on the control signal ENBX.

[0017] The data line driving circuits DD1 to DD8 perform 160 driving operations during the horizontal scanning period, and during the jth driving operation, data line switches SWEP((j-1)×k+1) to SWEP(j×k) are on, and the other data line switches are off. As a result, during the jth driving operation, data lines SL((j-1)×k+1) to SL(j×k) are driven. Focusing on the data line driving circuit DD1, the data line switches SWEP1, SWEP2, ..., SWEP1273 are turned on sequentially during the horizontal scanning period, and the data line driving circuit DD1 drives the data lines SL1, SL2, ..., SL1273 sequentially.

[0018] 2. First embodiment 2 shows a first detailed configuration example of a driver. The driver 100 includes a data line driving circuit 110 and a control circuit 40. The data line driving circuit 110 corresponds to any one of the data line driving circuits DD1 to DD8 in FIG.

[0019] The data line driving circuit 110 includes a capacitor circuit 10, a capacitor driving circuit 20, a charge compensation circuit 90, a variable capacitance circuit 30, and a detection circuit 50. The control circuit 40 includes a processing circuit , an interface circuit 44, and a register circuit .

[0020] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is, for example, an image interface circuit of the LVDS system, parallel RGB system, or display port system. LVDS is an abbreviation for Low Voltage Differential Signaling.

[0021] The processing circuit 42 determines the setting data CSW[4:0] for the capacitance value of the variable capacitance circuit 30 during initialization processing when the driver 100 is powered on, and stores the setting data CSW[4:0] in the register circuit 48. During normal operation to drive the electro-optical panel 200, the processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 using the setting data CSW[4:0] read from the register circuit 48. The processing circuit 42 also outputs gradation data DQ[10:0] for capacitance driving to the capacitor driving circuit 20 based on the gradation data GD[9:0].

[0022] The output node NVQ is a node connected to the data voltage output terminal TVQ, and the voltage at this output node NVQ is defined as the output voltage VQ. The load capacitance of the data voltage output terminal TVQ is defined as the electro-optical panel capacitance CP. The capacitor driving circuit 20 drives the capacitor circuit 10 based on the grayscale data DQ[10:0]. This causes the capacitor circuit 10 to supply charge to the output node NVQ, and the charge is redistributed among the capacitor circuit 10, the variable capacitance circuit 30, and the electro-optical panel capacitance CP. As a result, the output voltage VQ becomes a data voltage corresponding to the grayscale data DQ[10:0].

[0023] 3 is a diagram illustrating the relationship between grayscale data and data voltage. The processing circuit 42 converts the input grayscale data GD[9:0] into grayscale data DQ_GD[10:0]. Specifically, in the case of negative polarity drive, the processing circuit 42 converts the grayscale values ​​0 to 1023 of the grayscale data GD[9:0] into grayscale values ​​1023 to 0 of the grayscale data DQ_GD[10:0], and in the case of positive polarity drive, the processing circuit 42 converts the grayscale values ​​0 to 1023 of the grayscale data GD[9:0] into grayscale values ​​1024 to 2047 of the grayscale data DQ_GD[10:0].

[0024] VSH=0V is the low potential side power supply voltage of the capacitor driving circuit 20. VDH=15V is the high potential side power supply voltage of the capacitor circuit 10. The common voltage supplied to the counter electrode of the electro-optical panel 200 is VC=7.5V. The data voltage supplied to the pixel is 7.5V to 2.5V in negative polarity driving and 7.5V to 12.5V in positive polarity driving.

[0025] In the first embodiment, the processing circuit 42 outputs the gradation data DQ_GD[10:0] as gradation data DQ[10:0] for capacitive driving to the capacitor driving circuit 20. However, in some of the embodiments described below, the processing circuit 42 generates the gradation data DQ[10:0] for capacitive driving by adding an excess / deficiency gradation value for charge compensation to the gradation data DQ_GD[10:0].

[0026] The charge compensation circuit 90 compensates for the insufficient or excessive charge at the output node NVQ that occurs when the data line switch of the electro-optical panel 200 changes from off to on. The insufficient or excessive charge causes the output voltage VQ to deviate from the data voltage, but the charge compensation circuit 90 can bring the output voltage VQ closer to the data voltage by injecting or discharging compensation charge that compensates for the insufficient or excessive charge into or from the output node NVQ. The charge compensation circuit 90 compensates for the charge by charge redistribution using a capacitor, thereby compensating for the charge faster than an amplifier circuit.

[0027] The processing circuit 42 calculates the setting data DCC[4:0] that sets the amount of compensation charge based on the grayscale data DQ_GD[10:0], and the charge compensation circuit 90 injects or discharges the compensation charge into or from the output node NVQ based on the setting data DCC[4:0]. Note that the number of bits of the setting data may be arbitrary.

[0028] A method for determining the capacitance value of the variable capacitance circuit 30 and an example of the configuration of the variable capacitance circuit 30 will be described below.

[0029] The detection circuit 50 compares a given detection voltage with the output voltage VQ and outputs the result as a detection signal DET. The detection circuit 50 is, for example, a comparator.

[0030] The processing circuit 42 outputs grayscale data DQ[10:0] corresponding to a given data voltage to the capacitor driving circuit 20. At this time, the given detection voltage is set to the same voltage as the given data voltage, which is the expected value of the output voltage VQ. The processing circuit 42 sequentially changes the value of the setting data CSW[4:0], thereby sequentially changing the capacitance value of the variable capacitance circuit 30. The processing circuit 42 determines the capacitance value of the variable capacitance circuit 30 based on the detection signal DET at each capacitance value. That is, the processing circuit 42 determines the capacitance value at which the output voltage VQ becomes a given detection voltage based on the detection signal DET, and stores the setting data CSW[4:0] of that capacitance value in the register circuit 48.

[0031] The variable capacitance circuit 30 includes first to fifth adjustment capacitors and first to fifth adjustment switches. One end of the first adjustment switch is connected to the output node NVQ, and the other end is connected to one end of the first adjustment capacitor. The other end of the first adjustment capacitor is connected to the ground node. The same applies to the second to fifth adjustment capacitors and the second to fifth adjustment switches. The capacitance values ​​of the first to fifth adjustment capacitors are binary weighted. The first adjustment switch is controlled to be on or off by CSW[0]. Similarly, the second to fifth adjustment switches are controlled to be on or off by CSW[1] to CSW[4].

[0032] FIG. 4 shows an example of the detailed configuration of a capacitor circuit and a capacitor driving circuit, and an example of the capacitance on the electro-optical panel side. Note that hereinafter, the same symbol as the symbol of the capacitor is used to represent the capacitance value of the capacitor. For example, the capacitance value of capacitor C1 is written as C1. Furthermore, the same symbol as the symbol of the data is used to represent the value indicated by the data. For example, when focusing on the gradation value of the gradation data DQ[10:0], the gradation value is represented by DQ.

[0033] The capacitor circuit 10 includes first to n-th capacitors C1 to Cn. The capacitor drive circuit 20 includes first to n-th drive circuits DR1 to DRn. Although an example where n=10 will be described below, n may be any integer equal to or greater than 2. n may be set to the same number as the number of bits of the grayscale data DQ[10:0].

[0034] One end of the capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor driving node NDRi. i is an integer greater than or equal to 1 and less than or equal to 10. The capacitors C1 to C10 have binary-weighted capacitance values. Specifically, the capacitance value of the capacitor Ci is 2 (i-1) ×C1.

[0035] The processing circuit 42 outputs the ith bit DQ[i-1] of the grayscale data DQ[10:0] to the input node of the drive circuit DRi. When the bit DQ[i-1] is at a first logic level, the drive circuit DRi outputs a first voltage level to the capacitor drive node NDRi, and when the bit DQ[i-1] is at a second logic level, the drive circuit DRi outputs a second voltage level to the capacitor drive node NDRi. For example, the first logic level is "0," the second logic level is "1," the first voltage level is the low-potential power supply voltage VSH, and the second voltage level is the high-potential power supply voltage VDH. The drive circuit DRi is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the drive circuit DRi and a buffer circuit that buffers the output of the level shifter.

[0036] When the drive circuits DR1 to DR11 drive the capacitors C1 to C11, charge redistribution occurs between the capacitors C1 to C11, the variable capacitance circuit 30, and the electro-optical panel-side capacitance CP, and as a result, a data voltage is output to the output node NVQ.

[0037] The electro-optical panel capacitance CP is the total capacitance seen from the data voltage output terminal TVQ. For example, the electro-optical panel capacitance CP is the sum of a board capacitance CP1, which is the parasitic capacitance of the printed circuit board, and a panel capacitance CP2, which is the parasitic capacitance within the electro-optical panel 200. The printed circuit board is a board on which the driver 100 is mounted and which is connected to the electro-optical panel 200.

[0038] Assume that the sum of the capacitance values ​​of capacitors C1 to C11 is Ctot = C1 + C2 + ··· + C11, and the capacitance value of variable capacitance circuit 30 is CF. As an example, CF is set so that Ctot / (CF + CP) = 2. In this case, at the maximum gradation value DQ = 2047, VQ = 15V × {Ctot / (Ctot + CF + CP)} + 2.5V = 10V + 2.5V = 12.5V. At the minimum gradation value DQ = 0, VQ = 0V × {Ctot / (Ctot + CF + CP)} + 2.5V = 0V + 2.5V = 2.5V. If DQ = DQ_GD in FIG. 3, the same data voltage as in the example of FIG. 3 is realized.

[0039] The charge of the output node NVQ is initialized during a blanking period, etc. As an example, an initialization voltage of 2.5V is supplied to the output node NVQ, and the gradation data DQ[10:0] with a gradation value DQ=0 indicating that voltage is input to the capacitor driving circuit 20.

[0040] 5 shows an example of signal waveforms when the charge compensation circuit of this embodiment is not used. In the following, an example of signal waveforms related to the data lines SL1 and SL9 in one horizontal scanning period will be described in which the data line driving circuit 110 is the data line driving circuit DD1 shown in FIG.

[0041] The data line switches SWEP1 and SWEP9 are turned on, and the data line drive circuit DD1 outputs the precharge voltage VPR. This charges the signal supply line DL1 and the data lines SL1 and SL9 with the precharge voltage VPR. Next, the data line switches SWEP1 and SWEP9 are turned off.

[0042] Next, the data line driving circuit DD1 starts capacitive driving, and the signal supply line DL1 is charged with the data voltage SV1. Next, the data line switch SWEP1 is turned on to connect the signal supply line DL1 and the data line SL1. The data line SL1 is charged, and then the data line switch SWEP1 is turned off. Before the signal supply line DL1 and the data line SL1 are connected, the signal supply line DL1 has the data voltage SV1, and the data line SL1 has the precharge voltage VPR. Therefore, when the signal supply line DL1 and the data line SL1 are connected, charge redistribution occurs, and the voltage of the signal supply line DL1 shifts from SV1 to SV1'. Letting this shift be ΔV1, then SV1' = SV1 - ΔV1. When SV1 > VPR, SV1' < SV1, and when SV1 < VPR, SV1' > SV1. This voltage SV1' is written to the data line SL1.

[0043] Next, the data line driving circuit DD1 starts capacitive driving, and the signal supply line DL9 is charged. The target voltage is the data voltage SV9, but since it is shifted by the above ΔV1, the signal supply line DL9 is charged with the voltage SV9 - ΔV1. Next, the data line switch SWEP9 is turned on to connect the signal supply line DL1 and the data line SL9. The data line SL9 is charged, and then the data line switch SWEP9 is turned off. When the signal supply line DL1 and the data line SL9 are connected, charge redistribution occurs, and the voltage of the signal supply line DL1 shifts from SV9 - ΔV1 to SV9' = SV9 - ΔV1 - ΔV2. This voltage SV9' is written to the data line SL9.

[0044] As described above, when the data line switch is turned on and the signal supply line and the data line are connected, the charge of the signal supply line moves to the data line, and then the data line switch is turned off. In capacitive driving, it is necessary to conserve the charge of the output node. However, due to the above charge movement, an excess or deficiency of charge occurs, and the charge conservation in capacitive driving no longer holds. In Patent Document 1 described above, an amplifier circuit is used to compensate for the excess or deficiency of charge. However, with an increase in the number of pixels or frame rate, etc., the power consumption or circuit area of the amplifier circuit increases.

[0045] FIG. 6 is an example of a first signal waveform when the charge compensation circuit of the present embodiment is used. FIG. 6 shows an example of a signal waveform when charge compensation is started at the timing when the data line switch is turned on.

[0046] The charge compensation circuit 90 injects or discharges the compensation charge corresponding to ΔV1 to / from the output node NVQ at the timing when the data line switch SWEP1 changes from off to on. The charge compensation circuit 90 injects charge when SV1 > VPR and discharges charge when SV1 < VPR. Similarly, the charge compensation circuit 90 injects or discharges the compensation charge corresponding to ΔV2 to / from the output node NVQ at the timing when the data line switch SWEP9 changes from off to on.

[0047] The processing circuit 42 updates the set value DCC of the setting data DCC[4:0] to the charge compensation circuit 90 at the timing when the data line switch changes from off to on. Thereby, charge compensation is started at the timing when the data line switch changes from off to on. The set value DCC is a set value of the compensation charge amount, and the method for determining the set value DCC will be described later.

[0048] FIG. 7 is an example of a second signal waveform when the charge compensation circuit of the present embodiment is used. FIG. 7 shows an example of a signal waveform when charge compensation is started at the timing when the capacitance driving is started.

[0049] When the capacitance driving starts, the charge compensation circuit 90 injects or discharges the compensation charge corresponding to ΔV1 to / from the output node NVQ. As a result, the voltage of the signal supply line DL1 becomes SV1”. When SV1 > VPR, the charge compensation circuit 90 injects charge, so SV1” > SV1. When SV1 < VPR, the charge compensation circuit 90 discharges charge, so SV1” < SV1. When the data line switch SWEP9 turns on from off, the voltages of the signal supply line DL1 and the data line SL1 become the data voltage SV1 due to charge redistribution. Similarly, when the capacitance driving starts, the charge compensation circuit 90 injects or discharges the compensation charge corresponding to ΔV2 to / from the output node NVQ. As a result, the voltage of the signal supply line DL1 becomes SV9”. When the data line switch SWEP9 turns on from off, the voltages of the signal supply line DL1 and the data line SL9 become the data voltage SV9.

[0050] The processing circuit 42 updates the set value DCC of the setting data DCC[4:0] to the charge compensation circuit 90 at the timing when the capacitance driving starts. As a result, charge compensation starts at the timing when the capacitance driving starts.

[0051] As described above, by using the charge compensation circuit 90 to compensate for the excess or deficiency charge by charge redistribution, the voltage of the data line can be asymptotically approximated to the data voltage at a higher speed compared to the case of using an amplifier circuit. Also, even when an amplifier circuit is further used in combination, it is possible to reduce the amount of charge that the amplifier circuit should compensate.

[0052] FIG. 8 shows a first detailed configuration example of the charge compensation circuit. The charge compensation circuit 90 includes a charge compensation capacitor circuit 92 and first to mth compensation drive circuits DRC1 to DRCm. The charge compensation capacitor circuit 92 includes first to mth compensation capacitors CC1 to CCm. Hereinafter, an example of m = 5 will be described, but m may be an integer of 2 or more. m may be set to the same number as the number of bits of the setting data DCC[4:0].

[0053] One end of the compensation capacitor CCr is connected to the output node NVQ, and the other end is connected to the node NDRCr. r is an integer greater than or equal to 1 and less than or equal to m=5. The compensation capacitors CC1 to CC5 have binary-weighted capacitance values. Specifically, the capacitance value of the compensation capacitor CCr is 2 (r-1) ×CC1. The capacitance value CC1 is a capacitance value at a predetermined ratio to the capacitance value C1 of the LSB of the capacitor circuit 10. The predetermined ratio is, for example, 1, 1 / 2, or 1 / 4, but is not limited to these. For example, if CC1=C1 / 4, charge compensation can be performed with a resolution of LSB / 4.

[0054] The driver circuit DRCr outputs the rth compensation signal to the node NDRCr. Specifically, the processing circuit 42 outputs the rth bit DCC[r-1] of the setting data DCC[4:0] to the input node of the compensation driver circuit DRCr. The compensation driver circuit DRCr outputs a first voltage level to the node NDRCr when the bit DCC[r-1] is at a first logic level, and outputs a second voltage level to the node NDRCr when the bit DCC[r-1] is at a second logic level. For example, the first logic level is "0," the second logic level is "1," the first voltage level is the low-potential power supply voltage VSH, and the second voltage level is the high-potential power supply voltage VDH. The compensation driver circuit DRCr is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the compensation driver circuit DRCr and a buffer circuit that buffers the output of the level shifter.

[0055] 9 shows a first detailed configuration example of the processing circuit. The processing circuit 42 includes adders ADA1 and ADA2, a multiplier MXA, and latch circuits LTA1 and LTA2. Note that the number of bits of data that does not specify the number of bits may be any number. Furthermore, the number of bits of data that does specify the number of bits may be expanded within the processing circuit 42 and used for calculations.

[0056] The latch circuit LTA1 latches the grayscale data DQ_GD[10:0] and outputs the latched data to the capacitor driving circuit 20 as the grayscale data DQ[10:0]. The adder ADA1 subtracts the precharge grayscale data DPRE[10:0] from the grayscale data DQ[10:0]. The multiplier MXA multiplies the output data of the adder ADA1 by the data of the coefficient Coef and outputs the result as the excess / deficiency grayscale data DCC_DQ. The adder ADA2 adds the excess / deficiency grayscale data DCC_DQ and the setting data DCC[4:0]. The latch circuit LTA2 latches the output data of the adder ADA2 and outputs the latched data to the charge compensation circuit 90 as the setting data DCC[4:0]. The setting data DCC[4:0] becomes the accumulated data of the excess / deficiency grayscale data DCC_DQ. The latch circuit LTA2 is reset by the horizontal synchronization signal HSYNC.

[0057] A specific calculation example will be shown below. Figure 10 shows an example of the capacitance values ​​of the capacitively driven capacitors. The capacitance value corresponding to the LSB of the gradation data DQ[10:0] is C1 = 0.048828 pF. As mentioned above, the capacitance values ​​of C2 to C11 are binary weighted with C1 as the reference. When the drive circuit DR1 drives the capacitor C1 with VSH = 15 V, the charge held by the capacitor C1 relative to ground is C1 × 15 V = 0.73242 pC. Similarly, the charge amounts of C2 to C11 are C2 × 15 V to C11 × 15 V.

[0058] Figure 11 is a table explaining the formula for calculating the excess / deficiency gradation value. Here, the parasitic capacitance of one data line is assumed to be 4 pF. Also, the precharge voltage is assumed to be 2.5 V. The precharge gradation value corresponding to the precharge voltage is DPRE=0.

[0059] The coefficient Coef is determined, for example, by an inspection process for the electro-optical device or circuit simulation. Assume that the capacitive driving gradation value is set to 1024. The data voltage for the gradation value 1024 is 7.5V. The excess or deficiency of charge resulting from the connection between the signal supply line and the data line is 4pF × (7.5V - 2.5V) = 20pC. To convert this excess or deficiency of charge into a gradation value, it is divided by the charge amount of C1, 0.73242pC, corresponding to 1LSB. This results in an excess or deficiency gradation value of 27.25 for the gradation value 1024. The coefficient Coef is the excess or deficiency gradation value per gradation, and is 27.25 / 1024. For example, the coefficient Coef is stored in a nonvolatile memory external to the driver 100.

[0060] During initialization processing when the power is turned on, the display controller 300 or the like reads the coefficient Coef from the nonvolatile memory and writes it to the register circuit 48 of the driver 100. The processing circuit 42 performs calculations using the coefficient Coef stored in the register circuit 48. The processing circuit 42 determines the excess / deficiency gradation value from the gradation value DQ_GD of the gradation data DQ_GD[10:0] using the following equation (1). DCC_DQ=(DQ_GD-DPRE)×Coef (1)

[0061] In the example of FIG. 11, DCC_DQ=(DQ_GD-0)×(27.25 / 1024).

[0062] 12 shows an example of calculations for drive orders 1 to 4 in a horizontal scanning period. In each drive order, one data line is driven, and drive order 1 indicates the first drive order in a horizontal scanning period. Here, the precharge grayscale value is set to DPRE=25.

[0063] Assume that the gradation values ​​DQ_GD=1024, 1640, 1750, and 2048 for drive orders 1, 2, 3, and 4. In this case, the excess and deficiency gradation values ​​for drive orders 1, 2, 3, and 4 are DCC_DQ=26.5, 42.75, 45.75, and 53.75. The setting value DCC of the charge compensation circuit 90 is the cumulative value of the excess and deficiency gradation values ​​DCC_DQ, so the setting values ​​for drive orders 1, 2, 3, and 4 are DCC=26.5, 69.25, 115, and 168.75. The gradation value for capacitive driving is DQ=DQ_GD.

[0064] For example, the excess / deficiency gradation value DCC_DQ=26.5 in drive order 1 corresponds to ΔV1 in Fig. 5, and the excess / deficiency gradation value DCC_DQ=47.25 in drive order 2 corresponds to ΔV2 in Fig. 5. The charge compensation circuit 90 compensates for ΔV1 in drive order 1 and compensates for ΔV2 in drive order 2, so that ΔV1+ΔV2 is ultimately compensated for in drive order 2. For this reason, the cumulative value of the excess / deficiency gradation value DCC_DQ is used as the setting value DCC of the charge compensation circuit 90.

[0065] In the above-described embodiment, the driver 100 includes a data voltage output terminal TVQ, a capacitor driving circuit 20, a capacitor circuit 10, a processing circuit 42, and a charge compensation circuit 90. The data voltage output terminal TVQ is electrically connected to the data lines via the data line switches of the electro-optical panel 200. The capacitor driving circuit 20 outputs first to n-th capacitor driving voltages corresponding to grayscale data to first to n-th capacitor driving nodes NDR1 to NDRn, where n is an integer equal to or greater than 2. The capacitor circuit 10 includes first to n-th capacitors C1 to Cn provided between an output node NVQ, which is the node of the data voltage output terminal TVQ, and the first to n-th capacitor driving nodes NDR1 to NDRn. The processing circuit 42 calculates the amount of excess or deficiency charge, which is the amount of charge deficiency or excess charge at the output node NVQ when the data line switch is turned on. The charge compensation circuit 90 includes a charge compensation capacitor circuit 92. The charge compensation circuit 90 uses a charge compensation capacitor circuit 92 to inject or discharge compensation charge into or from the output node NVQ based on the excess or deficiency of charge calculated by the processing circuit 42 .

[0066] According to this embodiment, the charge compensation circuit 90 can compensate for excess or deficiency of charge by charge redistribution using the charge compensation capacitor circuit 92. This allows the voltage on the data line to approach the data voltage more quickly than when an amplifier circuit is used to compensate for excess or deficiency of charge. Alternatively, even when an amplifier circuit is further used, it is possible to reduce the amount of charge that the amplifier circuit must compensate for. This allows the amplifier circuit to consume less power or be smaller in size.

[0067] In this embodiment, the voltage of the data line when the data line switch is off is the precharge voltage VPR. At this time, the processing circuit 42 calculates the excess or deficiency of charge caused by the difference between the precharge voltage VPR and the target voltage corresponding to the grayscale data when the data line switch is turned on from off.

[0068] Capacitive driving is premised on the conservation of charge at the output node NVQ, but as explained in Figure 5 etc., the data line is precharged with the precharge voltage VPR before driving, so when the output node NVQ charged with the data voltage is connected to the data line, the charge at the output node NVQ is no longer conserved. According to this embodiment, by calculating the excess or deficiency of charge caused by the difference between the precharge voltage VPR and the target voltage corresponding to the gradation data DQ[10:0], it is possible to bring the output node NVQ closer to a charge conservation state and bring the voltage of the data line closer to the target voltage.

[0069] The target voltage is a data voltage indicated by the grayscale data, and is the original voltage that should be output to the data line.

[0070] In this embodiment, the gradation value corresponding to the target voltage is DQ_GD, the gradation value corresponding to the precharge voltage VPR is DPRE, a coefficient indicating the ratio of the excess or deficiency charge amount to the difference between the target voltage and the precharge voltage VPR is Coef, and an excess or deficiency gradation value that compensates for the excess or deficiency charge amount is DCC_DQ. At this time, the processing circuit 42 calculates the excess or deficiency gradation value by the formula DCC_DQ=(DQ_GD-DPRE)×Coef. The charge compensation circuit 90 injects or discharges compensation charge into or from the output node NVQ based on the excess or deficiency gradation value DCC_DQ.

[0071] According to this embodiment, the above calculation results in an excess / deficiency gradation value DCC_DQ, which is a gradation value corresponding to the excess or deficiency of charge. The gradation value corresponding to the charge amount is the gradation value when the charge amount of the first capacitor C1 of the capacitor circuit 10 is set to one gradation. By using the excess / deficiency gradation value DCC_DQ, the excess or deficiency of charge can be handled based on the charge amount corresponding to one gradation. For example, the capacitance value of the capacitor of the charge compensation capacitor circuit 92 may be set to, for example, twice or half the capacitance value of the first capacitor C1 of the capacitor circuit 10. This allows the capacitor to compensate for the excess or deficiency of charge equivalent to two gradations or one-half gradation.

[0072] In this embodiment, the charge compensation capacitor circuit 92 includes first to m-th compensation capacitors CC1 to CCm, one end of which is connected to the output node NVQ. The charge compensation circuit 90 includes first to m-th compensation drive circuits DRC1 to DRCm, which output first to m-th compensation signals based on the excess or deficiency of charge to the other ends of the first to m-th compensation capacitors CC1 to CCm.

[0073] According to this embodiment, the other ends of the first to m-th compensation capacitors CC1 to CCm are driven by first to m-th compensation signals based on the excess or deficiency of charge, thereby causing compensation charges based on the excess or deficiency of charge to be injected into or discharged from the output node NVQ from the first to m-th compensation capacitors CC1 to CCm.

[0074] Furthermore, in this embodiment, the processing circuit 42 outputs a setting value DCC for the charge compensation circuit 90 based on the accumulated value of the excess or deficiency of charge for each data line. The first to m-th compensation drive circuits DRC1 to DRCm output first to m-th compensation signals corresponding to the setting value DCC. The first to m-th compensation capacitors CC1 to CCm are driven by the first to m-th compensation signals to inject or discharge compensation charges corresponding to the excess or deficiency of charge into or from the output node NVQ.

[0075] By performing charge compensation when a certain data line is driven, the output node NVQ is maintained in a charge storage state, and further charge compensation is performed when the next data line is driven based on that charge state. Therefore, charge compensation is cumulative. In this embodiment, the setting value DCC of the charge compensation circuit 90 is output based on the cumulative value of the excess or deficiency of charge for each data line, so charge compensation is cumulative.

[0076] 3. Second embodiment 13 shows a second detailed configuration example of the driver. In this configuration example, the processing circuit 42 outputs a control signal CNT to the charge compensation circuit 90, which controls the compensation operation of the charge compensation circuit 90, based on the excess / deficiency gradation value DCC_DQ. Note that components that have already been described are given the same reference numerals, and descriptions of those components will be omitted where appropriate.

[0077] In the second embodiment, the charge compensation circuit 90 injects or discharges compensation charges of the same amount as the excess or deficiency of charge into or from the output node NVQ when driving each data line, similar to the first embodiment, except that the configuration of the charge compensation circuit 90 is different.

[0078] 14 shows a second detailed configuration example of the charge compensation circuit. The charge compensation circuit 90 includes a charge compensation capacitor circuit 92, a first compensation drive circuit DRA, a first switch SAQ, a second switch SAVD, a third switch SAVS, a second compensation drive circuit DRB, a fourth switch SBQ, a fifth switch SBVD, and a sixth switch SBVS. The charge compensation capacitor circuit 92 includes a first compensation capacitor CAV and a second compensation capacitor CBV.

[0079] One end of the switch SAQ is connected to the output node NVQ, and the other end is connected to the node NCAV. One end of the switch SAVD is connected to a high-potential power supply node NVDH to which a high-potential power supply voltage VDH is supplied, and the other end is connected to the node NCAV. One end of the switch SAVS is connected to a low-potential power supply node NVSH to which a low-potential power supply voltage VSH is supplied, and the other end is connected to the node NCAV. One end of the compensation capacitor CAV is connected to the node NCAV, and the other end is connected to the node NDRA.

[0080] One end of the switch SBQ is connected to the output node NVQ, and the other end is connected to the node NCBV. One end of the switch SBVD is connected to a high-potential power supply node NVDH to which a high-potential power supply voltage VDH is supplied, and the other end is connected to the node NCBV. One end of the switch SBVS is connected to a low-potential power supply node NVSH to which a low-potential power supply voltage VSH is supplied, and the other end is connected to the node NCBV. One end of the compensation capacitor CBV is connected to the node NCBV, and the other end is connected to the node NDRB.

[0081] The processing circuit 42 outputs, as the control signals CNT, a control signal AQ that controls the switch SAQ to be on or off, a control signal AVD that controls the switch SAVD to be on or off, a control signal AVS that controls the switch SAVS to be on or off, a control signal DA for the compensation drive circuit DRA, and setting data SETA that sets the capacitance value of the compensation capacitor CAV.The processing circuit 42 also outputs, as the control signals CNT, a control signal BQ that controls the switch SBQ to be on or off, a control signal BVD that controls the switch SBVD to be on or off, a control signal BVS that controls the switch SBVS to be on or off, a control signal DB for the compensation drive circuit DRB, and setting data SETB that sets the capacitance value of the compensation capacitor CBV.

[0082] Each of the switches SAQ, SAVD, SAVS, SBQ, SBVD, and SBVS is an analog switch, and is, for example, an N-type transistor, a P-type transistor, or a transfer gate in which these are connected in parallel.

[0083] The compensation capacitor CAV is configured with a compensation variable capacitance circuit whose capacitance value is variable. Assume that the number of bits of the setting data SETA is 9. In this case, the compensation variable capacitance circuit includes first to ninth capacitors and first to ninth switches. One end of the first switch is connected to the node NCAV, and the other end is connected to one end of the first capacitor. The other end of the first capacitor is connected to the node NDRA. Similarly, one end of the second to ninth switches is connected to the node NCAV, and the other end is connected to one end of the second to ninth capacitors. The other ends of the second to ninth capacitors are connected to the node NDRA. The capacitance values ​​of the second to ninth capacitors are binary-weighted based on the capacitance value of the first capacitor. The first switch is controlled to be on or off by the first bit SETA[0] of the setting data. Similarly, the second to ninth switches are controlled to be on or off by the second to ninth bits SETA[1] to SETA[8] of the setting data. The compensation capacitor CBV has a similar configuration.

[0084] The compensation drive circuit DRA outputs a first voltage level to the node NDRA when the control signal DA is at a first logic level, and outputs a second voltage level to the node NDRA when the control signal DA is at a second logic level. For example, the first logic level is "0," the second logic level is "1," the first voltage level is the low-potential power supply voltage VSH, and the second voltage level is the high-potential power supply voltage VDH. The compensation drive circuit DRA is composed of, for example, a level shifter that shifts the input logic level to the output voltage level of the compensation drive circuit DRA, and a buffer circuit that buffers the output of the level shifter. The compensation drive circuit DRB has a similar configuration.

[0085] 15 shows an example of the waveform of the control signal output from the processing circuit to the charge compensation circuit in Embodiment 2. The control signal for the switch indicates ON when it is at a high level, and OFF when it is at a low level.

[0086] The signals DA and DB are at a low level, and the compensation drive circuits DRA and DRB output VSH=0V.

[0087] Before drive order 1, the capacitance value of compensation capacitor CAV is set to the maximum value, and switch SAVD is turned on. As a result, the first to ninth capacitors of compensation capacitor CAV are charged with VDH = 15 V. After that, switch SAVD is turned off.

[0088] In drive sequence 1, the capacitance value of compensation capacitor CAV is set by the capacitance setting value SETA at the time of injection, and switch SAQ is turned on. As a result, compensation charge corresponding to the capacitance setting value SETA at the time of injection is injected from compensation capacitor CAV to output node NVQ.

[0089] In drive order 1, the capacitance value of compensation capacitor CBV is set to the maximum value, and switch SBVS is turned on. As a result, the first to ninth capacitors of compensation capacitor CBV are charged with VSH=0 V. Then, switch SBVS is turned off.

[0090] In drive sequence 2, the capacitance value of compensation capacitor CBV is set by the capacitance setting value SETB at the time of discharge, and switch SBQ is turned on. As a result, compensation charge corresponding to the capacitance setting value SETB at the time of discharge is injected from compensation capacitor CBV to output node NVQ.

[0091] In drive sequence 2, the capacitance value of compensation capacitor CAV is set to the maximum value, and switch SAVD is turned on.

[0092] In the subsequent driving orders, the same operation as above is repeated, so that charge compensation is performed by compensation capacitor CAV in odd-numbered driving orders and by compensation capacitor CBV in even-numbered driving orders. Charge is discharged by compensation capacitor CAV in driving order 5, in which case switch SAVS is turned on in driving order 4. Charge is injected by compensation capacitor CBV in driving order 6, in which case switch SBVD is turned on in driving order 5.

[0093] In each of the driving sequences 1, 3, and 5, the compensation capacitor CAV may inject or discharge charges. In each of the driving sequences 2, 4, and 6, the compensation capacitor CBV may inject or discharge charges.

[0094] 16 shows a second detailed configuration example of the processing circuit 42. The processing circuit 42 includes an adder ADC, a multiplier MXC, latch circuits LTC1 and LTC2, a charge calculation circuit DKC, and a signal output circuit SSC. The calculation of the gradation data DQ[10:0] and the calculation of the excess / deficiency gradation data DCC_DQ are the same as those in FIG.

[0095] The latch circuit LTC2 latches the excess / deficiency gradation data DCC_DQ, which is the output data of the multiplier MXC, and outputs it to the charge calculation circuit DKC. The charge calculation circuit DKC calculates capacitance setting data DCCE based on the excess / deficiency gradation data DCC_DQ and the gradation data DQ_GD[10:0]. The signal output circuit SSC outputs a control signal CNT to the charge compensation circuit 90 based on the capacitance setting data DCCE. Specifically, the signal output circuit SSC outputs a switch control signal depending on whether charge is being injected or discharged, and outputs the capacitance setting data DCCE as setting data SETA for the compensation capacitor CAV or setting data SETB for the compensation capacitor CBV.

[0096] A specific calculation example will be shown below. 17, the charge calculation circuit DKC uses grayscale values ​​for calculating the compensation charge. Specifically, the display grayscale values ​​0 to 2048 corresponding to 2.5V to 12.5V are expanded to calculation grayscale values ​​0 to 3072 corresponding to VSH=0V to VDH=15V. That is, 512 is added to the display grayscale values ​​0 to 2048, converting them into calculation grayscale values ​​512 to 2560. Furthermore, the lower limit of the calculation grayscale values ​​is expanded to 0 corresponding to VSH=0V, and the upper limit is expanded to 3072 corresponding to VDH=15V.

[0097] 18 is a table for explaining the calculation formula for the capacitance setting value. The calculation method for the excess / deficiency gradation value DCC_DQ is the same as in the first embodiment.

[0098] When DCC_DQ>0, there is a charge shortage, and DCC_DQ represents the shortage gradation value. At this time, the charge amount calculation circuit DKC calculates the capacitance setting value DCCE at the time of charge injection using the following equation (2). DCCE=DCC_DQ / (3072-(DQ_GD+512))×3072 ···(2)

[0099] When DCC_DQ<0, there is an excess charge, and DCC_DQ represents an excess gradation value. At this time, the charge amount calculation circuit DKC calculates the capacitance setting value DCCE when discharging the charge using the following equation (3). DCCE=-DCC_DQ / (DQ_GD+512)×3072 ···(3)

[0100] In the above equations (2) and (3), 512 is the grayscale value for calculation corresponding to the grayscale value DQ_GD=0, and 3072 is the grayscale value for calculation corresponding to the high-potential power supply voltage VDH.

[0101] 19 shows an example of calculations for drive orders 1 to 4 in the horizontal scanning period. Here, the precharge grayscale value is set to DPRE=512 in the grayscale value for display. The coefficient for calculating the excess / deficiency grayscale value DCC_DQ is set to Coef=27.25, as in the first embodiment.

[0102] In the drive orders 1, 2, 3, and 4, the gradation values ​​DQ_GD=2048, 0, 1024, and 0. In this case, the excess and deficiency gradation values ​​in the drive orders 1, 2, 3, and 4 are DCC_DQ=40.75, -13.75, 13.5, and -13.75. When DCC_DQ>0, DCC_DQ is a deficient gradation value, and when DCC_DQ<, DCC_DQ is an excess gradation value. The capacitance setting value DCCE is calculated using the above formula (2) or (3). The gradation value for capacitive driving is DQ=DQ_GD.

[0103] For example, suppose the capacitance value of the first capacitor of the compensation capacitors CAV and CBV is half the capacitance value of the capacitor C1 of the capacitor circuit 10. When the capacitance setting value DCCE is represented by 9-bit capacitance setting data DCCE[8:0], its LSB DCCE[0] corresponds to 1 / 2 gradation. For example, in drive order 2, the capacitance setting value at the time of charge discharge is DCCE=82.5, so DCCE[8:0]=010100101. By setting the capacitance value of the compensation capacitor CBV using this DCCE[8:0], a compensation charge corresponding to the excess gradation value DCC_DQ=-13.75 is discharged from the output node NVQ.

[0104] In the above embodiment, the charge compensation capacitor circuit 92 includes a first compensation capacitor CAV. The charge compensation circuit 90 includes a first switch SAQ, a second switch SAVD, and a third switch SAVS. One end of the first switch SAQ is connected to the output node NVQ, and the other end is connected to one end of the first compensation capacitor CAV. The second switch SAVD is provided between the high-potential side power supply node NVDH and the other end of the first switch SAQ. The third switch SAVS is provided between the low-potential side power supply node NVSH and the other end of the first switch SAQ.

[0105] According to this embodiment, when the second switch SAVD is turned on, one end of the first compensation capacitor CAV can be charged with the high-potential power supply voltage VDH, when the first switch SAQ is turned on, compensation charge can be injected from one end of the first compensation capacitor CAV to the output node NVQ, when the third switch is turned on, one end of the first compensation capacitor CAV can be charged with the low-potential power supply voltage VSH, and when the first switch SAQ is turned on, compensation charge can be discharged from the output node NVQ to one end of the first compensation capacitor CAV.

[0106] In this embodiment, in a preparation period before the data lines are driven, the first switch SAQ is off, and the second switch SAVD or the third switch SAVS is on. In a compensation period including the period when the data lines are driven, the first switch SAQ is on, and the second switch SAVD and the third switch SAVS are off.

[0107] According to this embodiment, one end of the first compensation capacitor CAV can be charged with the high-potential power supply voltage VDH or the low-potential power supply voltage VSH during the preparation period, and compensation charge can be injected into or discharged from the output node NVQ during the compensation period.

[0108] 15 , taking the compensation capacitor CAV as an example, the preparation period corresponds to the period in which the second switch SAVD or the third switch SAVS is on before the driving order 1 and in the driving orders 2, 4, and 6. The compensation period corresponds to the period in which the first switch SAQ is on in the driving orders 1, 3, and 5.

[0109] In this embodiment, the first compensation capacitor CAV is a compensation variable capacitance circuit whose capacitance is variable. The processing circuit 42 sets the capacitance of the compensation variable capacitance circuit based on the excess or deficiency of the electric charge.

[0110] According to this embodiment, the capacitance value of the compensation variable capacitance circuit is set based on the amount of excess or deficiency charge, and compensation charge corresponding to the amount of excess or deficiency charge is injected from the first compensation capacitor CAV to the output node NVQ or discharged from the output node NVQ to the first compensation capacitor CAV during the compensation period.

[0111] In this embodiment, the charge compensation capacitor circuit 92 also includes a second compensation capacitor CBV. The charge compensation circuit 90 includes a fourth switch SBQ, a fifth switch SBVD, and a sixth switch SBVS. One end of the fourth switch SBQ is connected to the output node NVQ, and the other end is connected to one end of the second compensation capacitor CBV. The fifth switch SBVD is provided between the high-potential side power supply node NVDH and the other end of the fourth switch SBQ. The sixth switch SBVS is provided between the low-potential side power supply node NVSH and the other end of the fourth switch SBQ.

[0112] According to this embodiment, charge compensation can be performed alternately by the first compensation capacitor CAV and the second compensation capacitor CBV. That is, the compensation period for charge compensation by the first compensation capacitor CAV can be used as a preparatory period for charge compensation by the second compensation capacitor CBV, and the preparatory period for charge compensation by the first compensation capacitor CAV can be used as a compensation period for charge compensation by the second compensation capacitor CBV. This makes it easier to accommodate faster driving due to higher pixel counts or higher frame rates.

[0113] 4. Third embodiment In the third embodiment, excess or deficiency of charge is compensated for by adding excess or deficiency grayscale values ​​to the grayscale values ​​of capacitive driving using the capacitor circuit 10 and the capacitor driving circuit 20. This compensation causes the deviation of the capacitive driving grayscale values ​​from the original grayscale values ​​to accumulate, and the excess or deficiency of charge cannot be fully compensated for by the capacitive driving. In response to this, the charge compensation circuit 90 supplies compensation charges to reduce the accumulation of the deviation.

[0114] A detailed configuration example of the driver 100 in the third embodiment is similar to that of the second embodiment shown in Fig. 13. However, the content of the control signal CNT is different.

[0115] 20 shows a second detailed configuration example of the charge compensation circuit. In this configuration example, the compensation capacitors CAV and CBV have fixed capacitance values. The processing circuit 42 outputs control signals AQ, AVD, AVS, DA, BQ, BVD, BVS, and DB as the control signal CNT.

[0116] FIG. 21 shows a first example of the signal waveform of the control signal output from the processing circuit to the charge compensation circuit in the third embodiment. The control signals DA and DB of the compensation drive circuits DRA and DRB and the control signals AVD, AVS, BVD, and BVS of the switches SAVD, SAVS, SBVD, and SBVS are the same as those in FIG. 15 of the second embodiment. In the odd-numbered drive orders, the switch SAQ turns on when charge compensation is performed by the compensation capacitor CAV, and remains off when charge compensation is not performed by the compensation capacitor CAV. FIG. 21 shows an example in which charge compensation is performed in drive orders 1 and 5, but not in drive order 3. In the even-numbered drive orders, the switch SBQ turns on when charge compensation is performed by the compensation capacitor CBV, and remains off when charge compensation is not performed by the compensation capacitor CBV. FIG. 21 shows an example in which charge compensation is performed in drive orders 2 and 6, but not in drive order 4.

[0117] In each of the driving sequences 1, 3, and 5, the compensation capacitor CAV may or may not inject or discharge charges. In each of the driving sequences 2, 4, and 6, the compensation capacitor CBV may or may not inject or discharge charges.

[0118] FIG. 22 shows a second signal waveform example of the control signal output from the processing circuit to the charge compensation circuit in the third embodiment.

[0119] In this waveform example, the compensation drive circuits DRA and DRB drive the other ends of the compensation capacitors CAV and CBV. That is, in drive order 1, the switch SAQ turns on and the control signal DA changes from low to high. This changes the output of the compensation drive circuit DRA from VSH=0V to VDH=15V, driving the other end of the compensation capacitor CAV. In drive order 2, the switch SBQ turns on and the control signal DB changes from high to low. This changes the output of the compensation drive circuit DRB from VDH=15V to VSH=0V, driving the other end of the compensation capacitor CBV.

[0120] By driving the other ends of the compensation capacitors CAV and CBV, the amount of compensation charge can be increased, or the capacitance values ​​of the compensation capacitors CAV and CBV can be reduced while maintaining the amount of compensation charge.

[0121] 23 shows a third detailed configuration example of the processing circuit. The processing circuit 42 includes adders ADB1, ADB2, and ADB3, a multiplier MXB, latch circuits LTB1 and LTB2, a charge calculation circuit DKB, and a signal output circuit SSB. The calculation of the excess / deficiency gradation data DCC_DQ is the same as in FIG. 9.

[0122] The adder ADB2 subtracts the excess / deficiency gradation data DCC_DQ from the charge-compensated accumulated data DCCB output by the charge calculation circuit DKB. The latch circuit LTB2 latches the output data of the adder ADB2 and outputs the latched data to the charge calculation circuit DKB as charge-compensated accumulated data DCCF.

[0123] The charge calculation circuit DKB calculates the compensation charge DCCA, the excess / deficiency gradation data DCCD for capacitive driving, and the accumulated data DCCB after charge compensation based on the accumulated data DCCF before charge compensation and the gradation data DQ_GD[10:0]. A charge deficiency is indicated when the accumulated value DCCF<0, and an excess / deficiency is indicated when the accumulated value DCCF>0. The compensation charge DCCA is the charge injection amount and the charge discharge amount as described in FIG. 22. When -DCCF≧the threshold for the charge injection amount, the charge calculation circuit DKB calculates the charge injection amount using the following equation (4) described later in FIG. 24. When -DCCF<the threshold for the charge injection amount, the charge calculation circuit DKB sets the charge injection amount to 0. When DCCF≧the threshold for the charge discharge amount, the charge calculation circuit DKB calculates the charge discharge amount using the following equation (5) described later in FIG. 24. When DCCF<the threshold for the charge discharge amount, the charge discharge amount is set to 0. The accumulated value before charge compensation is DCCB=DCCF+charge injection amount−charge discharge amount. The excess / deficiency gradation value for capacitive driving is DCCD=-INT(DCCB). INT() is a function that returns the integer value of the argument.

[0124] The signal output circuit SSB outputs a control signal CNT to the charge compensation circuit 90 based on the compensation charge amount DCCA. Specifically, the compensation charge amount DCCA is the charge injection amount and the charge discharge amount. If the charge injection amount is equal to or greater than the threshold for the charge injection amount, the signal output circuit SSB outputs a switch control signal to the charge compensation circuit 90 to instruct charge injection, and if the charge discharge amount is equal to or greater than the threshold for the charge discharge amount, the signal output circuit SSB outputs a switch control signal to instruct charge discharge to the charge compensation circuit 90. The adder ADB3 adds the gradation data DQ_GD[10:0] latched by the latch circuit LTB1 to the excess / deficiency gradation data DCCD from the charge amount calculation circuit DKB, and outputs the result to the capacitor drive circuit 20 as gradation data DQ[10:0].

[0125] A specific calculation example will be shown below. 24 is a table explaining the calculation formulas for the amount of charge injected and the amount of charge discharged. Here, an example is shown in which charge is injected by compensation capacitor CAV and discharged by compensation capacitor CBV. As with FIG. 17 for the second embodiment, grayscale data for charge calculation is used.

[0126] The charge amount calculation circuit DKB calculates the compensation charge DCCA, which is the amount of injected charge, using the following equation (4): The charge amount calculation circuit DKB calculates the compensation charge DCCA, which is the amount of discharged charge, using the following equation (5): DCCA=(3072-(DQ_GD+512))×(312 / 3072) ···(4) DCCA=(DQ_GD+512)×(80 / 3072) ···(5)

[0127] In the above equation (4), 312 in the coefficient (312 / 3072) is the ratio of the capacitance value of the compensation capacitor CAV to the capacitance value of the capacitive-drive capacitor C1. In the above equation (5), 80 in the coefficient (80 / 3072) is the ratio of the capacitance value of the compensation capacitor CBV to the capacitance value of the capacitive-drive capacitor C1. In the above equations (4) and (5), 512 is the gradation value for calculation corresponding to the gradation value DQ_GD=0. 3072 is the gradation value for calculation corresponding to the high-potential power supply voltage VDH.

[0128] 25 shows an example of calculations in drive orders 1 to 4 of the horizontal scanning period. Here, the precharge grayscale value is set to DPRE=512 in the grayscale value for display. The coefficient for calculating the excess / deficiency grayscale value DCC_DQ is set to Coef=27.25, as in the first embodiment.

[0129] The threshold for the amount of charge injection is set to 52, and the threshold for the amount of charge discharge is set to 13.33. For example, the display controller 300 or the like writes these thresholds to the register circuit 48 of the driver 100, and the processing circuit 42 performs calculations using the thresholds read from the register circuit 48. The threshold for the amount of charge injection is set, for example, to a value close to the minimum value of the amount of charge injection in the range of gradation values ​​DQ_GD=0 to 2047. When DQ_GD=2047, the amount of charge injection becomes the minimum value of 52. Here, this minimum value 52 is used as the threshold. The threshold for the amount of charge discharge is set, for example, to a value close to the minimum value of the amount of charge injection in the range of gradation values ​​DQ_GD=0 to 2047. When DQ_GD=0, the amount of charge discharge becomes the minimum value of 13.33. Here, this minimum value 13.33 is used as the threshold.

[0130] In drive order 1, the gradation value is assumed to be DQ_GD=512. In this case, the excess / deficiency gradation value is DCC_DQ=0, and the accumulated value before charge compensation is DCCF=0. Since -DCCF<52, DCCF<13.33, the compensation charge amount DCCA is charge injection amount=0, and charge discharge amount=0. The accumulated value after charge compensation is DCCB=0+0-0=0. The excess / deficiency gradation value for capacitive driving is DCCD=-INT(0)=0, and the gradation value for capacitive driving is DQ=512+0=512.

[0131] In drive order 2, assume that the gradation value DQ_GD = 256. In this case, the excess / deficiency gradation value is DCC_DQ = -7, and the accumulated value before charge compensation is DCCF = 0 - 7 = 7. Since -DCCF < 52 and DCCF < 13.33, the compensation charge amount DCCA is charge injection amount = 0 and charge discharge amount = 0. The accumulated value after charge compensation is DCCB = 7 + 0 - 0 = 7. The excess / deficiency gradation value for capacitive driving is DCCD = -INT(7) = -7, and the gradation value for capacitive driving is DQ = 256 + (-7) = 249.

[0132] In drive order 3, assume that the gradation value DQ_GD = 128. In this case, the excess / deficiency gradation value is DCC_DQ = -10.25, and the cumulative value before charge compensation is DCCF = 7 - (-10.25) = 17.25. Since -DCCF < 52 and DCCF ≥ 13.33, the compensation charge amount DCCA is charge injection amount = 0 and charge discharge amount = 16.67. The charge discharge amount is calculated using equation (5) above. The cumulative value after charge compensation is DCCB = 17.25 + 0 - 16.67 = 0.58. The excess / deficiency gradation value for capacitive driving is -DCCD = INT (0.58) = 0, and the gradation value for capacitive driving is DQ = 128 + 0 = 128.

[0133] In drive order 4, assume that the gradation value DQ_GD = 1024. In this case, the excess / deficiency gradation value is DCC_DQ = 13.5, and the cumulative value before charge compensation is DCCF = 0.58 - 13.5 = -12.92. Since -DCCF < 52 and DCCF < 13.33, the compensation charge amount DCCA is charge injection amount = 0 and charge discharge amount = 0. The cumulative value after charge compensation is DCCB = -12.92 + 0 - 16.67 = -12.92. The excess / deficiency gradation value for capacitive driving is DCCD = -INT(-12.92) = 13, and the gradation value for capacitive driving is DQ = 1024 + 13 = 1037.

[0134] If charge compensation circuit 90 had not discharged charge in drive order 3, the excess / deficiency gradation value for capacitive driving would be -17, due to the cumulative value of 17.25 before charge compensation. This excess / deficiency gradation value represents the cumulative deviation of the capacitive driving gradation value from the original gradation value. In this embodiment, when charge compensation circuit 90 discharges charge, the cumulative value decreases by the amount of discharge, and the cumulative value before charge compensation becomes 0.58. As a result, the excess / deficiency gradation value for capacitive driving becomes 0, and the deviation is reduced. In this way, by repeating compensation for excess / deficiency charge by capacitive driving and charge compensation by charge compensation circuit 90, the charge preservation state of output node NVQ is maintained overall.

[0135] In the above embodiment, a plurality of data lines are driven in sequence. It is assumed that the pth data line among the plurality of data lines is driven, where p is an integer equal to or greater than 1. At this time, the processing circuit 42 calculates a pth excess / deficiency gradation value DCC_DQ that compensates for the excess / deficiency charge amount in the pth data line, and calculates a cumulative value DCCF of the first to p-1th excess / deficiency gradation values ​​DCC_DQ calculated when the first to p-1th data lines are driven and the pth excess / deficiency gradation value DCC_DQ. When the cumulative value DCCF is equal to or greater than a threshold, the processing circuit 42 injects or discharges compensation charge from the charge compensation circuit 90 into or from the output node NVQ.

[0136] According to this embodiment, when the accumulated value DCCF, which indicates the accumulated excess or deficiency of charge, is equal to or greater than a threshold, charge compensation is performed by the charge compensation circuit 90. This makes it possible to compensate for excess or deficiency of charge using a compensation capacitor with a fixed capacitance value.

[0137] 25, p=3. At this time, the processing circuit 42 calculates the excess / deficiency gradation value DCC_DQ=-10.25 in drive order 3, and obtains a cumulative value DCCF=17.25 of the excess / deficiency gradation values ​​DCC_DQ=0, -7 in drive orders 1 and 2 and the excess / deficiency gradation value DCC_DQ=-10.25 in drive order 3. In the example of FIG. 25, the threshold for the amount of charge discharge is 13.33, and DCCF=17.25≧13.33, so the processing circuit 42 causes the charge compensation circuit 90 to inject or discharge compensation charge into or from the output node NVQ.

[0138] Furthermore, in this embodiment, when the accumulation value DCCF is smaller than the threshold value, the processing circuit 42 outputs the gradation data DQ[10:0] corrected based on the accumulation value DCCF to the capacitor driving circuit 20. When the accumulation value DCCF is equal to or greater than the threshold value, the processing circuit 42 subtracts the gradation value corresponding to the compensation charge from the accumulation value DCCF, and outputs the gradation data DQ[10:0] corrected based on the accumulation value DCCB after the subtraction to the capacitor driving circuit 20.

[0139] According to this embodiment, capacitive driving is performed using the gradation data DQ[10:0] corrected based on the accumulated value, thereby compensating for excess or deficiency of charge through capacitive driving. This compensation causes the deviation of the gradation value of the capacitive driving from the original gradation value to accumulate, and the capacitive driving is no longer able to fully compensate for the excess or deficiency of charge. In response to this, the charge compensation circuit 90 supplies compensation charge, thereby reducing the accumulation of the deviation. In this way, by repeating the compensation for excess or deficiency of charge through capacitive driving and the charge compensation by the charge compensation circuit 90, the charge preservation state of the output node NVQ is maintained as a whole.

[0140] 25, in drive order 2, the accumulated value DCCF=7 is smaller than the threshold value 13.33. The processing circuit 42 outputs the gradation data DQ[10:0] of 256-7=249, corrected based on the accumulated value DCCF=7, to the capacitor drive circuit 20. In drive order 3, the accumulated value DCCF=17.25 is greater than or equal to the threshold value 13.33. The processing circuit 42 subtracts the gradation value 16.67, which corresponds to the compensation charge, from the accumulated value DCCF=17.25, and outputs the gradation data DQ[10:0] of 128-0=128, corrected based on the accumulated value DCCB=0.58 after the subtraction, to the capacitor drive circuit 20.

[0141] 5. Electronic equipment 26 shows an example of the configuration of an electronic device including a driver according to this embodiment. Various electronic devices incorporating a display device can be envisioned as examples of the electronic device according to this embodiment. For example, the electronic device may be a projector, a television, an information processing device, a portable information terminal, a car navigation system, or a portable game terminal.

[0142] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0143] The electro-optical panel 200 is, for example, a matrix-type liquid crystal display panel. Alternatively, the electro-optical panel 200 may be an EL display panel using self-luminous elements. EL stands for Electro-Luminescence. The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it may be composed of buttons, a mouse, a keyboard, or a touch panel attached to the electro-optical panel 200. The data interface unit 340 is an interface unit that inputs and outputs image data or control data. For example, it may be a wired communication interface such as USB or a wireless communication interface such as wireless LAN. The memory unit 320 stores image data input from the data interface unit 340. Alternatively, the memory unit 320 functions as a working memory for the processing device 310 or the display controller 300. The processing device 310 controls various components of the electronic device and processes various data. The processing device 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 controls the driver 100. For example, the display controller 300 converts image data transferred from the data interface unit 340 or the storage unit 320 into a format acceptable to the driver 100, and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on the image data transferred from the display controller 300.

[0144] The driver of the present embodiment described above includes a data voltage output terminal, a capacitor driving circuit, a capacitor circuit, a processing circuit, and a charge compensation circuit. The data voltage output terminal is electrically connected to the data lines via the data line switches of the electro-optical panel. The capacitor driving circuit outputs first to n-th capacitor driving voltages corresponding to grayscale data to the first to n-th capacitor driving nodes, where n is an integer equal to or greater than 2. The capacitor circuit has first to n-th capacitors provided between an output node, which is a node of the data voltage output terminal, and the first to n-th capacitor driving nodes. The processing circuit calculates the amount of excess or deficiency charge, which is the amount of deficiency or excess charge at the output node when the data line switch is turned on. The charge compensation circuit has a charge compensation capacitor circuit and uses the charge compensation capacitor circuit to inject or discharge compensation charge into or from the output node based on the amount of excess or deficiency charge calculated by the processing circuit.

[0145] According to this embodiment, the charge compensation circuit can compensate for excess or deficiency of charge by charge redistribution using a charge compensation capacitor circuit. This allows the voltage on the data line to approach the data voltage more quickly than when an amplifier circuit is used to compensate for excess or deficiency of charge. Alternatively, even when an amplifier circuit is further used, the amount of charge that the amplifier circuit must compensate for can be reduced.

[0146] In this embodiment, the voltage of the data line when the data line switch is off may be a precharge voltage, and the processing circuit may calculate the excess or deficiency of charge caused by the difference between the precharge voltage and the target voltage corresponding to the grayscale data when the data line switch is turned on from off.

[0147] According to this embodiment, the excess or deficiency of charge caused by the difference between the precharge voltage and the target voltage corresponding to the grayscale data is calculated, so that the output node can be brought closer to a charge-storing state, thereby bringing the voltage of the data line closer to the target voltage.

[0148] In this embodiment, the grayscale value corresponding to the target voltage may be DQ_GD, the grayscale value corresponding to the precharge voltage may be DPRE, a coefficient indicating the ratio of the excess or deficiency charge amount to the difference between the target voltage and the precharge voltage may be Coef, and an excess or deficiency grayscale value that compensates for the excess or deficiency charge amount may be DCC_DQ. In this case, the processing circuit may calculate the excess or deficiency grayscale value by DCC_DQ=(DQ_GD-DPRE)×Coef. The charge compensation circuit may inject or discharge compensation charge into or from the output node based on the excess or deficiency grayscale value.

[0149] According to this embodiment, the above calculation results in an excess / deficiency gradation value, which is a gradation value corresponding to the excess / deficiency of charge. By using the excess / deficiency gradation value, the excess / deficiency of charge can be handled based on the charge amount corresponding to one gradation. For example, the capacitance value of the capacitor in the charge compensation capacitor circuit may be set to, for example, twice or half the capacitance value of the first capacitor in the capacitor circuit. This allows the capacitor to compensate for the excess / deficiency of charge corresponding to two gradations or one-half gradation.

[0150] In this embodiment, the charge compensation capacitor circuit may include first to mth compensation capacitors, one end of which is connected to the output node, and first to mth compensation drive circuits, each of which outputs first to mth compensation signals based on the excess or deficiency of charge to the other end of the first to mth compensation capacitors.

[0151] According to this embodiment, the other ends of the first to mth compensation capacitors are driven by the first to mth compensation signals based on the excess or deficiency of the electric charge, and thus the compensation charges based on the excess or deficiency of the electric charge are injected into or discharged from the first to mth compensation capacitors to the output node.

[0152] In this embodiment, the processing circuit may output a setting value for the charge compensation circuit based on the accumulated value of the excess or deficiency of charge for each data line. The first to mth compensation drive circuits may output first to mth compensation signals corresponding to the setting value. The first to mth compensation capacitors may be driven by the first to mth compensation signals to inject or discharge compensation charges corresponding to the excess or deficiency of charge into or from the output node.

[0153] By performing charge compensation when a certain data line is driven, the output node is maintained in a charge storage state, and further charge compensation is performed when the next data line is driven based on that charge state. Therefore, charge compensation is cumulative. In this embodiment, the setting value of the charge compensation circuit is output based on the cumulative value of the excess or deficiency of charge for each data line, so charge compensation is cumulative.

[0154] In this embodiment, the charge compensation capacitor circuit may include a first compensation capacitor. The charge compensation circuit may include first to third switches. One end of the first switch may be connected to the output node and the other end of the first compensation capacitor. The second switch may be provided between the high potential side power supply node and the other end of the first switch. The third switch may be provided between the low potential side power supply node and the other end of the first switch.

[0155] According to this embodiment, when the second switch is turned on, one end of the first compensation capacitor CAV can be charged with the high-potential power supply voltage, when the first switch is turned on, compensation charge can be injected from one end of the first compensation capacitor to the output node, when the third switch is turned on, one end of the first compensation capacitor can be charged with the low-potential power supply voltage, and when the first switch is turned on, compensation charge can be discharged from the output node to one end of the first compensation capacitor.

[0156] In this embodiment, the first switch may be off and the second switch or the third switch may be on during a preparation period before the data line is driven. In a compensation period including a period during which the data line is driven, the first switch may be on and the second switch and the third switch may be off.

[0157] According to this embodiment, one end of the first compensation capacitor can be charged with the high-potential power supply voltage or the low-potential power supply voltage during the preparation period, and compensation charges can be injected into or discharged from the output node during the compensation period.

[0158] In this embodiment, the first compensation capacitor may be a compensation variable capacitance circuit whose capacitance is variable, and the processing circuit may set the capacitance of the compensation variable capacitance circuit based on the excess or deficiency of the charge.

[0159] According to this embodiment, the capacitance value of the compensation variable capacitance circuit is set based on the amount of excess or deficiency charge, and compensation charge corresponding to the amount of excess or deficiency charge is injected from the first compensation capacitor to the output node or discharged from the output node to the first compensation capacitor during the compensation period.

[0160] Furthermore, in this embodiment, multiple data lines may be driven in sequence. It is assumed that the pth data line among the multiple data lines is driven, where p is an integer equal to or greater than 1. In this case, the processing circuit may calculate a pth excess / deficiency gradation value that compensates for the excess / deficiency charge amount in the pth data line, and may obtain an accumulated value of the 1st to (p-1th)th excess / deficiency gradation values ​​and the pth excess / deficiency gradation value calculated when the 1st to (p-1th)th data lines are driven. When the accumulated value is equal to or greater than a threshold, the processing circuit may cause the charge compensation circuit to inject or discharge compensation charge into or from the output node.

[0161] According to this embodiment, when the accumulated value indicating the accumulated excess or deficiency of charge is equal to or greater than a threshold, charge compensation is performed by the charge compensation circuit, thereby making it possible to compensate for excess or deficiency of charge using a compensation capacitor with a fixed capacitance.

[0162] In this embodiment, when the accumulated value is smaller than a threshold value, the processing circuit may output gradation data corrected based on the accumulated value to the capacitor driving circuit.When the accumulated value is equal to or greater than the threshold value, the processing circuit may subtract a gradation value corresponding to the compensation charge from the accumulated value, and output gradation data corrected based on the accumulated value after subtraction to the capacitor driving circuit.

[0163] According to this embodiment, capacitive driving is performed using gradation data corrected based on the accumulated value, thereby compensating for excess or deficiency of charge through capacitive driving. This compensation causes the deviation of the capacitive driving gradation value from the original gradation value to accumulate, and the capacitive driving is no longer able to fully compensate for the excess or deficiency of charge. In response to this, the charge compensation circuit supplies compensation charge, thereby reducing the accumulation of the deviation.

[0164] In this embodiment, the charge compensation capacitor circuit may include a second compensation capacitor. The charge compensation circuit may include fourth to sixth switches. One end of the fourth switch may be connected to the output node and the other end of the fourth switch may be connected to one end of the second compensation capacitor. The fifth switch may be provided between the high potential side power supply node and the other end of the fourth switch. The sixth switch may be provided between the low potential side power supply node and the other end of the fourth switch.

[0165] According to this embodiment, charge compensation can be performed alternately using the first compensation capacitor and the second compensation capacitor. That is, the compensation period for charge compensation by the first compensation capacitor can be used as a preparatory period for charge compensation by the second compensation capacitor, and the preparatory period for charge compensation by the first compensation capacitor can be used as a compensation period for charge compensation by the second compensation capacitor. This makes it easier to accommodate faster driving due to higher pixel counts or higher frame rates.

[0166] The electro-optical device of this embodiment includes any one of the drivers described above and an electro-optical panel.

[0167] The electronic device of this embodiment includes any one of the drivers described above.

[0168] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the control circuit, data line driving circuit, driver, electro-optical panel, electro-optical device, electronic equipment, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0169] 10...capacitor circuit, 20...capacitor driving circuit, 30...variable capacitance circuit, 40...control circuit, 42...processing circuit, 44...interface circuit, 48...register circuit, 50...detection circuit, 90...charge compensation circuit, 92...charge compensation capacitor circuit, 100...driver, 110...data line driving circuit, 200...electro-optical panel, 300...display controller, 310...processing device, 320...memory unit, 330...user interface unit, 340...data interface unit, 400...electro-optical device, 500...electronic device, C1 to C11...capacitor, CAV, CBV...compensation capacitor, CBV...compensation capacitor, CC1 to CC5...compensation capacitor, DL1 ~DL8...signal supply line, DQ...grayscale data, DQ_GD...grayscale data, DR1~DR11...drive circuit, DRA, DRB...compensation drive circuit, DRC1~DRC5...compensation drive circuit, NDR1~NDR11...capacitor drive node, NVDH...high-potential power supply node, NVQ...output node, NVSH...low-potential power supply node, SAQ...first switch, SAVD...second switch, SAVS...third switch, SBQ...fourth switch, SBVD...fifth switch, SBVS...sixth switch, SETA...,SETB...capacitance setting value, SL1~SL1280...data line, TVQ...data voltage output terminal, VDH...high-potential power supply voltage, VPR...precharge voltage, VSH...low-potential power supply voltage

Claims

1. a data voltage output terminal electrically connected to the data line via the data line switch of the electro-optical panel; a capacitor driving circuit that outputs first to n-th capacitor driving voltages (n is an integer of 2 or more) corresponding to the grayscale data to first to n-th capacitor driving nodes; a capacitor circuit having first to n-th capacitors provided between an output node which is a node of the data voltage output terminal and the first to n-th capacitor driving nodes; a processing circuit for calculating an excess or deficiency of electric charge, which is an amount of electric charge deficiency or an amount of electric charge surplus or deficiency at the output node when the data line switch is turned on; a charge compensation circuit including a charge compensation capacitor circuit, which uses the charge compensation capacitor circuit to inject or discharge compensation charge into or from the output node based on the excess or deficiency of charge calculated by the processing circuit; A driver comprising:

2. 2. The driver according to claim 1, When the voltage of the data line when the data line switch is off is a precharge voltage, The processing circuitry A driver that calculates the excess or deficiency of electric charge caused by the difference between the precharge voltage and a target voltage corresponding to the grayscale data when the data line switch is turned on from off.

3. 3. The driver according to claim 2, When the gradation value corresponding to the target voltage is DQ_GD, the gradation value corresponding to the precharge voltage is DPRE, a coefficient indicating the ratio of the excess or deficiency charge amount to the difference between the target voltage and the precharge voltage is Coef, and an excess or deficiency gradation value compensating for the excess or deficiency charge amount is DCC_DQ, The processing circuitry The excess or deficiency gradation value is calculated by DCC_DQ=(DQ_GD-DPRE)×Coef, The charge compensation circuit comprises: A driver that injects or discharges the compensation charge into or from the output node based on the excess or deficiency gray level.

4. 4. The driver according to claim 1, The charge compensation capacitor circuit comprises: first to m-th compensation capacitors (m is an integer of 2 or more) having one end connected to the output node; The charge compensation circuit comprises: a driver including first to mth compensation drive circuits that output first to mth compensation signals based on the excess or deficiency of the electric charge to the other ends of the first to mth compensation capacitors;

5. 5. The driver according to claim 4, The processing circuitry outputting a setting value of the charge compensation circuit based on an accumulated value of the excess or deficiency of the charge for each data line; The first to mth compensation driving circuits are outputting the first to mth compensation signals corresponding to the set values; The first to mth compensation capacitors are: A driver characterized in that, when driven by the first to mth compensation signals, the driver injects or discharges the compensation charge corresponding to the excess or deficiency of the charge into or from the output node.

6. 4. The driver according to claim 1, The charge compensation capacitor circuit comprises: a first compensation capacitor; The charge compensation circuit comprises: a first switch having one end connected to the output node and the other end connected to one end of the first compensation capacitor; a second switch provided between a high potential side power supply node and the other end of the first switch; a third switch provided between a low potential side power supply node and the other end of the first switch; A driver comprising:

7. 7. The driver according to claim 6, In a preparation period before the data line is driven, the first switch is off, and the second switch or the third switch is on, The driver is characterized in that, during a compensation period including a period during which the data line is driven, the first switch is on, and the second switch and the third switch are off.

8. 8. The driver according to claim 6 or 7, The first compensation capacitor is a compensating variable capacitance circuit whose capacitance value is variable, The processing circuitry A driver that sets the capacitance value of the compensating variable capacitance circuit based on the amount of excess or deficiency of electric charge.

9. 8. The driver according to claim 6 or 7, The processing circuitry When a data line of a first driving order among the plurality of data lines to be driven in sequence is driven, a first excess / deficiency gradation value that compensates for the excess / deficiency charge amount of the data line of the first driving order is calculated, and the first excess / deficiency gradation value is set as a cumulative value; When a p-th data line (p is an integer of 2 or more) of the plurality of data lines is driven, a p-th excess / deficiency gradation value that compensates for the excess / deficiency charge amount in the p-th data line is calculated, and the accumulated value obtained by accumulating the first excess / deficiency gradation value to the p-th excess / deficiency gradation value is obtained; When the accumulated value is equal to or greater than a threshold, the driver causes the charge compensation circuit to inject or drain the compensation charge into or from the output node.

10. 10. The driver according to claim 9, The processing circuitry When the cumulative value is smaller than a threshold value, the grayscale data corrected based on the cumulative value is output to the capacitor driving circuit; When the accumulated value is equal to or greater than a threshold value, a gradation value corresponding to the compensation charge is subtracted from the accumulated value, and the gradation data corrected based on the accumulated value after subtraction is output to the capacitor driving circuit.

11. 11. A driver according to any one of claims 6 to 10, The charge compensation capacitor circuit comprises: a second compensation capacitor; The charge compensation circuit comprises: a fourth switch having one end connected to the output node and the other end connected to one end of the second compensation capacitor; a fifth switch provided between the high potential side power supply node and the other end of the fourth switch; a sixth switch provided between the low potential side power supply node and the other end of the fourth switch; A driver comprising:

12. A driver according to any one of claims 1 to 11; the electro-optical panel; An electro-optical device comprising:

13. 12. An electronic device comprising a driver according to any one of claims 1 to 11.

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