Electronic devices

Abstract

To provide a novel electronic device.SOLUTION: The electronic device has a housing and a display device. The display device has a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer has a driving circuit and a calculation circuit. The second layer has a pixel circuit and a cell array. The third layer has a light-receiving device and a light-emitting device. The pixel circuit has a function of controlling the light emission from the light-emitting device. The driving circuit has a function of controlling the pixel circuit. The calculation circuit has a function of performing calculation processing based on first data according to the current output from the light-receiving device and second data according to the potential held by the cell array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One aspect of the present invention relates to an electronic device. 1. Field of the Invention One aspect of the present invention relates to a wearable electronic device including a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In recent years, head-mounted display (HMD) type electronic devices suitable for applications such as virtual reality (VR) and augmented reality (AR) have become widespread. HMDs can display images in a 360-degree area around the observer in response to the user's head movements, line of sight, or operations, allowing the user to experience a high level of immersion and realism.

[0004] The display device provided in the HMD is configured to be viewed by magnifying it via optical components or the like. In this case, there is a risk that the inclusion of optical components will increase the size of the housing, or that the user will be more likely to see the pixels and perceive them as grainy, so there is a demand for high-definition and / or miniaturization of the display device. For example, Patent Document 1 discloses an HMD with fine pixels achieved by using transistors capable of high-speed operation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-2856 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to provide a more advanced user experience, it is desirable for an HMD-type electronic device to have a configuration that incorporates not only a display function but also a sensing function. However, when multiple sensors, such as image sensors or temperature sensors, are attached to the housing, the number of components increases, which can lead to an increase in the size of the HMD-type electronic device and a significant decrease in wearability.

[0007] An object of one embodiment of the present invention is to provide a miniaturized and lightweight electronic device, or to provide an electronic device with excellent wearability, or to provide a novel electronic device.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is an electronic device having a housing and a display device, the display device having a first layer, a second layer, and a third layer, the first layer, the second layer, and the third layer being provided on different layers, the first layer having a driver circuit and an arithmetic circuit, the second layer having a pixel circuit and a cell array, the third layer having a light-receiving device and a light-emitting device, the pixel circuit having a function of controlling the light emission of the light-emitting device, the driver circuit having a function of controlling the pixel circuit, and the arithmetic circuit having a function of performing arithmetic processing based on first data corresponding to a current output by the light-receiving device and second data corresponding to a potential held in the cell array.

[0010] In one embodiment of the present invention, the electronic device preferably includes a first transistor having a semiconductor layer including silicon in a channel formation region, and a second transistor having a semiconductor layer including metal oxide in a channel formation region.

[0011] In one embodiment of the present invention, the metal oxide is preferably an electronic device containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0012] In one embodiment of the present invention, the electronic device is preferably one in which the light-receiving device has an organic light-emitting diode and the light-emitting device is an organic EL device.

[0013] In one embodiment of the present invention, the separation of the light-emitting device and the light-receiving device is performed by a photolithographic method, and the electronic device is preferred.

[0014] In one aspect of the present invention, the electronic device is preferably one in which the housing has a function of positioning the display device in a position where it can image the user's eye, and the light-receiving device has a function of imaging the user's eye and / or the area around the eye.

[0015] In one aspect of the present invention, the electronic device is preferably such that the light-emitting device is provided in a display section of the display device, and the light-receiving devices are arranged on both ends of the display section.

[0016] In one aspect of the present invention, the electronic device preferably has a housing including a mounting portion and a pair of lenses.

[0017] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0018] According to one embodiment of the present invention, it is possible to provide a miniaturized and lightweight electronic device, an electronic device with excellent wearability, or a novel electronic device.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0020] [Figure 1] 1A to 1C are diagrams illustrating a configuration example of a display device and a configuration example of an electronic device. [Figure 2] 2A to 2E are diagrams illustrating examples of the configuration of a display device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a display device. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a display device. [Figure 5] 5(A) and 5(B) are diagrams illustrating an example of the configuration of a display device. [Figure 6] 6A and 6B are diagrams illustrating an example of the configuration of an electronic device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a display device. [Figure 8] 8(A) and (B) are diagrams illustrating an example of the configuration of a neural network. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a display device. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a display device. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a display device. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a display device. [Figure 13] 13(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 14] 14A to 14D are diagrams illustrating examples of the configuration of a display device. [Figure 15] 15A to 15D are diagrams illustrating configuration examples of display devices. [Figure 16] 16(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 17] 17A to 17D are diagrams illustrating configuration examples of display devices. [Figure 18] 18A to 18D are diagrams illustrating configuration examples of display devices. [Figure 19] 19(A) and (B) are diagrams illustrating an example of the configuration of a display device. [Figure 20] 20A to 20G are diagrams illustrating examples of the configuration of a display device. [Figure 21] FIG. 21 is a diagram illustrating an example of the configuration of a display device. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0023] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when a voltage V between the gate and the source of an n-channel transistor is applied. gs is the threshold voltage V th (For p-channel transistors, V thThis refers to a state of being (higher than)

[0024] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including an oxide or an oxide semiconductor.

[0025] (Embodiment 1) In one embodiment of the present invention, an electronic device according to one embodiment of the present invention will be described. The electronic device according to one embodiment of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0026] <Example of electronic device configuration> FIG. 1(A) is a perspective view of a goggle-type electronic device 100 as an example of a wearable electronic device. In the electronic device 100 shown in FIG. 1(A), a pair of display devices 10_L and 10_R are provided in a housing 101. FIG. 1(A) also shows the eyes 102 (eyeballs) of a user when wearing the electronic device 100. As shown in FIG. 1(A), the pair of display devices 10_L and 10_R are arranged, for example, at positions overlapping the eyes 102. The housing 101 may be provided with an acceleration sensor such as a gyro sensor, which can detect the orientation of the user's head and display an image according to that orientation.

[0027] In this specification, for example, when describing matters common to the display devices 10_L and 10_R, or when there is no need to distinguish between them, the display device may simply be referred to as "display device 10."

[0028] FIG. 1B is a schematic perspective view of a display device 10 that can be applied to the display devices 10_L and 10_R shown in FIG. 1A.

[0029] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 and a light receiving unit 14 provided between the substrate 11 and the substrate 12.

[0030] The display unit 13 is an area that displays an image in the display device 10. The display unit 13 is provided with pixels, each of which is made up of a pixel circuit and a light-emitting element connected to the pixel circuit. The display unit 13 is provided with a light-emitting element 61, the light intensity of which is controlled by the pixel circuit.

[0031] The light receiving section 14 is an area that captures an image of the periphery of the display device 10. The signals generated by the light receiving section 14 can be processed in an area where an arithmetic processing section made up of an arithmetic circuit and a cell array is provided. The light receiving section 14 is provided with a light receiving element 62 that outputs a current (photocurrent) according to the intensity of light. The light receiving element 62 is an element that converts light energy into electrical energy, and is sometimes called a photoelectric conversion element.

[0032] In this specification and the like, the term “element” may be replaced with “device” in some cases. For example, a display element, a light-emitting element, and a liquid crystal element may be replaced with a display device, a light-emitting device, and a liquid crystal device, for example.

[0033] Display device 10 receives various signals and power supply potentials from the outside via terminal unit 15, and is capable of displaying images in display unit 13 and capturing images in light-receiving unit 14. A plurality of layers are provided between substrate 11 and substrate 12, and each layer is provided with transistors for circuit operation, light-receiving elements 62 that output signals in response to received light, or light-emitting elements 61 that emit light. The layer on which the transistors are provided is provided with pixel circuits that control the light emission of the light-emitting elements 61, drive circuits that control the pixel circuits, arithmetic circuits that process signals generated by light-receiving elements 62, and cell arrays in which transistors are provided for performing arithmetic in the arithmetic circuits.

[0034] 1(C) is a schematic diagram illustrating a case where a display device 10 including a display unit 13 and a light receiving unit 14 is provided in a position close to a user's eye 102. In FIG. 1(C), the display unit 13 and the light receiving unit 14 are arranged such that the display unit 13 is arranged between the light receiving units 14.

[0035] The user's eye 102 can visually recognize an image by light 13A emitted from the light emitting element 61 in the display unit 13. The light 13A may include light such as infrared light in addition to visible light.

[0036] Furthermore, reflected light 14A from the user's eye 102 and / or its periphery is converted into an electrical signal by the light receiving element 62 in the light receiving unit 14. The information acquired by the light receiving unit 14 may be an image of the eyeball (or the state of the pupil) for gaze detection, or an image of movement around the eyeball (for example, the eyelid, between the eyebrows, inner corner of the eye, outer corner of the eye, etc.).

[0037] <Example of display and light receiving unit layout> 2A to 2E are schematic diagrams for explaining examples of the arrangement of the display unit 13 and the light receiving unit 14 shown in FIG. 1B and FIG. 1C.

[0038] In the example shown in FIG. 2(A), a configuration is illustrated in which the area of ​​the display unit 13 and the area of ​​the light receiving unit 14 are located at different positions. In FIG. 2(A), the light receiving units 14 are arranged in a line at both ends of the display unit 13. If an image of the eyelid movement up and down, such as blinking, is to be captured, it can be detected by the line-shaped light receiving units 14. By detecting the blinking of the eyelids in this manner, an inference operation according to the presence or absence of blinking can be performed in the arithmetic circuit connected to the light receiving units 14. Note that the light receiving units 14 that can be arranged in a line may also be arranged in a configuration in which multiple light receiving units 14 are arranged between the display units 13, as shown in FIG. 2(B).

[0039] 2(C) shows an example in which the light receiving units 14 are arranged so as to surround the periphery of the display unit 13. In FIG. 2(C), the light receiving units 14 are arranged in a ring shape. In such a ring-shaped arrangement, it is possible to detect the movement of the eyeball, for example, the eyelid, between the eyebrows, the inner corner of the eye, and the outer corner of the eye, and therefore it is possible to perform an inference operation of the gaze direction in an arithmetic circuit connected to the light receiving units 14 without capturing an image of the eyeball movement. Note that the light receiving units 14 that can be arranged in a ring shape are preferably arranged around the display unit 13, which is larger than the size of the eye 102, as shown in FIG. 2(D). In this case, the panel size L of the display device 10 is D The diagonal dimension of the display device 10 is set to 0.1 inches or more and 5 inches or less, preferably 0.5 inches or more and 3 inches or less, further preferably 1 inch or more and 2 inches or less, more preferably 1.3 inches or more and 1.7 inches or less, and even more preferably 1.5 inches or more and 1.6 inches or less, thereby enabling a configuration in which a display unit 13 according to the size of the eye 102 and a light receiving unit 14 according to the size of the eye 102 are provided. With this configuration, when the display device 10 is brought close to the user's eye 102, information about the user's eye 102 and its surroundings can be obtained by the light receiving unit 14, and the field of view of the image displayed on the display unit 13 can be increased.

[0040] 2A to 2D, the display area 13 and the light receiving area 14 are configured to be in different positions. That is, the light emitting element 61 and the light receiving element 62 are configured to be arranged in different places. By using this configuration, the layout densities of the light emitting element 61 and the light receiving element 62 can be made different.

[0041] Furthermore, the light-emitting elements 61 in the display unit 13 may be configured to correspond to the light-receiving elements 62 in the light-receiving unit 14. For example, as shown in FIG. 2(E), the display unit 13 and the light-receiving unit 14 may be configured to be in the same position. In the case of FIG. 2(E), for example, one pixel may be provided with light-emitting elements 61R, 61G, and 61B corresponding to each of the RGB colors, and a light-receiving element 62. With this configuration, the areas of the display unit 13 and the light-receiving unit 14 can be increased. The density of the light-emitting elements 61 and the light-receiving elements 62 can be made uniform.

[0042] <Example of display device configuration> The configuration of the display device 10 applicable to the display devices 10_L and 10_R shown in FIGS. 1(A) and 1(B) will be described with reference to FIGS. 3(A) and 3(B) to 5. FIG.

[0043] FIG. 3(A) is a perspective view that schematically shows the configuration of each layer provided between the substrate 11 and the substrate 12 in the display device 10 shown in FIG. 1(B).

[0044] A layer 20 is provided on the substrate 11. For example, the layer 20 includes a driver circuit 30 and an arithmetic circuit 40. The layer 20 includes a transistor 21 (also referred to as a Si transistor) having silicon in a channel formation region 22. For example, the substrate 11 is a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate.

[0045] The transistor 21 can be, for example, a transistor having single crystal silicon in a channel formation region. In particular, when a transistor having single crystal silicon in a channel formation region is used as the transistor provided in the layer 20, the on-state current of the transistor can be increased. This is preferable because the circuit included in the layer 20 can be driven at high speed. Furthermore, since a Si transistor can be formed by microfabrication to have a channel length of 3 nm to 10 nm, it is possible to provide an accelerator such as a CPU or GPU, an application processor, or the like, in addition to a dedicated arithmetic circuit 40 such as an artificial neural network (hereinafter sometimes referred to as a neural network) and / or a driver circuit 30.

[0046] The driving circuit 30 includes, for example, a gate driver circuit, a source driver circuit, etc. The gate driver circuit, the source driver circuit, etc. can be arranged to overlap the display unit 13 and / or the light receiving unit 14. Therefore, compared to when the driving circuit 30 and the display unit 13 are arranged side by side, the width of the non-display area (also called a frame) existing on the periphery of the display unit 13 of the display device 10 can be made extremely narrow, thereby realizing a compact display device 10. Furthermore, when the driving circuit 30 is arranged on the periphery of the display unit 13 of the display device 10, the gate driver circuit and the source driver circuit are arranged together on the periphery, but the driving circuit 30 can be divided into multiple parts and arranged in the area overlapping with the display unit 13.

[0047] The arithmetic circuit 40 is a circuit having the function of executing product-sum calculations in an artificial neural network. For example, it is a circuit having the function of performing inference processing based on a hierarchical neural network such as a deep neural network (DNN) or a convolutional neural network (CNN), and a detailed configuration will be described in detail in the second embodiment. The arithmetic circuit 40 is capable of performing product-sum calculations using minute currents corresponding to the voltages of analog values ​​in the cell array CA described below, and therefore can perform calculations using minute currents flowing through the light-receiving elements 62 as input data. This is effective in reducing the circuit area, reducing power consumption, and improving calculation efficiency.

[0048] A layer 50 is provided on the layer 20. The layer 50 includes a pixel circuit portion 51P including a plurality of pixel circuits 51 and a cell array CA including a plurality of cells IM. The layer 50 includes a transistor 52 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. The layer 50 can be stacked on the layer 20. Alternatively, the layer 50 can be formed on a separate substrate and then bonded to the separate substrate.

[0049] The OS transistor 52 preferably has a channel formation region formed of an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. Such an OS transistor has a very low off-state current. Therefore, it is preferable to use an OS transistor, particularly as a transistor provided in the pixel circuit 51 and the cell IM, because analog data written to the pixel circuit 51 and the cell IM can be retained for a long period of time.

[0050] A layer 60 is provided on the layer 50. A substrate 12 is provided on the layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. The layer 60 has a display section 13 in which a plurality of light-emitting elements 61 are provided, and a light-receiving section 14 in which a plurality of light-receiving elements 62 are provided. The layer 60 can be configured to be laminated on the layer 50. The light-emitting element 61 can be, for example, an organic electroluminescence element (also referred to as an organic EL element). However, the light-emitting element 61 is not limited thereto, and an inorganic EL element made of an inorganic material can also be used. Note that "organic EL element" and "inorganic EL element" may be collectively referred to as "EL element." The light-emitting element 61 may contain an inorganic compound such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0051] As shown in FIG. 3A, the display device 10 of one embodiment of the present invention can have a stacked structure including a light-emitting element 61, a pixel circuit 51, and a driver circuit 30, thereby achieving an extremely high pixel aperture ratio (effective display area ratio). Furthermore, the pixel circuits 51 can be arranged at extremely high density, thereby achieving extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, and therefore, pixels are not visible even when the display portion is enlarged by the lens, providing a highly immersive display experience.

[0052] As shown in FIG. 3A, the display device 10 of one embodiment of the present invention can have a stacked structure including a light-receiving element 62, a cell array CA, and an arithmetic circuit 40. This allows for efficient arithmetic processing using a small current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have a structure in which the light-receiving portion 14 is located close to the display portion 13. This allows the user to view an image with their eye and capture images of the user's eye and / or its surroundings. Furthermore, the cell IM of the cell array CA can retain analog data written in response to a small current for a long time. Furthermore, the arithmetic circuit 40, which performs product-sum calculations using a small current, can perform arithmetic processing with high arithmetic efficiency.

[0053] 3(B) shows a block diagram of each component of the layer 20, layer 50, and layer 60 in FIG. 3(A). The driving circuit 30 in the layer 20 outputs signals GS and DS (for example, GS is a signal for driving a gate line, and DS is a signal corresponding to image data) for controlling the pixel circuit section 51P in the layer 50. The pixel circuit section 51P in the layer 50 supplies a current I corresponding to image data to a light emitting element 61 (not shown) in the display section 13 in the layer 60. EL The light emitting element 61 (not shown) in the display unit 13 on the layer 60 outputs a current I ELThe light is emitted in accordance with the image, and the user can visually recognize the image.

[0054] In the block diagram shown in FIG. 3B, the light receiving element 62 (not shown) in the light receiving unit 14 in the layer 60 captures an image of the user's eye and / or the area around the eye, and thereby generates a current I PS It outputs the current I PS is output to the cell array CA in the layer 50 and the arithmetic circuit 40 in the layer 20. The cell array CA in the layer 50 receives the current I PS , and a signal D corresponding to a product-sum operation in response to a control signal from the arithmetic circuit 40 in the layer 20. MAC to the arithmetic circuit 40 in the layer 20. The arithmetic circuit 40 in the layer 20 can perform inference processing based on a neural network.

[0055] The layer 50 provided on the layer 20 can have a structure of two or more layers. For example, as shown in FIG. 4A, layers 50_1 and 50_2 each having a transistor 52 that is an OS transistor can be provided. In FIG. 4A, a pixel circuit portion 51P having a pixel circuit 51 is provided in the layer 50_1, and a cell array CA having a cell IM is provided in the layer 50_2. This configuration can increase the area in which the pixel circuit 51 and the cell IM can be provided.

[0056] 4(B) shows a block diagram of each component of the layer 20, the layer 50_1, the layer 50_2, and the layer 60 in FIG. 4(A), similar to FIG. 3(B). As shown in FIG. 4(B), the driving circuit 30 in the layer 20 and the pixel circuit section 51P in the layer 50_1 are electrically connected via the layer 50_2. Incidentally, it is preferable to provide layers for providing wiring between the layer 20 and the layer 50_1 and between the layer 50_1 and the layer 50_2, since this facilitates electrical connection of circuits between different layers.

[0057] 4(B), the light receiving section 14 on the layer 60 and the cell array on the layer 50_2 are electrically connected via the layer 50_1. Incidentally, it is preferable to have a layer for providing wiring between the layer 60 and the layer 50_1 and between the layer 50_1 and the layer 50_2, since this facilitates electrical connection of circuits between different layers.

[0058] As mentioned above, the arithmetic circuit 40 in the layer 20 can perform inference processing based on a neural network. In FIG. 5A, the output data D is output by performing inference processing based on the neural network NN of the arithmetic circuit 40 in the block diagram shown in FIG. 3B. OUT is illustrated.

[0059] An example of inference processing in the neural network NN will be described with reference to Figure 5(B). The arithmetic circuit 40 capable of arithmetic processing based on the neural network NN captures an image of the user's eye 102 and its surroundings with the light receiving element 62 of the light receiving unit 14, and uses the minute current flowing through the light receiving element 62 as input data. The arithmetic circuit 40 and the cell array CA perform product-sum operations using the input data and weight data held in the cells IM, and execute arithmetic processing based on the neural network. The output data D obtained by the arithmetic circuit 40 is OUT For example, "whether the eyes are blinking or not," "how open they are," "body temperature," etc. can be inferred from the user's eyes 102 and their surroundings.

[0060] As described above, the display device of one embodiment of the present invention can have a stacked structure of a light-emitting element, a pixel circuit, and a driver circuit. The driver circuit, which is a peripheral circuit, can be arranged to overlap with the pixel circuit, and the width of the frame can be made extremely narrow, so that the display device can be made smaller and lighter. Therefore, the electronic device of one embodiment of the present invention can be an electronic device with excellent wearability.

[0061] In addition, by stacking the circuits in the display device of one embodiment of the present invention, wiring connecting the circuits can be shortened, thereby achieving a light-weight display device. Furthermore, the display device of one embodiment of the present invention can have a display portion with improved pixel resolution. Therefore, an electronic device including the display device can have excellent display quality.

[0062] Furthermore, a display device according to one embodiment of the present invention can have a stacked structure of a light-receiving element, a cell array, and an arithmetic circuit. Since the light-receiving element, the cell array, and the arithmetic circuit can be positioned close to each other, a minute current output by the light-receiving element can be used as input data. The arithmetic circuit and the cell array can perform arithmetic processing with excellent arithmetic efficiency. Furthermore, an electronic device including the display device according to one embodiment of the present invention can have a light-receiving unit located close to a display unit, allowing a user to view an image with their eye and capturing an image of the user's eye and / or its surroundings. Furthermore, the cell array in the display device can retain analog data written in response to a minute current for a long period of time. An arithmetic circuit that performs a product-sum operation using a minute current can perform arithmetic processing with excellent arithmetic efficiency.

[0063] <Other configuration examples of electronic devices> FIG. 6A is a perspective view showing the rear, bottom, and right side of the electronic device 100 described in FIG. 1A.

[0064] 6(A), a housing 101 of an electronic device 100 includes, as an example, a mounting portion 106, a buffer member 107, and a pair of lenses 108 in addition to a pair of display devices 10_L and 10_R. The display units 13 of the pair of display devices 10_L and 10_R are each provided at a position inside the housing 101 where they can be viewed through the lenses 108.

[0065] The light receiving units 14 of the pair of display devices 10_L and 10_R are provided at positions where they can acquire information about the user's eye 102 and its surroundings. The acquisition of information about the user's eye 102 and its surroundings by the light receiving units 14 may be performed via a lens 108 inside the housing 101 or may be performed without using the lens 108.

[0066] 6(A) is provided with an input terminal 109 and an output terminal 110. A cable can be connected to the input terminal 109 to supply an image signal (image data) from a video output device or the like, or power for charging a battery provided within the housing 101. The output terminal 110 functions as, for example, an audio output terminal, and earphones, headphones, etc. can be connected.

[0067] Furthermore, the housing 101 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that the housing 101 has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0068] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, thereby preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good on the skin and does not make the user feel cold when worn in cold seasons, etc. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the wearing part 106, removable, as this makes cleaning or replacement easier.

[0069] The electronic device according to one embodiment of the present invention may further include earphones 106A. The earphones 106A have a communication unit (not shown) and have a wireless communication function. The earphones 106A can output audio data using the wireless communication function. The earphones 106A may also have a vibration mechanism that functions as a bone conduction earphone.

[0070] 6B, the earphone 106A can be configured to be directly connected to the wearing unit 106 or connected by wire. The earphone 106B and the wearing unit 106 may have a magnet. This allows the earphone 106B to be fixed to the wearing unit 106 by magnetic force, which is preferable as it makes storage easier.

[0071] 7A is a perspective view of a glasses-type electronic device 100A, which is another example of a wearable electronic device. The electronic device 100A shown in FIG. 7A includes a pair of display devices 10_L and 10_R in a housing 101.

[0072] The electronic device 100A can project an image displayed on the display unit 13 of the display devices 10_L and 10_R onto a display area 104 of the optical member 103. Furthermore, because the optical member 103 is translucent, the user can see the image displayed in the display area 104 superimposed on a transmitted image visually recognized through the optical member 103. Therefore, the electronic device 100A is an electronic device capable of AR display.

[0073] Furthermore, although not shown, the housing 101 is provided with a connector to which a wireless receiver or a cable can be connected, and a video signal or the like can be supplied to the housing 101. Furthermore, by providing the housing 101 with an acceleration sensor such as a gyro sensor, the direction of the user's head can be detected and an image corresponding to that direction can be displayed in the display area 104.

[0074] 7(B), a method for projecting an image onto the display area 104 of the electronic device 100A will be described. The display device 10, a lens 111, and a reflector 112 are provided inside the housing 101. The optical member 103 also has a reflecting surface 113 that functions as a half mirror in a portion corresponding to the display area 104.

[0075] Light 115 emitted from display device 10 passes through lens 111 and is reflected by reflector 112 toward optical member 103. Inside optical member 103, light 115 is repeatedly totally reflected at the end surface of optical member 103 and reaches reflecting surface 113, whereby an image is projected onto reflecting surface 113. This allows the user to view both light 115 reflected by reflecting surface 113 and transmitted light 116 that has passed through optical member 103 (including reflecting surface 113).

[0076] 7(B) shows an example in which the reflector 112 and the reflecting surface 113 each have a curved surface. This allows for greater freedom in optical design and allows for a thinner optical member 103 than when these surfaces are flat. Note that the reflector 112 and the reflecting surface 113 may also be flat.

[0077] A member having a mirror surface, preferably one with high reflectivity, can be used as the reflector 112. Furthermore, a half mirror utilizing reflection from a metal film may be used as the reflecting surface 113, but the transmittance of the transmitted light 116 can be increased by using a prism or the like utilizing total reflection.

[0078] Here, it is preferable that the housing 101 has a mechanism for adjusting the distance between the lens 111 and the display device 10 or the angle therebetween. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, the lens 111 or the display device 10, or both, may be configured to be movable in the direction of the optical axis.

[0079] Furthermore, it is preferable that the housing 101 has a mechanism that can adjust the angle of the reflector 112. By changing the angle of the reflector 112, it is possible to change the position of the display area 104 where an image is displayed. This makes it possible to position the display area 104 in an optimal position according to the position of the user's eyes.

[0080] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0081] (Embodiment 2) An arithmetic circuit included in a display device of one embodiment of the present invention will be described. The arithmetic circuit can be used for arithmetic processing of an artificial neural network. As an example of the artificial neural network, a hierarchical neural network can be used.

[0082] <Hierarchical neural network> As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network ANN shown in FIG. 8(A) is an example, and the neural network ANN has first to Rth layers (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 8(A) illustrates the (k-1)th layer and the kth layer (where k is an integer of 3 or more and R-1 or less) as intermediate layers, and does not illustrate the other intermediate layers.

[0083] Each layer of the neural network ANN has one or more neurons. In FIG. 8(A), the first layer has a neuron N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m(k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0084] In addition, in Figure 8(A), neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0085] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) Focus on.

[0086] Figure 8(B) shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 8B shows the weight data w1 between the (k-1)th layer and the kth layer. (k-1) j(k) , w i (k-1) j (k) , w m (k-1) j (k) , and the activation function f(u j (k) ) is shown.

[0087] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0088] <Configuration example 1 of an arithmetic circuit> Next, a configuration example of the arithmetic circuit 40_1 that can be used in the above-mentioned hierarchical neural network will be described. The arithmetic circuit 40_1 can be applied to the arithmetic circuit 40 described in the above embodiment.

[0089] The arithmetic circuit 40_1 shown in FIG. 9 includes, for example, an array portion ALP, a circuit ILD, a circuit WLD, a circuit XLD, a circuit AFP, and circuits TW[1] to TW[n].

[0090] The circuit ILD and the circuit AFP are electrically connected to the wirings OL[1] to OL[n] and the wirings OLB[1] to OLB[n] via the circuits TW[1] to TW[n].

[0091] The circuits TW[1] to TW[n] function as switching circuits. In each of the circuits TW[1] to TW[n], it is possible to switch between inputting the output signals of the wirings OL[1] to OL[n] and OLB[1] to OLB[n] to the circuit AFP and inputting the output signals of the circuit ILD to the wirings OL[1] to OL[n] and OLB[1] to OLB[n].

[0092] The circuit WLD is electrically connected to the wirings WL[1] to WL[m] and the wirings WX1L[1] to WX1L[m]. The circuit XLD is electrically connected to the wirings WX1L[1] to WX1L[m].

[0093] The arithmetic circuit 40_1 shown in Fig. 9 has circuits MP in which array units ALP are arranged in a matrix of m x n. In Fig. 9, the circuit MP located in the i-th row and j-th column (where i is an integer of 1 to m, and j is an integer of 1 to n) is represented as circuit MP[i,j]. However, in Fig. 9, only circuit MP[1,1], circuit MP[1,m], circuit MP[i,j], circuit MP[n,1], and circuit MP[n,m] are shown, and the other circuits MP are not shown.

[0094] The circuit MP[i,j] is electrically connected to the wiring WL[i], the wiring WX1L[i], the wiring OL[j], and the wiring OLB[j].

[0095] For example, the circuit MP[i,j] has a function of holding a weighting coefficient (also referred to as first data). The weighting coefficient may also be referred to as a weight value. Specifically, the circuit MP[i,j] holds information corresponding to the weighting coefficient input from the wiring OL[j] and the wiring OLB[j].

[0096] The circuit ILD has a function of outputting information corresponding to first data, which is a weighting coefficient, to the wirings OL[1] to OL[n] and the wirings OLB[1] to OLB[n].

[0097] The information corresponding to the weighting coefficient may be, for example, a potential, a resistance value, a current value, etc. When a current value is used as the information corresponding to the weighting coefficient, the input current can be generated using a current output type digital-to-analog converter (IDAC).

[0098] Furthermore, the circuit MP[i,j] has a function of outputting the product of an input value (also referred to as second data) input from the wiring WX1L[i] and a weighting coefficient (first data). As a specific example, when the second data is input from the wiring WX1L[i], the circuit MP[i,j] outputs a current corresponding to the product of the first data and the second data to the wiring OL[j] and the wiring OLB[j]. Note that although FIG. 9 illustrates an example in which the wiring OL[j] and the wiring OLB[j] are provided, one embodiment of the present invention is not limited thereto. Only one of the wiring OL[j] and the wiring OLB[j] may be provided.

[0099] The circuit XLD has a function of supplying second data, which is an input value, to the wirings WX1L[1] to WX1L[m].

[0100] The information corresponding to the input value may be, for example, a potential, a current value, etc. When a current value is used as the information corresponding to the input value, the input current can be generated using a current output type digital-to-analog conversion circuit.

[0101] The currents corresponding to the products of the first data and second data output from the circuits MP[1,j] to MP[m,j] are added together and output to the wiring OL[j] and the wiring OLB[j]. In this way, the arithmetic circuit can perform a product-sum operation on the weighting coefficients and the input values.

[0102] The circuit XLD and the circuit WLD have a function of selecting a circuit MP to which information corresponding to the first data input from the circuit ILD is to be written. For example, when writing information to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit XLD supplies, for example, a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WX1L[i] and supplies, for example, a potential for turning off the write switching elements included in the circuits MP other than the i-th row to the wiring WX1L. The circuit WLD supplies, for example, a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WL[i] and supplies, for example, a potential for turning off the write switching elements included in the circuits MP other than the i-th row to the wiring WL.

[0103] The circuit AFP includes circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is electrically connected to the wiring OL[j] and the wiring OLB[j] via the circuit TW[j] having a switching function. The circuit ACTF[j] generates a signal according to information (for example, a potential, a current value, etc.) corresponding to the result of a product-sum operation input from the wiring OL[j] and the wiring OLB[j], and outputs z j (k) The circuit AFP compares information (such as potential, current value, etc.) corresponding to the result of the sum-of-products operation input from the wiring OL[j] and wiring OLB[j], generates a signal according to the comparison result, and outputs z j (k) It can be output as:

[0104] <Circuit MP> Next, the circuit MP will be described. An example of a circuit configuration applicable to the circuit MP[i,j] is shown in Fig. 10. The circuit MP[i,j] has transistors M1 to M3 and a capacitor C1. Note that a holding unit HC is configured, for example, by the transistor M2 and the capacitor C1.

[0105] 10, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0106] The transistors M1 to M3 shown in FIG. 10 are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M3 has a first gate and a second gate.

[0107] Furthermore, the arithmetic circuit 40_1 described in this embodiment does not depend on the connection configuration of the back gates of the transistors. The transistors M1 to M3 shown in FIG. 10 have back gates, but the connection configuration of the back gates is not shown. However, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor.

[0108] In the circuit MP of FIG. 10, a first terminal of the transistor M1 is electrically connected to a wiring VE. A second terminal of the transistor M1 is electrically connected to a first terminal of the transistor M3. A gate of the transistor M1 is electrically connected to a first terminal of the capacitor C1 and a first terminal of the transistor M2. A second terminal of the capacitor C1 is electrically connected to a wiring VE. A second terminal of the transistor M2 is electrically connected to a wiring OL. A gate of the transistor M2 is electrically connected to a wiring WL. A second terminal of the transistor M3 is electrically connected to the wiring OL, and a gate of the transistor M3 is electrically connected to a wiring WX1L.

[0109] The circuit MCr has a different connection configuration from the circuit MC. The second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0110] In the holding unit HC shown in FIG. 10, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as a node n1.

[0111] The holding unit HC has a function of holding a potential corresponding to the weighting coefficient (first data). The holding unit HC included in the circuit MC of FIG. 10 can hold the potential by inputting a current of a predetermined value from the wiring OL when the transistors M2 and M3 are turned on, writing a potential corresponding to the current value to the capacitor C1, and then turning off the transistor M2. This allows the potential of the node n1 to be held as a potential corresponding to the weighting coefficient (first data). Therefore, when the first data is input, the influence of variations in the current characteristics (threshold voltage, etc.) of the transistor M1 can be reduced.

[0112] The current input to the wiring OL can be input and generated using a current output type digital-to-analog conversion circuit.

[0113] In addition, since the transistor M1 holds the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current. For example, an OS transistor can be used as the transistor M1. Alternatively, a transistor with a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side, thereby reducing the off-state current.

[0114] In this way, an arithmetic circuit with high arithmetic accuracy is provided.

[0115] <Configuration example 2 of arithmetic circuit> Another example of an arithmetic circuit 40_2 that performs a product-sum operation will be described below. The arithmetic circuit 40_2 is applicable to the arithmetic circuit 40 described in the above embodiment.

[0116] 11 shows an example of the configuration of an arithmetic circuit that performs a product-sum operation on first data that is positive or "0" and second data that is positive or "0". The arithmetic circuit 40_2 shown in FIG. 11 is a circuit that performs a product-sum operation on first data that corresponds to the potential held in each cell and input second data, and calculates an activation function using the result of the product-sum operation. Note that the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0117] This arithmetic circuit can also be called a memory because it also functions as a memory that holds the first data. In particular, when analog data is used as the first data, it can be called an analog memory.

[0118] The arithmetic circuit 40_2 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit PTC, a circuit SWS1, a circuit SWS2, a cell array CA, and a circuit ITS.

[0119] The circuit PTC includes circuits PTR[1] to PTR[m]. The circuits PTR[1] to PTR[m] have a function of turning on or off the wirings EIL[1] to EIL[m] and the wirings XCL[1] to XCL[m]. That is, each of the circuits PTR[1] to PTR[m] functions as a switching element. For example, each of the circuits PTR[1] to PTR[m] includes switches SA[1] to SA[m].

[0120] The cell array CA has cells IM[1,1] to IM[m,n] (where m is an integer greater than or equal to 1 and n is an integer greater than or equal to 1) and cells IMref[1] to IMref[m]. Each of cells IM[1,1] to IM[m,n] has a function of holding a potential corresponding to the amount of current corresponding to first data, and cells IMref[1] to IMref[m] have a function of supplying the held potential and a potential corresponding to second data required for performing a product-sum operation to wirings XCL[1] to XCL[m].

[0121] Note that the cell array CA in Figure 11 has n+1 cells arranged in a matrix in the row direction and m cells arranged in the column direction, but the cell array CA may also be configured to have two or more cells arranged in a matrix in the row direction and one or more cells arranged in the column direction.

[0122] Each of cells IM[1,1] to IM[m,n] has, for example, a transistor F1, a transistor F2, and a capacitance C5, and each of cells IMref[1] to IMref[m] has, for example, a transistor F1m, a transistor F2m, and a capacitance C5m.

[0123] In particular, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors F1 included in each of the cells IM[1,1] to IM[m,n] are equal to each other, and it is also preferable that the sizes of the transistors F2 included in each of the cells IM[1,1] to IM[m,n] are equal to each other. It is also preferable that the sizes of the transistors F1m included in each of the cells IMref[1] to IMref[m] are equal to each other, and it is also preferable that the sizes of the transistors F2m included in each of the cells IMref[1] to IMref[m] are equal to each other. It is also preferable that the sizes of the transistors F1 and F1m are equal to each other, and it is also preferable that the sizes of the transistors F2 and F2m are equal to each other.

[0124] Unless otherwise specified, the transistors F1 and F1m are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to voltages within a range in which they operate in a linear region. However, one aspect of the present invention is not limited to this. For example, the transistors F1 and F1m may operate in a saturation region when they are on, or may operate in both a linear region and a saturation region.

[0125] Furthermore, unless otherwise specified, the transistors F2 and F2m are considered to operate in the subthreshold region (i.e., in the transistor F2 or F2m, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to be appropriately biased to voltages within the range in which they operate in the subthreshold region. Therefore, the transistors F2 and F2m also include a case in which they operate such that an off-state current flows between the source and the drain.

[0126] For example, the transistor F1 and / or the transistor F1m is preferably an OS transistor. In addition, the channel formation region of the transistor F1 and / or the transistor F1m is more preferably an oxide containing at least one of indium, an element M (the element M may be one or more elements selected from aluminum, gallium, yttrium, tin, etc.), and zinc.

[0127] By using OS transistors as the transistors F1 and / or F1m, the leakage current of the transistors F1 and / or F1m can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when the transistors F1 and / or F1m are off, the leakage current from the retention node to the write word line can be significantly reduced, thereby reducing the number of refresh operations of the potential of the retention node, thereby reducing the power consumption of the sum-of-products operation circuit. Furthermore, by significantly reducing the leakage current from the retention node to the write word line, the cell can retain the potential of the retention node for a long time, thereby improving the operation accuracy of the arithmetic circuit.

[0128] Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can be manufactured simultaneously with the transistors F1 and F1m, which may shorten the manufacturing process of the product-sum operation circuit. The transistors F2 and / or the transistor F2m can be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single-crystal silicon.

[0129] Incidentally, when an arithmetic circuit or the like is highly integrated on a chip, the chip may generate heat due to the operation of the circuit. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, resulting in a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so their field-effect mobility is less likely to change with temperature, and their operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, using OS transistors makes it easier to perform the product-sum operation described below, even in high-temperature environments. Therefore, when configuring an arithmetic circuit that is resistant to heat generation due to operation, it is preferable to use OS transistors as the transistors.

[0130] In each of the cells IM[1,1] to IM[m,n], a first terminal of the transistor F1 is electrically connected to a gate of the transistor F2. A first terminal of the transistor F2 is electrically connected to a wiring VE. A first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

[0131] In each of the cells IMref[1] to IMref[m], a first terminal of the transistor F1m is electrically connected to a gate of the transistor F2m, a first terminal of the transistor F2m is electrically connected to a wiring VE, and a first terminal of the capacitor C5m is electrically connected to the gate of the transistor F2m.

[0132] The arithmetic circuit described in this embodiment does not depend on the polarity of the transistors included in the arithmetic circuit. For example, although the transistors F1 and F2 shown in FIG. 11 are n-channel transistors, some or all of the transistors may be replaced with p-channel transistors.

[0133] The above-described modifications to the transistor structures and polarities are not limited to transistors F1 and F2. For example, the same applies to transistors F1m, F2m, transistors F3[1] to F3[n], and transistors F4[1] to F4[n], which will be described later, as well as transistors described elsewhere in the specification or shown in other drawings.

[0134] The wiring VE is a wiring for passing a current between the first terminal and the second terminal of the transistor F2 of each of the cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2 of each of the cells IMref[1] and IMref[m]. As an example, the wiring VE functions as a wiring for supplying a constant voltage. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0135] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,1] is designated as node NN[1,1].

[0136] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,1] is designated as node NN[m,1].

[0137] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,n] is referred to as node NN[1,n].

[0138] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is designated as node NN[m,n].

[0139] In cell IMref[1], the second terminal of transistor F1m is electrically connected to line XCL[1], and the gate of transistor F1m is electrically connected to line WSL[1]. The second terminal of transistor F2m is electrically connected to line XCL[1], and the second terminal of capacitor C5 is electrically connected to line XCL[1]. In FIG. 11, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[1] is referred to as node NNref[1].

[0140] In cell IMref[m], the second terminal of transistor F1m is electrically connected to line XCL[m], and the gate of transistor F1m is electrically connected to line WSL[m]. The second terminal of transistor F2m is electrically connected to line XCL[m], and the second terminal of capacitor C5 is electrically connected to line XCL[m]. In FIG. 11, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[m] is referred to as node NNref[m].

[0141] The above-mentioned nodes NN[1,1], NN[m,1], NN[1,n], NN[m,n], NNref[1], and NMref[m] function as holding nodes for the respective cells.

[0142] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in the on state, transistor F2 is configured as a diode. When transistor F1 is in the on state and a current of magnitude I flows from wiring WCL to the second terminal of transistor F2, with the constant voltage provided by wiring VE as the ground potential (GND), the potential of the gate (node ​​NN) of transistor F2 is determined according to the current magnitude I. Since transistor F1 is in the on state, the potential of the second terminal of transistor F2 is ideally equal to the gate (node ​​NN) of transistor F2. By turning transistor F1 off, the potential of the gate (node ​​NN) of transistor F2 is maintained. This allows transistor F2 to pass a current of magnitude I between its source and drain, depending on the ground potential of the first terminal of transistor F2 and the potential of the gate (node ​​NN) of transistor F2. In this specification and the like, this operation is referred to as "the amount of current flowing between the source and drain of the transistor F2 is programmed to I", etc.

[0143] The circuit SWS1 includes, for example, transistors F3[1] to F3[n]. A first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and a gate of the transistor F3[1] is electrically connected to the wiring SWL1. A first terminal of the transistor F3[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F3[n] is electrically connected to the circuit WCS, and a gate of the transistor F3[n] is electrically connected to the wiring SWL1.

[0144] The transistors F3[1] to F3[n] are preferably OS transistors that can be applied to the transistor F1 and / or the transistor F2, for example.

[0145] The circuit SWS1 functions as a circuit that brings the circuit WCS and each of the wirings WCL[1] to WCL[n] into a conductive state or a non-conductive state.

[0146] The circuit SWS2 includes, for example, transistors F4[1] to F4[n]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1], a second terminal of the transistor F4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1], and a gate of the transistor F4[1] is electrically connected to the wiring SWL2. A first terminal of the transistor F4[n] is electrically connected to the wiring WCL[n], a second terminal of the transistor F4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n], and a gate of the transistor F4[n] is electrically connected to the wiring SWL2.

[0147] The transistors F4[1] to F4[n] are preferably OS transistors that can be applied to the transistor F1 and / or the transistor F2, for example.

[0148] The circuit SWS2 functions as a circuit that brings the wiring WCL[1] and the conversion circuit ITRZ[1] and the wiring WCL[n] and the conversion circuit ITRZ[n] into a conductive state or a non-conductive state.

[0149] The circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.

[0150] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of supplying a current corresponding to the reference data or a current corresponding to the second data to each of the cells IMref[1] to IMref[m] included in the cell array CA.

[0151] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing first data to the cells IM[1,1] to IM[m,n], the circuit WSD supplies a predetermined signal to the wirings WSL[1] to WSL[m] to select a row of the cell array CA to which the first data is to be written.

[0152] For example, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2. The circuit WSD has a function of bringing the circuit WCS and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL1, and a function of bringing the conversion circuits ITRZ[1] to ITRZ[n] and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL2.

[0153] Each of the conversion circuits ITRZ[1] to ITRZ[n] has, for example, an input terminal and an output terminal. For example, the output terminal of the conversion circuit ITRZ[1] is electrically connected to the wiring OL[1], and the output terminal of the conversion circuit ITRZ[n] is electrically connected to the wiring OL[n].

[0154] Each of the conversion circuits ITRZ[1] to ITRZ[n] has a function of converting a current input to an input terminal into a voltage corresponding to the current and outputting the voltage from an output terminal. The voltage may be, for example, an analog voltage or a digital voltage. Each of the conversion circuits ITRZ[1] to ITRZ[n] may also have a function-based arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage, and the calculation result may be output to the wiring OL[1] to wiring OL[n].

[0155] In particular, when performing calculations on a hierarchical neural network, the above-mentioned functions may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like.

[0156] A current output type digital-analog conversion circuit can be used as the circuit WCS shown in Fig. 11. Also, a current output type digital-analog conversion circuit can be used as the circuit XCS shown in Fig. 11.

[0157] <3D structure of sensor and calculation circuit> Next, a three-dimensional structure will be described when the display device 10 is provided with an arithmetic circuit 40 capable of performing calculations using the output of a sensor provided in a part of the display device 10. The display device 10_SDV shown in Fig. 12 has a layer PDL, a layer ERL, a layer CCL, and a layer PHL. The layers CCL and PHL are provided with the components of the arithmetic circuit 40_2 described above.

[0158] Note that, since the display device 10_SDV shown in FIG. 12 is shown as a three-dimensional structure, arrows indicating the x-direction, y-direction, and z-direction are added to FIG. 12. Note that the x-direction, y-direction, and z-direction are shown as directions that are perpendicular to each other, as an example. Furthermore, in this specification, one of the x-direction, y-direction, and z-direction may be referred to as the "first direction" or "first direction." Furthermore, the other may be referred to as the "second direction" or "second direction." Furthermore, the remaining one may be referred to as the "third direction" or "third direction."

[0159] The layer CCL is located above the layer PHL, the layer ERL is located above the layer CCL, and the layer PDL is located above the layer ERL. In other words, the layers PHL, CCL, ERL, and PDL are stacked in this order in the z direction.

[0160] The layer PDL has a sensor array SCA, for example. The sensor array SCA has a plurality of electrodes and a plurality of sensors. In Fig. 12, for example, electrodes DNK[1] to DNK[m] (where m is an integer greater than or equal to 1) are shown as the plurality of electrodes, and sensors SNC[1] to SNC[m] are shown as the plurality of sensors. In addition, for example, m electrodes DNK are arranged in a matrix on the layer PDL, and sensors SNC[1] to SNC[m] are provided on the electrodes DNK[1] to DNK[m], respectively.

[0161] 12, the layer PDL shows only the symbols of the electrodes DNK[1], DNK[i] (where i is an integer between 1 and m), and DNK[m] among the electrodes DNK[1] to DNK[m]. Also, in the layer PDL shown in FIG. 12, the layer PDL shows only the symbols of the sensors SNC[1], SNC[i], and SNC[m] among the sensors SNC[1] to SNC[m].

[0162] The sensors SNC[1] to SNC[m] convert sensed information into current values ​​and output the current values. The electrodes DNK[1] to DNK[m] function as terminals for outputting the current values ​​in the sensors SNC[1] to SNC[m]. For example, a light-receiving element can be used as the sensor SNC. By using a light-receiving element as the sensors SNC[1] to SNC[m], the layer PDL can be used as part of the image sensor. In this case, it is desirable that the range of light intensity that the light-receiving element can sense includes the intensity of light irradiated in the environment in which the light-receiving element is used. FIG. 12 also shows a display device 10_SDV employing a sensor SNC having a photodiode PD as the light-receiving element. The photodiode PD is preferably an organic light-emitting diode that can be provided in the same layer as the light-emitting element.

[0163] The circuit configuration of the sensor SNC[i] may be such that one of the input terminal or output terminal of the photodiode PD included in the sensor SNC[i] is electrically connected to the wiring EIL[i] via the electrode DNK[i]. The circuit configuration of the sensor SNC[i] may be such that a switch that cuts off the power supply to temporarily stop the sensor SNC[i] is provided. A light-emitting element (not shown) for displaying information may be provided on the same layer as the sensor SNC[i].

[0164] The layer ERL has wirings EIL[1] to EIL[m]. In the layer ERL shown in FIG. 12, the reference symbols for the wirings EIL[1], EIL[i], and EIL[m] are selected from the wirings EIL[1] to EIL[m].

[0165] The wiring EIL[1] is electrically connected to the electrode DNK[1] on the layer PDL. The wiring EIL[i] is electrically connected to the electrode DNK[i] on the layer PDL. The wiring EIL[m] is electrically connected to the electrode DNK[m] on the layer PDL.

[0166] Specifically, for example, when viewed from above the display device 10_SDV (viewing in the opposite direction of the z-axis arrow shown in Figure 12), plugs (sometimes called contact holes, etc.) are provided at the points where each of the electrodes DNK[1] to DNK[m] intersects with the wiring EIL[1] to EIL[m], electrically connecting each of the electrodes DNK[1] to DNK[m] to each of the wiring EIL[1] to EIL[m].

[0167] Therefore, when information is sensed in each of the sensors SNC[1] to SNC[m], the wiring EIL[1] to EIL[m] function as a path through which a current flows in an amount corresponding to the information output by each of the sensors SNC[1] to SNC[m].

[0168] Note that the layer PDL is preferably configured such that the sensors SNC[1] to SNC[m] can sequentially perform sensing, respectively, and current can sequentially flow through the wirings EIL[1] to EIL[m]. In this case, for example, the layer PDL may be configured to include signal lines for selecting the sensors SNC[1] to SNC[m], and signals or the like may be sequentially sent to the signal lines to operate the sensors SNC[1] to SNC[m] sequentially.

[0169] Furthermore, when the sensors SNC[1] to SNC[m] are light receiving elements configured with photodiodes or the like, the layer PDL of the display device 10_SDV may be configured, for example, so that the output terminal (cathode) of the photodiode is electrically connected to the electrode DNK. Alternatively, as another configuration example of the layer PDL of the display device 10_SDV, the layer PDL may be configured so that the input terminal (anode) of the photodiode is electrically connected to the electrode DNK.

[0170] Furthermore, when the sensors SNC[1] to SNC[m] are light-receiving elements configured with photodiodes or the like, for example, by preparing a filter that irradiates only one of the sensors SNC[1] to SNC[m] with light, the sensors SNC[1] to SNC[m] can be operated sequentially. Since there are m sensors SNC, there are m types of filters that irradiate only one sensor SNC with light. Furthermore, if there is prepared an additional filter that does not irradiate any of the sensors SNC[1] to SNC[m] with light, there will be m+1 types of filters. When light is irradiated onto the layer PDL, the sensors SNC[1] to SNC[m] can perform sensing sequentially by sequentially switching such filters.

[0171] Furthermore, when the sensors SNC[1] to SNC[m] are light receiving elements configured with photodiodes or the like, for example, the display device 10_SDV may be configured to individually irradiate the sensors SNC[1] to SNC[m] with light. By configuring the sensors SNC[1] to SNC[m] to individually irradiate them with light, the sensors SNC[1] to SNC[m] can sequentially irradiate them with light, allowing the sensors SNC[1] to SNC[m] to perform sensing sequentially.

[0172] The layer CCL includes a cell array CA. The layer PHL includes, for example, circuits PTC, XCS, WCS, WSD, ITS, SWS1, and SWS2. As shown in Figure 12, the cell array CA can be configured to be located above the circuits XCS, WCS, WSD, ITS, SWS1, and SWS2, which correspond to the peripheral circuits of the cell array CA.

[0173] The cell array CA has a plurality of cells, each of which has a function of holding first data for performing a multiply-and-accumulate operation, a function of multiplying the first data by second data, and the like.

[0174] The cell array CA is also electrically connected to a plurality of wirings. Specifically, for example, FIG. 12 shows a configuration in which the cell array CA is electrically connected to wirings WCL[1] to WCL[n] (where n is an integer equal to or greater than 1), wirings WSL[1] to WSL[m], and wirings XCL[1] to XCL[m]. In particular, the wirings WCL[1] to WCL[n] electrically connect the circuit SWS1 and the circuit SWS2. That is, the circuit SWS1 can be said to be electrically connected to the circuit SWS2 via the cell array CA by the wirings WCL[1] to WCL[n]. In FIG. 12, the wirings WSL[1] to WSL[m], wirings XCL[1] to XCL[m], and wirings WCL[1] to WCL[n] extend in the z-direction.

[0175] Furthermore, each of the cells in the cell array CA is electrically connected to one of the lines WCL[1] through WCL[n], one of the lines WSL[1] through WSL[m], and one of the lines XCL[1] through XCL[m]. Therefore, the cells included in the cell array CA are arranged in a matrix of at least m rows and n columns.

[0176] The circuit WCS has a function of supplying current to the wirings WCL[1] to WCL[n] in an amount corresponding to the first data, and therefore is electrically connected to each of the wirings WCL[1] to WCL[n] via the circuit SWS1.

[0177] The circuit SWS1 has a function of bringing the circuit WCS into electrical continuity or non-conduction between the circuit WCS and each of the wirings WCL[1] to WCL[n].

[0178] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing first data to a cell included in the cell array CA, the circuit WSD has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. In other words, the wirings WSL[1] to WSL[m] function as write word lines.

[0179] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of supplying a current corresponding to reference data (described later) or second data to the wirings XCL[1] to XCL[m].

[0180] The circuit PTC includes circuits PTR[1] to PTR[m]. A first terminal of the circuit PTR[1] is electrically connected to a wiring XCL[1], a first terminal of the circuit PTR[i] is electrically connected to a wiring XCL[i], and a first terminal of the circuit PTR[m] is electrically connected to a wiring XCL[m].

[0181] In addition, the second terminal of the circuit PTR[1] is electrically connected to the wiring EIL[1] of the layer ERL, the second terminal of the circuit PTR[i] is electrically connected to the wiring EIL[i] of the layer ERL, and the second terminal of the circuit PTR[m] is electrically connected to the wiring EIL[m] of the layer ERL.

[0182] Specifically, for example, when viewed from above the display device 10_SDV, plugs or the like are provided at the points where the second terminals of the circuits PTR[1] to PTR[m] intersect with the wirings EIL[1] to EIL[m], respectively, to electrically connect the second terminals of the circuits PTR[1] to PTR[m] with the wirings EIL[1] to EIL[m], respectively.

[0183] The circuit PTR[1] has a function of bringing the wiring EIL[1] and the wiring XCL[1] into a conductive state or a non-conductive state. Similarly, the circuit PTR[i] has a function of bringing the wiring EIL[i] and the wiring XCL[i] into a conductive state or a non-conductive state, and the circuit PTR[m] has a function of bringing the wiring EIL[m] and the wiring XCL[m] into a conductive state or a non-conductive state. In other words, each of the circuits PTR[1] to PTR[m] functions as a switching element.

[0184] The circuit ITS has a function of acquiring the amount of current flowing through the wirings WCL[1] to WCL[n] and outputting a result according to the amount of current to the wirings OL[1] to OL[n]. Therefore, the circuit ITS is electrically connected to each of the wirings WCL[1] to WCL[n] via the circuit SWS2. The circuit ITS is also electrically connected to each of the wirings OL[1] to OL[n].

[0185] The circuit SWS2 has a function of bringing the circuit ITS into a conductive state or a non-conductive state between the circuit ITS and each of the wirings WCL[1] to WCL[n].

[0186] 12, the wirings EIL[1] to EIL[m] preferably extend along the x-direction. That is, the direction in which the wirings EIL[1] to EIL[m] extend is preferably substantially parallel to the wirings XCL[1] to XCL[m] when viewed in the y-direction, and more preferably parallel. Furthermore, for example, the wirings EIL[1] to EIL[m] preferably extend substantially parallel to the wirings XCL[1] to XCL[m] included in the layer CCL when viewed from above, and more preferably parallel.

[0187] As described above, by applying the display device 10_SDV shown in Fig. 12, the location of the sensor array SCA on the display device including the arithmetic circuit (layer CCL) can be determined almost freely. Therefore, for example, the sensor array SCA can be disposed at or near the center of the display device when viewed from above. Furthermore, the layout of the arithmetic circuit included in the layer CCL does not depend on the location of the sensor array SCA, which increases the degree of freedom in the layout of the arithmetic circuit and its surrounding wiring.

[0188] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0189] (Embodiment 3) In this embodiment, a driver circuit, a three-dimensional structure of a pixel circuit and a light-emitting element, a configuration example of a pixel circuit, a top schematic view of a light-emitting element and a cross-sectional schematic view thereof, a configuration example of a light-emitting element, a configuration example of a light-emitting element and a light-receiving element, and a configuration example of a cross-sectional view of a display device will be described.

[0190] <Three-dimensional structure of driving circuits, pixel circuits, and light-emitting elements> 13(A) and 13(B) show a configuration example of a pixel circuit 51 and a light-emitting element 61 connected to the pixel circuit 51. Fig. 13(A) is a diagram showing the connection of each element, and Fig. 13(B) is a diagram schematically showing the hierarchical relationship between a layer 20 including a drive circuit 30, a layer 50 including a plurality of transistors that the pixel circuit 51 has, and a layer 60 including the light-emitting element 61.

[0191] 13A and 13B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The transistors 52A, 52B, and 52C can be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from that of the gate electrode.

[0192] The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0193] The transistor 52A has a function of controlling the conductive state or non-conductive state based on the potential of a first electrode electrically connected to the gate electrode of the transistor 52B, a second electrode electrically connected to the wiring SL functioning as a source line, and the wiring GL1 functioning as a gate line.

[0194] The transistor 52C has a function of controlling the conductive state or non-conductive state based on the potentials of a first electrode electrically connected to the wiring V0, a ​​second electrode electrically connected to the light-emitting element 61, and a wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the drive circuit 30 or the arithmetic circuit 40.

[0195] The capacitor 53 includes a conductive film electrically connected to the gate electrode of the transistor 52B and a conductive film electrically connected to the second electrode of the transistor 52C.

[0196] The light-emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 52B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0197] This makes it possible to control the intensity of light emitted by the light-emitting element 61 in accordance with an image signal applied to the gate electrode of the transistor 52B. Also, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential of the transistor 52B.

[0198] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 40 or the like.

[0199] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous light-emitting element such as an organic light-emitting element (also referred to as an OLED (organic light-emitting diode)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0200] In the configuration shown in FIG. 13B as an example, the wiring electrically connecting the pixel circuit 51 and the driver circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. Therefore, data can be written at high speed, allowing the display device 10 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 10 has a large number of pixel circuits 51, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of images displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display unit is close to the user.

[0201] 13(A) and 13(B) may be provided with the arithmetic circuit 40, the cell array CA, and the photodiode PD, which is a light-receiving element, respectively, as described in the second embodiment. Therefore, the display device 10 may be configured to include an arithmetic circuit and a drive circuit, a pixel circuit and a cell array, a light-emitting element, and a light-receiving element.

[0202] 13A and 13B show an example of the pixel circuit 51 including three transistors in total, but one embodiment of the present invention is not limited thereto. Below, a configuration example of a pixel circuit that can be applied to the pixel circuit 51 will be described.

[0203] 14A illustrates a pixel circuit 51A including a transistor 52A, a transistor 52B, and a capacitor 53. Also illustrated in Fig. 14A is a light-emitting element 61 connected to the pixel circuit 51A. The pixel circuit 51A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0204] The transistor 52A has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL, and the other electrically connected to the gate of the transistor 52B and one electrode of the capacitor C1. The transistor 52B has one of its source and drain electrically connected to the wiring ANO, and the other electrically connected to the anode of the light-emitting element 61. The capacitor C1 has the other electrode electrically connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode electrically connected to the wiring VCOM.

[0205] 14B has a configuration in which a transistor 52C is added to the pixel circuit 51A. A wiring V0 is electrically connected to the pixel circuit 51B.

[0206] A pixel circuit 51C shown in FIG. 14(C) is an example in which transistors each having a pair of gates are used as the transistors 52A and 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 14(D) is an example in which the same transistors are used in the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors each having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0207] 15A has a configuration in which a transistor 52D is added to the pixel circuit 51B. The pixel circuit 51E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0208] The gate of the transistor 52D is electrically connected to a wiring GL3, one of the source and the drain of the transistor 52D is electrically connected to the gate of the transistor 52B, and the other is electrically connected to a wiring V0. The gate of the transistor 52A is electrically connected to a wiring GL1, and the gate of the transistor 52C is electrically connected to a wiring GL2.

[0209] By simultaneously turning on transistors 52C and 52D, the source and gate of transistor 52B have the same potential, and transistor 52B can be turned off. This forcibly cuts off the current flowing through light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0210] 15B is an example in which a capacitor 53A is added to the pixel circuit 51E. The capacitor 53A functions as a storage capacitor.

[0211] 15(C) and 15(D) are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, and transistor 52B is a transistor in which one gate is electrically connected to its source.

[0212] <Top view and cross-sectional view of the light-emitting element> 16(A) is a schematic top view illustrating a configuration example in which a light-emitting element and a light-receiving element are arranged in one pixel in a display device 10 according to one embodiment of the present invention. The display device 10 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, a plurality of light-emitting elements 61B that emit blue light, and a plurality of light-receiving elements 62. In FIG. 16(A), in order to easily distinguish between the light-emitting elements 61, the light-emitting regions of the light-emitting elements 61 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving elements 62 are labeled with PD.

[0213] The light-emitting elements 61R, 61G, 61B, and the light-receiving elements 62 are arranged in a matrix. FIG. 16A shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged in the X direction, and the light-receiving elements 62 are arranged below them. FIG. 16A also shows an example in which the light-emitting elements 61 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in FIG. 16A, a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting element 61R, a sub-pixel having the light-emitting element 61G, and a sub-pixel having the light-emitting element 61B arranged in the X direction, and a sub-pixel having the light-receiving element 62 provided below these sub-pixels.

[0214] It is preferable to use EL elements such as OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum-dot Light Emitting Diodes) as the light-emitting elements 61R, 61G, and 61B. Examples of light-emitting materials that the EL elements have include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and materials that exhibit thermally activated delayed fluorescence (TADF materials).

[0215] For example, a pn-type or pin-type photodiode can be used as the light receiving element 62. The light receiving element 62 functions as a photoelectric conversion element that detects light incident on the light receiving element 62 and generates an electric charge. The amount of electric charge generated is determined based on the amount of incident light.

[0216] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light receiving element 62. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0217] In one embodiment of the present invention, an organic EL element is used as the light-emitting element 61, and an organic photodiode is used as the light-receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. The organic EL elements and the organic photodiode are preferably separated from each other by photolithography. This allows the distance between the light-emitting elements and the organic photodiode to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0218] 16(A) shows a common electrode 81 and a connection electrode 82. Here, the connection electrode 82 is electrically connected to the common electrode 81. The connection electrode 82 is provided outside the display section where the light-emitting elements 61 and the light-receiving elements 62 are arranged. Also in FIG. 16(A), the common electrode 81 having an area overlapping with the light-emitting elements 61, the light-receiving elements 62, and the connection electrode 82 is shown by a dashed line.

[0219] The connection electrodes 82 can be provided along the periphery of the display unit. For example, they may be provided along one side of the periphery of the display unit, or they may be provided over two or more sides of the periphery of the display unit. That is, if the top surface of the display unit has a rectangular shape, the top surface of the connection electrodes 82 can have a strip-like, L-shaped, U-shaped (square bracket-shaped), quadrangular, or the like shape.

[0220] Fig. 16(B) is a schematic top view showing an example of the configuration of the display device 10, which is a modification of the display device 10 shown in Fig. 16(A). The display device 10 shown in Fig. 16(B) differs from the display device 10 shown in Fig. 16(A) in that it includes a light-emitting element 61IR that emits infrared light. The light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0221] 16(B), in addition to light-emitting elements 61R, 61G, and 61B, a light-emitting element 61IR is arranged in the X direction, and a light-receiving element 62 is arranged below them. The light-receiving element 62 has a function of detecting infrared light.

[0222] Fig. 17(A) is a cross-sectional view corresponding to dashed dotted line A1-A2 in Fig. 16(A), and Fig. 17(B) is a cross-sectional view corresponding to dashed dotted line B1-B2 in Fig. 16(A). Fig. 17(C) is a cross-sectional view corresponding to dashed dotted line C1-C2 in Fig. 16(A), and Fig. 17(D) is a cross-sectional view corresponding to dashed dotted line D1-D2 in Fig. 16(A). The light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62 are provided on a substrate 83. Furthermore, when the display device 10 includes a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0223] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0224] 17A shows an example of the cross-sectional configuration of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, and FIG.

[0225] The light-emitting element 61R has a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G has a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B has a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 has a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0226] The common layer 89 functions as an electron injection layer in the light-emitting element 61. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving element 62. Therefore, the light-receiving element 62 does not need to have the electron transport layer 88PD.

[0227] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0228] The pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light-emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the common electrode 81 are provided in common to the light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62.

[0229] 17A, the light-emitting element 61 and the light-receiving element 62 may have a hole-blocking layer and an electron-blocking layer. The light-emitting element 61 and the light-receiving element 62 may have a layer containing a bipolar substance (a substance having high electron-transporting and hole-transporting properties) or the like.

[0230] A gap is provided between the common layer 89 and the insulating layer 92, which will be described later. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole-transporting layer 86, and the hole-injecting layer 85. This prevents short circuits in the light-emitting element 61 and the light-receiving element 62.

[0231] The voids are more easily formed, for example, as the distance between the light-emitting layers 87 becomes shorter. For example, the voids can be suitably formed when the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.

[0232] 17A illustrates a configuration in which, from bottom to top, the light-emitting element 61 is provided with a pixel electrode 84, a hole injection layer 85, a hole transport layer 86, a light-emitting layer 87, an electron transport layer 88, a common layer 89 (electron injection layer), and a common electrode 81, and the light-receiving element 62 is provided with a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, the common layer 89, and a common electrode 81, but one embodiment of the present invention is not limited to this. For example, the light-emitting element 61 may be provided with, from bottom to top, a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode, and the light-receiving element 62 may be provided with, from bottom to top, a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode. In this case, the hole injection layer of the light-emitting element 61 can be a common layer, and the common layer can be provided between the hole transport layer and the common electrode of the light-receiving element 62. Also, in the light-emitting element 61, the electron injection layer can be separated for each element.

[0233] In the following description, the electron transport layer is assumed to be provided above the hole transport layer. However, the following description can also be applied to the case where the electron transport layer is provided below the hole transport layer, for example, by replacing "electrons" with "holes" and "holes" with "electrons."

[0234] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0235] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transporting material. Examples of the hole transporting material include 10 -6 cm 2A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0236] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 -6 cm 2 A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0237] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0238] Examples of the electron injection layer include lithium, cesium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), and lithium oxide (LiO x ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used.

[0239] Alternatively, the electron injection layer may be formed using a material having electron transport properties. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring may be used as the material having electron transport properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring may be used.

[0240] The lowest unoccupied molecular orbital (LUMO) of an organic compound having an unshared electron pair is preferably -3.6 eV or more and -2.3 eV or less. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, etc.

[0241] Examples of organic compounds with lone electron pairs include 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), and 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz). NBPhen has a higher glass transition temperature (Tg) and better heat resistance than BPhen.

[0242] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0243] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0244] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0245] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0246] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). One or more organic compounds may be a hole-transporting material or an electron-transporting material, or both. Alternatively, a bipolar material or a TADF material may be used as the one or more organic compounds.

[0247] The light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient light emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing for efficient light emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0248] The light-emitting layer 87R of the light-emitting element 61R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 contains an organic compound that has detection sensitivity in the wavelength range of visible light, for example.

[0249] A conductive film that is translucent to visible light is used for either the pixel electrode 84 or the common electrode 81, and a conductive film that is reflective is used for the other. By making the pixel electrode 84 translucent and the common electrode 81 reflective, the display device 10 can be made into a bottom-emission display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 translucent, the display device 10 can be made into a top-emission display device. Note that by making both the pixel electrode 84 and the common electrode 81 translucent, the display device 10 can also be made into a dual-emission display device.

[0250] Furthermore, the light-emitting element 61 preferably has a micro-optical resonator (microcavity) structure, which allows the light emitted from the light-emitting layer 87 to resonate between the pixel electrode 84 and the common electrode 81, thereby intensifying the light emitted from the light-emitting element 61.

[0251] When the light-emitting element 61 has a microcavity structure, it is preferable that one of the common electrode 81 and the pixel electrode 84 is an electrode having both light-transmitting and reflective properties (semi-transmissive / semi-reflective electrode), and the other of the common electrode 81 and the pixel electrode 84 is an electrode having reflective properties (reflective electrode). Here, the semi-transmissive / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode having transparency to visible light (also called a transparent electrode). The transparent electrode can be referred to as an optical adjustment layer.

[0252] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode for the light emitting element 61 that has a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm). The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 -2When a light-emitting element that emits near-infrared light is used in the display device, the transmittance and reflectance of these electrodes for near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less) are preferably within the above-mentioned ranges.

[0253] An insulating layer 92 is provided to cover the end portions of the pixel electrodes 84R, 84G, 84B, and 84PD. The end portions of the insulating layer 92 are preferably tapered. Note that the insulating layer 92 does not have to be provided if it is not necessary.

[0254] For example, the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. In addition, the end of the hole injection layer 85R, the end of the hole injection layer 85G, the end of the hole injection layer 85B, and the end of the hole transport layer 86PD are located on the insulating layer 92.

[0255] 17(A), between light-emitting elements 61 emitting light of different colors, a gap is provided, for example, between two light-emitting layers 87. In this manner, for example, light-emitting layer 87R, light-emitting layer 87G, and light-emitting layer 87B are preferably provided so as not to be in contact with one another. This makes it possible to preferably prevent current from flowing through two adjacent light-emitting layers 87, thereby preventing unintended light emission. This makes it possible to increase the contrast of the display device 10, thereby improving the display quality of the display device 10.

[0256] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has the function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0257] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0258] In this specification and the like, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

[0259] Alternatively, a laminated film of an inorganic insulating film and an organic insulating film may be used as the protective layer 91. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 91 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 91, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0260] 17(C) shows an example of a cross-sectional configuration of the display device 10 in the Y direction, specifically showing an example of a cross-sectional configuration of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting element 61G and the light-emitting element 61B can also be arranged in the Y direction in the same manner as the light-emitting element 61R.

[0261] 17(D) shows a connection portion 93 where the connection electrode 82 and the common electrode 81 are electrically connected. In the connection portion 93, the common electrode 81 is provided in contact with the connection electrode 82, and a protective layer 91 is provided to cover the common electrode 81. In addition, an insulating layer 92 is provided to cover the end of the connection electrode 82.

[0262] <Configuration example of light-emitting element> As shown in FIG. 18A, the light-emitting element has an EL layer 686 between a pair of electrodes (electrode 672 and electrode 688). The EL layer 686 can be formed with a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with a high electron-injecting property (electron-injecting layer) and a layer containing a substance with a high electron-transporting property (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole-injecting property (hole-injecting layer) and a layer containing a substance with a high hole-transporting property (hole-transporting layer).

[0263] A structure having the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 18A is referred to as a single structure in this specification.

[0264] 18(B) shows a modification of the EL layer 686 included in the light-emitting element shown in Fig. 18(A). Specifically, the light-emitting element shown in Fig. 18(B) includes a layer 4430-1 on an electrode 672, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and an electrode 688 on the layer 4420-2. For example, when the electrode 672 is an anode and the electrode 688 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. 18B, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0265] Note that a structure in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, and light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 18C is also a variation of the single structure.

[0266] 18(D), a configuration in which a plurality of light-emitting units (EL layer 686a, EL layer 686b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure. Note that in this specification, the configuration shown in FIG. 18(D) is referred to as a tandem structure, but is not limited thereto, and for example, the tandem structure may also be referred to as a stack structure. Note that a tandem structure can be used to provide a light-emitting element that can emit light with high brightness.

[0267] 18C and 18D, the layer 4420 and the layer 4430 may have a stacked structure including two or more layers as shown in FIG. 18B.

[0268] Furthermore, a structure in which each light-emitting element produces a different emission color (here, blue (B), green (G), and red (R)) is sometimes called an SBS (Side By Side) structure.

[0269] Furthermore, when comparing the above-mentioned single and tandem structures with the SBS structure, the order of decreasing power consumption is SBS, tandem, and single. If you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are simpler than those of the SBS structure, allowing for lower manufacturing costs or higher manufacturing yields.

[0270] The color of light emitted from the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 686. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0271] A light-emitting element that emits white light preferably has a structure in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected so that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a light-emitting element that emits white light as a whole can be obtained. The same applies to a light-emitting element having three or more light-emitting layers.

[0272] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0273] <Configuration example of light emitting element and light receiving element>

[0274] A display device according to one embodiment of the present invention is a top-emission display device that emits light in a direction opposite to a substrate on which a light-emitting element is formed. In this embodiment, a display device including a top-emission light-emitting element and a light-receiving element will be described as an example.

[0275] In this specification, unless otherwise specified, even when describing a configuration having a plurality of elements (e.g., light-emitting elements, light-emitting layers), when describing matters common to each element, the alphabet will be omitted. For example, when describing matters common to light-emitting layer 383R and light-emitting layer 383G, etc., they may be referred to as light-emitting layer 383.

[0276] The display device 380A shown in Figure 19 (A) has a light receiving element 370PD, a light emitting element 370R that emits red (R) light, a light emitting element 370G that emits green (G) light, and a light emitting element 370B that emits blue (B) light.

[0277] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. Light-emitting element 370R has a light-emitting layer 383R, light-emitting element 370G has a light-emitting layer 383G, and light-emitting element 370B has a light-emitting layer 383B. Light-emitting layer 383R contains a light-emitting material that emits red light, light-emitting layer 383G contains a light-emitting material that emits green light, and light-emitting layer 383B contains a light-emitting material that emits blue light.

[0278] The light emitting element is an electroluminescent element that emits light toward the common electrode 375 when a voltage is applied between the pixel electrode 371 and the common electrode 375 .

[0279] The light receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

[0280] The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0281] In this embodiment, in both the light-emitting element and the light-receiving element, the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. In other words, by applying a reverse bias between the pixel electrode 371 and the common electrode 375 and driving the light-receiving element, the light-receiving element can detect light incident on the light-receiving element, generate electric charges, and extract the electric charges as a current.

[0282] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can be configured in common with the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Therefore, the light-receiving element 370PD can be built into the display device without significantly increasing the number of manufacturing steps.

[0283] In the display device 380A, the light receiving element 370PD and the light emitting element have a common configuration, except that the active layer 373 of the light receiving element 370PD and the light emitting layer 383 of the light emitting element are fabricated separately. However, the configuration of the light receiving element 370PD and the light emitting element is not limited to this. The light receiving element 370PD and the light emitting element may have layers fabricated separately from each other, in addition to the active layer 373 and the light emitting layer 383. It is preferable that the light receiving element 370PD and the light emitting element have one or more layers used in common (common layers). This allows the light receiving element 370PD to be incorporated into the display device without significantly increasing the number of manufacturing steps.

[0284] A conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode 371 and the common electrode 375. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

[0285] The light-emitting element included in the display device of this embodiment preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element preferably has an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other preferably has an electrode that is reflective to visible light (reflective electrode). When the light-emitting element has a microcavity structure, light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0286] The semi-transmitting / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode that is transparent to visible light (also called a transparent electrode).

[0287] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the light emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is 1×10 -2 When the light-emitting element emits near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less), the transmittance or reflectance of these electrodes for near-infrared light preferably satisfies the above-mentioned numerical range, similar to the transmittance or reflectance for visible light.

[0288] The light-emitting element has at least a light-emitting layer 383. The light-emitting element may further have, in addition to the light-emitting layer 383, a layer containing a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole-blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, an electron-blocking material, a bipolar substance (a substance having a high electron-transporting property and a high hole-transporting property), or the like.

[0289] For example, the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common, or the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer formed differently from each other.

[0290] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0291] In a light-emitting element, the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. In a light-receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0292] In a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. In a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a 1×10 -6 cm 2 A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0293] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0294] The light-emitting layer 383 is a layer containing a light-emitting substance. The light-emitting layer 383 can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0295] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0296] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0297] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0298] The light-emitting layer 383 may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material can be used.

[0299] The light-emitting layer 383 preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This structure allows efficient emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting substance, the energy transfer becomes smooth, allowing efficient emission. This structure simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0300] As a combination of materials that form an exciplex, it is preferable that the HOMO level (highest occupied molecular orbital level) of the hole-transporting material is equal to or higher than the HOMO level of the electron-transporting material. It is also preferable that the LUMO level (lowest unoccupied molecular orbital level) of the hole-transporting material is equal to or higher than the LUMO level of the electron-transporting material. The LUMO level and HOMO level of the material can be derived from the electrochemical properties (reduction potential and oxidation potential) of the material measured by cyclic voltammetry (CV).

[0301] The formation of exciplexes can be confirmed, for example, by comparing the emission spectra of the hole-transporting material, the electron-transporting material, and the mixed film of these materials and observing the phenomenon that the emission spectrum of the mixed film is shifted to longer wavelengths than the emission spectra of each material (or has a new peak at longer wavelengths). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of the hole-transporting material, the transient PL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response, such as the transient PL lifetime of the mixed film having a longer-lived component or a larger proportion of delayed components than the transient PL lifetimes of the individual materials. The above-mentioned transient PL can also be interpreted as transient electroluminescence (EL). In other words, the formation of exciplexes can also be confirmed by comparing the transient EL of the hole-transporting material, the transient EL of the electron-transporting material, and the mixed film of these materials and observing differences in transient response.

[0302] The active layer 373 includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon and an organic semiconductor including an organic compound. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer 373 is shown. By using an organic semiconductor, the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum evaporation), which is preferable because a common manufacturing device can be used.

[0303] The active layer 373 has an n-type semiconductor material, such as fullerene (e.g., C 60 , C 70Examples of electron-accepting organic semiconductor materials include fullerene derivatives and other fullerenes. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when the π-electron conjugation (resonance) spreads on a plane, as in benzene, the electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the large spread of π-electrons. High electron-accepting properties allow charge separation to occur quickly and efficiently, making them useful as light-receiving elements. C 60 , C 70 Both have a wide absorption band in the visible light region, especially C 70 is C 60 It is preferable because it has a larger π-electron conjugated system and a broad absorption band in the long wavelength region compared to [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), and 1',1'',4',4''-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2'',3''][5,6]fullerene-C60 (abbreviation: ICBA).

[0304] Furthermore, examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0305] Examples of the p-type semiconductor material of the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0306] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0307] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0308] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0309] For example, the active layer 373 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or alternatively, the active layer 373 may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0310] The light-emitting element and the light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element and the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0311] For example, polymer compounds such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS) and inorganic compounds such as molybdenum oxide and copper iodide (CuI) can be used as hole-transporting materials, and inorganic compounds such as zinc oxide (ZnO) can be used as electron-transporting materials.

[0312] Furthermore, a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]]polymer (abbreviated as PBDB-T) or a PBDB-T derivative, which functions as a donor, can be used for the active layer 373. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0313] Furthermore, three or more types of materials may be mixed in the active layer 373. For example, in order to expand the wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0314] A display device 380B shown in FIG. 19(B) differs from the display device 380A in that a light receiving element 370PD and a light emitting element 370R have the same configuration.

[0315] The light receiving element 370PD and the light emitting element 370R have the active layer 373 and the light emitting layer 383R in common.

[0316] Here, it is preferable that light receiving element 370PD has the same configuration as a light emitting element that emits light of a longer wavelength than the light to be detected. For example, light receiving element 370PD configured to detect blue light can have the same configuration as one or both of light emitting element 370R and light emitting element 370G. For example, light receiving element 370PD configured to detect green light can have the same configuration as light emitting element 370R.

[0317] By using a common structure for the light-receiving element 370PD and the light-emitting element 370R, the number of film-forming steps and the number of masks can be reduced compared to a structure in which the light-receiving element 370PD and the light-emitting element 370R have separate layers, thereby reducing the manufacturing steps and manufacturing costs of the display device.

[0318] Furthermore, by using a common configuration for the light receiving element 370PD and the light emitting element 370R, the margin for misalignment can be narrowed compared to a configuration in which the light receiving element 370PD and the light emitting element 370R have separate layers. This allows for an increased pixel aperture ratio and improved light extraction efficiency of the display device. This also extends the life of the light emitting element. Furthermore, the display device can display high brightness. Furthermore, it also allows for higher resolution of the display device.

[0319] Light-emitting layer 383R includes a light-emitting material that emits red light. Active layer 373 includes an organic compound that absorbs light with a wavelength shorter than red (for example, one or both of green light and blue light). Active layer 373 preferably includes an organic compound that does not easily absorb red light and absorbs light with a wavelength shorter than red. This allows red light to be extracted efficiently from light-emitting element 370R, and light-receiving element 370PD to detect light with a wavelength shorter than red with high accuracy.

[0320] Furthermore, in the display device 380B, an example is shown in which the light emitting element 370R and the light receiving element 370PD have the same configuration, but the light emitting element 370R and the light receiving element 370PD may have optical adjustment layers of different thicknesses.

[0321] 20(A) and 20(B) includes a light receiving / emitting element 370SR, a light emitting element 370G, and a light emitting element 370B that emit red (R) light and have a light receiving function. The configuration of the light emitting element 370G and the light emitting element 370B can be based on the configuration of the display device 380A described above.

[0322] The light emitting / receiving element 370SR has, stacked in this order, a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, a light emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375. The light emitting / receiving element 370SR has the same configuration as the light emitting element 370R and the light receiving element 370PD exemplified in the display device 380B.

[0323] 20A shows a case where the light emitting / receiving element 370SR functions as a light emitting element. In FIG. 20A, an example is shown in which the light emitting element 370B emits blue light, the light emitting element 370G emits green light, and the light emitting / receiving element 370SR emits red light.

[0324] Fig. 20(B) shows a case where the light receiving / emitting element 370SR functions as a light receiving element. Fig. 20(B) shows an example where the light receiving / emitting element 370SR receives blue light emitted by the light emitting element 370B and green light emitted by the light emitting element 370G.

[0325] The light emitting element 370B, the light emitting element 370G, and the light emitting / receiving element 370SR each have a pixel electrode 371 and a common electrode 375. In this embodiment, a case will be described in which the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. The light emitting / receiving element 370SR is driven by applying a reverse bias between the pixel electrode 371 and the common electrode 375, so that the light emitting / receiving element 370SR can detect light incident on the light emitting / receiving element 370SR, generate electric charges, and extract the charges as a current.

[0326] The light emitting / receiving element 370SR can be said to have a configuration in which an active layer 373 is added to a light emitting element. In other words, the light emitting / receiving element 370SR can be formed in parallel with the formation of the light emitting element by simply adding a step of forming the active layer 373 to the manufacturing process of the light emitting element. Furthermore, the light emitting element and the light emitting / receiving element can be formed on the same substrate. Therefore, it is possible to provide the display unit with either or both of an imaging function and a sensing function without significantly increasing the manufacturing process.

[0327] There are no limitations on the stacking order of the light-emitting layer 383R and the active layer 373. Figures 20(A) and 20(B) show an example in which the active layer 373 is provided on the hole-transporting layer 382, ​​and the light-emitting layer 383R is provided on the active layer 373. The stacking order of the light-emitting layer 383R and the active layer 373 may be reversed.

[0328] Furthermore, the light emitting / receiving element may not have at least one layer selected from the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. The light emitting / receiving element may also have other functional layers such as a hole blocking layer and an electron blocking layer.

[0329] In the light emitting / receiving element, a conductive film that transmits visible light is used for the electrode on the light extraction side, and a conductive film that reflects visible light is preferably used for the electrode on the non-light extraction side.

[0330] The functions and materials of the layers constituting the light emitting / receiving element are similar to those of the layers constituting the light emitting element and the light receiving element, and therefore detailed description thereof will be omitted.

[0331] 20C to 20G show examples of stacked structures of light emitting and receiving elements.

[0332] The light emitting / receiving element shown in FIG. 20C includes a first electrode 377, a hole injection layer 381, a hole transport layer 382, ​​a light emitting layer 383R, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a second electrode 378.

[0333] FIG. 20C shows an example in which a light-emitting layer 383R is provided on a hole-transporting layer 382, ​​and an active layer 373 is stacked on the light-emitting layer 383R.

[0334] As shown in FIGS. 20(A) to 20(C), the active layer 373 and the light emitting layer 383R may be in contact with each other.

[0335] A buffer layer is preferably provided between the active layer 373 and the light-emitting layer 383R. In this case, the buffer layer preferably has hole-transporting and electron-transporting properties. For example, a bipolar substance is preferably used for the buffer layer. Alternatively, the buffer layer may be at least one layer selected from a hole-injection layer, a hole-transport layer, an electron-transport layer, an electron-injection layer, a hole-blocking layer, an electron-blocking layer, and the like. Figure 20(D) shows an example in which a hole-transporting layer 382 is used as the buffer layer.

[0336] By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, it is possible to suppress the transfer of excitation energy from the light-emitting layer 383R to the active layer 373. In addition, the buffer layer can be used to adjust the optical path length (cavity length) of the microcavity structure. Therefore, a light-emitting / receiving element having a buffer layer between the active layer 373 and the light-emitting layer 383R can obtain high light-emitting efficiency.

[0337] FIG. 20(E) shows an example of a laminated structure in which a hole transport layer 382-1, a light-emitting layer 383R, a hole transport layer 382-2, and an active layer 373 are laminated in this order on a hole injection layer 381. The hole transport layer 382-2 functions as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. Alternatively, the hole transport layer 382-2 may be replaced with a layer that can be used as a buffer layer. Alternatively, the positions of the active layer 373 and the light-emitting layer 383R may be interchanged.

[0338] 20(F) differs from the light-emitting / receiving element shown in Fig. 20(A) in that it does not have the hole transport layer 382. In this way, the light-emitting / receiving element may not have at least one layer among the hole injection layer 381, the hole transport layer 382, ​​the electron transport layer 384, and the electron injection layer 385. Furthermore, the light-emitting / receiving element may have other functional layers such as a hole blocking layer or an electron blocking layer.

[0339] The light emitting / receiving device shown in FIG. 20(G) differs from the light emitting / receiving device shown in FIG. 20(A) in that it does not have the active layer 373 and the light emitting layer 383R, but has a layer 389 that serves as both the light emitting layer and the active layer.

[0340] The layer that serves as both the light-emitting layer and the active layer can be, for example, a layer containing three materials: an n-type semiconductor that can be used for the active layer 373, a p-type semiconductor that can be used for the active layer 373, and a light-emitting substance that can be used for the light-emitting layer 383R.

[0341] It is preferable that the lowest energy absorption band in the absorption spectrum of the mixed material of n-type and p-type semiconductors does not overlap with the maximum peak in the emission spectrum (PL spectrum) of the luminescent substance, and it is more preferable that they are sufficiently separated from each other.

[0342] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0343] <Example of cross-sectional view configuration> 21 is a cross-sectional view showing a configuration example of the display device 10. The display device 10 has a configuration in which a transistor 310 having a channel formed in a substrate 301 and a transistor 320 having a channel formed in a semiconductor layer containing a metal oxide are stacked.

[0344] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and a transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0345] The transistor 320 can be used as a transistor that forms a pixel circuit or a transistor that forms a memory cell. The transistor 310 can be used as a transistor that forms a memory cell, a transistor that forms a driver circuit for driving the pixel circuit, or a transistor that forms an arithmetic circuit. The transistors 310 and 320 can be used as transistors that form various circuits such as an arithmetic circuit or a memory circuit.

[0346] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311 and functions as an insulating layer.

[0347] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0348] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0349] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0350] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0351] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0352] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties. The semiconductor layer 321 preferably includes a metal oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide for a channel formation region has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor as a transistor provided in a pixel circuit because analog data written to the pixel circuit can be retained for a long period of time. Similarly, it is preferable to use an OS transistor as a transistor used in a memory cell because analog data written to the memory cell can be retained for a long period of time.

[0353] A pair of conductive layers 325 is provided over and in contact with the semiconductor layer 321 and functions as a source electrode and a drain electrode.

[0354] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be formed using an insulating film similar to the insulating layer 332.

[0355] An opening is provided in the insulating layer 328 and the insulating layer 264, reaching the semiconductor layer 321. An insulating layer 323 and a conductive layer 324 are buried inside the opening and are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, as well as the top surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0356] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0357] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0358] A plug 274 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265 , the insulating layer 329 , and the insulating layer 264 .

[0359] Capacitor 240 has conductive layer 241, conductive layer 245, and insulating layer 243 positioned therebetween. Conductive layer 241 functions as one electrode of capacitor 240, conductive layer 245 functions as the other electrode of capacitor 240, and insulating layer 243 functions as a dielectric of capacitor 240.

[0360] The conductive layer 245 is provided over the insulating layer 265 and is buried in the insulating layer 254. The conductive layer 245 is electrically connected to one of the source and drain of the transistor 320 by a plug 274 buried in the insulating layers 328, 264, 329, and 265. The insulating layer 243 is provided to cover the conductive layer 245. The conductive layer 241 is provided in a region overlapping with the conductive layer 245 with the insulating layer 243 interposed therebetween.

[0361] An insulating layer 255 is provided to cover the capacitor 240, and a light emitting element 61, a light receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light emitting element 61 and the light receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. The substrate 420 can be a light-transmitting substrate.

[0362] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are electrically connected to either the source or drain of the transistor 320 by a plug 256 embedded in the insulating layer 255, a conductive layer 245 embedded in the insulating layer 254, and a plug 274 embedded in the insulating layers 328, 264, 329, and 265.

[0363] By using this configuration, it is possible to arrange OS transistors that constitute pixel circuits and memory cells directly below the light-receiving elements and light-emitting elements, and it is also possible to arrange driving circuits, arithmetic circuits, etc., making it possible to miniaturize a display device with high performance.

[0364] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0365] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0366] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0367] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0368] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0369] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0370] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0371] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0372] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0373] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0374] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0375] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0376] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0377] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0378] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0379] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B.

[0380] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0381] In this specification, a structure in which different light-emitting layers are created for each color light-emitting element (here, blue (B), green (G), and red (R)), or in which the light-emitting layers are painted differently, may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting element that can emit white light may be referred to as a white light-emitting element. In addition, a white light-emitting element can be combined with a colored layer (for example, a color filter) to form a light-emitting element that displays full color.

[0382] Furthermore, light-emitting elements can be broadly classified into a single structure and a tandem structure. A single-structure element has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration that emits white light from the entire light-emitting element can be obtained. The same applies to light-emitting elements having three or more light-emitting layers.

[0383] A tandem-structured element preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the light-emitting units may be combined to obtain white light. The structure for obtaining white light is the same as that of the single-structure element. In a tandem-structured element, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0384] Furthermore, when comparing the above-mentioned white light-emitting element (single structure or tandem structure) with a light-emitting element having an SBS structure, the light-emitting element having an SBS structure can reduce power consumption compared to the white light-emitting element. If you want to keep power consumption low, it is preferable to use a light-emitting element having an SBS structure. On the other hand, the manufacturing process of a white light-emitting element is simpler than that of a light-emitting element having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields. [Explanation of symbols]

[0385] 10_L Display device 10_R Display device 101 Case 102 Eyes 11 Circuit Board 12 PCB 13 Display section 14 Light receiving part 15 Terminal section 61 Light-emitting element 62 Photodetector

Claims

1. The device has a housing and a display device, the display device having a first layer, a second layer, and a third layer; the first layer, the second layer, and the third layer are provided on different layers, the first layer has a driving circuit and an arithmetic circuit; the second layer includes a pixel circuit and a cell array; the third layer has a light receiving device and a light emitting device; the pixel circuit has a function of controlling light emission of the light-emitting device, the drive circuit has a function of controlling the pixel circuit, a light receiving section in which the light receiving device is arranged, the light receiving section being arranged to surround a display section in which the light emitting device is arranged, in a plan view; the arithmetic circuit has a function of performing a product-sum operation based on first data corresponding to a current output by the light-receiving device and second data corresponding to a potential held in the cell array, the cell array is arranged to overlap with the arithmetic circuit, the housing has a function of disposing the display device at a position where it can capture an image of a user's eye; The light receiving device is an electronic device having a function of capturing an image of the user's eye and / or the area around the eye.

2. In claim 1, the first layer includes a first transistor having a semiconductor layer having silicon in a channel formation region; The second layer includes a second transistor having a semiconductor layer having a metal oxide in a channel formation region.

Images