Display substrate and manufacturing method thereof, display device

Abstract

To provide a display substrate and a manufacturing method thereof, and a display device.SOLUTION: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate comprises: a base substrate including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are provided in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers, the plurality of power lines are configured to supply a plurality of power supply voltages to the plurality of cascaded first shift registers included in the first scan driving circuit, the first signal line group includes at least one timing signal line, the second signal line group includes a first trigger signal line configured to supply a first trigger signal to the first shift register of the first stage, and the first trigger signal line is located between the plurality of power lines and the pixel array region. The display substrate facilitates the introduction of signal lines and is advantageous for realizing the display of a large-size display panel.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device. [Background technology]

[0002] In the display technology field, for example, a pixel array of a liquid crystal display panel or an organic light-emitting diode (OLED) display panel generally includes multiple rows of gate lines and multiple columns of data lines intersecting the gate lines. The gate lines may be driven by a bonded integrated driving circuit. In recent years, with the continuous improvement of manufacturing processes for amorphous silicon thin film transistors or oxide thin film transistors, it has become possible to directly integrate a gate line driving circuit on a thin film transistor array substrate to form a Gate Driver On Array (GOA) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to supply on-off voltage signals (scanning signals) to multiple rows of gate lines in a pixel array, thereby controlling the sequential turning-on of the multiple rows of gate lines and generating grayscale voltages required for each grayscale of a display image in each pixel cell, thereby supplying data signals to pixel cells in corresponding rows in the pixel array via the data lines, so as to display one frame of an image. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure provides a display substrate including: a base substrate including a pixel array region and a peripheral region; and a first scan drive circuit, a plurality of power supply lines, a first signal line group, and a second signal line group, the first scan drive circuit being disposed in the peripheral region and located on a first side of the base substrate. The first scan drive circuit includes a plurality of cascaded first shift registers, the plurality of power supply lines being configured to supply a plurality of power supply voltages to the cascaded first shift registers included in the first scan drive circuit, the first signal line group including at least one timing signal line configured to supply at least one timing signal to the cascaded first shift registers included in the first scan drive circuit, and the second signal line group including a first trigger signal line connected to a first-stage first shift register among the cascaded first shift registers included in the first scan drive circuit and configured to supply a first trigger signal to the first-stage first shift register, the first trigger signal line being located between the plurality of power supply lines and the pixel array region.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the second signal line group is located on a side of the first scanning drive circuit that is closer to the pixel array region, and the first signal line group is located on the other side of the first scanning drive circuit that is opposite to the side on which the second signal line group is located.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel array region includes a first display region and a second display region that are parallel to each other and do not overlap, the first scan drive circuit is connected to the first display region and drives the first display region for display, the display substrate further includes a second scan drive circuit provided in the peripheral region and located on a first side of the base substrate, the second scan drive circuit is arranged in sequence with the first scan drive circuit along the scanning direction of the pixel array and is connected to the second display region and drives the second display region for display, the second scan drive circuit includes a plurality of cascaded second shift registers, and the second signal line group further includes a second trigger signal line connected to a first-stage second shift register among the plurality of cascaded second shift registers included in the second scan drive circuit and supplies a second trigger signal to the first-stage second shift register included in the second scan drive circuit.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, the extension lengths of the first trigger signal line and the second trigger signal line are the same as the arrangement lengths of the first scan driving circuit and the second scan driving circuit.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the first trigger signal line and the second trigger signal line are arranged in parallel.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of power supply lines include a first power supply line and a second power supply line, and the first power supply line and the second power supply line are configured to supply the same first power supply voltage.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projection of the first power supply line onto the base substrate partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base substrate, and the orthogonal projection of the second power supply line onto the base substrate is located between the orthogonal projection of the first power supply line onto the base substrate and the orthogonal projection of the second signal line group onto the base substrate.

[0010] For example, a display substrate according to at least one embodiment of the present disclosure further includes at least one first resistor, the first resistor being located away from the first stage first shift register of the first scan driving circuit, and the first trigger signal line being connected to the first stage first shift register of the first scan driving circuit via the at least one first resistor.

[0011] For example, a display substrate according to at least one embodiment of the present disclosure further includes at least one second resistor, the second resistor being located between a first shift register in the final stage of the first scan driving circuit and a second shift register in the first stage of the second scan driving circuit, and the second trigger signal line being connected to the second shift register in the first stage of the second scan driving circuit via the at least one second resistor.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the first resistor and the second resistor have different resistance values.

[0013] For example, a display substrate according to at least one embodiment of the present disclosure further includes a folding line located between the first display area and the second display area, the second resistor is located in the extension direction of the folding line, and the extension direction of the folding line is perpendicular to the extension direction of the first signal line group and the second signal line group.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projection of the at least one second resistor onto the base substrate is located between the orthogonal projection of the first shift register in the final stage of the first scan driving circuit onto the base substrate and the orthogonal projection of the second shift register in the first stage of the second scan driving circuit onto the base substrate.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the at least one first resistor is located between the base substrate and the second signal line group in a direction perpendicular to the base substrate, and the orthogonal projection of the at least one first resistor onto the base substrate is located on the side away from the pixel array region of the orthogonal projection of the second signal line group onto the base substrate.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the material of the first resistor is a semiconductor material.

[0017] For example, a display substrate according to at least one embodiment of the present disclosure further includes at least one first connecting line and at least one second connecting line, wherein the first connecting line connects one end of the at least one first resistor to a first shift register of a first stage of the first scan driving circuit, and the second connecting line connects the other end of the at least one first resistor to the first trigger signal line.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the first connecting line and the second connecting line are located on a side of the at least one first resistor that is farther from the base substrate.

[0019] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first conductive connection portion, a second conductive connection portion, a first insulating layer, and a second insulating layer, wherein the first conductive connection portion and the second conductive connection portion are located on the side of the first connecting line and the second connecting line away from the base substrate and are provided in the same layer as the plurality of power supply lines, the first signal line group, and the second signal line group, the first insulating layer is located between the at least one first resistor and the first connecting line and the second connecting line in a direction perpendicular to the base substrate, and the second insulating layer is located between the first connecting line and the second connecting line and the first conductive connection portion and the second conductive connection portion in a direction perpendicular to the base substrate. One end of the first conductive connection portion is connected to one end of the first connection line via a through hole that penetrates the second insulating layer, the other end of the first conductive connection portion is connected to one end of the at least one first resistor via a through hole that penetrates the first insulating layer and the second insulating layer, the other end of the first connection line is connected to a first shift register of a first stage of the first scan driving circuit, one end of the second conductive connection portion is connected to one end of the second connection line via a through hole that penetrates the second insulating layer, the other end of the second conductive connection portion is connected to the other end of the at least one first resistor via a through hole that penetrates the first insulating layer and the second insulating layer, and the other end of the second connection line is connected to the first trigger signal line via a through hole that penetrates the second insulating layer.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, each first shift register of the first scanning drive circuit includes a first component transistor connected to the first power supply line, and a second component transistor and a third component transistor connected to the second power supply line, and the orthogonal projection of the first component transistor onto the base substrate is located between the orthogonal projection of the first signal line group onto the base substrate and the orthogonal projection of the first power supply line onto the base substrate, and is close to the orthogonal projection of the first power supply line onto the base substrate, and the orthogonal projection of the second component transistor and the third component transistor onto the base substrate is located between the orthogonal projection of the first power supply line onto the base substrate and the orthogonal projection of the second power supply line onto the base substrate, and is close to the orthogonal projection of the second power supply line onto the base substrate.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of power supply lines include a third power supply line and a fourth power supply line, the third power supply line and the fourth power supply line are configured to supply the same second power supply voltage, the orthogonal projection of the fourth power supply line onto the base substrate partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base substrate, and the orthogonal projection of the third power supply line onto the base substrate is located between the orthogonal projection of the fourth power supply line onto the base substrate and the orthogonal projection of the first signal line group onto the base substrate.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, each first shift register of the first scanning drive circuit further includes a fourth component transistor connected to the third power supply line and a fifth component transistor connected to the fourth power supply line, and the orthogonal projection of the fourth component transistor onto the base substrate is located on the side of the orthogonal projection of the third power supply line onto the base substrate that is away from the orthogonal projection of the first signal line group onto the base substrate and is close to the orthogonal projection of the third power supply line onto the base substrate, and the orthogonal projection of the fifth component transistor onto the base substrate is located between the orthogonal projection of the fourth power supply line onto the base substrate and the orthogonal projection of the second signal line group onto the base substrate and is close to the orthogonal projection of the fourth power supply line onto the base substrate.

[0023] At least one embodiment of the present disclosure provides a display substrate including a base substrate including a pixel array region and a peripheral region, and a first scanning drive circuit, a plurality of power lines, a first group of signal lines, and a second group of signal lines provided in the peripheral region and located on a first side of the base substrate. the first scan drive circuit includes a plurality of cascaded first shift registers, the plurality of power supply lines are configured to supply a plurality of power supply voltages to the cascaded first shift registers included in the first scan drive circuit; the first signal line group includes at least one timing signal line configured to supply at least one timing signal to the cascaded first shift registers included in the first scan drive circuit; the second signal line group includes a first trigger signal line connected to a first-stage first shift register among the cascaded first shift registers included in the first scan drive circuit and configured to supply a first trigger signal to the first-stage first shift register; the first scan drive circuit includes a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor being connected to the first signal line group, respectively; and the extension directions of channels of the first transistor, the second transistor, and the third transistor are parallel to the extension directions of the first signal line group and the second signal line group.

[0024] For example, in at least one embodiment of the display substrate of the present disclosure, the first scanning driving circuit further includes a sixth transistor and a seventh transistor connected to the first signal line group, respectively, and the extension direction of the channels of the sixth transistor and the seventh transistor is parallel to the extension direction of the first signal line group and the second signal line group.

[0025] At least one embodiment of the present disclosure further provides a display device including a display substrate according to any embodiment of the present disclosure.

[0026] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, the method including the steps of providing a base substrate, and sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the base substrate, wherein the power supply lines, the first group of signal lines, and the second group of signal lines are located on the third conductive layer, the first scanning driving circuit is formed on the semiconductor layer, the first conductive layer, and the second conductive layer, and the first scanning driving circuit is connected to the power supply lines, the first group of signal lines, and the second group of signal lines via through holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer, respectively. [Brief explanation of the drawings]

[0027] In order to more clearly describe the technical solutions of the embodiments of the present invention, the drawings of the embodiments are briefly described below. It is obvious that the drawings in the following description only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0028] [Figure 1] FIG. 2 is a circuit diagram of a light emission control shift register. [Figure 2] 2 is a signal timing chart during operation of the light emission control shift register shown in FIG. 1. [Figure 3] FIG. 2 is a schematic diagram of a first resistor and a second resistor in accordance with at least one embodiment of the present disclosure. [Figure 4] 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] FIG. 1 is a schematic diagram illustrating a layout of a display substrate according to at least one embodiment of the present disclosure. [Figure 5B] FIG. 10 is a schematic layout diagram of a display substrate including a first-stage shift register of a second scan driving circuit. [Figure 6A] 5B is a plan view of the wiring in each layer of the display substrate shown in FIG. 5A. FIG. [Figure 6B] 5C is a plan view of wiring in each layer of the first-stage shift register included in the display substrate shown in FIG. 5B. FIG. [Figure 7A]5B is a plan view of the wiring in each layer of the display substrate shown in FIG. 5A. FIG. [Figure 7B] 5C is a plan view of wiring in each layer of the first-stage shift register included in the display substrate shown in FIG. 5B. FIG. [Figure 8] 5B is a plan view of wiring in each layer of the display substrate shown in FIG. 5A and a plan view of wiring in each layer of the first-stage shift register included in the display substrate shown in FIG. 5A. [Figure 9A] 5B is a plan view of the wiring in each layer of the display substrate shown in FIG. 5A. FIG. [Figure 9B] 5C is a plan view of wiring in each layer of the first-stage shift register included in the display substrate shown in FIG. 5B. FIG. [Figure 10] 5C is a cross-sectional view of the display substrate shown in FIG. 5B taken along the line AA'. [Figure 11] 1 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. [Figure 12] 1 is a flowchart of a method for manufacturing a display substrate in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present invention, the following will clearly and completely describe the technical solutions of the embodiments of the present invention with reference to the drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the described embodiments of the present invention, all other embodiments that can be obtained by those skilled in the art without any creative work are all included in the protection scope of the present invention.

[0030] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meaning as understood by a person of ordinary skill in the field to which this invention pertains. As used in this disclosure, the terms "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, the terms "one," "an," "the," and similar terms do not limit quantity but indicate the presence of at least one. Similar terms such as "comprises" and "includes" are intended to include the listed elements or items and their equivalents, but do not exclude other elements or items. Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections and may include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," and "right" are merely intended to indicate relative positions, and if the absolute position of the described objects is changed, the relative positions may change accordingly.

[0031] The present disclosure will be described below with reference to several specific embodiments. In order to make the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present invention is shown in more than one drawing, the same reference numeral will be used in each drawing.

[0032] Fig. 1 is a circuit diagram of the light-emission control shift register. Fig. 2 is a signal timing chart during operation of the light-emission control shift register shown in Fig. 1. The operation process of the light-emission control shift register will be briefly described below with reference to Figs. 1 and 2.

[0033] 1, the light-emitting control shift register 100 includes ten transistors (a first transistor T1, a second transistor T2, ..., a tenth transistor T10) and three capacitors (a first capacitor C1, a second capacitor C2, and a third capacitor C3). For example, when a plurality of light-emitting control shift registers 100 are cascaded, the first electrode of the first transistor T1 of the first-stage shift register 100 is connected to the first trigger signal line ESTV1 to receive the first trigger signal ESTV1, and the first electrode of the first transistor T1 of each of the other stages of the light-emitting control shift register 100 is connected to the previous-stage light-emitting control shift register 100 to receive the first output signal EM output from the previous-stage light-emitting control shift register 100.

[0034] 1 and 2, CK denotes a first clock signal terminal, ECK denotes a first clock signal line and a first clock signal, the first clock signal terminal CK being connected to the first clock signal line ECK to receive the first clock signal, CB denotes a second clock signal terminal, ECB denotes a second clock signal line and a second clock signal, the second clock signal terminal CB being connected to the second clock signal line ECB to receive the second clock signal. For example, the first clock signal ECK and the second clock signal ECB may be pulse signals with a duty ratio greater than 50%. VGH1 denotes a first power line and a first power voltage supplied by the first power line, for example, the first power voltage is a DC high level. VGL1 denotes a third power line and a second power voltage supplied by the third power line, for example, the second power voltage is a DC low level and the first power voltage is greater than the second power voltage. N1, N2, N3, and N4 denote a first node, a second node, a third node, and a fourth node, respectively.

[0035] 1, the gate of the first transistor T1 is connected to the first clock signal terminal CK (i.e., the first clock signal line ECK) to receive the first clock signal, the first pole of the first transistor T1 is connected to the input terminal IN, and the second pole of the first transistor T1 is connected to the first node N1. For example, if the light-emitting control shift register is a first-stage shift register, the input terminal IN is connected to the first trigger signal line ESTV1 to receive the first trigger signal, and if the light-emitting control shift register is a shift register of any stage other than the first-stage shift register, the input terminal IN is connected to the output terminal OUT of the light-emitting control shift register of the previous stage.

[0036] The gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the first clock signal line ECK to receive the first clock signal, and the second pole of the second transistor T2 is connected to the second node N2.

[0037] The gate of the third transistor T3 is connected to the first clock signal line ECK to receive the first clock signal, the first electrode of the third transistor T3 is connected to the third power supply line VGL1 to receive the second power supply voltage, and the second electrode of the third transistor T3 is connected to the second node N2.

[0038] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (i.e., the second clock signal line ECB) to receive the second clock signal, the first pole of the fourth transistor T4 is connected to the first node N1, and the second pole of the fourth transistor T4 is connected to the first pole of the fifth transistor T5.

[0039] The gate of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the first power supply line VGH to receive the first power supply voltage.

[0040] The gate of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second clock signal line ECB to receive the second clock signal, and the second electrode of the sixth transistor T6 is connected to the third node N3.

[0041] A first end of the first capacitor C1 is connected to the second node N2, and a second end of the first capacitor C2 is connected to the third node N3.

[0042] The gate of the seventh transistor T7 is connected to the second clock signal line ECB to receive the second clock signal, the first gate of the seventh transistor T7 is connected to the third node N3, and the second gate of the seventh transistor T7 is connected to the fourth node N4.

[0043] The gate of the eighth transistor T8 is connected to the first node N1, the first electrode of the eighth transistor T8 is connected to the first power supply line VGH1 to receive the first power supply voltage, and the second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0044] The gate of the ninth transistor T9 is connected to the fourth node N4, the first electrode of the ninth transistor T9 is connected to the first power supply line VGH1 to receive the first power supply voltage, and the second electrode of the ninth transistor T9 is connected to the output terminal OUT.

[0045] A first end of the third capacitor C3 is connected to the fourth node N4, and a second end of the third capacitor C3 is connected to the first power supply line VGH1 to receive the first power supply voltage.

[0046] The gate of the tenth transistor T10 is connected to the first node N1, the first electrode of the tenth transistor T10 is connected to the third power supply line VGL1 to receive the second power supply voltage, and the second electrode of the tenth transistor T10 is connected to the output terminal OUT.

[0047] A first end of the second capacitor C2 is connected to the second clock signal line ECB to receive the second clock signal, and a second end of the second capacitor C2 is connected to the first node N1.

[0048] 1 are all P-type transistors, that is, each transistor is turned on when a low level is input to its gate and turned off when a high level is input to its gate. In this case, the first electrode may be the source, and the second electrode may be the drain.

[0049] The embodiments of the present disclosure include, but are not limited to, the configuration shown in FIG. 1 . For example, each transistor in the light-emission control shift register 100 may be an N-type transistor, or a combination of P-type and N-type transistors, and the port polarity of the selected type of transistor may be connected according to the port polarity of the corresponding transistor in the embodiments of the present disclosure.

[0050] 2 is a signal timing chart during operation of the light-emission control shift register shown in FIG. The operation process of the light-emission control shift register will be described in detail below with reference to FIGS. 1 and 2. For example, the operation principle of the first-stage light-emission control shift register 100 will be described, and the operation principles of the light-emission control shift registers 100 of the other stages will not be described in detail because they are similar. As shown in FIG. 2, the operation process of the light-emission control shift register includes six stages, namely, a first stage P1, a second stage P2, a third stage P3, a fourth stage P4, a fifth stage P5, and a sixth stage P6, and FIG. 2 shows the time-series waveforms of the signals at each stage.

[0051] In the first stage P1, as shown in FIG. 2, the first clock signal ECK is low, so the first transistor T1 and the third transistor T3 are turned on. The turned-on first transistor T1 transmits a high-level first trigger signal ESTV1 to the first node N1, causing the first node N1 to go high. This turns off the second transistor T2, the eighth transistor T8, and the tenth transistor T10. The turned-on third transistor T3 transmits a low-level second power supply voltage VGL1 to the second node N2, causing the second node N2 to go low. This turns on the fifth transistor T5 and the sixth transistor T6. The second clock signal ECB is high, so the seventh transistor T7 is turned off. The storage function of the third capacitor C3 maintains the fourth node N4 at a high level, causing the ninth transistor T9 to go off. In the first stage P1, the ninth transistor T9 and the tenth transistor T10 are both turned off, so that the first output signal output from the output terminal OUT_1 of the light-emitting control shift register 100 is maintained at the previous low level.

[0052] In the second stage P2, as shown in FIG. 4, the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. The first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off. The second node N2 continues to be held at a low level from the previous stage due to the storage effect of the first capacitor C1, so the fifth transistor T5 and the sixth transistor T6 are turned on. The first power supply voltage VGH1, which is at a high level, is transmitted to the first node N1 via the fifth transistor T5 and the fourth transistor T4, which are turned on, so the level of the first node N1 continues to be held at a high level from the previous stage, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Furthermore, since the low-level second clock signal ECB is transmitted to the fourth node N4 via the sixth transistor T6 and the seventh transistor T7 that are turned on, the level of the fourth node N4 becomes low, so that the ninth transistor T9 is turned on. The turned-on ninth transistor T9 outputs a high-level first power supply voltage VGH1, so that in the second stage P2, the first output signal output from the output terminal OUT_1 of the light-emitting control shift register 100 is high.

[0053] In the third stage P3, as shown in FIG. 4, the first clock signal ECK is low, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is high, so the fourth transistor T4 and the seventh transistor T7 are turned off. The storage effect of the third capacitor C3 maintains the fourth node N4 at the low level of the previous stage, so that the ninth transistor T9 is maintained in an on state. The turned-on ninth transistor T9 outputs a high-level first power supply voltage VGH1. Therefore, in the third stage P3, the output signal from the output terminal OUT_1 of the light-emitting control shift register 100 remains high. At the same time, in this stage, a high level is output from the output terminal OUT_2 of the second-stage light-emitting control shift register 100 (see, for example, the operation process of the first-stage light-emitting control shift register in the second stage P2).

[0054] In the fourth stage P4, as shown in FIG. 4, the first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the storage effect of the second capacitor C2, the level of the first node N1 is maintained at the high level of the previous stage, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 continues to be maintained at the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, since the low-level second clock signal ECB is transmitted to the fourth node N4 via the sixth transistor T6 and the seventh transistor T7, which are turned on, the fourth node N4 becomes low, so that the ninth transistor T9 is turned on and outputs a high-level first power supply voltage VGH1. Therefore, in the second stage P2, the first output signal output from the output terminal OUT_1 of the light-emitting control shift register 100 remains high. At the same time, in this stage, the output terminal OUT_2 of the second-stage light-emitting control shift register 100 outputs a high level (specifically, see the operation process of the first-stage light-emitting control shift register in the third stage P3).

[0055] 4, in the fifth stage P5, the first clock signal ECK is at a low level, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. The turned-on first transistor T1 transmits the first trigger signal ESTV of a low level to the first node N1 so that the level of the first node N1 becomes a low level.

[0056] For example, in the fifth stage P5, the low-level voltage of the first clock signal ECK is −6 V, the low-level voltage of the first trigger signal ESTV1 is −6 V, and the threshold voltage Vth of the first transistor T1 is −1.5 V. Because the first transistor T1 is a P-type transistor, the gate-source voltage Vgs of the first transistor T1 must be smaller than the threshold voltage Vth of the first transistor T1 so that the first transistor T1 is turned on. Therefore, when the first node N1 is charged to −4.5 V, the first transistor T1 is turned off, and in this case, charging to the first node N1 is stopped. That is, since the low-level voltage of the first node N1 is −4.5 V at this stage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on. The second transistor T2, which has been turned on, transmits a low-level first clock signal ECK to the second node N2, thereby further lowering the level of the second node N2, so that the second node N2 continues to be held at the low level of the previous stage, thereby turning on the fifth transistor T5 and the sixth transistor T6. Meanwhile, the eighth transistor T8, which has been turned on, transmits a high-level first power supply voltage VGH1 to the fourth node N4, thereby raising the level of the fourth node N4 to a high level, so that the ninth transistor T9 is turned off. The tenth transistor T10, which has been turned on, outputs a low-level second power supply voltage VGL (e.g., −6 V) in response to the low level (e.g., −4.5 V) of the first node N1. Similarly, the threshold voltage Vth of the tenth transistor T10 is −1.5 V, and the gate-source voltage Vgs of the tenth transistor T10 needs to be smaller than the threshold voltage Vth of the tenth transistor T10 so that the tenth transistor T10 is turned on. Therefore, when the voltage output from the output terminal OUT is −3 V, the tenth transistor T10 is turned off. That is, at this stage, the low-level voltage of the output terminal OUT is −3 V, and therefore, at the fifth stage P5, the output signal output from the output terminal OUT_1 of the light-emitting control shift register 100 becomes a first low level (e.g., −3 V).At the same time, at this stage, a high level is output from the output terminal OUT_2 of the second-stage light-emission control shift register 100 (specifically, the operation process of the first-stage light-emission control shift register in the fourth stage P4 may be referred to).

[0057] 4, in the sixth stage P6, the first clock signal ECK is at a high level and the second clock signal ECB is at a low level, so that the fourth transistor T4 and the seventh transistor T7 are turned on. As the second clock signal ECB changes from a high level in the fifth stage P5 to a low level, for example, by an amount of change Δt (e.g., greater than 6 V), the level of the first node N1 changes from a low level (e.g., −4.5 V) in the fifth stage P5 to a lower low level (e.g., −4.5 V−Δt) due to the bootstrap effect of the second capacitor C2. As a result, the second transistor T2 and the tenth transistor T10 are turned on under the control of the low level (e.g., −4.5 V−Δt) of the first node N1. Due to the conduction characteristic of the tenth transistor T10, the low level of the second power supply voltage VGL (e.g., −6 V) can be fully output to the output terminal OUT. For example, in this sixth stage P6, the voltage output from the output terminal OUT is a second low level (e.g., −6 V). At the same time, in this stage, a low level (e.g., −3 V; specifically, the operation process of the first shift register of the first stage in the fourth stage P4 may be referred to) is output from the output terminal OUT_2 of the second-stage first shift register 100.

[0058] For example, as shown in Fig. 1, the wiring is densely packed on the left side of the display substrate, leaving relatively little space for the first trigger signal line ESTV1, making it inconvenient to introduce multiple trigger signal lines.In addition, as shown in Fig. 1, there is only one first power supply line VGH1, and the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are wound around to be connected to the first power supply line VGH1, which takes up a large amount of space in the vertical direction of the display substrate, which is disadvantageous in layout design of the display substrate.

[0059] At least one embodiment of the present disclosure provides a display substrate including a base substrate including a pixel array region and a peripheral region, and a first scan drive circuit, a plurality of power supply lines, a first signal line group, and a second signal line group provided in the peripheral region and located on a first side of the base substrate, wherein the first scan drive circuit includes a plurality of cascaded first shift registers, the plurality of power supply lines being configured to supply a plurality of power supply voltages to the cascaded first shift registers included in the first scan drive circuit, the first signal line group including at least one timing signal line configured to supply at least one timing signal to the cascaded first shift registers included in the first scan drive circuit, and the second signal line group including a first trigger signal line located between the plurality of power supply lines and the pixel array region, the first trigger signal line being connected to a first-stage first shift register among the cascaded first shift registers included in the first scan drive circuit and configured to supply a first trigger signal to the first-stage first shift register.

[0060] At least one embodiment of the present disclosure further provides a display device and a manufacturing method corresponding to the display substrate.

[0061] In the display substrate according to the above embodiment of the present disclosure, the first trigger signal line is arranged between the plurality of power supply lines and the pixel array area, which makes it easy to introduce the signal line and is advantageous for realizing the display of a large-sized display panel.

[0062] Hereinafter, embodiments and some examples of the present disclosure will be described in detail with reference to the accompanying drawings.

[0063] At least one embodiment of the present disclosure provides a display substrate. For example, the display substrate may be applied to a scan driving circuit with one driver per row, i.e., an output signal output from a single-stage shift register drives only one row of pixel cells. Compared with a scan driving circuit with two drivers per row, a scan driving circuit with one driver per row reduces the load that needs to be driven by half, thereby providing stronger driving capability and being more suitable for displaying on a large-sized display panel.

[0064] In addition, the display substrate may also be applied to a single-row double-drive scan driving circuit, that is, an output signal output from one stage of a shift register can drive two rows of pixel cells, and the embodiments of the present disclosure are not limited thereto.

[0065] 4 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. The display substrate 1 includes, for example, a base substrate 10, a first scan driving circuit 130, a plurality of power lines 140, a first signal line group 150, and a second signal line group 160, as shown in FIG.

[0066] For example, the base substrate 100 may be made of a suitable material, such as glass, plastic, quartz, etc., and the embodiments of the present disclosure are not limited thereto. For example, the base substrate 10 includes a pixel array region 110 and a peripheral region 120. A first scan driving circuit 130, a plurality of power lines 140, a first group of signal lines 150, and a second group of signal lines 160 are disposed in the peripheral region 120 and located on a first side of the base substrate 10, for example, on the left side of the base substrate 10.

[0067] The pixel array region 110 includes, for example, a plurality of pixel cells P arranged in an array. For example, each of the plurality of pixel cells P includes a pixel circuit, and may further include, for example, a light-emitting element (not shown).

[0068] For example, the first scan driving circuit 130 includes a plurality of cascaded first shift registers 100, such as a plurality of shift registers 100 as shown in FIG. 1. For clarity and brevity, the first shift register 100 will be referred to as shift register 100 hereinafter. This also applies to the following embodiments, and will not be described in detail. For example, the output terminals of the plurality of shift registers 100 are respectively connected to the emission control terminals of the pixel circuits of each row located in the pixel array area to provide output signals (e.g., emission control signals) to the pixel circuits of each row, thereby driving the light-emitting elements to emit light. For example, the pixel circuits may be pixel circuits including circuit configurations known in the art, such as 2T1C, 4T2C, 8T2C, etc., and will not be described in detail here.

[0069] For example, the first scan driving circuit 130 includes at least one transistor, and the extension direction of the channel of the at least one transistor is parallel to the extension direction of the first signal line group 150 and the second signal line group 160, thereby reducing the area of ​​the first scan driving circuit 130 in the direction perpendicular to the length direction of the channel, improving process consistency, and producing a relatively favorable channel effect.

[0070] For example, the first scan driving circuit 130 includes a first transistor T1, a second transistor T2, and a third transistor T3, each connected to a first signal line group 150, e.g., a first clock signal ECK of the first signal line group 150. For example, the extension direction of the channels of the first transistor T1, the second transistor T2, and the third transistor T3 is parallel to the extension direction of the first signal line group 150 and the second signal line group 160. For example, the extension direction of the channel is the extension direction from the first pole to the second pole of the transistor, e.g., the extension direction from the first pole to the second pole of the first transistor T1.

[0071] For example, the first scanning driving circuit 130 further includes a sixth transistor T6 and a seventh transistor T7 respectively connected to the first signal line group 150, and the extension direction of the channels of the sixth transistor T6 and the seventh transistor T7 is parallel to the extension direction of the first signal line group 150 and the second signal line group 160.

[0072] For example, the multiple power supply lines 140 are configured to supply multiple power supply voltages, such as a first power supply voltage (e.g., a high level DC) and a second power supply voltage (e.g., a low level DC), to the multiple cascaded shift registers 100 included in the first scan drive circuit 130.

[0073] The first signal line group 150 includes at least one timing signal line, for example, the first clock signal line ECK and the second clock signal line ECB, configured to supply at least one timing signal, for example, the first clock signal ECK and the second clock signal ECB, to a plurality of cascaded shift registers 100 included in the first scan drive circuit 130.

[0074] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1 that is connected to a first-stage shift register among the plurality of cascaded shift registers 100 included in the first scan drive circuit 150 and is configured to supply a first trigger signal to the first-stage shift register. For example, the first trigger signal line ESTV1 is located between the plurality of power supply lines 140 and the pixel array region 110. For example, as shown in FIG. 4 , the first trigger signal line ESTV1 may be located to the right of the first scan drive circuit 130, that is, the orthogonal projection of the first trigger signal line ESTV1 onto the base substrate 10 is located between the orthogonal projection of the first scan drive circuit 130 onto the base substrate 10 and the orthogonal projection of the pixel array region 110 onto the base substrate 10. Naturally, the first trigger signal line ESTV1 may be located between the transistors of the first scan drive circuit 130, i.e., the orthogonal projection of the first trigger signal line ESTV1 onto the base substrate 10 at least partially overlaps with the orthogonal projection of the first scan drive circuit 130 onto the base substrate 10, and the trigger signal line may be located in an area where wiring is not densely packed to facilitate the introduction of the trigger signal line, and the embodiments of the present disclosure are not limited thereto.

[0075] In addition, the display substrate may further include a plurality of scan driving circuits and a plurality of trigger signal lines respectively connected to the first stage shift registers of the plurality of scan driving circuits, and the embodiments of the present disclosure are not limited thereto.

[0076] For example, in some cases, when the display substrate further includes a plurality of scan drive circuits such as a second scan drive circuit and a third scan drive circuit, the display substrate further includes a plurality of trigger signal lines such as a second trigger signal line ESTV2 connected to the first-stage shift register of the second scan drive circuit and a third trigger signal line connected to the first-stage shift register of the third scan drive circuit. For example, the plurality of scan drive circuits such as the second scan drive circuit and the third scan drive circuit have the same configuration as the first scan drive circuit, are arranged sequentially from the first scan drive circuit, and together drive a pixel array region of the display substrate. For example, the pixel array region includes a plurality of display regions that do not overlap each other (for example, are arranged side by side), and the plurality of scan drive circuits such as the first scan drive circuit, the second scan drive circuit, and the third scan drive circuit each drive a corresponding display region.

[0077] For example, when a plurality of scan driving circuits are included, the second signal line group 160 further includes the plurality of trigger signal lines. For example, the plurality of trigger signal lines may be located between the plurality of power lines 140 and the pixel array region 110, for example, to the right of each scan driving circuit or at least overlapping each scan driving circuit. For ease of introduction of the trigger signal lines, it is sufficient that they are located in an area where wiring is not densely packed, and the embodiment of the present disclosure is not limited thereto.

[0078] The display substrate according to the above embodiment of the present disclosure adjusts the position of the first trigger signal line, thereby avoiding problems such as the inability to introduce more signal lines due to dense wiring and winding connections, which is more advantageous for realizing a narrow frame design for the display panel, and thus for realizing the display of a large-sized display panel.

[0079] Fig. 5A is a schematic layout diagram of a display substrate according to at least one embodiment of the present disclosure. Fig. 5B is a schematic layout diagram of a display substrate including a first-stage shift register of a second scan driving circuit. Fig. 10 is a cross-sectional view of the display substrate shown in Fig. 5B along the AA' direction. Naturally, Fig. 10 may be used to explain the stacked configuration shown in Fig. 5A.

[0080] The stacked configuration of the first-stage shift register shown in FIG. 5B may be applied to the first-stage shift register of each scan drive circuit by simply changing the connection with the corresponding trigger signal, i.e., the first-stage shift register of the first scan drive circuit is connected to the first trigger signal line ESTV1, the first-stage shift register of the second scan drive circuit is connected to the second trigger signal line ESTV2, and so on.

[0081] Figures 6A, 7A, 8, and 9A respectively show plan views of wiring in each layer of the display substrate shown in Figure 5A. Figure 6A is a plan view of a semiconductor layer of a display substrate according to at least one embodiment of the present disclosure, Figure 7A is a plan view of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure, Figure 8 is a plan view of a second conductive layer of a display substrate according to at least one embodiment of the present disclosure, and Figure 9A is a plan view of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure.

[0082] For example, interlayer insulating layers (including, for example, a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located between the layer configurations shown in Figures 6A to 9A. For example, first insulating layer 350 (as shown in Figure 10) is located between semiconductor layer 310 shown in Figure 6A and first conductive layer 320 shown in Figure 7A, second insulating layer 360 (as shown in Figure 10) is located between first conductive layer 320 shown in Figure 7A and second conductive layer 330 shown in Figure 8, and third insulating layer 370 (as shown in Figure 10) is located between second conductive layer 330 shown in Figure 8 and third conductive layer 340 shown in Figure 9A.

[0083] For example, as shown in FIG. 10, the display substrate further includes a fourth insulating layer 380, which is located on the third conductive layer 340 and is used to protect the third conductive layer 340.

[0084] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resin, or other suitable materials, and the embodiments of the present disclosure are not limited in this regard.

[0085] Note that the display substrate shown in FIG. 5A will be described using the layout design of one shift register and the signal lines connected thereto in the first scan driving circuit as an example. The layout embodiments of the shift registers in the other stages may refer to the layout form shown in FIG. 5A and will not be described in detail here. Needless to say, other layout forms may be adopted, and the embodiments of the present disclosure are not limited thereto. Naturally, the shift registers in the other stages of the scan driving circuits may also refer to the layout form shown in FIG. 5A or use other layout forms, and the embodiments of the present disclosure are not limited thereto.

[0086] Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described in detail with reference to FIGS. 5A to 9A.

[0087] For example, the first transistor T1 to the tenth transistor T10 of the shift register 100 shown in FIG. 5A may be formed on a semiconductor layer 310 shown in FIG. 6A. The semiconductor layer 310 may be formed by patterning a semiconductor material. The semiconductor layer 310 may have a short rod shape or a curved or bent shape as needed, as shown in FIG. 6A, and may be used to fabricate the active layers of the first transistor T1 to the tenth transistor T10. Each active layer may include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region may be doped with impurities to have semiconductor properties, and the source region and the drain region may be doped with impurities to have conductivity on both sides of the channel region. For example, the source region corresponds to the source (also called the first pole) of the transistor, and the drain region corresponds to the drain (also called the second pole) of the transistor. 10, taking the first transistor T1 as an example, the active layer of the first transistor T1 includes a source region S1, a drain region D1 (as indicated by the dashed lines in FIG. 10), and a channel region P1, and the first transistor T1 further includes a gate G1, which is located in the first conductive layer 320 and will be described below, so will not be described in detail here. Note that although the drain region D1 of the first transistor T1 is not shown in the cross-sectional view taken along the line AA′ in FIG. 5B, for clarity, the drain region D1 of the first transistor T1 is added in FIG. 10 by a dashed line.

[0088] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon may include low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., but the embodiments of the present disclosure are not limited thereto. Note that the source region and drain region may be regions doped with n-type impurities or p-type impurities, but the embodiments of the present disclosure are not limited thereto.

[0089] In other examples, the first and second poles of each transistor may be located in other conductive layers and connected to the corresponding active layers via through holes in an insulating layer located between the semiconductor layer and the first and second poles, and the embodiments of the present disclosure are not limited thereto.

[0090] 7A shows the first conductive layer 320 of the display substrate. The first conductive layer 320 is provided on a first insulating layer, thereby being insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include the first electrodes CE11, CE12, and CE13 of the first capacitor C1 through the third capacitor C3 and the gates of the first transistor T1 through the tenth transistor T10, and accordingly, the first insulating layer also serves as a gate insulating layer. As shown in FIG. 7A, the gates of the first transistor T1 through the tenth transistor T10 are portions where the semiconductor layer configuration of each transistor overlaps with the wiring of the first conductive layer 320.

[0091] 8 shows the second conductive layer 330 of the display substrate. The second conductive layer 330 includes second electrodes CE21, CE22, and CE23 of the first to third capacitors C1 to C3. For example, the second electrode CE21 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 at least partially overlaps with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 at least partially overlaps with the first electrode CE13 to form the third capacitor C3.

[0092] 9A shows the third conductive layer 340 of this display substrate. The third conductive layer 340 includes a first signal line group 150, a plurality of power lines 140, and a second signal line group 160. The third conductive layer further includes conductive connections connecting the transistors, capacitors, and signal lines. As shown in FIGS. 5A and 9A, the first signal line group 150, the plurality of power lines 140, and the second signal line group 160 are connected to transistors in other layers that need to be connected via at least one through-hole. The transistors are also connected via at least one through-hole or bridge-connected via conductive connections, which will not be described in detail here.

[0093] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, and the embodiments of the present disclosure are not limited thereto. For example, the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, and will not be described in detail here.

[0094] 5A is a diagram showing the stacking positional relationship between the semiconductor layer 310 shown in FIG. 6A, the first conductive layer 320 shown in FIG. 7A, the second conductive layer 330 shown in FIG. 8, and the third conductive layer 340 shown in FIG. 9A.

[0095] 5A and 9A, in at least one example, the display substrate includes a first signal line group 150 (e.g., including a first clock signal line ECK and a second clock signal line ECB) arranged in order along the row direction, a plurality of power supply lines 140 (e.g., including a third power supply line VGL1, a first power supply line VGH1, and a fourth power supply line VGL2), and a second signal line group 160 (e.g., including a first trigger signal line ESTV1). Note that when a second scan drive circuit is included, the second signal line group 160 further includes, for example, a second trigger signal line ESTV2.

[0096] 4 or 5A, the second signal line group 160 is located on a side of the first scan drive circuit 130 that is closer to the pixel array region 110, and the first signal line group 150 is located on the other side of the first scan drive circuit 130 that is opposite to the side on which the second signal line group 160 is located. For example, as shown in FIG. 4 or 5A, the second signal line group 160 is located on the right side of the shift register 100, and the first signal line group 150 is located on the left side of the shift register 100.

[0097] In this embodiment, the second signal line group 160, including the first trigger signal line ESTV1 and the second trigger signal line ESTV2, is provided on the right side of the shift register, i.e., away from the first signal line group 150 and the plurality of power supply lines 140, thereby preventing congestion of wiring caused by an excessive number of signal lines on the left side. This prevents the space left for the trigger signal lines from being too small due to congestion of wiring, which affects the introduction of other signal lines.

[0098] 5A, the plurality of power supply lines 140 include a first power supply line VGH1, a second power supply line VGH2, a third power supply line VGL1, and a fourth power supply line VGL2. For example, the first power supply line VGH1 and the second power supply line VGH2 supply the same first power supply voltage, for example, a DC high voltage.

[0099] For example, the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base substrate 10, and the orthogonal projection of the second power supply line VGH2 onto the base substrate 10 is located between the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 and the orthogonal projection of the second signal line group 160 onto the base substrate 10.

[0100] Note that, because the orthogonal projection of the first scan drive circuit onto the base substrate 10 is not a continuous region, the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 may partially overlap with the orthogonal projections onto the base substrate 10 of some transistors and capacitors of the first scan drive circuit. The embodiments of the present disclosure are not limited to this. For example, as shown in FIG. 5A , the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 overlaps with the wiring in the first conductive layer 320. For example, the orthogonal projection partially overlaps with the wiring connecting the gate of the third transistor T3 and the gate of the first transistor T1, the wiring connecting the gate of the fourth transistor T4, the wiring connecting the gate of the fifth transistor T5, and the wiring connecting the gate of the second transistor T2.

[0101] For example, as shown in FIG. 5A , each shift register of the first scan drive circuit includes a first transistor connected to a first power supply line VGH1 and second and third transistors connected to a second power supply line VGH2. For example, the fifth transistor T5 is an example of a first transistor, the eighth transistor T8 is an example of a second transistor, and the ninth transistor T9 is an example of a third transistor. Hereinafter, an example will be described in which the first transistor is the fifth transistor T5, the second transistor is the eighth transistor T8, and the third transistor is the ninth transistor T9, but the embodiments of the present disclosure are not limited to this. The following embodiments are similar to this example and will not be described in detail.

[0102] For example, the orthogonal projection of the fifth transistor T5 onto the base substrate 10 is between the orthogonal projection of the first signal line group 150 onto the base substrate 10 and the orthogonal projection of the first power supply line VGH1 onto the base substrate 10, and is close to the orthogonal projection of the first power supply line VGH1 onto the base substrate 10. The orthogonal projections of the eighth transistor T8 and the ninth transistor T9 onto the base substrate 10 are between the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 and the orthogonal projection of the second power supply line VGH2 onto the base substrate 10, and are close to the orthogonal projection of the second power supply line VGH2 onto the base substrate 10. In other words, by providing the first power supply line VGH1 at a position close to the fifth transistor T5 and providing the eighth transistor T8 and the ninth transistor T9 at a position close to the second power supply line VGH2, it is possible to avoid the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 being wound so as to be connected to a single power supply line (for example, the first power supply line VGH1). This avoids occupying space due to winding of the wiring in the vertical direction of the display substrate.

[0103] For example, the third power supply line VGL1 and the fourth power supply line VGL2 are configured to supply the same second power supply voltage, e.g., a low DC voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthogonal projection of the fourth power supply line VGL2 onto the base substrate 10 partially overlaps with the orthogonal projection of the first scan drive circuit onto the base substrate 10, and the orthogonal projection of the third power supply line VGL1 onto the base substrate 10 is located between the orthogonal projection of the third power supply line VGL1 onto the base substrate 10 and the orthogonal projection of the first signal line group 150 onto the base substrate 10.

[0104] As described above, the orthogonal projection of the first scan drive circuit onto the base substrate 10 is not a continuous region, so the orthogonal projection of the fourth power supply line VGL2 onto the base substrate 10 may partially overlap with the orthogonal projections onto the base substrate 10 of some of the transistors and capacitors of the first scan drive circuit. The embodiments of the present disclosure are not limited to this. For example, as shown in FIG. 5A , the orthogonal projection of the fourth power supply line VGL2 onto the base substrate 10 overlaps with the wiring in the first conductive layer 320. For example, it partially overlaps with the wiring connecting the gate of the eighth transistor T8, the wiring connecting the gate of the tenth transistor T10, and the first electrode CE12 of the second capacitor C2.

[0105] For example, each shift register of the first scan drive circuit further includes a fourth component transistor connected to the third power supply line VGL1, and also includes a fifth component transistor connected to the fourth power supply line VGL2. For example, the third transistor T3 is an example of the fourth component transistor, and the tenth transistor T10 is an example of the fifth component transistor. Hereinafter, an example will be described in which the third transistor T3 is the fourth component transistor and the tenth transistor T10 is the fifth component transistor, but the embodiments of the present disclosure are not limited to this. The following embodiments are similar to this and will not be described in detail.

[0106] For example, the orthogonal projection of the third transistor T3 onto the base substrate 10 is on the side of the orthogonal projection of the third power supply line VGL1 onto the base substrate 10 that is away from the orthogonal projection of the first signal line group 150 onto the base substrate 10, and is close to the orthogonal projection of the third power supply line VGL1 onto the base substrate 10. For example, the orthogonal projection of the tenth transistor T10 onto the base substrate 10 is between the orthogonal projection of the fourth power supply line VGL2 onto the base substrate 10 and the orthogonal projection of the second signal line group 160 onto the base substrate 10, and is close to the orthogonal projection of the tenth transistor T10 onto the base substrate 10. That is, by providing the third power line VGL1 near the third transistor T3 and the tenth transistor T10 near the fourth power line VGL2, it is possible to avoid winding the third transistor T3 and the tenth transistor T10 so that they are both connected to a single power line (for example, the third power line VGL1) or to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display substrate, respectively, thereby avoiding the occupation of space due to winding of the wiring in the vertical direction of the display substrate.

[0107] In at least one embodiment of the present disclosure, the first power supply line VGH1, the second power supply line VGH2, the third power supply line VGL1, and the fourth power supply line VGL2 are provided near the transistors to which they are connected, thereby preventing the transistors from being wound so that they are all connected to a single power supply line. This prevents the wiring from taking up space in the vertical direction of the display substrate due to the winding of the wiring, which is advantageous for realizing a narrow frame design.

[0108] In some other embodiments, the pixel array region 110 includes a first display region and a second display region (not shown) that are parallel to each other and do not overlap, and the first scan drive circuit 130 is connected to the first display region to drive the first display region for display.

[0109] The display substrate further includes a second scan driving circuit disposed in the peripheral region and located on one side of the base substrate. For example, the second scan driving circuit is arranged in order from the first scan driving circuit along the scanning direction (e.g., the column direction) of the pixel array, connected to the second display area, and drives the second display area to display. For example, the second scan driving circuit includes a plurality of cascaded second shift registers (e.g., the first-stage shift register 132 shown in FIG. 5B). For example, the configuration of the second shift register is the same as the circuit configuration of the first shift register, and both adopt the circuit configuration of the shift register shown in FIG. 1. Naturally, the configuration of the second shift register may be different from the circuit configuration of the first shift register, and the embodiments of the present disclosure are not limited thereto. For clarity and conciseness, the second shift register will hereinafter be abbreviated as shift register. Since the following embodiments are similar, a detailed description will not be given.

[0110] For example, the display substrate is a folded display substrate and further includes a folding line located between the first display area and the second display area. For example, the second resistor R2 is located in the extending direction of the folding line, and the extending direction of the folding line is perpendicular to the extending direction of the first signal line group 150 and the second signal line group 160, so that the signal lines can penetrate the entire display substrate. For example, the extending direction of the first signal line group 150 and the second signal line group 160 is the vertical direction shown in FIG. 4, and the extending direction of the folding line is the horizontal direction.

[0111] For example, as shown in FIG. 5B , the second signal line group 160 further includes a second trigger signal line ESTV2. The second trigger signal line ESTV2 is connected to a first-stage shift register 132 among a plurality of cascaded shift registers included in the second scan drive circuit, and supplies a second trigger signal to the first-stage shift register 132 included in the second scan drive circuit. For example, the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are arranged adjacent to each other. The first trigger signal line ESTV1 and the second trigger signal line ESTV2 extend in parallel, and their extension lengths are the same as the arrangement lengths of the first scan drive circuit and the second scan drive circuit. For example, they can penetrate the entire display panel. This prevents differences in wiring resistance due to differences in the lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 from affecting the trigger signals transmitted by each line. Accordingly, for example, when multiple scan drive circuits are included, the other trigger signal lines may also be arranged adjacent to and in parallel with the first trigger signal line ESTV1 and the second trigger signal line ESTV2, and the extension lengths thereof may all be the same as the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.

[0112] 5B schematically shows only the final-stage shift register 131 of the first scan drive circuit and the first-stage shift register 132 of the second scan drive circuit. The layout of the other stages of the shift registers may refer to the layout shown in FIG. 5A and will not be described in detail.

[0113] 6B, 7B, 8, and 9B each show a plan view of wiring in each layer of the first-stage shift register included in the display substrate shown in Fig. 5B. Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described in detail with reference to Figs. 5B to 9B.

[0114] The semiconductor layer shown in FIG. 6B is similar to the semiconductor layer shown in FIG. 6A except that it further includes at least one resistor (e.g., second resistor R2). The first conductive layer 320 shown in FIG. 7B is similar to the first conductive layer 320 shown in FIG. 7A except that it further includes a first connection line L1 and a second connection line L2. The third conductive layer 340 shown in FIG. 9B is similar to the third conductive layer 340 shown in FIG. 9A except that it further includes a first conductive connection portion 341 and a second conductive connection portion 342. Specific connection relationships will be described in detail below.

[0115] For example, when an output signal is output from the final-stage shift register 131 of the first scan drive circuit, the second trigger signal line ESTV2 supplies a second trigger signal to the first-stage shift register 132 of the second scan drive circuit, thereby driving the multiple cascaded shift registers included therein to output output signals row by row. Note that the first trigger signal line ESTV1 supplies the first trigger signal to the first scan drive circuit, and the second trigger signal line ESTV2 supplies the second trigger signal to the second scan drive circuit at the same time, thereby simultaneously driving the first scan drive circuit and the second scan drive circuit to operate, and it is only necessary to drive the pixel cells in the pixel array region of the display substrate so as to display a normal image, and the embodiments of the present disclosure are not limited thereto.

[0116] For example, in some cases, as shown in FIG. 3, the display substrate further includes at least one first resistor R1 (as shown in FIG. 3). For example, the first resistor R1 is located away from the first-stage first shift register of the first scan drive circuit 130. For example, the first trigger signal line ESTV1 is connected to the first-stage shift register of the first scan drive circuit 130 (e.g., the first transistor T1 of the first-stage shift register) via the first resistor R1. For example, as shown in FIG. 5B, if the display substrate includes the second scan drive circuit 230, the display substrate may further include at least one second resistor R2. For example, the second resistor R2 is located between the last-stage first shift register of the first scan drive circuit 130 and the first-stage second shift register of the second scan drive circuit 230. For example, the second trigger signal line ESTV2 is connected to the second shift register of the first stage of the second scan drive circuit 230 via a second resistor R2, and is connected to, for example, the first transistor T1 of the shift register 132 of the first stage of the second scan drive circuit 230.

[0117] For example, the resistance value of the first resistor R1 is different from the resistance value of the second resistor R2. For example, in some examples, the first trigger signal line ESTV1 is connected to the controller 20 from the upper side of the display substrate to receive the first trigger signal, and the second trigger signal line ESTV2 is inserted through the center of the display substrate and connected to the controller to receive the second trigger signal. As a result, the wiring resistances (loads) of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are different. For example, if the load of the first trigger signal line ESTV1 is greater than the load of the second trigger signal line ESTV2, the first resistor R1 is smaller than the second resistor R2, and the value obtained by adding the resistance value of the first resistor to the resistance value of the wiring resistance in the first trigger signal line ESTV1 is approximately equal to the value obtained by adding the resistance value of the second resistor to the resistance value of the wiring resistance in the second trigger signal line ESTV1. For example, in some examples, the resistance value of the first resistor R1 is 5000 ohms, the resistance value of the second resistor R2 is 5500 ohms, the resistance value of the wiring resistor in the first trigger signal line ESTV1 is 1000 ohms, and the resistance value of the wiring resistor in the second trigger signal line ESTV1 is 500 ohms.

[0118] In addition, if the display substrate includes multiple scan driving circuits, the display substrate may further include multiple resistors connecting the first-stage shift registers of the multiple scan driving circuits to corresponding trigger signal lines. For example, if the display substrate includes multiple scan driving circuits such as a third scan driving circuit and a fourth scan driving circuit, the display substrate may accordingly further include a third resistor, a fourth resistor, etc. connected to the first transistor T1 of the first-stage shift register, although the embodiments of the present disclosure are not limited thereto. For example, the configurations of the other multiple resistors may all refer to the configurations of the first resistor R2 and second resistor R2, and will not be described in detail.

[0119] For example, the first resistor and the second resistor may be the same or different, and may be determined according to actual circumstances, and the embodiments of the present disclosure are not limited thereto. For example, the first resistor and the second resistor may be made of a semiconductor material and may be disposed in the same layer as the active layer of the transistor. The first resistor and the second resistor may be located in the semiconductor layer shown in FIG. 6B.

[0120] 5B shows the connection configuration of the second resistor, and the second resistor R2 shown in FIG. 5B will be used as an example below. FIG. 10 is a cross-sectional view of the display substrate shown in FIG. 5B along the AA' direction. Hereinafter, the connection configuration of each resistor will be described in detail with reference to FIGS. 5B and 10, taking the second resistor as an example.

[0121] 5B and 10 , the second resistor R2 is located between the base substrate 10 and the second signal line group 160 (i.e., on the semiconductor layer 310) in the direction perpendicular to the base substrate 10, and the orthogonal projection of the second resistor R2 onto the base substrate 10 is located on the side of the second signal line group 160 that is away from the pixel array region when orthogonally projected onto the base substrate 10. Accordingly, the first resistor is located between the base substrate 10 and the second signal line group 160 (i.e., on the semiconductor layer 310) in the direction perpendicular to the base substrate 10, and the orthogonal projection of the first resistor onto the base substrate 10 is located on the side of the second signal line group 160 that is away from the pixel array region when orthogonally projected onto the base substrate 10. Note that the first resistor and the second resistor R2 are not limited to the positions shown in FIG. 5B and may be provided at other appropriate positions, as long as they are located at positions that make it easy to connect the trigger signal line and the first transistor T1, and the embodiments of the present disclosure are not limited thereto.

[0122] 5B, the display substrate further includes at least one first connection line L1 and at least one second connection line L2. The first connection line L1 connects one end of a second resistor R2 to a first-stage shift register (e.g., a first transistor T1) of a second scan driving circuit, and the second connection line L2 connects the other end of the second resistor R2 to a second trigger signal line ESTV2.

[0123] In addition, the display substrate further includes a plurality of first connecting lines and second connecting lines, which correspond one-to-one to resistors corresponding to other scan driving circuits, and the first resistors or other resistors are connected to the corresponding scan driving circuits and trigger signal lines via the corresponding first connecting lines and second connecting lines, for example, the first connecting line connects one end of the first resistor to the first stage shift register of the first scan driving circuit, and the second connecting line connects the other end of the first resistor to the first trigger signal line, which will not be described in detail here.

[0124] For example, the first connection line L1 and the second connection line L2 are located on the side of the second resistor R2 that is away from the base substrate 10, i.e., the first connection line L1 and the second connection line L2 are located on the first conductive layer 320 shown in Figure 7B, so when they are provided on the third conductive layer 340, signal disturbance due to intersection with the fourth power supply line VGL2 can be avoided.

[0125] For example, the display substrate may further include at least one first conductive connection portion L3 and at least one second conductive connection portion L4, so that each resistor is bridge-connected to the first and second connection lines. For example, the first conductive connection portion L3 and the second conductive connection portion L4 are located on the side of the first connection line L1 and the second connection line L2 that is farther from the base substrate 10, and are provided in the same layer as the plurality of power lines 140, the first signal line group 150, and the second signal line 160. That is, the first conductive connection portion L3 and the second conductive connection portion L4 are located on the third conductive layer 340 shown in FIG. 9B .

[0126] For example, as described above, the display substrate 1 further includes a first insulating layer 350, a second insulating layer 360, and a third insulating layer 370. For example, the first insulating layer 350 is located between the second resistor R2 (i.e., the semiconductor layer 310) and the first and second connecting lines L1 and L2 (i.e., the first conductive layer 320) in the direction perpendicular to the base substrate 10, and the second insulating layer 360 is located between the first and second connecting lines L1 and L2 (i.e., the first conductive layer 320) and the first and second conductive connecting portions L3 and L4 (i.e., the third conductive layer 340) in the direction perpendicular to the base substrate 10. Note that the second conductive layer 330 shown in FIG. 8 and the third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340 are further included between the second insulating layer 360 and the third conductive layer 340. The above description may be referred to for detailed description, and will not be described in detail here.

[0127] 5B and 10, one end of the first conductive connection L3 is connected to one end of the first connection line L1 via a through hole 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection L3 is connected to one end of the second resistor R2 via a through hole 134 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connection line L1 is connected to a first-stage shift register (e.g., the source S1 of the first transistor T1) of the first scan drive circuit via a through hole 135 that penetrates the second insulating layer 360 and the third insulating layer 370 and a through hole 139 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. For example, if the orthogonal projection of the other end of the first connecting line L1 onto the base substrate 10 at least partially overlaps with the orthogonal projection of the source S1 of the first transistor T1 onto the base substrate 10, the other end of the first connecting line L1 may be connected to the source S1 of the first transistor T1 via a through hole (not shown) penetrating the first insulating layer 350, and the embodiments of the present disclosure are not limited in this regard.

[0128] One end of the second conductive connection part L4 is connected to one end of the second connection line L2 via a through hole 136 that penetrates the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection part L4 is connected to the other end of the second resistor R2 via a through hole 137 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connection line L2 is connected to the second trigger signal line ESTV2 via a through hole 138 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0129] In addition, the display substrate further includes a plurality of first conductive connecting portions and second conductive connecting portions that correspond one-to-one to resistors corresponding to other scanning driving circuits, and the first resistors or other resistors are connected to corresponding first connecting lines and second connecting lines via corresponding first conductive connecting portions and second conductive connecting portions, which will not be described in detail here.

[0130] For example, one end of the first conductive connection portion is connected to one end of the first connection line via a through hole that penetrates the second insulating layer, the other end of the first conductive connection portion is connected to one end of the first resistor via a through hole that penetrates the first insulating layer and the second insulating layer, the other end of the first connection line is connected to the first stage shift register of the first scan driving circuit, one end of the second conductive connection portion is connected to one end of the second connection line via a through hole that penetrates the second insulating layer, the other end of the second conductive connection portion is connected to the other end of the first resistor via a through hole that penetrates the first insulating layer and the second insulating layer, and the other end of the second connection line is connected to the first trigger signal line via a through hole that penetrates the second insulating layer.

[0131] In the embodiment of the present disclosure, the first-stage shift register of each scan driving circuit is connected to a corresponding trigger signal via a resistor, which can prevent static electricity generated when the device is turned on from affecting each signal (e.g., trigger signal, clock signal, etc.), thereby making the output signal from the scan driving circuit more accurate and improving the display quality of the display panel.

[0132] At least one embodiment of the present disclosure further provides a display device. Fig. 11 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Fig. 11, the display device 2 includes a display substrate 1 according to any embodiment of the present disclosure, for example, the display substrate 1 shown in Fig. 4, Fig. 5A, or Fig. 5B.

[0133] The display device 2 may be any product or component having a display function, such as an OLED panel, an OLED television, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigation system, etc. The display device 2 may further include other components, and the embodiments of the present disclosure are not limited thereto.

[0134] For clarity and simplicity, the embodiments of the present disclosure do not show all components of the display device, and those skilled in the art can provide and implement other components (not shown) according to specific needs to realize the substrate function of the display device, and the embodiments of the present disclosure are not limited thereto.

[0135] The technical effects of the display device 2 according to the above embodiment may be referred to the technical effects of the display substrate 1 according to the embodiment of the present disclosure, and will not be described in detail here.

[0136] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. Figure 12 is a flowchart of the method for manufacturing a display substrate according to at least one embodiment of the present disclosure. This manufacturing method can be applied to, for example, manufacturing a display substrate according to any embodiment of the present disclosure. For example, it can be applied to manufacturing the display substrate shown in Figure 5A or 5B.

[0137] As shown in FIG. 12, the method for manufacturing the display substrate includes steps S110 to S120.

[0138] Step S110: Provide a base substrate.

[0139] Step S120: A first scan driving circuit, a plurality of power lines, a first group of signal lines, and a second group of signal lines are formed on a first side of the base substrate in the peripheral region of the base substrate.

[0140] Regarding step S110, the base substrate 10 may be made of, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure are not limited thereto. The base substrate 10 may include, for example, a pixel array region 110 and a peripheral region 120.

[0141] Regarding step S120, for example, the first scanning drive circuit 130, the plurality of power supply lines 140, the first signal line group 150 and the second signal line group 160 are arranged within the peripheral region 120 and on a first side of the base substrate 10, for example, on the left side of the base substrate 10.

[0142] For example, the first scan driving circuit 130 includes a plurality of cascaded shift registers 100, such as a plurality of shift registers as shown in FIG. 1. For example, the first transistor T1 to the tenth transistor T10 of the shift register may be formed on a semiconductor layer 310 shown in FIG. 6A. For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, or the like. For example, the oxide semiconductor may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon may include low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, but this is not limited to the embodiments of the present disclosure. Note that the source region and the drain region may be regions doped with n-type impurities or p-type impurities, but this is not limited to the embodiments of the present disclosure.

[0143] For example, the first electrodes CE11, CE12, and CE13 of the first capacitor C1 to the third capacitor C3 and the gates of the first transistor T1 to the tenth transistor T10 may be formed on the first conductive layer 320 shown in Fig. 7A. As shown in Fig. 7A, the gates of the first transistor T1 to the tenth transistor T10 are portions where the semiconductor layer configuration of each transistor and the wiring in the first conductive layer 320 overlap.

[0144] For example, the second electrodes CE21, CE22, and CE23 of the first to third capacitors C1 to C3 may be formed on the second conductive layer 330 shown in Fig. 8. For example, the second electrode CE21 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 at least partially overlaps with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 at least partially overlaps with the first electrode CE13 to form the third capacitor C3.

[0145] For example, the plurality of power supply lines 140, the first group of signal lines 150, and the second group of signal lines may be formed on a third conductive layer 340 shown in FIG. 9A. The third conductive layer further includes conductive connections that connect the transistors, capacitors, and signal lines. As shown in FIGS. 5A and 9A, the first group of signal lines 150, the plurality of power supply lines 140, and the second group of signal lines 160 are connected to transistors that need to be connected in other layers via at least one through-hole, and the transistors are also connected via at least one through-hole or bridge-connected via conductive connections, which will not be described in detail here.

[0146] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, and the embodiments of the present disclosure are not limited thereto. For example, the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, and will not be described in detail here.

[0147] For example, the plurality of power supply lines 140 are configured to supply power supply voltages to the plurality of cascaded shift registers 100 included in the first scan drive circuit 130. For example, the power supply lines 140 supply a first power supply voltage (e.g., having a DC high level) and a second power supply voltage (e.g., having a DC low level).

[0148] For example, the first signal line group 150 includes at least one timing signal line, for example, a first clock signal line ECK and a second clock signal line ECB configured to supply timing signals, for example, the first clock signal ECK and the second clock signal ECB, to a plurality of cascaded shift registers 100 included in the first scan drive circuit 130.

[0149] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1 that is connected to a first-stage shift register of the multiple cascaded shift registers 100 included in the first scan drive circuit 150 and is configured to supply a first trigger signal to the first-stage shift register. The first trigger signal line ESTV1 is provided, for example, between the multiple power supply lines 140 and the pixel array region 110.

[0150] 4 or 5A, the second signal line group 160 is formed on a side of the first scan drive circuit 130 that is closer to the pixel array region 110, and the first signal line group 150 is formed on the other side of the first scan drive circuit 130 that is opposite to the side on which the second signal line group 160 is located. For example, as shown in FIG. 4 or 5A, the second signal line group 160 is located on the right side of the shift register 100, and the first signal line group 150 is located on the left side of the shift register 100.

[0151] In this embodiment, the first trigger signal line ESTV1 is provided on the right side of the shift register, i.e., away from the first signal line group 150 and the plurality of power supply lines 140, thereby making it possible to avoid congestion of wiring caused by too many signal lines on the left side. This makes it possible to avoid the situation where the space left for the trigger signal line is too small due to congestion of wiring, which affects the introduction of other signal lines.

[0152] For example, step S120 includes forming the first power supply line VGH1, the second power supply line VGH2, and the third power supply line VGL1 on the base substrate 10, and further forming a fifth transistor T5 connected to the first power supply line VGH1, an eighth transistor T8 and a ninth transistor T9 connected to the second power supply line VGH2, a third transistor T3 connected to the third power supply line VGHL1, and a tenth transistor T10 connected to the fourth power supply line VGL2 on the base substrate 10. For example, the first power supply line VGH1 and the second power supply line VGH2 supply the same first power supply voltage, for example, a DC high voltage.

[0153] For example, the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base substrate 10, and the orthogonal projection of the second power supply line VGH2 onto the base substrate 10 is located between the orthogonal projection of the first power supply line VGH1 onto the base substrate 10 and the orthogonal projection of the second signal line group 160 onto the base substrate 10.

[0154] For example, by forming the first power supply line VGH1 in a position close to the fifth transistor T5 and the second power supply line VGH2 in a position close to the eighth transistor T8 and the ninth transistor T9, it is possible to avoid winding the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 so that they are all connected to a single power supply line (for example, the first power supply line VGH1), and it is possible to avoid occupying space due to winding the wiring in the vertical direction of the display substrate.

[0155] For example, the third power supply line VGL1 and the fourth power supply line VGL2 supply the same second power supply voltage, e.g., a low DC voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthogonal projection of the fourth power supply line VGL2 onto the base substrate 10 partially overlaps with the orthogonal projection of the first scan drive circuit onto the base substrate 10, and the orthogonal projection of the third power supply line VGL1 onto the base substrate 10 is located between the orthogonal projection of the third power supply line VGL1 onto the base substrate 10 and the orthogonal projection of the first signal line group 150 onto the base substrate 10.

[0156] For example, by forming the third power supply line VGL1 in a position close to the third transistor T3 and the fourth power supply line VGL2 in a position close to the tenth transistor T10, it is possible to avoid winding the third transistor T3 and the tenth transistor T10 so that they are both connected to one power supply line (for example, the third power supply line VGL1) or connected to the third power supply line VGL1 and the fourth power supply line VGL2 located on the left side of the display substrate, respectively, and it is possible to avoid occupying space due to winding of the wiring in the vertical direction of the display substrate.

[0157] For example, in some examples, the manufacturing method of the display substrate further includes a step of forming a second scan drive circuit in the peripheral region on the first side of the base substrate 10. For example, the second scan drive circuit includes a plurality of cascaded shift registers (e.g., the first-stage shift register 132 shown in FIG. 5B). For example, as shown in FIG. 5B, the second signal line group 160 further includes a second trigger signal line ESTV2 connected to the first-stage shift register 132 of the plurality of cascaded shift registers included in the second scan drive circuit and supplying a second trigger signal to the first-stage shift register 132 included in the second scan drive circuit.

[0158] For example, the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are both the same as the arrangement lengths of the first scan drive circuit and the second scan drive circuit, thereby preventing a difference in wiring resistance due to a difference in extension length between the first trigger signal line ESTV1 and the second trigger signal line ESTV2 from affecting the trigger signals transmitted by each of them. Accordingly, for example, when multiple scan drive circuits are included, the extension lengths of the other trigger signal lines may all be the same as the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.

[0159] For example, in some cases, the manufacturing method of the display substrate further includes a step of forming at least one first resistor and at least one second resistor between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10.

[0160] In addition, if the display substrate includes multiple scan driving circuits (for example, further including a third scan driving circuit, a fourth scan driving circuit, etc.), the manufacturing method for the display substrate further includes a step of forming resistors corresponding to the multiple scan driving circuits between the base substrate 10 and the second signal line group in a direction perpendicular to the base substrate 10, and the embodiments of the present disclosure are not limited thereto.

[0161] 5B and 10, the second resistor R2 is located between the base substrate 10 and the second signal line group 160 (i.e., on the semiconductor layer 310) in the direction perpendicular to the base substrate 10, and the orthogonal projection of the second resistor R2 onto the base substrate 10 is located on the side of the orthogonal projection of the second signal line group 160 onto the base substrate 10 that is farther from the pixel array region. Correspondingly, the first resistor is located between the base substrate 10 and the second signal line group 160 in the direction perpendicular to the base substrate 10, and the orthogonal projection of the first resistor onto the base substrate 10 is located on the side of the orthogonal projection of the second signal line group 160 onto the base substrate 10 that is farther from the pixel array region. Note that the first resistor R2 and the second resistor R2 are not limited to the positions shown in FIG. 5B and may be provided at other appropriate positions.

[0162] For example, in some cases, the manufacturing method of the display substrate further includes a step of forming at least one first connecting line and at least one second connecting line on the side of the first resistor R1 and the second resistor R2 away from the base substrate 10, i.e., on the first conductive layer 320. Therefore, when provided on the third conductive layer 340, signal disruption caused by crossing with the fourth power line VGL2 can be avoided.

[0163] For example, the first connection line connects one end of the first resistor to the first-stage shift register of the first scan drive circuit, and the second connection line connects the other end of the first resistor to the first trigger signal line. The first connection line L1 connects one end of the second resistor R2 to the first-stage shift register (e.g., the first transistor T1) of the second scan drive circuit, and the second connection line L2 connects the other end of the second resistor R2 to the second trigger signal line ESTV2.

[0164] For example, in some cases, the manufacturing method of the display substrate further includes the steps of forming a first conductive connection L3 and a second conductive connection L4 on the base substrate 10, the first conductive connection L3 and the second conductive connection L4 being arranged in the same layer as the plurality of power supply lines 140, the first signal line group 150 and the second signal line group 160; forming a first insulating layer 350 between the first resistor R1 (i.e., the semiconductor layer 310) and the first connecting line L1 and the second connecting line L2 (the first conductive layer 320) in a direction perpendicular to the base substrate 10; and forming a second insulating layer 360 between the first connecting line L1 and the second connecting line L2 (the first conductive layer 320) and the first conductive connection L3 and the second conductive connection L4 (i.e., the third conductive layer 340) in a direction perpendicular to the base substrate 10. In addition, the manufacturing method of the display substrate further includes a step of forming a second conductive layer 330 as shown in FIG. 8 between the second insulating layer 360 and the third conductive layer 340, and a third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340, and for detailed explanations, please refer to the above explanations and will not be described in detail here.

[0165] 5B and 10, one end of the first conductive connection L3 is connected to one end of the first connection line L1 via a through hole 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection L3 is connected to one end of the second resistor R2 via a through hole 134 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connection line L1 is connected to a first-stage shift register (e.g., the source S1 of the first transistor T1) of the first scan drive circuit via a through hole 135 that penetrates the second insulating layer 360 and the third insulating layer 370 and a through hole 139 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. For example, if the orthogonal projection of the other end of the first connecting line L1 onto the base substrate 10 at least partially overlaps with the orthogonal projection of the source S1 of the first transistor T1 onto the base substrate 10, the other end of the first connecting line L1 may be connected to the source S1 of the first transistor T1 via a through hole (not shown) penetrating the first insulating layer 350, and the embodiments of the present disclosure are not limited in this regard.

[0166] One end of the second conductive connection part L4 is connected to one end of the second connection line L2 via a through hole 136 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the second conductive connection part L4 is connected to the other end of the second resistor R2 via a through hole 137 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connection line L2 is connected to the second trigger signal line ESTV2 via a through hole 138 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0167] In the embodiment of the present disclosure, the first-stage shift register of each scan driving circuit is connected to a corresponding trigger signal via a resistor, thereby preventing static electricity generated when the device is turned on from affecting each signal (e.g., trigger signal, clock signal, etc.), thereby making the output signal from the scan driving circuit more accurate and improving the display quality of the display panel.

[0168] In some embodiments of the present disclosure, the manufacturing method flow of the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the manufacturing method flow includes operations that appear in a specific order, it is clear that the order of the operations is not limited. The manufacturing method may be performed once or multiple times according to predetermined conditions.

[0169] The technical effects of the manufacturing method of the display substrate according to the above embodiment may be referred to the technical effects of the display substrate according to the embodiment of the present disclosure, and will not be described in detail here.

[0170] The following points need to be explained: (1) The drawings of the embodiments of the present disclosure relate only to the configurations of the embodiments of the present disclosure, and other configurations may refer to the general design. (2) Unless inconsistent, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0171] The above are merely exemplary embodiments of the present disclosure and do not limit the scope of protection of the present disclosure, which is determined by the appended claims. [Explanation of symbols]

[0172] 10 Base board 20 Controller 100 Light Emitting Control Shift Register 110 pixel array area 120 Surrounding Area 130 First scan drive circuit 132 Shift Register 133~139 through holes 140 Power line 150 First signal line group 160 Second signal line group 230 Second scan drive circuit 310 Semiconductor layer 320 First conductive layer 330 Second conductive layer 340 Third conductive layer 341 first conductive connection part 342 second conductive connection 350 First insulating layer 360 Second insulating layer 360 Second insulating layer 370 Third insulating layer 380 4th insulating layer

Claims

1. a base substrate including a pixel array region and a peripheral region; a first scanning drive circuit, a plurality of power lines, a first group of signal lines, and a second group of signal lines, which are provided in the peripheral region and located on a first side of the base substrate; the first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power supply lines are configured to supply a plurality of power supply voltages to a plurality of cascade-connected first shift registers included in the first scan drive circuit; the first signal line group includes at least one timing signal line configured to supply at least one timing signal to a plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group includes a first trigger signal line connected to a first-stage first shift register among a plurality of cascade-connected first shift registers included in the first scan drive circuit, and configured to supply a first trigger signal to the first-stage first shift register; the first trigger signal line is located between the plurality of power supply lines and the pixel array region; a display substrate, wherein the plurality of power supply lines include a third power supply line, and at least one of the first shift registers includes a fourth configuration transistor connected to the third power supply line, and an orthogonal projection of the fourth configuration transistor onto the base substrate is located on a side of the orthogonal projection of the third power supply line onto the base substrate that is away from the orthogonal projection of the first signal line group onto the base substrate.

2. the second signal line group is located on a side of the first scan drive circuit that is closer to the pixel array region, The display substrate according to claim 1 , wherein the first signal line group is located on the other side of the first scanning drive circuit opposite to the side on which the second signal line group is located.

3. the plurality of power supply lines further include a fourth power supply line; The display substrate according to claim 2 , wherein an orthogonal projection of the fourth power supply line onto the base substrate partially overlaps an orthogonal projection of the first scan driving circuit onto the base substrate.

4. 4. The display substrate according to claim 3, wherein an orthogonal projection of the third power supply line onto the base substrate is located between an orthogonal projection of the fourth power supply line onto the base substrate and an orthogonal projection of the first signal line group onto the base substrate.

5. The display substrate of claim 4 , wherein the third power supply line and the fourth power supply line are configured to supply the same second power supply voltage.

6. At least one of the first shift registers further includes a fifth configuration transistor connected to the fourth power supply line; The display substrate according to claim 3 , wherein an orthogonal projection of the fifth constituent transistor onto the base substrate is located between an orthogonal projection of the fourth power supply line onto the base substrate and an orthogonal projection of the second signal line group onto the base substrate.

7. 2. The display substrate according to claim 1, wherein the first signal line group includes a first clock signal line configured to supply a first clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit.

8. 8. The display substrate of claim 7, wherein a gate of the fourth configuration transistor is connected to the first clock signal line to receive the first clock signal, a first pole of the fourth configuration transistor is connected to the third power supply line to receive a second power supply voltage, and a second pole of the fourth configuration transistor is connected to a second node.

9. the first signal line group includes a second clock signal line configured to supply a second clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit; 7. The display substrate of claim 6, wherein a gate of the fifth configuration transistor is connected to a first node, a first pole of the fifth configuration transistor is connected to a fourth power supply line to receive a second power supply voltage, and a second pole of the fifth configuration transistor is connected to an output terminal of the first shift register.

10. a base substrate including a pixel array region and a peripheral region; a first scanning drive circuit, a plurality of power lines, a first group of signal lines, and a second group of signal lines, which are provided in the peripheral region and located on a first side of the base substrate; the first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power supply lines are configured to supply a plurality of power supply voltages to a plurality of cascade-connected first shift registers included in the first scan drive circuit; the first signal line group includes at least one timing signal line configured to supply at least one timing signal to a plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group includes a first trigger signal line connected to a first-stage first shift register among a plurality of cascade-connected first shift registers included in the first scan drive circuit, and configured to supply a first trigger signal to the first-stage first shift register; the first trigger signal line is located between the plurality of power supply lines and the pixel array region; the first scan driving circuit includes a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor being connected to the first signal line group, respectively; A display substrate, wherein the extending direction of the channels of the first transistor, the second transistor, and the third transistor is parallel to the extending direction of the first signal line group and the second signal line group.

11. the first signal line group includes a first clock signal line configured to supply a first clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit; 11. The display substrate of claim 10, wherein a gate of the first transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the first transistor is connected to an input terminal of the first shift register, and a second electrode of the first transistor is connected to a first node.

12. the first signal line group includes a first clock signal line configured to supply a first clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit; 11. The display substrate of claim 10, wherein a gate of the second transistor is connected to a first node, a first pole of the second transistor is connected to the first clock signal line to receive the first clock signal, and a second pole of the second transistor is connected to a second node.

13. the first signal line group includes a first clock signal line configured to supply a first clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit; 11. The display substrate of claim 10, wherein the plurality of power supply lines include a third power supply line, a gate of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the third power supply line to receive a second power supply voltage, and a second electrode of the third transistor is connected to a second node N2.

14. the first scan driving circuit further includes a sixth transistor and a seventh transistor respectively connected to the first signal line group; The display substrate of claim 10 , wherein the extension direction of the channels of the sixth transistor and the seventh transistor is parallel to the extension direction of the first signal line group and the second signal line group.

15. the first signal line group includes a second clock signal line configured to supply a second clock signal to a plurality of cascaded first shift registers included in the first scan drive circuit; a gate of the sixth transistor is connected to a second node, a first pole of the sixth transistor is connected to the second clock signal line to receive the second clock signal, and a second pole of the sixth transistor is connected to a third node; 15. The display substrate of claim 14, wherein a gate of the seventh transistor is connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor is connected to a third node, and a second electrode of the seventh transistor is connected to a fourth node.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. providing a base substrate; forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in order in a direction perpendicular to the base substrate; the power supply lines and the first signal line group are located on the third conductive layer, the first scanning driving circuit is formed on the semiconductor layer, the first conductive layer, and the second conductive layer; 16. The method for manufacturing a display substrate according to claim 1, wherein the first scanning drive circuit is connected to the power supply line and the first signal line group via through holes that penetrate the first insulating layer, the second insulating layer, and the third insulating layer, respectively.

18. A base substrate including a pixel array region and a peripheral region; a first scanning drive circuit, a second scanning drive circuit, a first power supply line, a second power supply line, a first signal line group, and a second signal line group, which are provided in the peripheral region and located on a first side of the base substrate; the first scan driving circuit includes a plurality of cascaded first shift registers; the second scan driving circuit includes a plurality of second shift registers connected in cascade; the first power supply line is configured to supply a first power supply voltage to a plurality of cascaded first shift registers included in the first scan drive circuit; the second power supply line is configured to supply a second power supply voltage to a plurality of cascaded second shift registers included in the second scan drive circuit; the first signal line group includes at least one timing signal line configured to supply at least one timing signal to a plurality of cascaded first shift registers included in the first scan drive circuit; the second signal line group includes a first trigger signal line connected to a first-stage first shift register among a plurality of cascade-connected first shift registers included in the first scan drive circuit, and configured to supply a first trigger signal to the first-stage first shift register; the first trigger signal line is located between the first power supply line and the pixel array region; the second signal line group includes a second trigger signal line connected to a first-stage second shift register among a plurality of cascade-connected second shift registers included in the second scan drive circuit, and configured to supply a second trigger signal to the first-stage second shift register; The second trigger signal line is located between the second power supply line and the pixel array region.

19. A display substrate as described in Claim 18, wherein the extension length of the first trigger signal line and the second trigger signal line is the same as the arrangement length of the first scanning drive circuit and the second scanning drive circuit.

20. A display substrate as described in Claim 18, wherein the first trigger signal line and the second trigger signal line are arranged in parallel.

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