Access to core topology mapping

Abstract

The method, computer program product, and system include a processor issuing an instruction including processing core information including locations of processing cores (logical and / or physical cores) of a computing system and a selection of an operator. The processor sets security parameters of information returned by the instruction, which is topology information regarding the mapping of logical cores to physical cores. The processor obtains the topology information and utilizes an operating system to map logical cores to physical cores.

Description

[Technical Field]

[0001] The present invention relates to accessing the topology mapping of the core. [Background technology]

[0002] A physical core (also called a processing unit) or core is a well-partitioned element of logic that can independently perform all the functions of a processor (e.g., a central processing unit in a general-purpose microprocessor). A single logical core may be assigned to one or more physical cores. A physical core refers to the actual hardware component. Logical cores (also called logical processors) divide the processing power of a physical server, enabling parallel processing. An operating system (OS) views a logical core or logical processor as a processor, and therefore as capable of simultaneously executing its own stream of instructions. The OS can therefore assign concurrent, independent units of work to a logical core. A logical partition (LPAR) is a subset of a computer's hardware resources virtualized as a separate computer. In effect, a physical machine can be divided into multiple logical partitions, each hosting a separate instance of the OS. Summary of the Invention

[0003] Shortcomings of the prior art are addressed and additional advantages are achieved by providing a method for obtaining information for a global representation of a mapping of logical cores to physical cores across a hypervisor. The method includes, for example, issuing, by one or more processors of a computing system, an instruction including processing core information, the processing core information including locations of one or more processing cores of the computing system, the processing cores of the computing system including logical cores and physical cores, the instruction further including an operator selection. The method also includes setting, by the one or more processors, security parameters of information returned by the instruction based on the operator selection, the returned information including topology information regarding the mapping of logical cores to physical cores. The method also includes obtaining, by the one or more processors, the topology information based on the information including the locations and the security parameters. The method also includes, by the one or more processors, mapping logical cores to physical cores using the topology information via an operating system running on the computing system.

[0004] In some examples, the topology information is selected from the group consisting of information providing a global view of all logical partitions in the computing system and information providing a view of the logical partitions of one or more users in the computing system based on the security parameters.

[0005] In some examples, the information including the location of a processing core within a computing system includes data representing a preferred dispatch location of a logical core.

[0006] In some examples, the information containing the locations of processing cores within a computing system includes data representing the actual locations of the physical cores.

[0007] In some examples, the instructions include a block of information, which includes information including a location of a processing core within a computing system.

[0008] In some examples, the information including the locations of processing cores within the computing system includes, for each processing core, a location at a particular topological nesting level.

[0009] In some examples, the processing core information includes the maximum number of topology nesting levels in the computing system.

[0010] In some examples, the method also includes displaying, by one or more processors, the mapping to an internal interface of the computing system.

[0011] In some instances, the topology information relates to logical partitions of a given group, and membership within a given group is defined in the processing core information.

[0012] In some cases, the given group includes a hardware group.

[0013] In some examples, obtaining the topology information includes obtaining the topology information through an interface internal to the computing system.

[0014] Shortcomings of the prior art are addressed and additional advantages are achieved by providing a computer program product for obtaining information for a global representation of a mapping of logical cores to physical cores across hypervisors. The computer program product includes a storage medium readable by one or more processors and storing instructions executed by the one or more processors to perform a method. The method includes, for example, issuing, by one or more processors of a computing system, instructions including processing core information, the processing core information including locations of one or more processing cores of the computing system, the processing cores of the computing system including logical cores and physical cores, the instructions further including an operator selection. The computer program product also includes instructions, when executed by one or more processors, that cause the method to set, by the one or more processors, security parameters of information returned by the instructions based on the operator selection, the returned information including topology information regarding the mapping of logical cores to physical cores. The computer program product also includes instructions, when executed by one or more processors, that cause the method to obtain, by the one or more processors, the topology information based on the information including the locations and security parameters. The computer program product also includes instructions that, when executed by one or more processors, the method also includes mapping logical cores to physical cores by the one or more processors via an operating system running on the computing system utilizing the topology information.

[0015] In some examples of the computer program product, the topology information is selected from the group consisting of information providing a global view of all logical partitions in the computing system and information providing a view of the logical partitions of one or more users in the computing system based on the security parameters.

[0016] In some examples of the computer program product, the information containing the locations of processing cores within a computing system includes data representing preferred dispatch locations of logical cores.

[0017] In some examples of computer program products, the information containing the locations of processing cores within a computing system includes data representing the actual locations of the physical cores.

[0018] In some examples of computer program products, the instructions include a block of information, which includes information including a location of a processing core within a computing system.

[0019] In some examples of the computer program product, the information containing the locations of processing cores within the computing system includes, for each processing core, a location at a particular topological nesting level.

[0020] In some examples of the computer program product, the processing core information includes a maximum number of topological nesting levels in the computing system.

[0021] In some examples of computer program products, the method also includes displaying, by one or more processors, the mapping to an internal interface of the computing system.

[0022] In some examples of computer program products, topology information relates to logical partitions of a given group, and membership within a given group is defined in processing core information.

[0023] In some examples of computer program products, the given group includes a hardware group.

[0024] In some examples of the computer program product, obtaining the topology information includes obtaining the topology information through an interface internal to the computing system.

[0025] Shortcomings of the prior art are addressed and additional advantages are achieved by providing a system for obtaining information for a global representation of a mapping of logical cores to physical cores across a hypervisor. The system includes a memory, one or more processors in communication with the memory, and program instructions executable by the one or more processors via the memory to perform a method. The method includes, for example, issuing, by one or more processors of a computing system, instructions including processing core information, the processing core information including locations of one or more processing cores of the computing system, the processing cores of the computing system including logical cores and physical cores, the instructions further including an operator selection. The method performed by the system also includes setting, by the one or more processors, security parameters of information returned by the instructions based on the operator selection, the returned information including topology information regarding the mapping of logical cores to physical cores. The method performed by the system also includes obtaining, by the one or more processors, the topology information based on the information including the locations and security parameters. The method performed by the system also includes mapping, by one or more processors, via an operating system running on the computing system, logical cores to physical cores utilizing the topology information.

[0026] In some examples of the system, the topology information is selected from a group consisting of information providing a global view of all logical partitions in the computing system and information providing a view of the logical partitions of one or more users in the computing system based on the security parameters.

[0027] In some examples of the system, the information containing the locations of processing cores within the computing system includes data representing preferred dispatch locations of logical cores.

[0028] In some examples of systems, the information containing the locations of processing cores within a computing system includes data representing the actual locations of the physical cores.

[0029] In some examples of the system, the instructions include a block of information, which includes information including a location of a processing core within the computing system.

[0030] In some examples of the system, the information containing the locations of processing cores within the computing system includes, for each processing core, a location at a particular topological nesting level.

[0031] In some examples of systems, the processing core information includes the maximum number of topology nesting levels in the computing system.

[0032] In some examples of systems, the method also includes displaying, by one or more processors, the mapping to an internal interface of the computing system.

[0033] In some examples of the system, topology information relates to logical partitions of a given group, and membership within a given group is defined in processing core information.

[0034] In some examples of systems, a given group includes a hardware group.

[0035] In some examples of the system, obtaining the topology information includes obtaining the topology information through an interface internal to the computing system.

[0036] Methods, computer program products, and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0037] Additional features are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0038] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, as well as objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0039] [Figure 1] FIG. 1 illustrates a workflow including various aspects of some embodiments of the present invention. [Figure 2A] FIG. 1 illustrates various elements of a technical environment in which aspects of the present invention may be implemented. [Figure 2B] FIG. 1 illustrates various elements of a technical environment in which aspects of the present invention may be implemented. [Figure 2C] FIG. 1 illustrates various elements of a technical environment in which aspects of the present invention may be implemented. [Figure 3A] FIG. 1 illustrates various elements of a technical environment in which aspects of the present invention may be implemented. [Figure 3B] FIG. 1 illustrates various elements of a technical environment in which aspects of the present invention may be implemented. [Figure 4A] 2A-2C illustrate various aspects of example instructions issued in the workflow of FIG. 1. [Figure 4B] 2A-2C illustrate various aspects of example instructions issued in the workflow of FIG. 1. [Figure 5A] 2A-2C illustrate various aspects of example instructions issued in the workflow of FIG. 1. [Figure 5B] 2A-2C illustrate various aspects of example instructions issued in the workflow of FIG. 1. [Figure 6] FIG. 1 illustrates a workflow including various aspects of some embodiments of the present invention. [Figure 7] FIG. 1 illustrates an embodiment of a computing node that may be utilized within a cloud computing environment. [Figure 8] FIG. 1 illustrates a cloud computing environment in accordance with an embodiment of the present invention. [Figure 9] FIG. 1 illustrates an abstract model layer according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0040] The accompanying drawings, which are incorporated in and form a part of this specification, in which like reference numbers refer to identical or functionally similar elements throughout the individual views, and together with the detailed description of the invention, further illustrate the present invention and serve to explain the principles of the invention. As will be understood by one skilled in the art, the accompanying drawings are provided to facilitate an understanding of and illustrate aspects of certain embodiments of the invention. The invention is not limited to the embodiments shown in the figures.

[0041] As will be appreciated by those skilled in the art, program code referenced throughout this application includes both software and hardware. For example, the program code in certain embodiments of the present invention includes fixed-function hardware, while other embodiments use software-based implementations of the described functionality. Certain embodiments combine both types of program code. One example of program code, also referred to as one or more programs, is shown in FIG. 7 as program / utility 40, which includes a set (at least one) of program modules 42, and may be stored in memory 28.

[0042] The term "nesting level" is used herein to refer to a hierarchical level of hardware.

[0043] Embodiments of the present invention include computer-implemented methods, computer program products, and computer systems that enable a user to obtain logical partition (LPAR) topology data via an internal interface. In embodiments of the present invention, program code (executing on one or more processors) provides a user with topology information regarding the mapping of logical processing cores to physical processing cores in a computer system via an internal interface. As described in more detail herein, to provide this information, the program code (1) executes instructions containing information blocks and / or core information to a central processing unit (CPU) and sets security parameters for the returned information (e.g., based on the information blocks, security allows access to a specific partition (e.g., a partition dedicated to the user) or all partitions, or both), (2) in response to the instructions, provides information regarding the topology data mapping for use by an operating system (OS), and (3) displays this information on the internal interface. As described herein, embodiments of the present invention enable one or more processors to obtain data providing a desired global view by executing instructions containing specific information blocks. While various options exist for this particular information block, the options described herein are referred to as the Extended CPU / Core Info Block and the Extended Physical CPU / Core Info Block. As exemplified herein, units of data (e.g., words) are reserved for containing values ​​in these information blocks. In the case of the Extended CPU / Core Info Block, units of data are reserved for the coordinates of the preferred dispatch location of the logical core. In the case of the Extended Physical CPU / Core Info Block, units of data are reserved for the coordinates of the actual location information of the physical core. Based at least in part on including this information in the instructions, the program code obtains the desired topology data.

[0044] Aspects of various embodiments of the present invention are closely related to computing, as they address problems inherent to computing using intrinsic components of a computer. Currently, obtaining information about a global view of the mapping of logical cores to physical cores across hypervisors is not available. Addressing this problem involves a hypervisor, virtual machines (VMs), logical partitions (LPARs), and the systems that create and maintain LPARs, processor resources / system managers (PR / SMs)™ (which may also be considered a type of hypervisor). PR / SM™ is provided by International Business Machines Corporation, Armonk, New York. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. A hypervisor is a small software layer that allows multiple operating systems (OSs) to run in parallel with each other while sharing the same physical computing resources. These operating resources include virtual machines (VMs). VMs are software that can simulate a hardware computing environment. Hypervisors are also known as virtual machine monitors (VMMs). Hypervisors manage VMs by isolating them from each other (when VMs run in parallel with each other) and logically assigning each VM its own slice of the underlying physical computing resources, including, but not limited to, compute power, memory, and storage capacity. Hypervisors prevent VMs from interfering with each other. Thus, in a non-limiting example, if a particular OS experiences a problem (e.g., security is compromised, the OS crashes), other VMs that are not running the problematic OS can continue to function. One way system resources are divided is by creating and maintaining logical partitions (LPARs).An LPAR is a subset of processor hardware defined to support a specific operating system. Each LPAR contains various computing resources, including but not limited to processors, memory, and input / output (I / O) devices, and each LPAR operates as an independent system. A mainframe hardware computing system can contain multiple LPARs. A system considered both a processor resource and system manager (PR / SM) includes the combination of hardware and firmware that provides the partitioning of LPARs. Specifically, the PR / SM function creates and runs LPARs. While it is the PR / SM that creates and maintains LPARs, the term LPAR is sometimes used to refer to both the function that creates the partitions and the result of the function.

[0045] Returning to embodiments of the present invention and their close relationship to computing, as previously mentioned, information to provide a global view of mappings across hypervisors is not currently available. Utilizing external interfaces (of the computing system) to provide this information represents a security risk, and therefore, it is preferable to utilize internal resources to both transmit and retrieve this data. In embodiments of the present invention, program code executing on internal resources uses security controls to provide a global view of all logical partitions. In addition to allowing users to identify physical cores system-wide, embodiments of the present invention also improve the functionality of the computing system itself by providing users with the location of all logical cores for all LPARs to obtain the physical placement of the logical cores when they are running in conjunction with the hypervisor. With security procedures in place, obtaining this data internally, which was not previously possible, improves the functionality of the computing system as a whole, and obtaining this data also enables further improvements to the functionality of the computer system. This location information presents benefits including, but not limited to, (1) enabling improved (informed) scheduling decisions, (2) enabling dispatching (of logical cores) to preferred locations, (3) providing data for improved performance analysis of the computing system, or (4) improving the chances for identifying computing problems by providing improved diagnostic information, or combinations thereof. This additional improvement has practical applications within computing environments. Thus, aspects of embodiments of the present invention enable secure internal access to various data, which can be utilized to further improve the functionality of the computing system to which they relate.

[0046] Aspects of various embodiments of the present invention also represent a significant improvement over existing methods of obtaining data mapping logical and physical cores within a computing system. Unlike embodiments of the present invention, existing approaches do not provide a global view of all LPARs and their mapping to physical cores through an internal interface. Currently, some data (but not all data, as described herein) can be obtained using an interface to a computing system's hardware management console (HMC). In this existing approach, the HMC extracts limited data from the Processor Resource / System Manager (PR / SM) through an internal interface between the PR / SM and the HMC. However, this approach only provides the ability to extract limited information from LPAR dumps, and implementing this type of external interface presents a security risk that violates the security policies of many existing computing systems. Example aspects herein represent an improvement because there is no external interface for requesting or obtaining this data, as described in more detail below. Rather, in embodiments of the present invention, program code running on one or more processing resources obtains topology information for an LPAR through internal instructions (providing more data than the limited data provided in internal interfaces). Another problem with obtaining topology information using existing techniques is that user security access should limit the data provided. However, because current techniques do not utilize internal software interfaces and lack the breadth of data provided in embodiments of the present invention, computing system security is not integrated with any possible circumvention methods. Therefore, embodiments of the present invention not only provide this data through internal software interfaces, but also implement security policies surrounding the underlying system elements to provide this data.As described herein, existing techniques for accessing the mapping provide limited data because they only provide the ability for individual partitions to identify which physical cores they typically use. No global topology data is provided by the existing methods. Embodiments of the present invention provide a significant improvement, at least due to the global view provided.

[0047] Aspects of some embodiments of the present invention provide significant improvements over existing methods of obtaining topology data, at least because the topology information returned in embodiments of the present invention is more comprehensive and detailed than that provided by existing techniques. For example, in some existing techniques, a single CPU may issue an instruction that returns some (limited) information describing the location of that single CPU within the physical topology of a particular computing environment. However, some embodiments of the present invention include aspects of obtaining LPAR topology data for a particular computing environment through an internal interface, including utilizing new instructions and / or extensions to existing instructions. In embodiments of the present invention, the flexibility of obtaining LPAR topology data is superior to having a CPU issue a single, limited instruction, because an operator has the ability to select (e.g., through an interface) to determine the breadth of information returned (e.g., information about all issuing partitions, information about all defined partitions, or both). Thus, aspects of some embodiments of the present invention can provide a global view of all partitions and / or a view of a specific logical partition in addition to the physical locations of cores throughout the system. As described herein, some embodiments of the present invention include an application programming interface (API) call to a hypervisor to request the hypervisor to return one or more of: (1) the locations of all physical processors of a configuration, or (2) the locations within the hypervisor's topology where the hypervisor prefers to dispatch (i.e., run) the logical processors of the configuration, or both.

[0048] Aspects of embodiments of the present invention provide significantly more than other related aspects that simply assign physical cores to logical cores for resource sharing. Rather than simply assigning as described herein, in some embodiments of the present invention, program code provides coordinates of logical and physical cores across hierarchical levels of hardware. These coordinates constitute available dynamic mapping information for logical cores to physical cores of logical partitions and / or security controls for all logical partitions within a particular computing architecture.

[0049] 1 and 6 are workflows 100, 600 outlining various aspects of some embodiments of the present invention, including program code executed by one or more processors to obtain data mapping logical and physical cores within a computing system. Throughout the description of workflow 100 of FIG. 1, references are made to various other figures to provide example details regarding various aspects. For example, FIGS. 2A-2C, 3A-3B, and 7-9 are architectural diagrams illustrating various aspects of some computing environments in which aspects of FIG. 1 may be implemented. Meanwhile, FIGS. 4A-4B and 5A-5B detail various aspects of instructions utilized by program code in embodiments of the present invention to obtain LPAR data so that the program code can generate a global topology mapping of logical cores to physical cores.

[0050] 1, in workflow 100, program code executing on one or more processors issues an instruction (110) that includes one or more of: (1) an extended CPU or core information block, or (2) an extended physical CPU or core information block. By issuing this instruction (110), the program code ultimately obtains data (as further shown in FIG. 1) that maps logical and physical cores within the computing system, including all logical partitions (with security controls), the locations of all logical cores in all logical partitions and the physical placement of the logical cores running with the hypervisor, and information that provides a global view of the physical locations of cores throughout the system.

[0051] In addition to executing instructions 110, other aspects of the present invention may be implemented in many types of computing environments. In the examples herein, assuming that program code obtains data mapping logical and physical cores within a computing system, the computing environment into which these aspects are integrated includes, but is not limited to, elements including a hypervisor, VMs, logical LPARs, and a system that creates and maintains LPARs (which may also be considered a type of hypervisor). For illustrative purposes only and not to imply any limitation, Figures 2A-2C are examples of computing environments and elements of computing environments into which aspects of some embodiments of the present invention may be incorporated.

[0052] The computing environment of FIG. 2A is based on the z / Architecture® instruction set architecture offered by International Business Machines Corporation (Armonk, New York). However, the z / Architecture instruction set architecture is only one exemplary architecture, and other architectures or other types of computing environments of International Business Machines Corporation or other entities may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. The computing environment may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures of International Business Machines Corporation, or architectures of other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0053] 2A , in one example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, such as memory 12 (also known as system memory, main memory, primary storage, central storage, or storage), coupled to one or more processors, such as one or more general-purpose processors (also known as central processing units (CPUs) 13) and one or more special-purpose processors (e.g., neural network processor 31), and input / output (I / O) subsystem 14.

[0054] By way of example, the one or more special purpose processors may be separate from the one or more general purpose processors, or at least one special purpose processor may be embedded within at least one general purpose processor, or both. Other variations are possible.

[0055] I / O subsystem 14 may be part of or separate from the central electronic processing unit. I / O subsystem 14 directs the flow of information between main memory 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronic processing unit.

[0056] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0057] Central electronic processing unit 11 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronic processing unit 11 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as "hard drives"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from or writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with central electronic processing unit 11, including, but not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0058] Additionally, central electronic processing unit 11 can operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with central electronic processing unit 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0059] In one or more embodiments, central electronic processing unit 11 provides support for logical partitioning and / or virtualization. In one embodiment, as shown in FIG. 2B, memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. As previously mentioned, an example of hypervisor 21 is PR / SM™. In some embodiments, CEC 11 may be physically partitioned. For each physical partition, topology information about the physical partition may be obtained. In this embodiment, each physical partition functions as a separate machine.

[0060] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in fact only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation and / or other companies may be used in accordance with one or more aspects of the present invention. z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0061] Memory 12 is coupled to physical processor resources, such as CPU 13 (FIG. 2A), that can be assigned to logical partitions. For example, logical partition 20 may include one or more logical processors, each of which represents all or a portion of physical processor resources 13 that can be dynamically assigned to a logical partition.

[0062] In a further embodiment, the central electronic processing unit provides support for virtual machines (which may or may not support logical partitioning). As shown in FIG. 2C, memory 12 of central electronic processing unit 11 includes, for example, one or more virtual machines 26, a virtual machine manager (e.g., hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation (Armonk, New York). A hypervisor may be referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0063] The central electronic processing unit's virtual machine support provides the ability to operate multiple virtual machines 26, each capable of running a different program 29 and a guest operating system 30, such as the Linux® operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and operate with different programs. An operating system or application program running within a virtual machine appears to have access to the entire system, but in fact only a portion of it is available. While z / VM® and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation (an exclusive licensee of Linus Torvalds, owner of the trademark worldwide).

[0064] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to Figures 3A-3B. Figure 3A illustrates general aspects of a particular computing environment, while Figure 3B illustrates further details of instruction execution (e.g., 110 in Figure 1) within this environment. In this example, the computing environment is based on the z / Architecture® instruction set architecture offered by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture instruction set architecture is described in the published document "z / Architecture Principles of Operation," IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019.

[0065] 3A, computing environment 100 includes computer system 102, shown, for example, in the form of a general-purpose computing device. Computer system 102 may include, but is not limited to, one or more general-purpose processors or processing units 104 (e.g., central processing units (CPUs)), at least one special-purpose processor such as neural network processor 105, coupled together via one or more buses and / or other connections, memory 106 (e.g., also known as system memory, main memory, primary storage, central storage, or storage), and one or more input / output (I / O) interfaces 108. For example, processors 104, 105 and memory 106 are coupled to I / O interface 108 via one or more buses 110, and processors 104, 105 are coupled to each other via one or more buses 111.

[0066] Bus 111 may be, for example, a memory or cache coherence bus, and bus 110 may represent any one or more of several types of bus structures, including, for example, a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example only, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI).

[0067] For example, memory 106 may include a cache 112, such as a shared cache, that may be coupled to a local cache 114 of processor 104 and / or neural network processor 105, e.g., via one or more buses 111. Additionally, memory 106 may include one or more programs or applications 116 and at least one operating system 118. An exemplary operating system includes the z / OS® operating system offered by International Business Machines Corporation (Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. Memory 106 may include one or more computer-readable program instructions 120 that may be configured to perform functions of embodiments of aspects of the present invention.

[0068] Additionally, in one or more embodiments, memory 106 includes processor firmware 122. Processor firmware includes, for example, processor microcode or millicode. Processor firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, processor firmware includes, for example, microcode or millicode containing trusted software, proprietary code that is typically provided as microcode or millicode specific to the underlying hardware and that controls operating system access to the system's hardware.

[0069] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0070] The computer system 102 may communicate, for example, via the I / O interface 108, with a network interface 132 that enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0071] Computer system 102 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, computer system 102 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or an optical disk drive for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with computer system 102, including, but not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0072] Computer system 102 may operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0073] Referring to FIG. 1, in an alternative embodiment of the present invention, an instruction is issued (110). As implemented in the computing environment of FIG. 3A, a processor (e.g., processor 104 and / or processor 105) includes multiple functional components (or a subset thereof) used to execute instructions. As shown in FIG. 3B, these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed, an instruction decode unit 152 for decoding the fetched instructions and obtaining operands for the decoded instructions, one or more instruction execution components 154 for executing the decoded instructions, a memory access component 156 for accessing memory to execute the instructions, if necessary, and a writeback component 158 ​​for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in processing the instructions.

[0074] Returning to FIG. 1 , as previously described, an instruction issued by program code (110) includes a header and one or more (extended partition-time) information blocks. As previously described, these information blocks may include one or more of: (1) an extended CPU or core information block; or (2) an extended physical CPU or core information block; or both. In some examples, the extended physical-time-information block includes an extended physical header, followed by a 96-byte extended physical CPU / core information block for each physical CPU / core configured in the machine, or in a physical partition if the machine is physically partitioned. In some embodiments of the invention, the instruction includes a header, followed by one or more information blocks. The utilized header can take a variety of forms, but for purposes of this example, for simplicity of explanation, the header consists of two distinct parts. In some embodiments of the invention, the header includes an extended time information block header and an extended partition header. In some embodiments, if a value in the header (e.g., a physical data flag described later herein) indicates that data is present for the partition named in the instruction, then an extended physical time information block is available. In some embodiments of the present invention, each extended partition time information block includes an extended partition header, followed by an extended CPU / core information block for each logical CPU / core identified in the partition. In some embodiments of the present invention, this extended physical time information block, described in more detail herein, follows the last extended partition time information block.

[0075] 4A-4B and 5A-5B illustrate various aspects of example headers and information blocks utilized within instructions issued by one or more processors to obtain information for mapping topology data that may be utilized by the OS and to provide display of this information via an internal interface by program code. FIGS. 4A-4B are example portions of instruction headers that may be utilized in embodiments of the present invention. Specifically, FIG. 4A is an example of at least a portion of an extended time information block header, and FIG. 4B is an example of at least a portion of an extended partition header. Meanwhile, FIG. 5A is an example of at least a portion of an extended physical CPU or core information block, and FIG. 5B is an example of at least a portion of an extended CPU or core information block. The headers and information blocks may include instructions (e.g., 110 in FIG. 1 ) that, when executed by the processor, obtain topology data for use by the OS.

[0076] In embodiments of the present invention, within the instructions disclosed herein, an extended time information block includes an extended time information block header followed by one or more extended partition time information blocks. In turn, an extended partition time information block includes an extended partition header followed by an extended CPU / core information block for each recognized logical CPU / core within the partition. In some examples, the one or more headers may include various values, including, but not limited to, the number of logical partitions for which information is provided, whether the data resides in a particular physical partition, the number of CPUs / cores configured within the machine or, if the system is physically divided, within physical partitions, information indicating the location of the value within the instruction, a value associated with the (extended CPU / core or extended physical CPU / core) information block, including, but not limited to, the number of partitions, the number of configured logical CPUs / cores, or the number of recognized logical CPUs / cores, or any combination thereof.

[0077] Referring first to FIG. 4A , FIG. 4A illustrates at least a portion of an extended time information block header that may be utilized in embodiments of the present invention as part of an instruction to generate topology information for mapping logical cores to physical cores. Reviewing the specific details of FIG. 4A , which are provided as a non-limiting example for illustrative purposes only, in the example of FIG. 4A , the Npar 410 field contains a value representing the number of logical partitions for which information is provided. In this example, this value remains the same. The Flags 412 field is a physical data flag that indicates whether physical partition data is present (e.g., by being set to 1). These data are included in the extended physical time information block. The Physcpus 416 field contains the number of CPUs / cores configured within the machine, or within physical partitions if the system is physically partitioned. This number may include all physical CPUs / cores in the machine configuration report used to support the logical partitions reported in the returned extended partition time information block. Thus, Physcpus 416 may hold a number representing the number of CPUs / cores configured within the machine, or within physical partitions if the system is physically partitioned. In some embodiments of the invention, this number includes all physical CPUs / cores in the machine configuration report used to support the logical partition reported in the returned Extended Partition Time Info Block. The byte offset within the Extended Partition Time Info Block of the partition where the instruction was issued (e.g., 110 in Figure 1) is contained in the ThisPart418 field.

[0078] FIG. 4B is an example of at least a portion of a header referred to as an extended partition header, as previously described. In an embodiment of the present invention, the extended partition information block includes an extended partition header (FIG. 4B), followed by an extended CPU / core information block (e.g., FIGS. 5A-5B) for each recognized logical CPU / core within the partition. Thus, the extended partition header includes fields containing information specific to a particular partition, including, but not limited to, the partition number (e.g., PN 426 in FIG. 4B), the number of configured logical CPUs / cores (e.g., Cpus 428 in FIG. 4B), which may also include the number of configured secondary CPUs / cores, and the number of recognized logical CPUs / cores (e.g., Rcpus 430 in FIG. 4B), which may also include the number of configured secondary CPUs / cores. General-purpose CPUs include primary CPUs / cores (CPs). Secondary CPUs / cores are special-purpose engines, including, but not limited to, System z Integrated Information Processors (zIIPs) and integrated coupling facilities (ICFs).

[0079] Returning to FIG. 1, a processor issues an instruction (110) that includes information blocks, example characteristics of which are shown in FIGS. 5A-5B. As previously described and shown in FIGS. 5A-5B, the extended CPU or core information block includes space (see FIG. 5B) or data elements (e.g., words) for including preferred dispatch locations of logical cores, while the extended physical CPU or core information block includes space (see FIG. 5A) or data elements (e.g., words) for including actual locations of physical cores. Based at least in part on including this information in the instruction, program code obtains the desired topology data (e.g., 130 in FIG. 1).

[0080] Referring to FIGS. 5A-5B, some values ​​provided within the blocks depend on the characteristics of the computing system. For example, Cpuadd 510 is either a logical CPU address of a CPU or a logical core identification of a core. In some embodiments of the present invention, the extended physical CPU or core information block and the extended physical CPU or core information block include indicators describing either a preferred dispatch location of a logical core or the actual location of a physical core at a particular nesting level (i.e., hardware hierarchy level). Now, referring to the CordL(1-6) 522 and MNestC 524 fields in FIGS. 5A-5B, in the illustrated example, these data elements (e.g., words) are utilized in embodiments of the present invention to include a preferred dispatch location of a logical core or the actual location of a physical core in an instruction information block (which provides information for mapping topology data used by the operating system in response to this instruction). CordL(1-6) 522 includes a preferred dispatch location of a logical core (FIG. 5B) or the actual location of a physical core (FIG. 5A) at a particular nesting level (i.e., hardware hierarchy level). In both example information blocks, the value of MNestC 524 indicates the number of possible topological nesting levels of the configuration. In computing environments, including but not limited to those utilizing the z / Architecture described above, if a particular computing system includes four drawers with two nodes per drawer, three chips per node, and ten cores per chip, the CordL(X) field (e.g., 522 in Figures 5A-5B) provides the topological location of the described core. For example, field 522 may indicate that a particular core is in drawer 3, node 2, chip 1, core 8.

[0081] 5A-5B, the CordL(1-6) 522 field (the preferred dispatch location of the logical core (FIG. 5B) or the actual location of the physical core (FIG. 5A)) can contain more detailed information (or less detailed information).

[0082] An example of more detailed information that may be provided in some embodiments of the present invention is six 1-byte fields, each containing an 8-bit unsigned binary integer, at a position at a particular nesting level. The value of each element therefore indicates the coordinate of a preferred dispatch position for a logical core at a particular topology nesting level. In this example, the coordinate values ​​are 1-based. A value of 0 indicates (1) that the particular nesting level is not defined in the topology, (2) the machine cannot provide the value, or (3) that the logical core does not have a preferred dispatch position at this nesting level, or a combination thereof.

[0083] As previously mentioned, in various embodiments of the present invention, one or more fields within an instruction may indicate a value specifying a maximum topological nesting level. Both of the illustrated portions of an instruction block (e.g., FIGS. 5A-5B) contain values ​​specifying a maximum topological nesting level. As previously mentioned, in the example illustrated in FIGS. 5A-5B, the maximum number of topological nesting levels for a configuration is defined by the value contained in the MNestC 524 field. CordL(1) indicates the coordinate at the highest topological nesting level, as defined by the configuration. Depending on the level of topological nesting defined in the MNestC 524 field, CordL(2) through CordL(6) may provide coordinates at decreasing levels of nesting, respectively. Thus, the value of MNestC 524 indicates the number of potential topological nesting levels indicated for the configuration, as contained in the CordL(1) through CordL(6) fields (e.g., 522 in FIGS. 5A-5B).

[0084] The function of the MNestC524 field is further explained in the following non-limiting example. In this example, the MNestC524 field can contain an unsigned binary integer value. This value is model-dependent, with a maximum value of 6. As previously explained, this value specifies the maximum nesting level of the topology. In this non-limiting example, a specific value (e.g., 0) indicates that the model does not provide information about the topology nesting level through this instruction and that the nesting level coordinate is undefined. In this non-limiting example, a different specific value (e.g., 1) indicates that CordL(1) is the only field that can contain a valid, non-zero value, and that no actual topology nesting structure exists, such that all elements are at the same nesting level. Specific values ​​can indicate the topology nesting level, starting with the field (CordL(1)) and proceeding to values ​​of CordL(2), CordL(3), etc., up to the value indicated in MNestC. In some examples, the CordL(x) field is stored as 0 if x is greater than the level of the MNestC value.

[0085] Returning to FIG. 1 , after program code executing on one or more processors issues an instruction (110), based on receiving one of the instructions containing one of the extended CPU or core information blocks or the extended physical CPU or core information block, the program code applies a security protocol to determine (120) which partitions the user can access (e.g., the user's private partition or all partitions). In some embodiments of the present invention, based on an operator selection, the program code determines whether to issue information about the logical partition or all defined logical partitions in response to receiving the executed instruction. Next, in response to the instruction containing associated security information included in the instruction, the program code provides (130) topology information used by the OS to map logical cores to physical cores. This mapping is enabled because the returned information provides a global view of either all logical partitions or the user's logical partitions (depending on the instruction).

[0086] Embodiments of the present invention include computer-implemented methods, systems, and computer program products in which specific instructions for obtaining and providing topology information are executed such that both the obtaining and providing of topology information occurs in a manner internal to a computer system. Figure 6 is a workflow illustrating certain aspects of some embodiments of the present invention. In embodiments of the present invention, program code running on one or more processors in a computing system executes instructions including both processing core information (logical and physical cores) and an operator's selection (610). The program code sets security parameters for information returned by the instructions based on the operator's selection (620). The returned information includes topology information regarding the mapping of logical cores to physical cores. The program code obtains topology information based on the information including the locations and security parameters (630). For example, the program code obtains the topology information through an interface internal to the computing system. The program code utilizes a topology system via an operating system running on the computing system to map logical cores to physical cores (640). In some examples, the program code displays a mapping to an interface internal to the computing system (650).

[0087] In some examples, depending on security parameters, topology information may include, but is not limited to, information providing a global view of all logical partitions within a computing system, and / or information providing a view of the logical partitions of one or more users within the computing system.

[0088] In some examples, the information including the location of a processing core within a computing system includes data representing a preferred dispatch location of a logical core.

[0089] In some examples, the information containing the locations of processing cores within a computing system includes data representing the actual locations of the physical cores.

[0090] In some examples, the instructions include a block of information, which includes information including a location of a processing core within a computing system.

[0091] In some examples, the information including the locations of processing cores within the computing system includes, for each processing core, a location at a particular topological nesting level.

[0092] In some examples, the processing core information includes the maximum number of topology nesting levels in the computing system.

[0093] In some examples, the topology information relates to a particular group of logical partitions, and membership within the particular group is defined in the processing core information, which may be a hardware group.

[0094] Referring now to FIG. 7, this figure is a schematic diagram of an example computing node, which may be cloud computing node 10. Cloud computing node 10 is merely one example of a suitable cloud computing node and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the present invention described herein. In any event, cloud computing node 10 may implement and / or perform any of the functions described above. In embodiments of the present invention, one or more of the elements of computing system 102 of FIG. 2A, including but not limited to one or more processors 104, may comprise cloud computing node 10 (FIG. 7) and, if not cloud computing node 10, one or more general computing nodes that include features of cloud computing node 10, respectively.

[0095] Within cloud computing node 10 are computer systems / servers 12 that may operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer systems / servers 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0096] The computer system / server 12 may be described in the general context of computer system executable instructions, such as program modules being executed by the computer system. Typically, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 12 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0097] 7, a computer system / server 12 that may be utilized as a cloud computing node 10 is shown in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 that couples various system components, including system memory 28, to processor 16.

[0098] Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example only, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnects (PCI) bus.

[0099] The computer system / server 12 typically includes a variety of computer system-readable media, which may be any available media that can be accessed by the computer system / server 12, including both volatile and nonvolatile media, removable and non-removable media.

[0100] System memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and an optical disk drive may be provided for reading from or writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. In such examples, each may be connected to bus 18 by one or more data media interfaces. As shown and described in detail below, memory 28 may include at least one program product comprising a series of (e.g., at least one) program modules configured to perform the functions of embodiments of the present invention.

[0101] For example, a program / utility 40 including a set of (at least one) program modules 42 may be stored in memory 28, including, but not limited to, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or a combination thereof, may include an implementation of a network environment. The program modules 42 typically perform the functions and / or methods of embodiments of the present invention described herein.

[0102] Computer system / server 12 may communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, one or more devices that allow a user to interact with computer system / server 12, or any device (e.g., network card, modem, etc.) that allows computer system / server 12 to communicate with one or more other computing devices, or a combination thereof. Such communication may occur through an input / output (I / O) interface 22. Additionally, computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, through a network adapter 20. As shown, network adapter 20 communicates with other components of computer system / server 12 via a bus 18. It should be understood that other hardware and / or software components, not shown, may be used with computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0103] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the subject matter recited herein is not limited to cloud computing environments. Embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0104] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0105] The features are as follows:

[0106] On-demand self-service: Cloud customers can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without the need for human interaction with the service provider.

[0107] Broad network access: Capacity is available over the network and can be accessed through standard mechanisms, facilitating consumption by heterogeneous thin- or thick-client platforms (e.g., cell phones, laptops, and PDAs). Resource pooling: A provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated according to demand. There is a sense of location independence; consumers typically have no control or knowledge regarding the exact location of the resources offered, although at higher levels of abstraction, locations (e.g., countries, states, or data centers) may be specified. Rapid elasticity: Capacity is provisioned quickly and flexibly, sometimes automatically, and can be quickly scaled out and quickly released to scale in. Capacity available for provisioning often appears to consumers as available for unlimited purchase in any quantity at any time.

[0108] Metered Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0109] The service model is as follows:

[0110] Software as a Service (SaaS): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. Those applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application functions, except for the possibility of limited user-specific application configuration settings.

[0111] Platform as a Service (PaaS): The ability offered to a consumer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0112] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0113] The deployment model is as follows:

[0114] Private Cloud: This cloud infrastructure is operated solely for the organization, can be managed by the organization or a third party, and can reside on-premise or off-premise.

[0115] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premises or off-premises.

[0116] Public cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0117] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct but are joined together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0118] A cloud computing environment is a service-oriented environment that emphasizes statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0119] Referring now to FIG. 8, an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 10 may communicate with each other. The nodes 10 may be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as previously described herein. This enables the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, eliminating the need for cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 8 are intended to be illustrative only, and it is understood that computing node 10 and cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0120] Referring now to Figure 9, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 8) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 9 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0121] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0122] The virtualization layer 70 comprises an abstraction layer capable of providing virtual entities such as virtual servers 71 , virtual storage 72 , virtual networks including virtual private networks 73 , virtual applications and operating systems 74 , and virtual clients 75 .

[0123] In one example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to execute tasks within the cloud computing environment. Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and sends bills or invoices for the utilization of those resources. In one example, those resources may include application software licenses. Security verifies the identity of cloud users and tasks and protects data and other resources. User portal 83 provides users and system administrators with access to the cloud computing environment. Service level management 84 allocates and manages cloud computing resources to meet required service levels. Service level agreement (SLA) planning and execution 85 proactively prepares and procures cloud computing resources in accordance with SLAs in anticipation of upcoming demand.

[0124] The Workload Layer 90 illustrates examples of functionality available in a cloud computing environment. Examples of workloads and functionality that may be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and obtaining information regarding a global view of the mapping of logical cores to physical cores across hypervisors 96.

[0125] The present invention may be a system, method, or computer program product, or any combination thereof, at any possible level of technical detail of integration. The computer program product may include one or more computer-readable storage media containing computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0126] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0127] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0128] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0129] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0130] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, where the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0131] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0132] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may possibly be executed in the reverse order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0133] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0134] Corresponding structures, materials, acts, and equivalents of all means or steps and functional elements within the scope of the claims below are intended to include any structure, material, or act for performing a function in combination with other claimed elements, if any, when specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications, and to enable others skilled in the art to appreciate various embodiments with various modifications as may be suited to the particular use contemplated.

Claims

1. 1. A computer-implemented method comprising: issuing, by one or more processors of a computing system, an instruction including processing core information, the processing core information including locations of one or more processing cores of the computing system, the processing cores of the computing system including logical cores and physical cores, the instruction further including an operator selection; setting, by the one or more processors, security parameters of information returned by the instruction based on the operator's selection, the returned information including topology information regarding the mapping of the logical cores to the physical cores; obtaining, by the one or more processors, the topology information based on the information including the location and the security parameters; and mapping, by the one or more processors, via an operating system running on the computing system, the logical cores to the physical cores utilizing the topology information.

2. 2. The computer-implemented method of claim 1, wherein the topology information is selected based on the security parameters from the group consisting of information providing a global view of all logical partitions within the computing system and information providing a view of the logical partitions of one or more users within the computing system.

3. 2. The computer-implemented method of claim 1, wherein the information including the location of the processing core within the computing system includes data representing a preferred dispatch location of the logical core.

4. 2. The computer-implemented method of claim 1, wherein the information including the location of the processing core within the computing system includes data representing an actual location of the physical core.

5. 2. The computer-implemented method of claim 1, wherein the instructions include a block of information, the block of information including the location of the processing core within the computing system.

6. 2. The computer-implemented method of claim 1, wherein the information including the locations of the processing cores within the computing system includes, for each processing core, a location at a particular topological nesting level.

7. 7. The computer-implemented method of claim 6, wherein the processing core information includes a maximum number of topology nesting levels in the computing system.

8. The computer-implemented method of claim 1 , further comprising displaying, by the one or more processors, the mapping on an interface internal to the computing system.

9. 2. The computer-implemented method of claim 1, wherein the topology information relates to logical partitions of a given group, and membership within the given group is defined in the processing core information.

10. The computer-implemented method of claim 9 , wherein the given group comprises a hardware group.

11. 10. The computer-implemented method of claim 1, wherein obtaining the topology information comprises obtaining the topology information via an interface internal to the computing system.

12. A computer program causing one or more processors of a shared computing environment comprising a computing system to execute the computer-implemented method of any one of claims 1 to 11.

13. Memory and one or more processors in communication with the memory; and program instructions executable by said one or more processors in a shared computing environment of the computing system via said memory to perform a method, said method comprising: issuing, by the one or more processors of the computing system, an instruction including processing core information, the processing core information including locations of one or more processing cores of the computing system, the processing cores of the computing system including logical cores and physical cores, the instruction further including an operator selection; setting, by the one or more processors, security parameters of information returned by the instruction based on the operator's selection, the returned information including topology information regarding the mapping of the logical cores to the physical cores; obtaining, by the one or more processors, the topology information based on the information including the location and the security parameters; and mapping, by the one or more processors, via an operating system running on the computing system, the logical cores to the physical cores utilizing the topology information.

Images