signal transmission device

Abstract

To provide a signal transmitter with which it is possible to speed up switching between in-phase transmission and differential transmission.SOLUTION: A transmission buffer of the signal transmitter according to an embodiment includes a differential circuit unit that is connected between a first potential and a second potential, a variable current source unit that supplies a current to the differential circuit unit, a switch unit that switches states from a conductive state to a cutoff state and vice versa between a first transmission terminal and a fixed potential and between a second transmission terminal and the fixed potential, and a control unit that controls the current supplied to the differential circuit unit by the variable current source unit and controls the switch unit. A reception buffer includes a first differential pair of first conductive type that is connected between a third potential and a fourth potential, a second differential pair of second conductive type that is connected between the third potential and the fourth potential and outputs a third reception current in accordance with a first transmission signal, and outputs a fourth reception current in accordance with a second transmission signal, a first current mirror unit, and a second current mirror unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a signal transmission device. [Background technology]

[0002] For example, a signal transmission device, which is an interface circuit for communication between chips, is preferably an LVDS (Low-Voltage Differential Signaling) circuit that can reduce the voltage amplitude between chips from the viewpoint of current consumption and reduction of radiated noise.

[0003] Some LVDS signal transmission devices employ a transmission method that combines differential signals and in-phase signals.

[0004] For example, in the case of a format in which in-phase and differential signals are transmitted alternately every clock, the propagation delay of the differential transmission must be equal to the transition time between the in-phase transmission and the differential transmission.

[0005] That is, in an LVDS signal transmission device, it is necessary to increase the speed of switching between in-phase transmission and differential transmission. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-112453 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment is to provide a signal transmission device that can speed up switching between in-phase transmission and differential transmission. [Means for solving the problem]

[0008] A signal transmission device according to one embodiment is a signal transmission device including a transmission buffer and a reception buffer, The transmission buffer a differential circuit section connected between a first potential and a second potential, and configured to output a first transmission signal to the first transmission terminal and a second transmission signal to the second transmission terminal in response to a first input signal input via the first input terminal and a second input signal input via the second input terminal; a variable current source unit that supplies a current to the differential circuit unit; a switch unit that switches between a conductive state and a cut-off state between the first transmitting terminal and a fixed potential and between the second transmitting terminal and the fixed potential; a control unit that controls the current supplied from the variable current source unit to the differential circuit unit and also controls the operation of the switch unit, The receiving buffer a first differential pair of a first conductivity type connected between a third potential and a fourth potential, which outputs a first reception current in response to the first transmission signal input via a first reception terminal and outputs a second reception current in response to the second transmission signal input via a second reception terminal; a second differential pair of a second conductivity type connected between the third potential and the fourth potential, which outputs a third reception current in response to the first transmission signal and a fourth reception current in response to the second transmission signal; a first current mirror unit that causes a current obtained by current-mirroring the first received current to flow between the third potential and a second output terminal, and that causes a current obtained by current-mirroring the second received current to flow between the third potential and the first output terminal; a second current mirror unit configured to cause a current obtained by current-mirroring the third received current to flow between the second output terminal and the fourth potential, and to cause a current obtained by current-mirroring the fourth received current to flow between the first output terminal and the fourth potential. It is characterized by: [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a signal transmission device according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a configuration of a signal transmission device according to an embodiment. [Figure 3] FIG. 3 is a waveform diagram for explaining an example of the operation of the signal transmission device shown in FIG. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of a signal transmission device according to the second embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a signal transmission device according to the third embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a transmission buffer of a signal transmission device according to a modified example. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of a signal transmission system to which the signal transmission device according to each embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, a signal transmission device according to an embodiment will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0011] (First embodiment) [Signal transmission device] FIG. 1 is a diagram illustrating an example of the configuration of a signal transmission device according to the first embodiment.

[0012] The signal transmission device 100 according to the first embodiment is a signal transmission device of the LVDS (Low-Voltage Differential Signaling) system.

[0013] As shown in FIG. 1, the signal transmission device 100 according to the first embodiment includes a transmission buffer TX and a reception buffer RX.

[0014] The transmission buffer TX and the reception buffer RX are connected by a first wiring (wire) QP and a second wiring (wire) QN.

[0015] [Send Buffer] The transmission buffer TX outputs a first transmission signal 1a and a second transmission signal 1b in response to a first input signal INP input via a first input terminal TINP and a second input signal INN input via a second input terminal TINN. This transmission buffer circuit TX is an LVDS circuit.

[0016] As shown in FIG. 1, the transmission buffer TX includes, for example, a differential circuit unit M, variable current source units IT1 and IT2, switch units SW1 and SW2, and a control unit CON.

[0017] The differential circuit section M is connected between a first potential (for example, a power supply potential of the transmission buffer TX) V1 and a second potential (for example, a ground potential of the transmission buffer TX) V2.

[0018] The differential circuit section M is configured to output a first transmission signal 1a to a first transmission terminal TP and a second transmission signal 1b to a second transmission terminal TN in response to a first input signal INP input via a first input terminal TINP and a second input signal INN input via a second input terminal TINN.

[0019] The variable current source units IT1 and IT2 are connected between the first potential V1 and the second potential V2. The variable current source units IT1 and IT2 supply current to the differential circuit unit M, and the value of the current is variable.

[0020] The switch sections SW1 and SW2 are adapted to switch between a conductive state and a cut-off state between the first transmitting terminal TP and a fixed potential and between the second transmitting terminal TN and the fixed potential.

[0021] In the example shown in FIG. 1, the fixed potential is a second potential (for example, the ground potential of the transmission buffer TX) V2, but as will be described later, it may be a first potential (for example, the power supply potential of the transmission buffer TX) V1.

[0022] The control section CON controls the currents supplied from the variable current source sections IT1 and IT2 to the differential circuit section M, and also controls the operations of the switch sections SW1 and SW2.

[0023] Here, for example, when the first input signal INP and the second input signal INN are in-phase (common mode) signals (e.g., LL signals: in-phase signals at a "Low" level), the control unit CON controls the switch units SW1 and SW2 to turn on so that conduction is established between the first transmitting terminal TP and the fixed potential (here, the second potential V2) and between the second transmitting terminal TN and the fixed potential.

[0024] This allows the common mode voltage to fall rapidly when the first input signal INP and the second input signal INN are in-phase signals (for example, LL signals).

[0025] On the other hand, when the first input signal INP and the second input signal INN are differential signals, the control unit CON controls the switch units SW1 and SW2 to be turned off so that the first transmitting terminal TP and the fixed potential and the second transmitting terminal TN and the fixed potential are disconnected from each other.

[0026] Furthermore, when the first input signal INP and the second input signal INN are in-phase signals, the control section CON controls the variable current source section IT so that the current supplied to the differential circuit section M increases.

[0027] On the other hand, when the first input signal INP and the second input signal INN are differential signals, the control section CON controls the variable current source section IT so that the current supplied to the differential circuit section M decreases.

[0028] This allows the common mode voltage to rise rapidly when the first input signal INP and the second input signal INN are differential signals.

[0029] 1, a first wiring (wire) QP is connected between the first transmitting terminal TP and the first receiving terminal RP, and the first transmission signal output from the transmitting buffer TX is transmitted to the receiving buffer RX via the first wiring QP. Also, a second wiring (wire) QN is connected between the second transmitting terminal TN and the second receiving terminal RN, and the second transmission signal output from the transmitting buffer TX is transmitted to the receiving buffer RX via the second wiring QN.

[0030] [Receive buffer] The receiving buffer RX outputs a first output signal OUTP to a first output terminal TOUTP and a second output signal OUTN to a second output terminal TOUTN in response to the first transmission signal 1a and the second transmission signal 1b. The receiving circuit RX is an LVDS circuit.

[0031] As shown in FIG. 1, the receive buffer RX includes, for example, a first differential pair (nMOS differential pair) G1 of a first conductivity type, a second differential pair (pMOS differential pair) G2 of a second conductivity type, an input resistor Z, a first current mirror unit F1, a second current mirror unit F2, a first constant current source IR1, and a second constant current source IR2.

[0032] The first differential pair (nMOS differential pair) G1 is connected between a third potential (for example, a power supply potential of the receiving buffer RX) V3 and a fourth potential (for example, a ground potential of the receiving buffer RX) V4. The first differential pair G1 outputs a first receiving current H1 in response to a first transmission signal 2a input via a first receiving terminal RP, and outputs a second receiving current H2 in response to a second transmission signal 2b input via a second receiving terminal RN.

[0033] The first constant current source IR1 is connected between the fourth potential V4 and the first differential pair G1, and supplies a current to the first differential pair G1.

[0034] The input resistor Z is connected between the first receiving terminal RP and the second receiving terminal RN.

[0035] The second differential pair (pMOS differential pair) G2 is connected between the third potential V3 and the fourth potential V4. The second differential pair G2 outputs a third receiving current H3 in response to the first transmission signal 2a, and outputs a fourth receiving current H4 in response to the second transmission signal 2b.

[0036] The second constant current source IR2 is connected between the third potential V3 and the second differential pair G2, and supplies a current to the second differential pair G2.

[0037] In addition, the first current mirror section F1 is configured to flow a current that is a current mirror of the first receiving current H1 between the third potential V3 and the second output terminal TOUTN, and to flow a current that is a current mirror of the second receiving current H2 between the third potential V3 and the first output terminal TOUTP.

[0038] In addition, the second current mirror section F2 flows a current that is a current mirror of the third receiving current H3 between the second output terminal TOUTN and the fourth potential V4, and flows a current that is a current mirror of the fourth receiving current H4 between the first output terminal TOUTP and the fourth potential V4.

[0039] Here, for example, when the first transmission signal 2a and the second transmission signal 2b input to the receiving buffer RX are in-phase signals (here, LL signals), the first differential pair G1 is turned off (two nMOS transistors are turned off) to stop the output of the first and second receiving currents H1 and H2, and the second differential pair G2 is turned on (two pMOS transistors are turned on) to output the third and fourth receiving currents H3 and H4.

[0040] As a result, when the first transmission signal 2a and the second transmission signal 2b input to the receiving buffer RX are in-phase signals (LL signals in this case), the first current mirror unit F1 does not allow current to flow between the third potential V3 and the first and second output terminals TOUTP, TOUTN, and the second current mirror unit F2 allows current to flow between the fourth potential V4 and the first and second output terminals TOUTP, TOUTN. In other words, when the first transmission signal and the second transmission signal are in-phase signals (LL signals in this case), the first and second output signals OUTP, OUTN (in-phase signals (LL signals)) of "Low" level are output from the first and second output terminals TOUTP, TOUTN.

[0041] Therefore, when the first input signal INP and the second input signal INN are in-phase signals, the signal transmission device 100 outputs the first and second output signals OUTP and OUTN which are in-phase signals.

[0042] On the other hand, when the first transmission signal and the second transmission signal input to the receiving buffer RX are differential signals, the first differential pair G1 outputs first and second receiving currents H1 and H2, and the second differential pair G2 outputs third and fourth receiving currents in accordance with the first transmission signal and the second transmission signal.

[0043] As a result, when the first transmission signal and the second transmission signal input to the receiving buffer RX are differential signals, the first and second output signals OUTP and OUTN, which are differential signals, are output. Therefore, when the first input signal INP and the second input signal INN are differential signals, the first and second output signals OUTP and OUTN, which are differential signals, are output.

[0044] In this way, the signal transmission device 100, which is an LVDS circuit, comprises a transmission buffer TX that outputs a fixed signal of a predetermined potential corresponding to the input signal when the input signal is an in-phase signal, and a reception buffer RX that outputs an in-phase signal corresponding to the transmission signal when the transmission signal input from the transmission buffer TX is an in-phase signal.

[0045] Here, an example of each detailed configuration and operation of the signal transmission device 100 according to the first embodiment will be described with reference to the following specific examples.

[0046] Fig. 2 is a diagram showing an example of the configuration of a signal transmission device according to an embodiment. Fig. 3 is a waveform diagram for explaining an example of the operation of the signal transmission device shown in Fig. 2. In the following explanation, among the components shown in Fig. 2, the same components as those shown in Fig. 1 may be denoted by the same reference numerals as those shown in Fig. 1, and their explanation may be omitted. Note that each circuit configuration of the signal transmission device 100 according to the embodiment shown in Fig. 2 is an example, and may be replaced with a configuration that can perform similar functions.

[0047] [Send Buffer] As described in the first embodiment, the transmission buffer TX outputs a first transmission signal 1a and a second transmission signal 1b in response to a first input signal INP input via a first input terminal TINP and a second input signal INN input via a second input terminal TINN. This transmission buffer circuit TX is an LVDS circuit.

[0048] As shown in FIG. 2, the transmission buffer TX includes, for example, a differential circuit unit M, variable current source units IT1 and IT2, a switch unit SW, and a control unit CON.

[0049] [Differential circuit] As described above, the differential circuit section M is connected between the first potential V1 and the second potential V2, and outputs the first transmission signal 1a to the first transmission terminal TP and the second transmission signal 1b to the second transmission terminal TN in response to the first input signal INP input via the first input terminal TINP and the second input signal INN input via the second input terminal TINN.

[0050] As shown in FIG. 2, the differential circuit section M includes, for example, pMOS transistors (MOS transistors of a first conductivity type) Ma and Mb, and nMOS transistors (MOS transistors of a second conductivity type) Mc and Md.

[0051] The pMOS transistor Ma has a gate connected to the second input terminal INN, a source connected to the first variable current source IT1, and a drain connected to the first transmitting terminal TP, while the pMOS transistor Mb has a gate connected to the first input terminal INP, a source connected to the first variable current source IT1, and a drain connected to the second transmitting terminal TN.

[0052] The nMOS transistor Mc has a gate connected to the second input terminal INN, a source connected to the second variable current source IT2, and a drain connected to the first transmitting terminal TP. The nMOS transistor Md has a gate connected to the first input terminal INP, a source connected to the second variable current source IT2, and a drain connected to the second transmitting terminal TN.

[0053] [Variable current source] As shown in FIG. 2, the variable current source sections IT1 and IT2 include, for example, a first variable current source IT1 and a second variable current source IT2.

[0054] The first variable current source IT1 is connected between the first potential V1 and the differential circuit section M, and supplies a current to the differential circuit section M.

[0055] More specifically, the first variable current source IT1 includes, for example, a constant current source I1a and a pMOS transistor I1b, as shown in FIG.

[0056] The constant current source I1a is connected between the first potential V1 and the differential circuit M (the sources of the pMOS transistors Ma and Mb). This constant current source I1a is configured to supply a preset constant current to the differential circuit M. Note that the constant current source I1a may be configured as a current mirror circuit, for example, by using MOS transistors connected between the first potential V1 and the differential circuit M and having a preset voltage applied to their gates.

[0057] The pMOS transistor I1b has a gate connected to the control unit CON, a source connected to the first potential V1, and a drain connected to the differential circuit M (the sources of the pMOS transistors Ma and Mb). The pMOS transistor I1b is controlled to be turned on or off by a control signal S11 output by the control unit CON.

[0058] Here, the control unit CON adjusts the conduction state of this pMOS transistor I1b in response to the first and second input signals INP and INN, thereby changing the current output by the first variable current source IT1 that constitutes the variable current source units IT1 and IT2. Note that the control unit CON may also adjust the conduction state of this pMOS transistor I1b in response to an external signal, thereby changing the current output by the first variable current source IT1 that constitutes the variable current source units IT1 and IT2.

[0059] The second variable current source IT2 is connected between the second potential V2 and the differential circuit section M, and supplies a current to the differential circuit section M.

[0060] Furthermore, the second variable current source IT2 includes, for example, a constant current source I2a and nMOS transistors I2b, I2c, and I2d as shown in FIG.

[0061] The constant current source I2a is connected between the second potential V2 and the differential circuit M (the sources of the nMOS transistors Mc and Md). This constant current source I2a is configured to supply a preset constant current to the differential circuit M. Note that the constant current source I2a may be configured as a current mirror circuit, for example, by using MOS transistors connected between the second potential V2 and the differential circuit M and having a preset voltage applied to their gates.

[0062] The nMOS transistor I2b has a gate connected to the control unit CON, a source connected to the second potential V2, and a drain connected to the differential circuit M (the nMOS transistors Mc and the sources of Mc). The nMOS transistor I2b is controlled to be turned on or off by a control signal S12 output by the control unit CON.

[0063] Here, the control unit CON adjusts the conduction state of this nMOS transistor I2b in response to the first and second input signals INP and INN (or an external signal not shown), thereby changing the current output by the second variable current source IT2 that constitutes the variable current source units IT1 and IT2.

[0064] Furthermore, the nMOS transistor I2c is connected between the constant current source I2a and the second potential V2, with its gate connected to the first transmitting terminal TP (the sources of the pMOS transistor Ma and the nMOS transistor Mc). Furthermore, the nMOS transistor I2d is connected between the constant current source I2a and the second potential V2, with its gate connected to the second transmitting terminal TN (the drains of the pMOS transistor Mb and the nMOS transistor Md). These nMOS transistors I2c and I2d control the charging and discharging of the common-mode voltage at the first and second transmitting terminals TP and TN. Note that this nMOS transistor may be feedback-controlled by a differential amplifier based on a voltage obtained by dividing the output voltage of the differential circuit M.

[0065] [Switch section] As mentioned above, The switch sections SW1 and SW2 include, for example, a first switch SW1 and a second switch SW2 as shown in FIG.

[0066] The first switch SW1 is connected between the first transmitting terminal TP and the second potential V2. The first switch SW1 is controlled to be turned on / off by a control signal S10 output by the control unit CON. For example, as shown in FIG. 2, the first switch SW1 is configured as a MOS transistor connected between the first transmitting terminal TP and the second potential V2 and having a gate to which the control signal S10 is input.

[0067] The second switch SW2 is connected between the second transmitting terminal TN and the second potential V2. The second switch SW2 is controlled to be turned on or off by a control signal S10 output by the control unit CON. For example, as shown in Fig. 2, the second switch SW2 is connected between the second transmitting terminal TN and the second potential V2 and is configured as a MOS transistor having a gate to which the control signal S10 is input.

[0068] [Control Unit] As described above, the control unit CON controls the current supplied to the differential circuit unit M by the variable current source units IT1 and IT2 (first and second variable current sources IT1 and IT2), and also controls the operation of the switch units SW1 and SW2 (first and second switches SW1 and SW2).

[0069] As shown in FIG. 2, the control unit CON includes, for example, a NOR circuit C1, a first inverter C2, a delay circuit C3, and a second inverter C4.

[0070] The NOR circuit C1 receives the first input signal INP and the second input signal INN, and outputs a signal (switch control signal S10) obtained by performing an operation on the first input signal INP and the second input signal INN.

[0071] The first inverter C2 receives the signal (switch control signal S10) output by the NOR circuit C1, and outputs a signal obtained by inverting the signal (switch control signal S10).

[0072] The delay circuit C3 receives the signal output by the first inverter C2, delays the signal by a preset delay time, and outputs a signal (first current control signal S11).

[0073] In addition, the second inverter C4 receives the signal (first current control signal S11) output by the delay circuit C3 and outputs a signal (second current control signal S12) that is an inversion of the signal (first current control signal S11).

[0074] Here, for example, when the first input signal INP and the second input signal INN are differential signals, the control unit CON turns off the first switch SW1 and the second switch SW2 using the control signal S10.

[0075] On the other hand, when the first input signal INP and the second input signal INN are in-phase signals, the control unit CON turns on the first switch SW1 and the second switch SW2 by the control signal S10.

[0076] When the first input signal INP and the second input signal INN are in-phase signals, the control unit CON controls the switch unit SW to be on so as to establish electrical continuity between the first transmitting terminal TP and a fixed potential (here, the second potential V2) and between the second transmitting terminal TN and the fixed potential, and then, after a preset delay time has elapsed, controls the variable current source units IT1 and IT2 so as to increase the current supplied to the differential circuit unit M.

[0077] On the other hand, when the first input signal INP and the second input signal INN are differential signals, the control unit CON controls the switch units SW1 and SW2 to be turned off so that the first transmitting terminal TP and the fixed potential (second potential V2) and the second transmitting terminal TN and the fixed potential are disconnected, and then, after the delay time has elapsed, controls the variable current source units IT1 and IT2 so that the current supplied to the differential circuit unit M decreases.

[0078] Thus, in the example shown in FIG. 2, the control unit CON controls the operations of the first and second variable current sources IT1, IT2, the first switch SW1, and the second switch SW2 based on the input of the first input signal INP and the second input signal INN.

[0079] However, the present invention is not limited to this, and the control unit CON may be configured to control the operations of the first and second variable current sources IT1 and IT2, the first switch SW1, and the second switch SW2 based on an input of an external signal (not shown). In this case, for example, the NOR circuit C1 of the control unit CON may be omitted from the circuit configuration, and the external signal may be input to the first inverter C2, causing the delay circuit C3 to output a first current control signal S11 that controls the first variable current source unit IT1 and the second inverter C4 to output a second current control signal S12 that controls the second variable current source unit IT2. Furthermore, in this case, the control unit CON may output the external signal as a switch control signal S10 that controls the first and second switches SW1 and SW2.

[0080] [Receive buffer] As described in the first embodiment, the receiving buffer RX outputs the first output signal OUTP to the first output terminal TOUTP and the second output signal OUTN to the second output terminal TOUTN in response to the first transmission signal 1a and the second transmission signal 1b. This receiving circuit RX is an LVDS circuit.

[0081] As shown in FIG. 1, the receive buffer RX includes, for example, a first differential pair (nMOS differential pair) G1 of a first conductivity type, a second differential pair (pMOS differential pair) G2 of a second conductivity type, an input resistor Z, a first current mirror unit F1, a first constant current source IR1, and a second constant current source IR2.

[0082] [First differential pair] As described above, the first differential pair (nMOS differential pair) G1 is connected between a third potential (for example, a power supply potential of the receiving buffer RX) V3 and a fourth potential (for example, a ground potential of the receiving buffer RX) V4. This first differential pair G1 outputs a first receiving current H1 in response to a first transmission signal 2a input via a first receiving terminal RP, and outputs a second receiving current H2 in response to a second transmission signal 2b input via a second receiving terminal RN.

[0083] The first differential pair G1 includes, for example, nMOS transistors G1a and G1b as shown in FIG.

[0084] The nMOS transistor G1a has a source connected to the first constant current source IR1, a gate connected to the second receiving terminal RN, and a drain connected to the first current mirror section F1 (the drain of the pMOS transistor F1a).

[0085] The nMOS transistor G1b has a source connected to the first constant current source IR1, a gate connected to the first receiving terminal RP, and a drain connected to the first current mirror section F1 (the drain of the pMOS transistor F1c).

[0086] [Second differential pair] As described above, the second differential pair (pMOS differential pair) G2 is connected between the third potential V3 and the fourth potential V4. This second differential pair G2 outputs the third receiving current H3 in response to the first transmission signal 2a, and outputs the fourth receiving current H4 in response to the second transmission signal 2b.

[0087] The second differential pair G2 includes, for example, pMOS transistors G2a and G2b as shown in FIG.

[0088] The pMOS transistor G2a has a source connected via the second constant current source IR2, a gate connected to the first receiving terminal RP, and a drain connected to the second current mirror section F2 (the drain of the nMOS transistor F2a).

[0089] The pMOS transistor G2b has a source connected to the second constant current source IR2, a gate connected to the second receiving terminal RN, and a drain connected to the second current mirror section F2 (the drain of the nMOS transistor F2c).

[0090] [First current mirror section] As described above, the first current mirror section F1 flows a current obtained by current-mirroring the first receiving current H1 output by the first differential pair G1 between the third potential V3 and the second output terminal TOUTN, and also flows a current obtained by current-mirroring the second receiving current H2 output by the first differential pair G1 between the third potential V3 and the first output terminal TOUTP.

[0091] The first current mirror section F1 includes, for example, pMOS transistors F1a, F1b, F1c, and F1d as shown in FIG.

[0092] The pMOS transistor F1a has a source connected to the third potential V3, and a gate and a drain connected to the first differential pair G1 (the drain of the nMOS transistor G1a).

[0093] The pMOS transistor F1b has a source connected to the third potential V3, a drain connected to the first output terminal TOUTP, and a gate connected to the gate of the pMOS transistor F1a and the first differential pair G1 (the drain of the nMOS transistor G1a).

[0094] These pMOS transistors F1a and F1b form a current mirror circuit that mirrors the second receiving current H2 output from the first differential pair G1 and passes the resulting current between the third potential V3 and the first output terminal TOUTP.

[0095] Moreover, the pMOS transistor F1c has a source connected to the third potential V3, and a gate and a drain connected to the first differential pair G1 (the drain of the nMOS transistor G1b).

[0096] The pMOS transistor F1d has a source connected to the third potential V3, a drain connected to the second output terminal TOUTN, and a gate connected to the gate of the pMOS transistor F1c and the first differential pair G1 (the drain of the nMOS transistor G1b).

[0097] These pMOS transistors F1c and F1d form a current mirror circuit that mirrors the first receiving current H1 output from the first differential pair G1 and causes the current to flow between the third potential V3 and the second output terminal TOUTN.

[0098] [Second current mirror section] As described above, the second current mirror section F2 flows a current mirrored from the third receiving current H3 output by the second differential pair G2 between the second output terminal TOUN and the fourth potential V4, and also flows a current mirrored from the fourth receiving current H4 between the first output terminal TOUTP and the fourth potential V4.

[0099] The second current mirror section F2 includes, for example, nMOS transistors F2a, F2b, F2c, and F2d as shown in FIG.

[0100] The nMOS transistor F2a has a source connected to the fourth potential V4, and a gate and a drain connected to the second differential pair G2 (the drain of the pMOS transistor G2a).

[0101] The nMOS transistor F2b has a source connected to the fourth potential V4, a drain connected to the second output terminal TOUTN, and a gate connected to the gate of the pMOS transistor F2a and the second differential pair G2 (the drain of the pMOS transistor G2a).

[0102] These nMOS transistors F2a and F2b form a current mirror circuit that mirrors the third receiving current H3 output from the second differential pair G2 and passes the resulting current between the fourth potential V4 and the second output terminal TOUTN.

[0103] Moreover, the nMOS transistor F2c has a source connected to the fourth potential V4, and a gate and a drain connected to the second differential pair G2 (the drain of the pMOS transistor G2b).

[0104] The nMOS transistor F2d has a source connected to the fourth potential V4, a drain connected to the first output terminal TOUTP, and a gate connected to the gate of the nMOS transistor F2c and the second differential pair G2 (the drain of the pMOS transistor G2b).

[0105] These nMOS transistors F2c and F2d form a current mirror circuit that mirrors the fourth receiving current H4 output from the second differential pair G2 and passes the mirrored current between the fourth potential V4 and the first output terminal TOUTP.

[0106] [First constant current source], As described above, the first constant current source IR1 is connected between the fourth potential V4 and the first differential pair G1 to supply a current to the first differential pair G1. This constant current source IR1 may be configured as a current mirror circuit, for example, by using MOS transistors connected between the fourth potential V4 and the first differential pair G1 and having a preset voltage applied to their gates.

[0107] [Second constant current source] As described above, the second constant current source IR2 is connected between the third potential V3 and the second differential pair G2 to supply a current to the second differential pair G2. This constant current source IR2 may be configured as a current mirror circuit, for example, by using MOS transistors connected between the third potential V3 and the second differential pair G2 and having a preset voltage applied to their gates.

[0108] Next, an example of the operation of the signal transmission device 100 having the above configuration will be described. As already mentioned, Fig. 3 is a waveform diagram for explaining an example of the operation of the signal transmission device shown in Fig. 2.

[0109] Here, for example, as shown in FIG. 3, when the first input signal INP and the second input signal INN are differential signals, the control unit CON turns off the first switch SW1 and the second switch SW2 using a control signal S10 (up to time t1).

[0110] Then, at time t1, when the first input signal INP and the second input signal INN become in-phase signals (LL signals), the control unit CON controls the first and second switches SW1 and SS2 to turn on so as to establish conduction between the first transmitting terminal TP and a fixed potential (here, the second potential V2) and between the second transmitting terminal TN and the fixed potential, and then, after a preset delay time (from time t1 to time t2) has elapsed, the control unit CON controls the variable current source units IT1 and IT2 (turning on the pMOS transistor I1b and the nMOS transistor I2b) so as to increase the current supplied to the differential circuit unit M (from time t2 to time t4).

[0111] In this way, when the first transmission signal 2a and the second transmission signal 2b input to the receiving buffer RX are in-phase signals (LL signals), the first differential pair G1 of the receiving buffer RX is turned off (the two nMOS transistors G1a and G1b are turned off) to stop the output of the first and second receiving currents H1 and H2, and the second differential pair G2 is turned on (the two pMOS transistors G2a and G2b are turned on) to output the third and fourth receiving currents H3 and H4.

[0112] As a result, when the first transmission signal 2a and the second transmission signal 2b input to the receiving buffer RX are in-phase signals (LL signals), the first current mirror unit F1 does not allow current to flow between the third potential V3 and the first and second output terminals TOUTP, TOUTN, and the second current mirror unit F2 allows current to flow between the fourth potential V4 and the first and second output terminals TOUTP, TOUTN. In other words, when the first transmission signal and the second transmission signal are in-phase signals (LL signals in this case), the first and second output signals OUTP, OUTN (in-phase signals (LL signals)) of "Low" level are output from the first and second output terminals TOUTP, TOUTN.

[0113] Therefore, when the first input signal INP and the second input signal INN are in-phase signals, the signal transmission device 100 outputs the first and second output signals OUTP and OUTN which are in-phase signals (LL signals).

[0114] Then, at time t3, when the first input signal INP and the second input signal INN become differential signals, the control unit CON controls the first and second switches SW1 and SW2 to be turned off so as to cut off the connection between the first transmitting terminal TP and the fixed potential (second potential V2) and the connection between the second transmitting terminal TN and the fixed potential, and then, after the delay time (from time t3 to time t4) has elapsed, controls the variable current source units IT1 and IT2 (turns off the pMOS transistor I1b and the nMOS transistor I2b) so as to reduce the current supplied to the differential circuit unit M.

[0115] In this way, the drive current (current supplied by the variable current source units IT1 and IT2) of the differential circuit M increases at the timing of switching between in-phase transmission and differential transmission in the transmission buffer TX, thereby speeding up the switching operation.

[0116] Furthermore, when the first transmission signal and second transmission signal input to the receiving buffer RX become differential signals, the first differential pair G1 of the receiving buffer RX outputs first and second receiving currents H1 and H2, and the second differential pair G2 outputs third and fourth receiving currents, in accordance with the first and second transmission signals.

[0117] As a result, when the first transmission signal and second transmission signal input to the receiving buffer RX are differential signals, the first and second output signals OUTP and OUTN, which are differential signals, are output.

[0118] Therefore, when the first input signal INP and the second input signal INN are differential signals, the signal transmission device 100 outputs the first and second output signals OUTP and OUTN, which are differential signals.

[0119] Thereafter, the signal transmission device 100 repeats the same operations in response to the first and second input signals INP and INN.

[0120] As described above, in the signal transmission device 100, in the case of in-phase transmission, the operation of the transmission buffer TX achieves high-speed in-phase transmission, and since the reception buffer RX can output output signals OUTP and OUTN at a level fixed to a fixed potential (ground potential), it is possible to receive the signals using an inverter, thereby simplifying the downstream circuitry.

[0121] That is, the signal transmission device 100 according to the first embodiment can speed up switching between in-phase transmission and differential transmission.

[0122] In the first embodiment, an example of the configuration of the signal transmission device has been described. However, the configuration of this signal transmission device is not limited to this. Therefore, in the following second and third embodiments, other examples of the configuration of the signal transmission device will be described.

[0123] (Second embodiment) In the signal transmission device 100 according to the first embodiment described above, it is assumed that in-phase "Low" level signals are transmitted, and an example has been described in which the first and second transmission terminals TP and TN are connected to the second potential (ground potential) V2 as a fixed potential when the first and second input signals INP and INN are LL signals ("Low" level in-phase signals) as in-phase signals.

[0124] However, assuming a case where an in-phase "High" level signal is transmitted, when the first and second input signals INP, INN are in-phase HH signals ("High" level in-phase signals), the first and second transmitting terminals TP, TN may be connected to a first potential (power supply potential) V1 as a fixed potential.

[0125] Therefore, in the second embodiment, an example of a signal transmission device will be described assuming a case where in-phase "High" level signals are transmitted. Fig. 4 is a diagram showing an example of the configuration of a signal transmission device according to the second embodiment. In the following description, among the components shown in Fig. 4, the same components as those shown in Fig. 1 are assigned the same reference numerals as those shown in Fig. 1, and description thereof will be omitted.

[0126] In the signal transmission device 200 according to the second embodiment, for example, as shown in FIG. 4, the connection relationship between the switch sections SW1x and SW2x of the transmission buffer TX is different from that between the switch sections SW1 and SW2 of the transmission buffer TX according to the first embodiment shown in FIG.

[0127] That is, in the signal transmission device 200 according to the second embodiment, the switch sections SW1x and SW2x of the transmission buffer TX are configured to switch between a conductive state and a cut-off state between the first transmission terminal TP and a first potential V1, which is a fixed potential (e.g., the power supply potential of the transmission buffer TX), and between the second transmission terminal TN and the first potential, which is the fixed potential.

[0128] The control unit CON controls the currents supplied from the variable current source units IT1 and IT2 to the differential circuit unit M using control signals S11 and S12, and also controls the operations of the switch units SW1x and SW2x using a control signal S10x.

[0129] Here, in this second embodiment, for example, when the first input signal INP and the second input signal INN are in-phase (common mode) signals (i.e., HH signals: in-phase signals at a "High" level), the control unit CON controls the switch units SW1 and SW2 to be on so that conduction is established between the first transmitting terminal TP and the fixed potential (i.e., the first potential V1) and between the second transmitting terminal TN and the fixed potential.

[0130] This allows the common mode voltage to rise rapidly when the first input signal INP and the second input signal INN are in-phase signals (ie, HH signals).

[0131] On the other hand, when the first input signal INP and the second input signal INN are differential signals, the control unit CON controls the switch units SW1x and SW2x to be turned off so that the first transmitting terminal TP and the fixed potential and the second transmitting terminal TN and the fixed potential are disconnected from each other.

[0132] Other configurations and operations of the signal transmission device 200 of the second embodiment are similar to those of the signal transmission device 100 of the first embodiment.

[0133] That is, the signal transmission device according to the second embodiment can speed up switching between in-phase transmission and differential transmission.

[0134] (Third embodiment) In the signal transmission devices 100 and 200 according to the first and second embodiments described above, it is assumed that only one of an in-phase "Low" level signal or a "High" level signal is transmitted, and an example has been described in which, when the first and second input signals INP and INN are in-phase LL signals ("Low" level or "High" level in-phase signals), the first and second transmitting terminals TP and TN are connected to a second potential (ground potential) V2 or a first potential (power supply potential) as a fixed potential.

[0135] However, assuming a case where in-phase "Low" level signals and "High" level signals are transmitted, when the first and second input signals INP, INN are in-phase LL signals ("Low" level in-phase signals), the first and second transmitting terminals TP, TN may be connected to the second potential (ground potential) V2 as a fixed potential, and further when the first and second input signals INP, INN are in-phase HH signals ("High" level in-phase signals), the first and second transmitting terminals TP, TN may be connected to the first potential (fixed potential) V1 as a fixed potential.

[0136] Therefore, in the third embodiment, an example of a signal transmission device will be described assuming a case where in-phase "High" level signals are transmitted. Fig. 5 is a diagram showing an example of the configuration of a signal transmission device according to the third embodiment. In the following explanation, among the components shown in Fig. 5, the same components as those shown in Figs. 1 and 4 are assigned the same reference numerals as those shown in Figs. 1 and 4, and explanations thereof will be omitted.

[0137] In the signal transmission device 300 according to the third embodiment, for example, as shown in FIG. 5, the connection relationship of the switch units SW1, SW2, SW1x, and SW2x of the transmission buffer TX is a combination of the switch units SW1 and SW2 of the transmission buffer TX according to the first embodiment shown in FIG. 1 and the switch units SW1x and SW2x of the transmission buffer TX according to the second embodiment shown in FIG. 4.

[0138] In the signal transmission device 300 according to the third embodiment, the control unit CON controls the currents supplied by the variable current source units IT1 and IT2 to the differential circuit unit M using control signals S11 and S12, and also controls the operation of the switch units SW1, SW2, SW1x and SW2x using control signals S10 and S10x, but the specific control operations are the same as those in the first and second embodiments.

[0139] Other configurations and operations of the signal transmission device 300 of the third embodiment are similar to those of the signal transmission devices 100 and 200 of the first and second embodiments.

[0140] That is, the signal transmission device according to the third embodiment can speed up switching between in-phase transmission and differential transmission.

[0141] (Variation) Here, a more specific example of the configuration of the variable current source unit of the transmission buffer of the signal transmission device according to the embodiment shown in FIG. 2 will be described as a modified example.

[0142] Fig. 6 is a diagram showing an example of the configuration of a transmission buffer of a signal transmission device according to a modified example. In the following description, among the components shown in Fig. 6, the same components as those shown in Fig. 2 are denoted by the same reference numerals as those shown in Fig. 2, and the description thereof may be omitted.

[0143] The transmission buffer TX of the signal transmission device according to this modification may include a current mirror unit K that defines the currents of the constant current sources I1a and I2a of the variable current source units IT1 and IT2, as shown in Fig. 6. In this case, for example, as shown in Fig. 6, the constant current source I1a is a pMOS transistor having a source connected to a first potential V1 and a drain connected to the differential circuit M, and the constant current source I2a is an nMOS transistor having a source connected to a second potential V2 and a drain connected to the differential circuit M.

[0144] 6, the current mirror section K includes an nMOS transistor Ka having a drain and a gate to which a reference current IREF is input, an nMOS transistor Kb having a gate connected to the gate of the nMOS transistor Ka, an nMOS transistor Kc having a gate connected between the source of the nMOS transistor Ka and a second potential V2, a gate connected to the gate of the nMOS transistor I2a, and a reference voltage VREF applied thereto, for controlling the common-mode voltage, an nMOS transistor Kd having a gate connected between the source of the nMOS transistor Kb and the second potential V2, and a gate connected to the gate of the nMOS transistor Kc, for controlling the common-mode voltage, and a pMOS transistor Ke having a source connected to the first potential V1, a drain and a gate connected to the drain of the nMOS transistor Kb, and a gate connected to the gate of the pMOS transistor I1a.

[0145] The reference voltage VREF and reference current IREF input to the current mirror unit K having such a configuration cause a predetermined mirror current to flow, thereby defining the currents of the constant current source I1a, which is a pMOS transistor, and the constant current source I2a, which is an nMOS transistor, and thereby setting the common-mode voltage.

[0146] The other configurations and operations of the transmission buffer TX of the signal transmission device according to this modification are the same as those of the transmission buffer according to the embodiment shown in FIG.

[0147] (Fourth embodiment) In the fourth embodiment, an example of the configuration of a signal transmission system to which the signal transmission devices according to the first to third embodiments described above are applied will be described.

[0148] Fig. 7 is a diagram showing an example of the configuration of a signal transmission system to which a signal transmission device is applied. Note that, in the example of a signal transmission system 1000 shown in Fig. 7, a configuration in which the signal transmission device 100 according to the first embodiment is applied is shown, but the signal transmission devices 200 and 300 according to the second and third embodiments are also similarly applied.

[0149] As shown in FIG. 7, the signal transmission system 1000 transmits an input signal and outputs output signals OUTP and OUTN.

[0150] As shown in FIG. 7, for example, this signal transmission system 1000 includes a signal primary circuit (semiconductor chip) 1001 to which input signals INP and INN are input, an insulating primary circuit (semiconductor chip) 1001Z that transmits signals between this signal primary circuit 1001, a signal secondary circuit (semiconductor chip) 1002 that outputs output signals OUTP and OUTN, and an insulating secondary circuit (semiconductor chip) 1002Z that transmits signals between this signal secondary circuit 1002.

[0151] 7, signals are transmitted between the isolated primary circuit 1001Z and the isolated secondary circuit 1002Z by a magnetically coupled isolation element Z having an electrically isolated insulating transformer structure. In particular, the signal transmission device 100 according to the first embodiment is applied to the signal transmission between the semiconductor chips of the signal primary circuit 1001 and the isolated primary circuit 1001Z, and the signal transmission device 100 according to the first embodiment is applied to the signal transmission between the semiconductor chips of the signal secondary circuit 1002 and the isolated secondary circuit 1002Z.

[0152] As already described, the signal transmission devices 200 and 300 according to the second and third embodiments may also be applied to the signal transmission system 1000 in the same manner.

[0153] As already mentioned, the first to third signal transmission devices 100, 200, 300 are capable of speeding up switching between in-phase transmission and differential transmission, and therefore the signal transmission system 1000 to which these signal transmission devices are applied can also speed up switching between in-phase transmission and differential transmission.

[0154] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0155] 100, 200, 300 signal transmission device TX transmit buffer M Differential circuit section IT1, IT2 variable current source section SW1, SW2 switch section CON control unit RX receive buffer G1 1st differential pair G2 Second differential pair Z input resistance F1 First current mirror IR1 1st constant current source IR2 2nd constant current source 1000 Signal Transmission System

Claims

1. A signal transmission device having a transmission buffer and a reception buffer, The transmission buffer a differential circuit section connected between a first potential and a second potential, and configured to output a first transmission signal to the first transmission terminal and a second transmission signal to the second transmission terminal in response to a first input signal input via the first input terminal and a second input signal input via the second input terminal; a variable current source unit that supplies a current to the differential circuit unit; a switch unit that switches between a conductive state and a cut-off state between the first transmitting terminal and a fixed potential and between the second transmitting terminal and the fixed potential; a control unit that controls the current supplied from the variable current source unit to the differential circuit unit and also controls the operation of the switch unit, The receiving buffer a first differential pair of a first conductivity type connected between a third potential and a fourth potential, which outputs a first reception current in response to the first transmission signal input via a first reception terminal and outputs a second reception current in response to the second transmission signal input via a second reception terminal; a second differential pair of a second conductivity type connected between the third potential and the fourth potential, which outputs a third reception current in response to the first transmission signal and a fourth reception current in response to the second transmission signal; a first current mirror unit that causes a current obtained by current-mirroring the first received current to flow between the third potential and a second output terminal, and that causes a current obtained by current-mirroring the second received current to flow between the third potential and the first output terminal; a second current mirror unit configured to cause a current obtained by current-mirroring the third received current to flow between the second output terminal and the fourth potential, and to cause a current obtained by current-mirroring the fourth received current to flow between the first output terminal and the fourth potential, The control unit When the first input signal and the second input signal are in-phase signals, the switch unit is controlled so that a state of conduction is established between the first transmitting terminal and the fixed potential and between the second transmitting terminal and the fixed potential. A signal transmission device characterized by:

2. The control unit When the first input signal and the second input signal are differential signals, the switch unit is controlled so that the first transmitting terminal and the fixed potential and the second transmitting terminal and the fixed potential are disconnected from each other.

2. The signal transmission device according to claim 1.

3. The control unit when the first input signal and the second input signal are in-phase signals, controlling the variable current source unit so that the current supplied to the differential circuit unit increases; On the other hand, when the first input signal and the second input signal are differential signals, the variable current source unit is controlled so that the current supplied to the differential circuit unit is reduced.

3. The signal transmission device according to claim 2.

4. The control unit when the first input signal and the second input signal are in-phase signals, controlling the switch unit to be on so as to establish a conductive state between the first transmitting terminal and the fixed potential and between the second transmitting terminal and the fixed potential, and then controlling the variable current source unit so as to increase the current supplied to the differential circuit unit after a preset delay time has elapsed; On the other hand, when the first input signal and the second input signal are differential signals, the switch unit is controlled to be turned off so that the first transmitting terminal and the fixed potential and the second transmitting terminal and the fixed potential are disconnected, and then, after the delay time has elapsed, the variable current source unit is controlled so that the current supplied to the differential circuit unit is reduced.

4. The signal transmission device according to claim 3.

5. 2. The signal transmission device according to claim 1, wherein the fixed potential is the first potential or the second potential.

6. The receiving buffer a first constant current source connected between the fourth potential and the first differential pair and supplying a current to the first differential pair; a second constant current source connected between the third potential and the second differential pair and supplying a current to the second differential pair.

2. The signal transmission device according to claim 1.

7. a transmission buffer that outputs a fixed signal of a predetermined potential corresponding to the input signal when the input signal is an in-phase signal; a receiving buffer that, when a transmission signal input from the transmitting buffer is an in-phase signal, outputs an in-phase signal corresponding to the transmission signal; the transmission buffer and the reception buffer are connected by a first wiring and a second wiring, The control unit of the transmission buffer When the input signal is an in-phase signal, a switch unit of the transmission buffer is controlled so that a conduction state is established between a first transmission terminal of the transmission buffer connected to the first wiring and a fixed potential, and between a second transmission terminal of the transmission buffer connected to the second wiring and the fixed potential.

1. An LVDS circuit comprising:

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