Display device and method for controlling the display device

Abstract

To improve the reliability of a display device by detecting defects in the display device.SOLUTION: A sensing circuit is configured to in response to applying a first reference voltage to a subpixel via a reference line during a first sensing period, acquire a first sensing voltage charged in the reference line as a first sampling value when the switching and sensing transistors are turned on and acquire the first sensing voltage charged in the reference line as a second sampling value when the switching and sensing transistors are turned off, and the timing controller determines that a display device has a defect on the basis of the first difference value between the first sampling value and the second sampling value.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] This specification relates to a display device and a method of controlling the display device.

Background Art

[0002] As information technology develops, the market for display devices, which are the connection medium between users and information, is growing. As a result, the use of display devices such as light emitting display devices (LED), quantum dot display devices (QDD), and liquid crystal display devices (LCD) is increasing.

[0003] The above-described display device includes a display panel including sub-pixels, a driving unit that outputs a driving signal for driving the display panel, a power supply unit that generates a power supply to be supplied to the display panel or the driving unit, and the like.

[0004] When a driving signal, such as a scan signal, a data signal, etc., is supplied to the sub-pixels formed on the display panel of such a display device, the selected sub-pixels can transmit light or emit light directly, thereby displaying an image.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This specification improves the driving stability and driving reliability of a display device.

Means for Solving the Problems

[0006] This specification provides a display device comprising a display panel including a subpixel having a switching transistor connected to a data line and a sensing transistor connected to a reference line, a drive circuit connected to the data line, a sensing circuit connected to the reference line, and a timing controller controlling at least one of the drive circuit and the sensing circuit, wherein the sensing circuit acquires a first sensing voltage charged to the reference line as a first sampling value during the period when the switching transistor and the sensing transistor are turned on in response to the application of a first reference voltage to the subpixel via the reference line during a first sensing period, and acquires a first sensing voltage charged to the reference line as a second sampling value during the period when the switching transistor and the sensing transistor are turned off, and the timing controller determines that the display device is defective based on a first difference value between the first sampling value and the second sampling value.

[0007] The sensing circuit, in response to applying a second reference voltage different from the first reference voltage to the subpixel via the reference line during a second sensing period in which the switching transistor and the sensing transistor are turned off, may acquire the second sensing voltage charged to the reference line as a third sampling value during the period in which the second reference voltage is applied to the reference line, and may acquire the second sensing voltage charged to the reference line as a fourth sampling value during the period in which the second reference voltage is not applied to the reference line.

[0008] The timing controller further comprises a data driving unit including the driving circuit and the sensing circuit, and the timing controller can determine that the display device is defective based on a second difference value between the third sampling value and the fourth sampling value.

[0009] The second sensing period may be scheduled to run when the first difference value is greater than a predetermined value, and may be skipped or not run if the first difference value is less than the predetermined value.

[0010] The first sensing period and the second sensing period may be included in the drive start period during which power is applied to the display panel.

[0011] The first sensing period and the second sensing period may include a drive termination period in which an instruction is given to shut off the power supplied to the display panel.

[0012] The first sensing period may include the drive start period in which power is applied to the display panel, and the second sensing period may include the drive end period in which an instruction is given to cut off the power applied to the display panel.

[0013] In other respects, this specification describes a method for controlling a display device, The present invention provides a method comprising the steps of: applying a first reference voltage to a reference line connected to a subpixel included in the display panel of the display device using a sensing circuit included in the display device; acquiring the first reference voltage charged to the reference line as a first sampling value during the period when the switching transistor and sensing transistor included in the subpixel are turned on, and acquiring the first reference voltage charged to the reference line as a second sampling value during the period when the switching transistor and sensing transistor are turned off; and determining that the display device is defective using a timing controller of the display device based on a first difference value between the first sampling value and the second sampling value.

[0014] The procedure may include the steps of: applying a second reference voltage different from the first reference voltage via the reference line when the switching transistor and the sensing transistor are turned off; acquiring the second sensing voltage charged on the reference line as a third sampling value during the period when the second reference voltage is applied to the reference line; and acquiring the second sensing voltage charged on the reference line as a fourth sampling value during the period when the second reference voltage is not applied to the reference line.

[0015] Based on the second difference value between the third sampling value and the fourth sampling value, it can be determined that the display device is defective. [Effects of the Invention]

[0016] This specification improves the lifespan of a display device by compensating for elements contained in the subpixels that make up the display panel, and also improves the stability and reliability of the display device by detecting the presence or absence of defects in the entire display device, including the display panel and drive unit. [Brief explanation of the drawing]

[0017] [Figure 1] This is a block diagram illustrating a light-emitting display device. [Figure 2] Figure 1 is a schematic diagram showing the subpixel configuration. [Figure 3] This is an example diagram of a pixel composed of subpixels. [Figure 4] This is a diagram illustrating the configuration of a gate-in-panel gate drive unit. [Figure 5] This is a diagram illustrating the configuration of a gate-in-panel gate drive unit. [Figure 6] This figure shows an example of the arrangement of a gate-in-panel type gate drive unit. [Figure 7] This is a simplified illustrative diagram showing a subpixel and data driving unit according to the first embodiment. [Figure 8] It is an exemplary diagram that briefly shows a subpixel and a data driving unit according to a second example of an embodiment. [Figure 9] It is a waveform diagram for explaining a sensing period and a display period of an embodiment. [Figure 10] It is an exemplary diagram that shows a part of the configuration included in the data driving unit according to an embodiment in more detail. [Figure 11] It is an exemplary diagram that shows a method of sensing a display panel according to an embodiment. [Figure 12] It is an exemplary diagram that shows a method of sensing a display panel according to an embodiment. [Figure 13] It is a driving waveform diagram of a first sensing step for determining the presence or absence of a defect in a light-emitting display device according to an embodiment. [Figure 14] It is an exemplary diagram that shows the difference between sensing voltages sensed in a first sensing step. [Figure 15] It is a driving waveform diagram of a second sensing step for determining the presence or absence of a defect in a light-emitting display device according to an embodiment. [Figure 16] It is an exemplary diagram that shows the operation of a device performed in a second sensing step. [Figure 17] It is an exemplary diagram that shows the operation of a device performed in a second sensing step. [Figure 18] It is a diagram that exemplarily shows defects that may appear in elements, signal lines, and power supply lines of a light-emitting display device according to an embodiment. [Figure 19] It is a diagram that exemplarily shows defects that may appear in signal lines of a light-emitting display device according to an embodiment. [Figure 20] It is a block diagram that exemplarily shows an internal configuration of a data driving unit according to an embodiment. [Figure 21] It is a flowchart that exemplarily shows a process of digitally processing a sensing voltage based on the data driving unit of FIG. 20 and configuring it in a form that can be transferred to a timing controller. [Figure 22]This flowchart exemplifies the process of digitally processing the sensed voltage based on the data drive unit in Figure 20 and configuring it in a format that can be transferred to the timing controller. [Figure 23] This flowchart exemplifies the process of digitally processing the sensed voltage based on the data drive unit in Figure 20 and configuring it in a format that can be transferred to the timing controller. [Modes for carrying out the invention]

[0018] This specification can be implemented in, and is not limited to, televisions, video players, personal computers (PCs), home theaters, automotive electrical equipment, smartphones, and the like. This specification may consist of light-emitting display devices (LEDs), quantum dot display devices (QDDs), liquid crystal display devices (LCDs), and the like. However, for the sake of explanation, a light-emitting display device that directly emits light based on inorganic or organic light-emitting diodes will be used as an example below.

[0019] Figure 1 is a schematic block diagram showing a light-emitting display device, Figure 2 is a schematic configuration diagram showing the subpixels shown in Figure 1, and Figure 3 is an example diagram of a pixel made up of subpixels.

[0020] As shown in Figures 1 to 3, the light-emitting display device may include a video supply unit 110, a timing controller 120, a gate drive unit 130, a data drive unit 140, a display panel 150, and a power supply unit 180, etc.

[0021] The video supply unit (set or host system) 110 can output various drive signals in addition to video data signals supplied from an external source or video data signals stored in internal memory. The video supply unit 110 can supply data signals and various drive signals to the timing controller 120.

[0022] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the gate drive unit 130, a data timing control signal DDC for controlling the operating timing of the data drive unit 140, and various synchronization signals. The timing controller 120 can supply the data signal DATA supplied from the video supply unit 110 to the data drive unit 140 along with the data timing control signal DDC. The timing controller 120 may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0023] The gate drive unit 130 can output a gate signal (or gate voltage) in response to a gate timing control signal GDC supplied from the timing controller 120. The gate drive unit 130 can supply gate signals to subpixels included in the display panel 150 via gate lines GL1 to GLm. The gate drive unit 130 may be formed in the form of an IC, or it may be formed directly on the display panel 150 using a gate-in-panel (Gate In Panel) method, but is not limited to these.

[0024] The data drive unit 140 can sample and latch data signals (DATA) in response to a data timing control signal DDC or the like supplied from the timing controller 120, and convert the digital data signals into analog data voltages based on a gamma reference voltage and output them. The data drive unit 140 can supply data voltages to subpixels included in the display panel 150 via data lines DL1 to DLn. The data drive unit 140 is formed in the form of an IC and can be mounted on the display panel 150 or on a printed circuit board, but is not limited to that.

[0025] The power supply unit 180 can generate a high-potential first power supply and a low-potential second power supply based on an externally supplied external input voltage. The power supply unit 180 can output the first power supply via the first power supply line EVDD and the second power supply via the second power supply line EVSS. In addition to the first and second power supplies, the power supply unit 180 can generate and output voltages required to drive the gate drive unit 130 (e.g., scan high voltage and scan low voltage) and voltages required to drive the data drive unit 140 (drain voltage and half-drain voltage).

[0026] The display panel 150 can display images in response to drive signals including gate signals and data voltages, a first power supply, a second power supply, and the like. The subpixels of the display panel 150 can directly emit light. The display panel 150 can be fabricated on a rigid or ductile substrate such as glass, silicon, or polyimide. For example, one subpixel SP may be connected to a first data line DL1, a first gate line GL1, a first power supply line EVDD, and a second power supply line EVSS, and may include a pixel circuit consisting of a switching transistor, a drive transistor, a capacitor, an organic light-emitting diode, and the like.

[0027] Subpixel SPs used in light-emitting devices have complex circuit configurations because they directly emit light. Furthermore, the compensation circuits that compensate for degradation of not only the organic light-emitting diodes (OLEDs) themselves, but also the drive transistors that supply the drive current necessary to drive the OLEDs, are diverse. Therefore, please note that subpixel SPs are often simply shown in block form.

[0028] Light-emitting subpixels may consist of pixels containing red, green, and blue, or pixels containing red, green, blue, and white. For example, one pixel P may include a red subpixel SPR connected to a first data line DL1, a white subpixel SPW connected to a second data line DL2, a green subpixel SPG connected to a third data line DL3, and a blue subpixel SPB connected to a fourth data line DL4. The red subpixel SPR, white subpixel SPW, green subpixel SPG, and blue subpixel SPB may all be connected in common to a first reference line VREF1. The first reference line VREF1 can be used to detect degradation of an element contained in one of the red subpixel SPR, white subpixel SPW, green subpixel SPG, and blue subpixel SPB, as described below.

[0029] On the other hand, the above description made it seem as if the timing controller 120, gate drive unit 130, data drive unit 140, etc., were separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, gate drive unit 130, and data drive unit 140 can be integrated into a single IC. Furthermore, the timing controller 120, gate drive unit 130, data drive unit 140, power supply unit 180, and display panel 150 can be defined as a display module as an assembly for displaying images.

[0030] In the above example, pixel P is shown with the red subpixel SPR, white subpixel SPW, green subpixel SPG, and blue subpixel SPB arranged in that order. However, the arrangement order and orientation of the subpixels may vary depending on the method of implementing the light-emitting display device.

[0031] Figures 4 and 5 illustrate the configuration of the gate-in-panel type gate drive unit, and Figure 6 shows an example of the arrangement of the gate-in-panel type gate drive unit.

[0032] As shown in Figure 4, the gate-in-panel type gate drive unit may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a drive clock signal Clks and a start signal Vst, etc., based on signals and voltages output from the timing controller 120 and the power supply unit 180.

[0033] The shift register 131 operates based on signals (Clks, Vst) output from the level shifter 135 and can output gate signals (Gate[1] to Gate[m]) that can turn on or turn off transistors formed on the display panel. The shift register 131 can be formed as a thin film on the display panel using a gate-in-panel method.

[0034] As shown in Figures 4 and 5, unlike the shift register 131, the level shifter 135 may be formed independently as an IC or may be included inside the power supply unit 180. However, this is just one example and is not limited thereto.

[0035] As shown in Figure 6, the shift registers 131a and 131b that output gate signals from the gate-in-panel gate drive unit can be placed in the non-display area NA of the display panel 150. While the example shows the shift registers 131a and 131b placed in the left and right non-display areas NA of the display panel 150, they may also be placed in the top and bottom non-display areas NA of the display panel 150. They can also be placed within the display area AA of the display panel 150.

[0036] Figure 7 is a simplified illustrative diagram showing the subpixel and data drive unit according to the first example of the embodiment, Figure 8 is a simplified illustrative diagram showing the subpixel and data drive unit according to the second example of the embodiment, and Figure 9 is a waveform diagram illustrating the sensing period and display period as shown in the embodiment.

[0037] As shown in Figure 7, according to the first example, one subpixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light-emitting diode OLED.

[0038] The driver transistor DT may have its gate electrode connected to the first electrode of the capacitor CST, its first electrode connected to the first power line EVDD, and its second electrode connected to the anode electrode of the organic light-emitting diode OLED. The capacitor CST may have its first electrode connected to the gate electrode of the driver transistor DT and its second electrode connected to the anode electrode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may have its anode electrode connected to the second electrode of the driver transistor DT and its cathode electrode connected to the second power line EVSS.

[0039] The switching transistor SW may have its gate electrode connected to the first scan line Gate1 included in the first gate line GL1, its first electrode connected to the first data line DL1, and its second electrode connected to the gate electrode of the drive transistor DT. The sensing transistor ST may have its gate electrode connected to the second scan line Gate2 included in the first gate line GL1, its first electrode connected to the first reference line VREF1, and its second electrode connected to the anode electrode of the organic light-emitting diode OLED.

[0040] A sensing transistor (ST) is a type of compensation circuit added to compensate for the degradation (threshold voltage, mobility, etc.) of the driving transistor (DT) or the organic light-emitting diode (OLED). The sensing transistor (ST) may enable physical threshold voltage sensing based on the source follower operation of the driving transistor (DT). The sensing transistor (ST) may operate to acquire a sensed voltage via a sensing node defined between the driving transistor (DT) and the organic light-emitting diode (OLED).

[0041] According to one embodiment, the data driving unit 140 may include a driving circuit 141 for driving subpixels SP and a sensing circuit 145 for sensing subpixels SP. The driving circuit 141 is connected to a first data line DL1 via a first data channel DCH1. The driving circuit 141 may output a data voltage Vdata or the like for driving subpixels SP via the first data channel DCH1.

[0042] The sensing circuit 145 is connected to the first reference line VREF1 via the first sensing channel SCH1. The sensing circuit 145 can acquire a sensing voltage Vsen sensed from a subpixel SP via the first sensing channel SCH1. The sensing circuit 145 can acquire a sensing voltage Vsen based on current sensing, voltage sensing methods, etc.

[0043] As shown in Figure 8, according to the second example, the first gate line GL1 can be integrated into a single unit. That is, unlike the first example, the first gate line GL1 does not need to be distinguished into a first scan line and a second scan line. In this case, the switching transistor SW and the sensing transistor ST are connected in common to the first gate line GL1 and can be turned on or off simultaneously.

[0044] As shown in Figure 9, the light-emitting display device according to this embodiment can employ a driving method in which each of the following periods is distinct: a first driving period PWR_ON, a second driving period DISPLAY, and a third driving period PWR_OFF, during operation to drive the display panel.

[0045] The first drive period, PWR_ON, corresponds to the start period when power is applied to the display panel; the second drive period, DISPLAY, corresponds to the panel drive period when operations such as displaying images are performed after power is applied to the display panel; and the third drive period, PWR_OFF, may correspond to the end period when the power applied to the display panel is cut off. On the other hand, the third drive period, PWR_OFF, is a period during which the display panel is driven for a certain amount of time while displaying black so that sensing operations can be performed. In other words, the power applied to the display panel, etc., is not completely cut off during the third drive period (PWR_OFF).

[0046] The light-emitting display device according to this embodiment can sense the display panel during at least one of the following periods: the first drive period PWR_ON, the second drive period DISPLAY, and the third drive period PWR_OFF. Taking the second drive period DISPLAY as an example, the blank period BLK included in the vertical synchronization signal Vsync may be defined as the sensing period PSP, and the active period (ACT) included in the vertical synchronization signal Vsync may be defined as the display period DSP.

[0047] Figure 10 is an illustrative diagram showing in more detail some of the components included in the data-driven unit according to the embodiment, and Figures 11 and 12 are illustrative diagrams showing a method for sensing the display panel according to the embodiment. Hereinafter, the subpixel SP will be described using the structure shown in Figure 7 as an example.

[0048] As shown in the embodiment in Figure 10, the drive circuit 141 may include a digital-to-analog converter (DAC) for outputting a sensing data voltage, black data voltage, or display data voltage via a first data line DL1. The sensing circuit 145 may include a first voltage circuit (SPRE), a second voltage circuit (RPRE), a sampling circuit (SAM), an analog-to-digital converter (ADC), etc., for sensing by outputting a voltage via a first reference line (VREF1).

[0049] The first voltage circuit SPRE and the second voltage circuit RPRE may perform voltage output operations to initialize nodes and circuits contained within the subpixel SP, or to charge them to a specific voltage level. The first voltage circuit SPRE and the second voltage circuit RPRE may include a first reference voltage source VPRES and a second reference voltage source VPRER, respectively. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage may be set to a voltage lower than the second reference voltage.

[0050] The sampling circuit SAM may perform a sampling operation to acquire a sensing voltage via a first reference line VREF1. For example, the sampling circuit SAM may acquire a sensing voltage from a sensing capacitor PCAP formed on the first reference line VREF1 based on the sensing capacitor PCAP.

[0051] The analog-to-digital converter (ADC) can convert the analog sensing voltage acquired by the sampling circuit (SAM) into a digital sensing voltage and output it. For example, the analog-to-digital converter (ADC) can convert the analog sensing voltage charged in the sensing capacitor (PCAP) into a digital sensing voltage and output it.

[0052] The timing controller 120 may receive a sensing voltage (sensing data value) from the sensing circuit 145. Based on the sensing voltage, the timing controller 120 may determine whether or not the driving transistor DT or organic light-emitting diode OLED included in the subpixel SP has degraded, and may perform actions to compensate for the degradation. The timing controller 120 may also determine whether or not there is a defect in the light-emitting display device based on the sensing voltage, and may perform actions to notify or resolve the defect.

[0053] As shown in Figure 11, according to the first example, the light-emitting display device can perform a sequential sensing method that senses from the first gate line GL1 to the Mth gate line GLm of the display panel 150. In Figure 11, as an example, it is shown and explained that the sensing is performed sequentially from the first gate line GL1, which is the upper end of the display panel 150, but the sensing may also start from the Mth gate line GLm, which is the lower end of the display panel 150.

[0054] As shown in Figure 12, according to the second example, the light-emitting display device may perform a random sensing method that senses only the first gate line GLi of the display panel 150. In Figure 12, sensing only the first gate line GLi, which is one of a specific set of gate lines, is shown as an example, but the sensing target may be multiple gate lines.

[0055] Figure 13 is a drive waveform diagram of the first sensing step for determining whether or not there is a defect in the light-emitting display device according to the embodiment, and Figure 14 is an illustrative diagram showing the difference between the sensing voltages sensed in the first sensing step. Figures 16 and 17 are illustrative diagrams showing the operation of the device performed in the second sensing step, and Figure 13 is a drive waveform diagram of the second sensing step for determining whether or not there is a defect in the light-emitting display device according to the embodiment.

[0056] As shown in Figures 9, 10, 13, and 14, the light-emitting display device according to the embodiment can sense the display panel over at least one of the following periods: a first drive period PWR_ON, a second drive period DISPLAY, and a third drive period PWR_OFF, in order to determine whether or not there is a defect.

[0057] To ensure the display panel is operational at the appropriate time, operations to determine the presence or absence of defects in the light-emitting display device may be performed during the first drive period PWR_ON or the third drive period PWR_OFF, excluding the second drive period DISPLAY. Below, as an example, the determination of defects in the light-emitting display device is performed via the first sensing step in Figure 13 and the second sensing step in Figure 15. However, the first sensing step may be performed during the first drive period PWR_ON, and the second sensing step may be performed during the third drive period PWR_OFF.

[0058] As shown in Figures 10 and 13, the first sensing step is a step in which the presence or absence of defects between the display panel and the data drive unit that drives it is determined based on a method of randomly sensing a specific gate line of the display panel or a method of sequentially sensing all gate lines of the display panel. The first sensing step may include the 1-1 sensing period P1, the 1-2 sensing period P2, and the 1-3 sensing period P3. Hereinafter, the first subpixel will be defined as the subpixel to be sensed, and the operations performed in the first sensing step will be described.

[0059] During the first sensing period P1, a first reference voltage is applied to the first reference line VREF1 of the first subpixel included in the display panel. During the first sensing period P1, the first voltage circuit SPRE, which includes the first reference voltage source VPRES, is turned on in response to a high-voltage first voltage circuit control signal VpreS. The first voltage circuit control signal VpreS is applied at a high voltage during the first sensing period P1 and then changed to a low voltage. During the first sensing period P1, the sensing node of the drive transistor DT included in the first subpixel may be initialized by the first reference voltage.

[0060] During the first-to-second sensing period P2, a sensing data voltage Sdata may be applied to the first data line DL1 of the first subpixel included in the display panel. During the first-to-second sensing period P2, a high-voltage first scan signal and a first sensing signal Scan&Sense may be applied to the first scan line Gate1 and the second scan line Gate2. The switching transistor SW and sensing transistor ST included in the first subpixel may be turned on by the high-voltage first scan signal and the first sensing signal Scan&Sense. The first scan signal and the first sensing signal Scan&Sense are applied at high voltage during the first-to-second sensing period P2, and then changed to low voltage.

[0061] During the first-to-second sensing period P2, the drive transistor DT of the first subpixel may operate as a source follower due to the sensing data voltage Sdata. Due to the source follower operation of the drive transistor DT, the first sensing voltage Vsen1 applied to the sensing node of the first subpixel may decrease to the first reference voltage level and gradually increase, saturating to a voltage level close to the threshold voltage.

[0062] During the first-second sensing period P2, the sampling circuit SAM may turn on in response to a temporarily occurring first-first sampling control signal Sam1-1. During the first-second sensing period P2, the sampling circuit SAM may acquire the first sensing voltage Vsen1 applied to the sensing node of the first subpixel at the first sampling value a. The first-first sampling control signal Sam1-1 may be applied at a high voltage in the latter half of the first-second sensing period P2 and then changed to a low voltage. The first-first sampling control signal Sam1-1 may occur temporarily between the time when the first sensing voltage Vsen1 is set to a level close to the threshold voltage of the drive transistor DT and the time when the first scan signal and first sensing signal (Scan&Sense) change to a low voltage.

[0063] During the first to third sensing period P3, the sampling circuit SAM may turn on in response to the temporarily generated first to second sampling control signals Sam1-2. During the first to third sensing period P3, the sampling circuit SAM may acquire the first sensing voltage Vsen1 applied to the sensing node of the first subpixel as the second sampling value b. The first to second sampling control signals Sam1-2 may be applied at a high voltage during the first to third sensing period P3 and then changed to a low voltage. The first to second sampling control signals Sam1-2 may be generated temporarily after a certain delay time has elapsed since the first scan signal and the first sensing signal Scan&Sense were changed to low voltages.

[0064] The light-emitting display device according to the embodiment can first determine whether there is a defect between the display panel and the data drive unit that drives it by comparing a first sampling value (a) and a second sampling value (b). At this time, the determination procedure can be performed by a timing controller 120 or a video supply unit corresponding to a device higher than the timing controller, which provides the first sampling value (a) and the second sampling value (b) as a first sensing voltage (Vsen1) in digital form.

[0065] As shown in Figure 14, if there is a first voltage difference (ΔV) between the first sampled value (a) and the second sampled value (b) obtained in the two sensing processes, the timing controller 120 may store in memory the gate line number where the first voltage difference ΔV occurred or the position of the subpixel where the difference occurred. On the other hand, if there is no first voltage difference ΔV between the first sampled value (a) and the second sampled value (b), the timing controller 120 may control the device to omit (skip) the processing of the subsequent second sensing step.

[0066] As shown in Figures 10, 15-17, the second sensing step involves re-sensing the gate line numbers or subpixels where difference values ​​occurred in the first sensing step to obtain data for the display panel and its driving components. This step also secondarily determines the presence or absence of defects between the drive components. The second sensing step may include a 2-1 sensing period P1', a 2-2 sensing period P2', and a 2-3 sensing period P3'.

[0067] During the second sensing period P1', a low-voltage first scan signal and a first sensing signal, Scan&Sense, may be applied to the first scan line Gate1 and the second scan line Gate2. The switching transistor SW and sensing transistor ST included in the first subpixel may be turned off by the low-voltage first scan signal and the first sensing signal, Scan&Sense.

[0068] During the second sensing period P2', a second reference voltage Vprer may be applied to the first reference line VREF1 of the first subpixel included in the display panel. During the second sensing period P2', the second voltage circuit RPRE, which includes the second reference voltage source VPRER, may be turned on in response to a high-voltage second voltage circuit control signal VpreR. The second voltage circuit control signal VpreR is applied at a high voltage during the second sensing period P2' and then changed to a low voltage. During the second sensing period P2', the switching transistor SW and sensing transistor ST included in the first subpixel are turned off, so the second reference voltage Vprer may also be charged by the sensing capacitor PCAP of the first reference line VREF1 with the second sensing voltage Vsen2. On the other hand, the second reference voltage Vprer may be output at a more variable level than conventionally to improve the ability to judge the presence or absence of defects.

[0069] During the second-second sensing period P2', the sampling circuit SAM may turn on in response to the temporarily generated second-first sampling control signal Sam2-1. During the second-second sensing period P2', the sampling circuit SAM may acquire the second sensing voltage Vsen2 charged to the sensing capacitor PCAP of the first reference line VREF1 of the first subpixel as the third sampling value (c). The second-first sampling control signal Sam2-1 is applied at a high voltage in the middle to latter half of the second-second sensing period P2', and then changed to a low voltage.

[0070] During the second-to-third sensing period P3', the sampling circuit SAM may turn on in response to a temporarily generated second-to-second sampling control signal Sam2-2. During the second-to-third sensing period P3', the sampling circuit SAM may acquire the second sensing voltage Vsen2 charged to the sensing capacitor PCAP of the first reference line VREF1 of the first subpixel as the fourth sampling value (d). The second-to-second sampling control signal Sam2-2 may be applied at a high voltage during the second-to-third sensing period P3' and then changed to a low voltage. The second-to-third sensing period P3' may occur temporarily after a certain delay time has passed since the second voltage circuit control signal VpreR was changed to a low voltage.

[0071] The light-emitting display device according to this embodiment can secondarily determine whether there is a defect between the display panel and the data drive unit that drives it, based on a second voltage difference between a third sampling value (c) and a fourth sampling value (d). In this case, the determination procedure can be performed by a timing controller 120 or a video supply unit corresponding to a device higher than the timing controller, which provides the third sampling value (c) and the fourth sampling value (d) as a second sensing voltage Vsen2 in digital form.

[0072] On the other hand, the timing controller 120 can also secondarily determine whether there is a defect between the display panel and the data drive unit that drives it by comparing a sampled value (or reference sampled value) obtained from a normal subpixel under the same driving conditions with a third sampled value (c) or a fourth sampled value (d), without deriving a second voltage difference value.

[0073] Figure 18 is an illustrative diagram showing possible defects that may appear in the elements, signal lines, and power lines of the light-emitting display device according to the embodiment, and Figure 19 is an illustrative diagram showing possible defects that may appear in the signal lines of the light-emitting display device according to the embodiment. Hereinafter, we will explain, as an example, how the presence or absence of defects in the light-emitting display device is determined by a timing controller.

[0074] As shown in Figures 18 and 19, the display panel and the data drive unit 140 can be electrically connected to each other via pads PD1 and PD2 located in the pad area PDA (or bonding area). In addition to signal lines DL1 and VREF1 that electrically connect the display panel and the data drive unit 140, power lines may also be present in the pad area PDA (or bonding area). Therefore, if there is an open fault (or bonding fault) due to non-contact (non-contact due to cracks) between similar signal lines in the pad area PDA (or bonding area), or a short fault due to foreign object PTC contact (or moisture-permeable contact) between different signal lines, the sensing range may be exceeded or incorrect sensing values ​​may be acquired due to current leakage, etc.

[0075] The timing controller according to this embodiment can comprehensively determine whether or not there is a defect in the light-emitting display device based on the first voltage difference value obtained in the first sensing stage and the second voltage difference value obtained in the second sensing stage. This can be explained as follows.

[0076] The timing controller 120 can determine, based on the first voltage difference value obtained in the first sensing stage, whether there is a defect in at least one of the elements SW, CST, DT, OLED, and ST included in the subpixel SP of the display panel, whether there is a defect in the power line EVDD or EVSS of the display panel, and whether there is a defect in the signal lines DL1 and VREF1 located between the display panel and the data drive unit 140.

[0077] When a first voltage difference occurs, elements included in the sensing target subpixel, along with the data line and reference line located between the sensing target subpixel and the data drive unit, may be selected as defect candidates. Then, when a second voltage difference occurs, only the reference line located between the sensing target subpixel and the data drive unit may be selected as defect candidates.

[0078] In the first example, if only the first voltage difference occurs, the timing controller may determine that the element included in the sensing subpixel and at least one of the data line and reference line connected to it are the cause of the defect. In the second example, if only the second voltage difference occurs, the timing controller may determine that only the reference line is the cause of the defect. In the third example, if both the first and second voltage differences occur, the timing controller may determine that both the element included in the sensing subpixel and the data line and reference line connected to it are the cause of the defect.

[0079] On the other hand, the timing controller may include a lookup table that stores defect detection data capable of determining whether there are defects in the components included in the light-emitting display device based on a first voltage difference value and a second voltage difference value. In this case, the timing controller can more easily determine which components have defects by increasing or decreasing the first or second voltage difference value. Here, the defect detection data can be prepared through experimentation.

[0080] Figure 20 is a block diagram illustrating the internal configuration of the data drive unit according to the embodiment, and Figures 21 to 23 are flowcharts illustrating the process of digitally processing the sensing voltage based on the data drive unit in Figure 20 and configuring it to be transferable to the timing controller.

[0081] As shown in Figure 20, the data drive unit 40 according to this embodiment may include a drive circuit 141 and a sensing circuit 145. The drive circuit 141 may include a data reception and recovery unit RX&CDR, a first data processing and logic unit S2P&PLOG, a shift register unit SRES, a first latch unit LAT1, a second latch unit LAT2, a digital-to-analog conversion unit DAC, an output circuit COC, and the like.

[0082] The data reception and recovery unit RX&CDR receives and processes packet data transmitted from the timing controller, and may also play a role in recovering from reception errors such as data signals or clock signals contained in the packet data.

[0083] The first data processing and logic unit S2P&PLOG converts the serial signals output from the data reception and recovery unit RX&CDR into parallel signals, and also plays a role in separating and outputting control signals applied to the controller TCL and data signals applied to the first latch unit LAT1.

[0084] The shift register section SRES may have the role of generating signals so that the data signals applied to the first latch section LAT1 or the second latch section LAT2 are sampled and latched one line at a time.

[0085] The first latch unit LAT1 and the second latch unit LAT2 may be responsible for sampling and latching the data signal output from the first data processing and logic unit S2P&PLOG one line at a time and outputting it. Here, the second latch unit LAT2 may output a data signal based on the source output activation signal output from the first data processing and logic unit S2P&PLOG.

[0086] The digital-to-analog converter (DAC) can perform the role of converting the digital data signal output from the second latch unit (LAT2) into an analog data voltage based on the gamma reference voltage and outputting it.

[0087] The output circuit COC may play a role in amplifying the data voltage output from the digital-to-analog converter (DAC) and performing additional modulation before outputting it through the data channel.

[0088] The sensing circuit 145 may include a controller TCL, a sensing processing unit CIA, a maxing unit MUX, a sampling and downscaling unit SAM&DS, a gain amplifier GA, an analog-to-digital conversion unit ADC, a second data processing unit P2S, a data transmission unit TX, and the like.

[0089] The controller TCL may play a role in controlling the operating timing of the devices contained within the sensing circuit 145 based on control signals output from the first data processing and logic unit S2P&PLOG.

[0090] The sensing processing unit CIA may acquire the sensing voltage via a sensing channel connected to the reference line, process it, and output it. The sensing processing unit CIA may be configured according to the sensing method of the sensing circuit 145. For example, the sensing processing unit CIA may consist of a current integrating circuit or a voltage sensing circuit.

[0091] The MUX unit may have the role of selectively outputting a first reference voltage and a second reference voltage applied from an external source. The MUX unit may include a first voltage circuit that outputs the first reference voltage and a second voltage circuit that outputs the second reference voltage.

[0092] The sampling and downscaling unit SAM&DS samples the sensing voltage acquired by the sensing processing unit CIA and can also scale down the sensing voltage. As shown in Figures 20 and 21, the sampling and downscaling unit SAM&DS samples the sensing voltage in analog signal form output from the sensing processing unit CIA in sampled analog signal form, and then downscales it to output it in sampled and downscaled analog signal form.

[0093] The gain amplifier (GA) can adjust the gain for the sensing voltage output from the sampling and downscaling section (SAM&DS).

[0094] The analog-to-digital converter (ADC) can convert the analog sensing voltage output from the gain amplifier (GA) into a digital sensing voltage (sensing data value) and output it. As shown in Figures 20 and 22, the analog-to-digital converter (ADC) can output the analog sensing voltage output from the sampling and downscaling unit (SAM&DS) as a digital sensing voltage.

[0095] On the other hand, the circuit blocks (SHA, MDAC, FLASH, Digital Correction Logic) and the analog voltage and digital data in Figure 22 are shown illustratively to aid in understanding the detailed circuit configuration of the analog-to-digital converter (ADC) and its conversion method, and related matters; therefore, a detailed explanation will be omitted.

[0096] The second data processing unit P2S can perform the role of aligning the parallel digital sensing voltages output from the analog-to-digital converter (ADC) into serial digital sensing voltages. As shown in Figures 20 and 23, the second data processing unit P2S can sort the parallel digital sensing voltages Vsen (Parallel Data) output from the analog-to-digital converter (ADC) into the format of serial digital sensing voltages Vsen (Serial Data).

[0097] The data transmission unit TX can transmit serial digital sensing voltages output from the second data processing unit P2S to the timing controller. As shown in Figures 20 and 23, the data transmission unit TX can transmit the digital sensing voltage Vsen (Parallel Data) output from the second data processing unit P2S to the timing controller in a Bus-Low Voltage Differential Signalling (B-LVDS) transmission format (TX Format). On the other hand, the transmission format (TX Format) in Figure 23 is shown as an example to aid in understanding the data packet, so a detailed explanation is omitted.

[0098] In summary, this specification improves the lifespan of a display device by compensating for elements included in the subpixels constituting the display panel, and also improves the driving stability and driving reliability of the display device by detecting the presence or absence of defects in the entire display device. [Explanation of symbols]

[0099] 120 Timing Controller 140 Data-driven unit 150 Display Panels SP Subpixel 141 Drive Circuit 145 Sensing Circuit DL1 First Data Line VREF1 First Reference Line

Claims

1. A display panel comprising subpixels having an organic light-emitting diode, a capacitor, a drive transistor, a switching transistor, and a sensing transistor, wherein the organic light-emitting diode is connected between a first power line and a second power line, the switching transistor is connected between the gate electrode of the drive transistor and a data line to which a data signal is applied and is turned on / off by a first gate signal, the drive transistor is connected between the organic light-emitting diode and the first power line and is turned on / off by the data signal transferred by the switching transistor, the capacitor is connected between the gate electrode of the drive transistor and a sensing node, the sensing node is defined between the drive transistor and the organic light-emitting diode, and the sensing transistor is connected between the sensing node and a reference line and is turned on / off by a second gate signal, A data drive unit including a drive circuit connected to the data line, A sensing circuit connected to the reference line for sensing the subpixel, A display device including a timing controller connected to the data driving unit and controlling at least one of the driving circuit and the sensing circuit, The aforementioned sensing circuit is During the first sensing period, in response to applying a first reference voltage to the subpixel via the reference line, the first sensing voltage charged to the reference line is acquired as a first sampling value during the period when the switching transistor and the sensing transistor are turned on, and the first sensing voltage charged to the reference line is acquired as a second sampling value during the period when the switching transistor and the sensing transistor are turned off. The aforementioned timing controller Based on the first difference value between the first sampling value and the second sampling value, it is determined that the display device has a defect. The aforementioned sensing circuit is During the second sensing period in which the switching transistor and the sensing transistor are turned off, in response to applying a second reference voltage different from the first reference voltage to the subpixel via the reference line, the second sensing voltage charged to the reference line during the period in which the second reference voltage is applied to the reference line is acquired as a third sampling value, and the second sensing voltage charged to the reference line during the period in which the second reference voltage is not applied to the reference line is acquired as a fourth sampling value. The timing controller determines that the display device is defective based on the second difference value between the third sampling value and the fourth sampling value. The second sensing period is scheduled to be executed when the first difference value is greater than a predetermined value. The display device is configured such that if the first difference value is smaller than the predetermined value, the second sensing period is skipped or not performed.

2. The display device according to claim 1, wherein the first sensing period and the second sensing period are included in the drive start period during which power is applied to the display panel.

3. The display device according to claim 1, wherein the first sensing period and the second sensing period are included in the drive termination period during which an instruction is given to cut off the power supplied to the display panel.

4. The first sensing period is included in the drive start period during which power is applied to the display panel. The display device according to claim 1, wherein the second sensing period is included in the drive termination period in which an instruction is given to cut off the power supply applied to the display panel.

5. A method for controlling a display device, The steps include applying a first reference voltage to a reference line connected to a subpixel using a sensing circuit included in the display device, wherein the sensing circuit is configured to sense the subpixel; The sensing circuit acquires the first reference voltage charged to the reference line as a first sampling value during the period when the switching transistor and the sensing transistor are turned on, The sensing circuit acquires the first reference voltage charged to the reference line as a second sampling value during the period when the switching transistor and the sensing transistor are turned off, The timing control device of the display device determines that there is a defect in the display device based on a first difference value between the first sampling value and the second sampling value, The subpixel comprises an organic light-emitting diode, a capacitor, a drive transistor, a switching transistor, and a sensing transistor. The organic light-emitting diode is connected between the first power line and the second power line. The switching transistor is connected between the gate electrode of the drive transistor and the data line to which the data signal is applied, and is switched on / off by the first gate signal. The drive transistor is connected between the organic light-emitting diode and the first power line and is switched on / off by the data signal transferred by the switching transistor. The capacitor is connected between the gate electrode and the sensing node of the drive transistor, and the sensing node is defined between the drive transistor and the organic light-emitting diode. The sensing transistor is connected between the sensing node and the reference line and is switched on / off by the second gate signal. If the first difference value is greater than a predetermined value, When the switching transistor and the sensing transistor are turned off, a second reference voltage different from the first reference voltage is applied via the reference line. The steps include acquiring the second sensing voltage charged to the reference line as a third sampling value during the period in which the second reference voltage is applied to the reference line, The steps include acquiring the second sensing voltage charged to the reference line as a fourth sampling value during a period when the second reference voltage is not applied to the reference line, The further step is to determine that the display device is defective based on a second difference value between the third sampling value and the fourth sampling value, A method in which, if the first difference value is smaller than the predetermined value, the process for obtaining the second difference value is skipped or scheduled not to be executed.

6. The method according to claim 5, wherein the first reference voltage is applied to the reference line during a first sensing period which is included in the drive start period when power is supplied to the display panel.

7. The method according to claim 5, wherein the second reference voltage is applied to the reference line during a second sensing period included in the drive termination period in which an instruction is given to shut off the power to the display panel.

8. The method according to claim 5, further comprising the step of determining that the display device is defective based on a comparison between either the third sampling value or the fourth sampling value and a sampling value obtained from a normal subpixel under the same driving conditions.

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