Chip-embedded packaging substrate using a metal frame and method for manufacturing the same

Abstract

To provide a chip built-in packaging substrate by a metal frame and a manufacture method of the same.SOLUTION: A manufacture method includes: a step of preparing a metal plate; a step of forming a mold cavity penetrated to the metal plate and a metal frame surrounding the mold cavity, performing a selective partial etching to a first surface of the metal frame, and forming a first mold cavity; a step of building a chip into the mold cavity, directing the pattern surface of the chip to the first surface, laminating a medium layer to a second surface that is opposite to the first surface of the metal frame, and covering a back face of the chip by the medium layer to fill the mold cavity; a step of forming a blind via and a window to the medium layer; a step of forming a first circuit layer connected to a terminal of the chip to the first surface, and forming a second circuit layer to the second surface. A thickness in a packaging of a finished product of a substrate is thinner, and a wiring density is higher, and the number of steps and a material cost can be reduced.SELECTED DRAWING: Figure 1a

Description

Technical Field

[0001] This application relates to the technical field of electronic component packaging, and particularly to a chip-embedded packaging substrate with a metal frame and a method for manufacturing the same.

Background Art

[0002] Among the conventional technical solutions for a chip-embedded packaging substrate with a metal frame, the most common ones are as follows. First, a frame for embedding a chip is manufactured by an etching or mechanical method. After the chip is inserted, a media material is filled on both sides, then an electrical signal channel is opened by a method such as laser, and finally a pattern is manufactured by electroplating.

[0003] In the prior art, after the manufacture of the metal frame, due to the conductivity of the metal, when extracting the electrical signal of the chip later, it is necessary to press-bond a media material on both sides to extract the signal. In some products that require thinning, the media materials on both sides of the metal frame have a great influence on the thickness, and pressing-bonding the media materials on both sides will increase the process and material costs.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In view of this, the object of this application is to propose a chip-embedded packaging substrate with a metal frame and a method for manufacturing the same.

Means for Solving the Problems

[0005] For the above object, this application includes: a step of preparing a metal plate; a step of forming a cavity penetrating the metal plate and a metal frame surrounding the cavity on the metal plate, and performing selective partial etching on the first surface of the metal frame to form a first cavity in the metal frame; The process involves embedding a chip in the cavity, oriented the patterned surface of the chip toward the first surface, and laminating a media layer onto the second surface of the metal frame opposite the first surface, wherein the media layer covers the back surface of the chip and fills the first cavity. The steps include forming blind vias and windows in the media layer, wherein the blind vias are for exposing the second surface of the metal frame and the windows are for exposing the back surface of the chip, The present invention provides a method for manufacturing a chip-embedded packaging substrate using a metal frame, comprising the steps of forming a first circuit layer on the first surface and a second circuit layer on the second surface, wherein the second circuit layer is connected to the back surface of the chip by a first via pillar formed by electroplating the window and connected to the metal frame by a second via pillar formed by electroplating the blind via, and the first circuit layer is connected to the terminals of the chip.

[0006] The present invention also provides a chip-embedded packaging substrate with a metal frame, comprising a metal frame, a cavity surrounded by the metal frame, and a chip embedded in the cavity. A first cavity is formed on the first surface of the metal frame, and the thickness of the metal in the first cavity is less than the thickness of the metal plate. The patterned surface of the chip faces the first surface, a media layer is formed on the second surface of the metal frame facing the first surface, the media layer covers the back of the chip and fills the first cavity, Blind vias and windows are formed in the media layer, the blind vias are for exposing the second surface of the metal frame, and the windows are for exposing the back surface of the chip. A first circuit layer is formed on the first surface, a second circuit layer is formed on the second surface, the second circuit layer is connected to the back surface of the chip by a first via pillar formed by electroplating the window, and is connected to the metal frame by a second via pillar formed by electroplating the blind via, and the first circuit layer is connected to the terminals of the chip. [Effects of the Invention]

[0007] As can be seen from the above description, the chip-embedded packaging substrate with a metal frame and the method for manufacturing the same provided by this application, by plastic packaging a media layer on one side of the metal frame and designing the frame heights on all four sides of the cavity to be differentiated, allows the electrical signals of the chip to be directly extracted from the pattern surface of the chip by the media material filled in the lower frame side, eliminating the need to crimp the media material separately. This enables differentiated wiring design, improves wiring density, and solves to some extent the problems of conventional component-embedded packaging substrates, such as large packaging thickness, low wiring density, complex processes, and high material costs. [Brief explanation of the drawing]

[0008] To more clearly explain the technical solutions in this application or related technologies, the drawings used in the descriptions of the embodiments or related technologies are briefly introduced below. Needless to say, the drawings described below are merely embodiments of this application, and those skilled in the art can obtain other drawings from these drawings without performing any novel work. [Figure 1a] Figure 1a shows a schematic diagram of the pattern surface of a chip-embedded packaging substrate with a metal frame, which is an example of an embodiment of the present invention. [Figure 1b] Figure 1b is a cross-sectional view taken along the AA' direction in Figure 1a. [Figure 1c] Figure 1c is a cross-sectional view taken along the BB' direction in Figure 1a. [Figure 2a]Figure 2a shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2b] Figure 2b shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2c] Figure 2c shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2d] Figure 2d shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2e] Figure 2e shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2f] Figure 2f shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2g] Figure 2g shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Figure 2h] Figure 2h shows a schematic cross-sectional view of the intermediate structure at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] The present application will be described in more detail below, with reference to the drawings and using specific embodiments, in order to further clarify its purpose, technical solution, and advantages.

[0010] Unless otherwise defined, the technical or scientific terms used in the embodiments of this application have the general meanings understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate order, quantity, or importance, but are used to distinguish different components. The terms "includes" or similar terms mean that the element or object appearing before the term covers the element or object and its equivalent listed after the term, but do not exclude other elements or objects. The terms "connected" or similar terms are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. Terms such as "up," "down," "left," and "right" are used to describe only relative positions, and if the absolute position of the object being described changes, the relative position may change accordingly.

[0011] Conventional component-embedded packaging substrates typically use a pre-fabricated frame plate, attach a viscous material to one side of the frame plate, adhere the chip with the viscous material, and then build up the package by peeling off the viscous material. An additional media layer is then required on the pattern side of the chip to extract the electrical signal. Consequently, conventional component-embedded packaging substrates have problems such as large packaging thickness, low wiring density, complex processes, and high material costs.

[0012] In view of this, the embodiment of the present invention provides a chip-embedded packaging substrate with a metal frame and a method for manufacturing the same. By plastic-packaging a media layer on one side of the metal frame, and designing the frame heights around the four sides of the cavity to be differentiated, when extracting signals from the pattern surface of the chip, the electrical signals of the chip can be directly extracted by the media material filled in the lower-height frame edges. Since it is not necessary to crimp the media material separately, differentiated wiring designs can be realized, wiring density can be improved, and problems such as the large packaging thickness, low wiring density, complex processes, and high material costs of conventional component-embedded packaging substrates can be solved to some extent.

[0013] FIG. 1a shows a schematic diagram of a pattern surface of a chip-embedded packaging substrate with an exemplary metal frame according to an embodiment of the present application. FIG. 1b is a cross-sectional view taken along the AA' direction of FIG. 1a, and FIG. 1c is a cross-sectional view taken along the BB' direction of FIG. 1a.

[0014] As shown in FIGS. 1a to 1c and FIGS. 2a to 2h, the chip-embedded packaging substrate with the metal frame may include a metal frame 10, a cavity 11 surrounded by the metal frame 10, and a chip 20 embedded in the cavity 11. A first cavity 12 is formed on a first surface of the metal frame 10, and the metal thickness of the first cavity 12 is smaller than the thickness of the metal frame 10. The pattern surface of the chip 20 faces the first surface, and a media layer 30 is formed on a second surface of the metal frame 10 opposite to the first surface. The media layer 30 covers the back surface of the chip 20 and fills the first cavity 12. Blind vias 31 and windows 32 are formed in the media layer 30. The blind vias 31 are for exposing the second surface of the metal frame 10, and the windows 32 are for exposing the back surface of the chip 20. A first circuit layer 41 is formed on the first surface, and a second circuit layer 42 is formed on the second surface. The second circuit layer 42 is connected to the back surface of the chip 20 by a first via pillar formed by electroplating the window 32, and is connected to the metal frame 10 by a second via pillar formed by electroplating the blind via 31.

[0015] However, the first circuit layer 41 is connected to the terminals of the chip 20.

[0016] However, the metal frame 10 may be a copper plate (for example, a pure copper plate) because it has good heat dissipation and support strength. The thickness (i.e., height) of the metal frame 10 may be selected according to the design. Generally, the thickness of the metal frame 10 should be greater than the height of the embedded chip 20.

[0017] However, the cavity 11 may be considered as a hole penetrating the metal frame 10. The size of the cavity 11 should be larger than the size of the embedded chip 20. For example, the length and width of the cavity 11 may be larger than the length and width of the embedded chip 20, respectively. This helps to fill the space between the chip 20 and the cavity 11 with a medium material. The chip 20 has a patterned surface and a back surface separated by the height of the chip 20.

[0018] As shown in Figures 1b and 1c, the first cavity 12 may be a partial region of the metal frame 10 surrounding the cavity 11. This allows for the formation of a metal frame structure with a cavity by creating a height difference around the cavity 11, and after the cavity is filled with the media layer, the chip terminals can be directly extracted from the surface by the circuit without contact with the metal frame 10. Therefore, there is no need to laminate the media layer on both sides, which shortens the process time and further reduces the thickness of the substrate.

[0019] The first cavity 12 may be located at any position on the metal frame 10, as long as contact between the circuit on its surface and the metal frame 10 is avoided. In some embodiments, the first cavity 12 may be located on one frame of the metal frame 10, and the cavity may be located on multiple frames of the metal frame 10 around the cavity 11.

[0020] In some embodiments, the first cavity 12 may be recessed from the first surface to the second surface of the metal frame 10, and the cross-sectional shape of the first cavity 12 may be, for example, arched. The height of the metal in the first cavity 12 may be 8 μm or more.

[0021] In some embodiments, the blind via 31 may be opened in a frame facing the first cavity 12. This improves the stability of the connection between the second circuit layer 42 and the metal frame 10.

[0022] In some embodiments, the media layer 30 may be selected from Ajinomoto (ABF) resin or polypropylene (PP) resin. The media layer 30 may be formed by laminating the media material to the second surface of the metal frame 10 (i.e., the back surface of the chip 20). The surface of the media layer 30 may be provided flush with the terminals on the pattern surface of the chip 20. This makes it possible to reduce the thickness of the packaging substrate as much as possible.

[0023] The first via pillar and the second via pillar referred to in this embodiment may each independently include at least one copper pillar having a through via hole as an IO channel, thereby achieving interlayer conductivity. The size and / or shape of the multiple copper pillars having through via holes may be the same or different. The copper pillars having through via holes may be solid copper pillars or hollow pillars with copper plating on their surfaces. Preferably, the via pillar may include multiple copper pillars having through via holes as an IO channel.

[0024] The chip-embedded packaging substrate with a metal frame provided by the embodiment of the present invention is designed so that the height of the frame around the cavity 11 is differentiated. When extracting terminal signals from the pattern surface of the chip 20, the electrical signals of the chip 20 can be directly and independently extracted by the media layer filled in the lower-height first cavity 12 without contact with the metal frame 10. Since there is no need to separately crimp the media material, differentiated wiring design is realized, wiring density is improved, and the overall packaging thickness of the substrate can be reduced because there is no need to crimp another layer of media material onto the pattern surface of the chip 20.

[0025] Figures 2a to 2h show schematic cross-sectional views of the intermediate structures at each step of the manufacturing method for a chip-embedded packaging substrate using a metal frame according to an embodiment of the present invention.

[0026] The method for fabricating a chip-embedded packaging substrate using a metal frame includes the following steps: As shown in Figure 2a, a metal plate is prepared (step (a)). The metal plate may be a copper plate (for example, a pure copper plate). The thickness (i.e., height) of the metal plate may be selected according to the design. Generally, the thickness of the metal plate may be greater than the height of the embedded chip 20.

[0027] Next, as shown in Figures 2b to 2d, a cavity 11 is formed in the metal plate that penetrates the metal plate, and a metal frame 10 surrounding the cavity 11 is formed in the metal plate (step (b)). Selective local etching is performed on the first surface of the metal frame 10 around the cavity 11 to form a first cavity 12, thereby giving the first cavity 12 a different height from the metal frame 10. Figure 2c is a cross-sectional view along the AA' direction of Figure 2b, and Figure 2d is a cross-sectional view along the BB' direction of Figure 2b.

[0028] In some embodiments, the height of the metal in the first cavity 12 is less than the height of the rest of the metal frame 10. Generally, the first cavity 12 may be located in the center of the frame. Etching may be performed from a first surface (e.g., the bottom surface) of the metal frame 10 toward a second surface (e.g., the top surface) of the metal frame 10. The shape of the first cavity 12 may be a flat groove or the like. The height of the metal in the first cavity 12 may be 8 μm or more.

[0029] In some embodiments, the height of the metal in the first cavity 12 is not uniform; for example, the cross-section of the first cavity 12 may be arched. This allows the first cavity 12 itself to be formed as a structure with differences in height.

[0030] Next, as shown in Figures 2e to 2g, the chip 20 is embedded in the cavity 11, with the patterned surface of the chip 20 facing the first surface, and the media layer 30 is laminated to the back of the chip 20. The media layer 30 also fills the first cavity 12 and makes the media layer 30 flush with the first surface of the metal frame 10 (step (c)). Generally, a viscous material may be attached to the first surface of the metal frame 10 to bond the chip 20, and after forming the media layer 30 on the back of the chip 20 by lamination, the viscous material may be peeled off.

[0031] However, the media layer 30 may be selected from Ajinomoto (ABF) resin or polypropylene (PP) resin. The surface of the media layer 30 may be flush with the first surface of the metal frame 10 and the terminals of the chip 20, and the media layer 30 is formed on the second surface of the metal frame 10. By forming the media layer 30 on the back surface of the chip 20 by lamination, the media layer 30 can fill the gap between the chip 20 and the cavity 11, thereby filling the first cavity 12. As a result, by laminating the media layer 30 to one side, that is, by filling the first cavity 12 with the media layer 30, the electrical signals of the chip 20 can be directly extracted later, eliminating the need to crimp the media material alone, and later helping to realize differentiated wiring designs and reduce the thickness of the substrate.

[0032] Next, as shown in Figure 2h, blind vias 31 and windows 32 are formed on the surface of the media layer 30. The blind vias 31 are for exposing the second surface of the metal frame 10, and the windows 32 are for exposing the back surface of the chip 20 (step (d)). However, no change occurs in Figure 2g after this step. Generally, the blind vias 31 and windows 32 may be formed by a laser.

[0033] In some embodiments, the blind via 31 may be opened in a metal frame 10 facing the first cavity 12.

[0034] Next, as shown in Figures 1a and 1b, a first circuit layer 41 is formed on the first surface of the metal frame 10, and a second circuit layer 42 is formed on the surface of the medium layer 30 (step (e)). Generally, the first circuit layer 41 and the second circuit layer 42 may be fabricated by first creating a seed layer and then electroplating the pattern. Figure 1a shows a schematic diagram of the pattern surface of an exemplary metal frame chip-embedded packaging substrate according to an embodiment of the present invention. Figure 1b is a cross-sectional view along the AA' direction of Figure 1a, and Figure 1c is a cross-sectional view along the BB' direction of Figure 1a.

[0035] As shown in Figure 1b, the second circuit layer 42 is connected to the back of the chip 20 by a first via pillar formed by electroplating the window 32, and is also connected to the metal frame 10 by a second via pillar formed by electroplating the blind via 31. This connects the back of the chip 20 to the metal frame 10 via the second circuit layer 42, allowing the chip 20 to dissipate heat more effectively through the metal frame 10. As shown in Figure 1c, the first circuit layer 41 is connected to the terminals of the chip 20 to extract signals independently. Alternatively, the first circuit layer 41 and the second circuit layer 42 may be connected by the metal frame 10 for further heat dissipation. This allows some of the circuits of the first circuit layer 41 to be directly extracted from the terminals of the chip 20 and wired independently by the medium layer 30 filled in the first cavity 12, without having to press the medium layer 30 onto the pattern surface of the chip 20, thus increasing the wiring density and reducing the overall thickness of the substrate.

[0036] Those skilled in the art will understand that the descriptions of each of the embodiments above are illustrative and do not imply that the scope of the Application (including the claims) is limited to these examples. In the spirit of the Application, the technical features of the above embodiments or different embodiments can be combined with each other, the steps may be performed in any order, and many other variations of different embodiments of the above embodiments may exist, which for the sake of simplicity are not provided in the detailed description.

[0037] Furthermore, for the sake of simplification of explanation and description, and to ensure that the embodiments of this application are not difficult to understand, the provided drawings may or may not show connections to the well-known power / ground of integrated circuit (IC) chips and other components. Also, to ensure that the embodiments of this application are not difficult to understand, the apparatus may be shown in block diagram form, taking the following facts into consideration: the details of the embodiments relating to the apparatus in these block diagrams are largely dependent on the platform for implementing the embodiments of this application (i.e., these details are entirely within the realm of understanding for those skilled in the art). Where details (e.g., circuits) are specifically described to illustrate the exemplary embodiments of this application, it will be obvious to those skilled in the art that the embodiments can be implemented even if these details are absent or varied. Therefore, these descriptions are for illustrative purposes only, not limitation.

[0038] Although this application is described using specific embodiments thereof, many substitutions, amendments, and modifications of these embodiments are obvious to those skilled in the art.

[0039] The embodiments of this application are intended to include all such substitutions, amendments, and modifications that fall within the broad scope of the claims. Therefore, any omissions, amendments, equivalent substitutions, improvements, etc., in the spirit and principles of the embodiments of this application shall be included within the scope of the claims. [Explanation of Symbols]

[0040] 10 Metal frame, 11 Cavity, 12 First cavity, 20 Chip, 30 Medium layer, 31 Blind via, 32 Window, 41 First circuit layer, 42 Second circuit layer

Claims

1. The steps include preparing a metal plate and The steps include forming a cavity penetrating the metal plate and a metal frame surrounding the cavity in the metal plate, and performing selective partial etching on the first surface of the metal frame to form a first cavity in the metal frame, The process involves embedding a chip in the cavity, facing the patterned surface of the chip toward the first surface, and laminating a media layer onto the second surface of the metal frame opposite the first surface, wherein the media layer covers the back surface of the chip and fills the first cavity. The steps include forming blind vias and windows in the media layer, wherein the blind vias are for exposing the second surface of the metal frame and the windows are for exposing the back surface of the chip, The method includes forming a first circuit layer on the first surface and a second circuit layer on the second surface, wherein the second circuit layer is connected to the back surface of the chip by a first via pillar formed by electroplating the window and connected to the metal frame by a second via pillar formed by electroplating the blind via, and the first circuit layer is connected to the terminals of the chip. A method for manufacturing a chip-embedded packaging substrate using a metal frame, characterized in that the first circuit layer connected to the terminals of the chip is removed independently by the first cavity, and thereby is not connected to the metal frame.

2. The method for manufacturing a chip-embedded packaging substrate using a metal frame according to claim 1, characterized in that the thickness of the metal in the first cavity is smaller than the thickness of the metal plate.

3. The method for manufacturing a chip-embedded packaging substrate using a metal frame according to claim 1, characterized in that the thickness of the metal in the first cavity is 8 μm or more.

4. The method for manufacturing a chip-embedded packaging substrate using a metal frame according to claim 1, characterized in that the pattern surface of the chip is not covered by a media layer.

5. The method for manufacturing a chip-embedded packaging substrate using a metal frame according to claim 1, characterized in that the media layer is selected from ABF (Ajinomoto Build-up Film) (registered trademark) resin or polypropylene resin.

6. The method for manufacturing a chip-embedded packaging substrate using a metal frame according to claim 1, characterized in that the metal plate is a copper plate.

7. It includes a metal frame, a cavity surrounded by the metal frame, and a chip embedded in the cavity, A first cavity is formed on the first surface of the metal frame, and as a result, the thickness of the metal in the first cavity is smaller than the thickness of the metal frame. The patterned surface of the chip faces the first surface, a medium layer is formed on the second surface of the metal frame facing the first surface, the medium layer covers the back of the chip and fills the first cavity, Blind vias and windows are formed in the media layer, the blind vias are for exposing the second surface of the metal frame, and the windows are for exposing the back surface of the chip. A first circuit layer is formed on the first surface, a second circuit layer is formed on the second surface, the second circuit layer is connected to the back surface of the chip by a first via pillar formed by electroplating the window, and is connected to the metal frame by a second via pillar formed by electroplating the blind via, and the first circuit layer is connected to the terminals of the chip. A chip-embedded packaging substrate with a metal frame, characterized in that the first circuit layer connected to the terminals of the chip is independently removed by the first cavity, and thereby is not connected to the metal frame.

8. The chip-embedded packaging substrate with a metal frame according to claim 7, characterized in that the thickness of the metal in the first cavity is 8 μm or more.

9. The chip-embedded packaging substrate with a metal frame according to claim 7, characterized in that the pattern surface of the chip is not covered by a media layer.

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