Display panels and display devices

Abstract

To provide a display panel and a display device.SOLUTION: The display panel and the display device are disclosed. The display panel includes a base substrate with a first display region and a second display region. A pixel circuit for driving a light-emitting element in the second display region is arranged in the first display region alone and is not arranged in the second display region, and an excellent light transmittance of the second display region can be thus secured. The display panel disclosed in the present application can accordingly have an excellent display effect.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application is a divisional application of a Japanese patent application with the application number of Japanese Patent Application No. 2023-518291. The Japanese patent application is the national phase application of the international application with the application number PCT / CN2020 / 119673 filed on September 30, 2020, and all its contents are incorporated herein by reference. This application relates to the field of display technology, and particularly to display panels and display devices.

Background Art

[0002] The under-screen embedded camera technology is a new technology proposed to increase the screen occupancy rate of display devices.

[0003] In related technologies, a display panel equipped with an under-screen embedded camera generally includes a first display area for normal display and a second display area for arranging the camera. The second display area generally includes a plurality of light-emitting elements and a plurality of pixel circuits. Each pixel circuit is connected to one light-emitting element and is used to drive the light-emitting element to emit light. The pixel circuits and the light-emitting elements connected to each other overlap in a direction perpendicular to the display panel.

[0004] In related technologies, since pixel circuits are also installed in the second display area, the light transmittance of the second display area is poor, and correspondingly, the display effect of the display panel is poor.

Summary of the Invention

Means for Solving the Problems

[0005] This application provides a display panel and a display device, and the technical solution is as follows.

[0006] On one side, it has a first display area and a second display area, where the first display area includes a base substrate that at least partially surrounds the second display area, A plurality of first pixel circuits arranged in the first display area, a plurality of second pixel circuits arranged at intervals between the plurality of first pixel circuits, and a plurality of first light-emitting elements, A plurality of second light-emitting elements arranged in the second display area, Includes, Here, at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements, the orthographic projection of the at least one first pixel circuit onto the base substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element onto the base substrate, and at least one of the plurality of second pixel circuits is connected by a conductive wire to at least one of the plurality of second light-emitting elements. Regarding the display panel.

[0007] As one option, the density of the plurality of second light-emitting elements is the same as the density of the plurality of first light-emitting elements.

[0008] One option is that the resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

[0009] As one option, each of the first pixel circuits is connected to one of the first light-emitting elements. Furthermore, the orthographic projection of each of the first pixel circuits onto the base substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element onto the base substrate.

[0010] As one option, the plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a first direction, and the plurality of second pixel circuits include a plurality of rows of second pixel circuits extending along a first direction. Here, the multiple rows of second pixel circuits are arranged with gaps between the multiple rows of first pixel circuits.

[0011] As one option, the first pixel circuits, with the same or different number of rows, are arranged between any two adjacent rows of the second pixel circuits.

[0012] As one option, the plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a second direction, and the plurality of second pixel circuits include a plurality of rows of second pixel circuits extending along a second direction, the second direction intersects with the first direction, where the plurality of rows of second pixel circuits are spaced apart from the plurality of rows of first pixel circuits.

[0013] One option is that the first direction is perpendicular to the second direction.

[0014] As one option, the first display area includes a first sub-display area and a second sub-display area arranged sequentially along a first direction, and the first sub-display area includes two symmetrical target sub-display areas. Here, one of the target sub-display areas, the second display area, and the other target sub-display area are arranged sequentially along the second direction.

[0015] As one option, the second display area includes two third sub-display areas arranged symmetrically along the second direction, and the display panel includes a first conductive wire, a second conductive wire, and a third conductive wire. Each of the third sub-display areas includes k groups of light-emitting elements, each of the light-emitting elements includes multiple adjacent rows of the second light-emitting elements, the first to the kth light-emitting elements are arranged sequentially along the direction toward the other third sub-display area, and k is an integer greater than 0. Each target sub-display area includes k pixel circuit groups that correspond one-to-one with the k light-emitting groups, each pixel circuit group includes multiple adjacent rows of the second pixel circuits, the first to the kth pixel circuit groups are arranged sequentially along a direction away from the adjacent third sub-display area, and each second light-emitting element in each light-emitting group is connected to each second pixel circuit in a corresponding pixel circuit group by a first conductive wire, a second conductive wire, and / or a third conductive wire.

[0016] One of the options is that k is 4.

[0017] As one option, each of the second light-emitting elements in the first group of light-emitting elements is connected to each of the second pixel circuits in the first group of pixel circuits by the first conductive wire. Each of the second light-emitting elements in the second group of light-emitting elements is connected to each of the second pixel circuits in the second group of pixel circuits by a second conductive wire. Each of the second light-emitting elements in the third group of light-emitting elements is connected to each of the second pixel circuits in the third group of pixel circuits by the third conductive wire. Each of the second light-emitting elements in the fourth group of light-emitting elements is connected to each of the second pixel circuits in the fourth group of pixel circuits by the first conductive wire, the second conductive wire, and the third conductive wire.

[0018] As one option, the first conductive wire connected to each of the second light-emitting elements in the first group of light-emitting elements, the second conductive wire connected to each of the second light-emitting elements in the second group of light-emitting elements, and the third conductive wire connected to each of the second light-emitting elements in the third group of light-emitting elements include a first conductive wire segment, a second conductive wire segment, and a third conductive wire segment. One end of the first conductive wire segment is connected to the corresponding second light-emitting element, and the other end of the first conductive wire segment is connected to one end of the second conductive wire segment. The other end of the second conductive wire segment is connected to one end of the third conductive wire segment. The other end of the third conductive wire segment is connected to the corresponding second pixel circuit. Here, the first conductive wire segment and the third conductive wire segment extend along the first direction, the second conductive wire segment extends along the second direction, and the orthographic projection of the second conductive wire segment onto the base substrate at least partially overlaps with the orthographic projection of the second light-emitting element connected to the second conductive wire segment onto the base substrate.

[0019] As one option, the second conductive wire segment included in the first conductive wire at least partially overlaps with the second conductive wire segment included in the third conductive wire, the second conductive wire segment included in the first conductive wire does not overlap with the second conductive wire segment included in the second conductive wire, and the second conductive wire segment included in the third conductive wire does not overlap with the second conductive wire segment included in the second conductive wire.

[0020] As one option, the fourth group of light-emitting elements includes two first sub-light-emitting elements, two second sub-light-emitting elements, and two third sub-light-emitting elements, arranged symmetrically along the axis of the third sub-display area, each sub-light-emitting element including multiple adjacent rows of the second light-emitting elements, and the first, second, and third sub-light-emitting elements, arranged on the same side, are sequentially arranged along a direction away from the axis, and the axis extends along the second direction. The fourth pixel circuit group includes two first sub-pixel circuit groups corresponding one-to-one to the two first sub-light-emitting groups, two second sub-pixel circuit groups corresponding one-to-one to the two second sub-light-emitting groups, and two third sub-pixel circuit groups corresponding one-to-one to the two third sub-light-emitting groups. Here, each of the second light-emitting elements in each of the first sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding first sub-pixel circuit group by the first conductive line, and each of the second light-emitting elements in each of the second sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding second sub-pixel circuit group by the second conductive line, and each of the second light-emitting elements in each of the third sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding third sub-pixel circuit group by the third conductive line.

[0021] As one option, the first conductive line connected to each of the second light-emitting elements in each of the first sub-light-emitting element groups, the second conductive line connected to each of the second light-emitting elements in each of the second sub-light-emitting element groups, and the third conductive line connected to each of the second light-emitting elements in each of the third sub-light-emitting element groups include a fourth conductive line segment, a fifth conductive line segment, a sixth conductive line segment, and a seventh conductive line segment. One end of the fourth conductive line segment is connected to the corresponding second light-emitting element, and the other end of the fourth conductive line segment is connected to one end of the fifth conductive line segment. The other end of the fifth conductive line segment is connected to one end of the sixth conductive line segment. The other end of the sixth conductive line segment is connected to one end of the seventh conductive line segment. The other end of the seventh conductive line segment is connected to the corresponding second pixel circuit. Here, the fifth conductive line segment and the seventh conductive line segment extend along the first direction, the sixth conductive line segment extends along the second direction, and the fourth conductive line segment is disposed between the row where the connected second light-emitting element is located and the adjacent row. The fifth conductive wire segment included in the first conductive wire is disposed within the region where the second to fourth light-emitting element groups are located. The fifth conductive wire segment included in the second conductive wire is disposed within the region where the third and fourth light-emitting element groups are located. The fifth conductive wire segment included in the third conductive wire is disposed within the region where the fourth light-emitting element group is located. The sixth conductive wire segment on the side away from the second sub-display region along the axis is disposed on the side away from the second sub-display region of the second display region. The sixth conductive wire segment on the side close to the second sub-display region along the axis is disposed within the second display region close to the second sub-display region.

[0022] As an option, each of the first to third light-emitting element groups includes 12 columns of the second light-emitting elements, and the fourth light-emitting element group includes 8 columns of the second light-emitting elements. Each of the first to third pixel circuit groups includes 12 columns of the second pixel circuits, and the fourth pixel circuit group includes 8 columns of the second pixel circuits.

[0023] As an option, the display panel further includes a plurality of metal layers. The data cable connected to each of the second pixel circuits is disposed in the same layer as any of the metal layers. Here, the plurality of metal layers include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer.

[0024] As one option, in the second pixel circuits from the 1st to ith columns within each target sub-display area, along the direction away from the adjacent third sub-display area, data cables connected to the second pixel circuits located in odd-numbered columns are located in the same layer as the first gate metal layer, data cables connected to the second pixel circuits located in even-numbered columns are located in the same layer as the second gate metal layer, and data cables connected to the second pixel circuits from the ith to nth columns are located in the same layer as the first source-drain metal layer, where i is an integer greater than 1 and less than n, and n is equal to the total number of columns within each target sub-display area.

[0025] As one option, the data cable connected to each of the second pixel circuits includes a first data cable segment, a second data cable segment, and a third data cable segment. One end of the first data cable segment is connected to the corresponding metal layer, the other end is connected to one end of the second data cable segment, the other end of the second data cable segment is connected to one end of the third data cable segment, and the other end of the third data cable segment is connected to the second pixel circuit. Here, the second data cable segment extends along the first direction and is included in a data cable arranged in the same layer as the first gate metal layer, the second data cable segment is included in a data cable arranged in the same layer as the second gate metal layer, and the second data cable segment is included in a data cable arranged in the same layer as the first source drain metal layer, and these do not overlap each other.

[0026] As one option, the second source-drain metal layer covers the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

[0027] As one option, in the second pixel circuit of the same row, the data cable connected to the second pixel circuit located in the first sub-display area is different from the data cable connected to the second pixel circuit located in the second sub-display area.

[0028] As one option, the display panel further includes at least one row of dummy second pixel circuits, the at least one row of dummy second pixel circuits being located in the target sub-display area close to the second display area.

[0029] As one option, in the plurality of first pixel circuits and the plurality of second pixel circuits, the width of any of the pixel circuits is smaller than the width of any of the first light-emitting elements.

[0030] One option is that the difference between the width of each pixel circuit and the width of the first light-emitting element is 4 micrometers.

[0031] As one option, each of the second pixel circuits and each of the second light-emitting elements has a switching section, and the conductive wire is connected to the switching section of the at least one second pixel circuit and to the switching section of the at least one second light-emitting element, respectively.

[0032] One option is that the conductive wire is a transparent conductive wire.

[0033] One option is to use indium tin oxide as the material for the transparent conductive wire.

[0034] As one option, the second display area is a translucent display area.

[0035] In another aspect, the system includes an integrated circuit and the display panel described above. The integrated circuit is connected to the first pixel circuit and the second pixel circuit in the display panel and is used to drive the first pixel circuit and the second pixel circuit to operate. Regarding display devices.

[0036] As one option, the display device further includes a photosensitive sensor, the photosensitive sensor being located within a second display area of ​​the display panel.

[0037] As one option, the second display area is rectangular, and the area of ​​the orthographic projection of the photosensitive sensor onto the base substrate is less than or equal to the area of ​​the inscribed circle of the second display area. [Brief explanation of the drawing]

[0038] To more clearly illustrate the technical concepts in the embodiments of this application, the drawings used in describing the embodiments will be briefly described below. The drawings in the following description are only a few embodiments of the disclosure, and it will be obvious to those skilled in the art that other drawings can be obtained based on these drawings without any creative work.

[0039] [Figure 1] This is a schematic diagram of the structure of a display panel according to an embodiment of this application. [Figure 2] This is a schematic diagram of the structure of another display panel according to an embodiment of this application. [Figure 3] This is a schematic diagram of yet another display panel structure according to an embodiment of the present application. [Figure 4] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 5] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 6] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 7] This is a layout diagram of the pixel circuit before and after compression according to an embodiment of this application. [Figure 8] This is a schematic diagram of the structure of a display panel according to an embodiment of this application. [Figure 9] This is a schematic diagram of the structure of a pixel circuit according to an embodiment of this application. [Figure 10]This is a layout diagram of the pixel circuit configuration according to the embodiment of this application. [Figure 11] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 12] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 13] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 14] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 15] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 16] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 17] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 18] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 19] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 20] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 21] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 22] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 23] This is a schematic diagram of the structure of a conductive wire according to an embodiment of this application. [Figure 24] This is a schematic diagram of the structure of a conductive wire according to an embodiment of this application. [Figure 25] This is a schematic diagram of the structure of a conductive wire according to an embodiment of this application. [Figure 26] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 27] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 28] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 29] This is a cross-sectional view of a display panel according to an embodiment of the present application. [Figure 30] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 31] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 32] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 33] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 34] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 35] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 36] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 37] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 38] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 39] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 40] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 41] This is a schematic diagram of the structure of a data cable according to an embodiment of this application. [Figure 42] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 43] This is a schematic diagram of yet another display panel structure according to an embodiment of this application. [Figure 44] This is a schematic diagram of the structure of a display device according to an embodiment of this application. [Modes for carrying out the invention]

[0040] To further clarify the purpose, technical proposal, and advantages of this application, embodiments of this application will be described in more detail below with reference to the drawings.

[0041] With advancements in display technology, traditional notch or teardrop display designs could no longer meet users' needs for high screen-to-body ratios, leading to the development of display panels with a series of translucent display areas. In such display panels, hardware such as photosensitive sensors (e.g., cameras) can be placed in the translucent display area, eliminating the need for holes and thus enabling true full-screen display while maintaining the practicality of the display panel.

[0042] In the embodiments of this application, a display panel is provided that ensures good display effect in a non-transparent display area without reducing the number of pixels in the non-transparent display area, while reliably driving the light-emitting elements in the translucent display area and ensuring good light transmittance in the translucent display area.

[0043] Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of this application. As shown in Figure 1, the display panel may include a base substrate 01.

[0044] The base substrate 01 has a first display area A1 and a second display area A2, and the first display area A1 can at least partially surround the second display area A2. For example, the second display area A2 shown in Figure 1 is located in the center of the top of the base substrate 01, and correspondingly, the four sides of the rectangular first display area A1 may surround the second display area A2, that is, the second display area A2 may be surrounded by the first display area A1.

[0045] In some embodiments, the second display area A2 may be located at a position other than the top center of the base substrate 01 shown in Figure 1. For example, referring to Figure 1, the second display area A2 may be located at the upper left corner or the upper right corner of the base substrate 01.

[0046] Referring further to another display panel shown in Figure 2, the display panel may further include a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 arranged in a first display area A1, and a plurality of second light-emitting elements 40 arranged in a second display area A2, wherein the plurality of second pixel circuits 20 may be arranged with intervals between the plurality of first pixel circuits 10.

[0047] Here, at least one of the plurality of first pixel circuits 10 is connected to at least one of the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 onto the base substrate 01 overlaps at least partially with the orthographic projection of at least one first pixel circuit 30 onto the base substrate 01. The at least one first pixel circuit 10 can be used to drive the connected first light-emitting elements 30 to emit light by supplying a drive signal to the first light-emitting elements 30.

[0048] At least one of the plurality of second pixel circuits 20 is connected by a conductive wire L1 to at least one of the plurality of second light-emitting elements 40, and this at least one second pixel circuit 20 can be used to drive the connected second light-emitting element 40 to emit light by supplying a drive signal to the second light-emitting element 40. Because the second light-emitting elements 40 and the second pixel circuits 20 are located in different regions, the orthographic projection of at least one second pixel circuit 20 onto the base substrate 01 does not overlap with the orthographic projection of at least one second light-emitting element 40 onto the base substrate 01, as shown in Figure 2.

[0049] As one option, in the embodiment of this application, the first display area A1 can be set as a non-transparent display area, and the second display area A2 can be set as a translucent display area. That is, the first display area A1 described in the embodiment of this application cannot transmit light, and the second display area A2 can transmit light. In this way, there is no need to drill holes in the display panel, and the necessary hardware structures such as photosensitive sensors can be directly placed in the second display area A2, providing a robust foundation for realizing true full-screen display. Since the second display area A2 contains only light-emitting elements and does not contain pixel circuits, good light transmittance of the second display area A2 can also be ensured.

[0050] Based on the above, the embodiments of this application provide a display panel including a base substrate having a first display area and a second display area. Since the pixel circuit for driving the light-emitting elements in the second display area is arranged only in the first display area and not in the second display area, good light transmittance in the second display area is ensured. Correspondingly, the display effect of the display panel described in the embodiments of this application is good.

[0051] Figure 3 shows a schematic diagram of the structure of another display panel, using the display panel shown in Figure 2 as an example. Referring to Figure 3, it can be seen that the first display area A1 includes not only multiple pixels but also multiple rows of second pixel circuits 20, and the second display area A2 includes only multiple second light-emitting elements 40.

[0052] Here, a pixel refers to a structure including a pixel circuit and a light-emitting element. Referring to Figure 3, with the first pixel circuit 10 and the first light-emitting element 30 as an example, each pixel shown includes a red subpixel R, two green subpixels G1 and G2, and one blue subpixel B. The red subpixel R and blue subpixel B are arranged in the same column, and the two green subpixels G1 and G2 are arranged in the same column. Of course, in some embodiments, a pixel may include other colors and other numbers of subpixels, and the arrangement of each subpixel is not limited to the configuration shown in Figure 3. For example, each pixel may include only one red subpixel R, one blue subpixel B, and one green subpixel G.

[0053] As one option, in the embodiments of this application, the electrical connection relationship between the multiple first pixel circuits 10 and the multiple first light-emitting elements 30 may correspond one-to-one. That is, each of the first pixel circuits 10 may be connected to one first light-emitting element 30, and the first light-emitting elements 30 connected to each first pixel circuit 10 are different. As a result, referring to the display panel shown in Figure 2, the orthographic projection of each first pixel circuit 10 onto the base substrate 01 at least partially overlaps with the orthographic projection of the connected first light-emitting elements 30 onto the base substrate 01.

[0054] Similar to the electrical connection relationship between the first pixel circuit 10 and the first light-emitting element 30, the electrical connection relationship between multiple second pixel circuits 20 and multiple second light-emitting elements 40 may also correspond one-to-one. Furthermore, the orthographic projection of each second pixel circuit 20 onto the base substrate 01 does not overlap with the orthographic projection of the connected second light-emitting elements 40 onto the base substrate 01.

[0055] As one option, the density of the multiple second light-emitting elements 40 arranged in the second display area A2 may be the same as the density of the multiple first light-emitting elements 30 arranged in the first display area A1. That is, the number of light-emitting elements per inch is the same in the first display area A1 and the second display area A2. In other words, the first display area A1 (i.e., the main display area) does not have two sub-areas with different pixel densities, and furthermore, with respect to related technologies, when displaying the screen, there is no light / dark boundary in the first display area A1, resulting in a better display effect for the display panel.

[0056] Using the display panel shown in Figure 2 as an example, Figure 4 is a layout diagram of the display panel's configuration. Referring to Figure 4, the resolution of the first display area A1 is greater than the resolution of the second display area A2. That is, the area of ​​the first display area A1 is greater than the area of ​​the second display area A2, and the number of light-emitting elements included in the first display area A1 is greater than the number of light-emitting elements included in the second display area A2.

[0057] In some embodiments, the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2. For example, the area of ​​the first display area A1 may be the same as the area of ​​the second display area A2, and the number of light-emitting elements included in the first display area A1 may be the same as the number of light-emitting elements included in the second display area A2. Alternatively, the area of ​​the first display area A1 may be smaller than the area of ​​the second display area A2, and the number of light-emitting elements included in the first display area A1 may be smaller than the number of light-emitting elements included in the second display area A2.

[0058] As one option, Figure 5 is a partially enlarged schematic diagram of the display panel shown in Figure 4. Referring to Figures 4 and 5, the size of the first light-emitting element 30 may be larger than the size of the second light-emitting element 40, that is, the anode of the light-emitting element in the second display area A2 is smaller than the anode of the light-emitting element in the first display area A1. In this way, it is possible to ensure that the light transmittance of the second display area A2 is greater than that of the first display area A1. Furthermore, by further optimizing the shape and size of the anode of the second light-emitting element 40, even better light transmittance can be ensured. For example, referring to the display panel shown in Figure 3, the anode of the second light-emitting element 40 shown is elliptical.

[0059] To improve the light transmittance of the second display area A2, the conductive wire L1 described in the embodiments of this application may be a transparent conductive wire. For example, the conductive wire L1 can be made of a transparent material such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). Assuming that the conductive wire L1 is made of ITO material, it may also be called ITO wiring. In all the embodiments below, the description will be based on the example that the conductive wire L1 is ITO wiring.

[0060] As one option, in the embodiment of this application, the base substrate 01 has a light-transmitting display area, i.e., a second display area A2. As shown in Figure 6, the structure of the photosensitive sensor 50 (e.g., a camera) in the display module included in the display device can be directly placed in the second display area A2, meaning there is no need to drill additional holes in the display panel. In this way, a robust base can be provided for realizing a full-screen display panel.

[0061] As one option, the second display area A2 may be rectangular, and the area of ​​the orthographic projection of the photosensitive sensor 50 onto the base substrate 01 may be less than or equal to the area of ​​the inscribed circle of the second display area A2. That is, the size of the area where the photosensitive sensor 50 is located may be less than or equal to the size of the inscribed circle of the second display area A2. For example, referring to Figure 6, in the displayed display panel, the size of the area where the photosensitive sensor 50 is located is equal to the size of the inscribed circle YO of the second display area A2, that is, the shape of the area where the photosensitive sensor 50 is located may be circular, and therefore the area where the photosensitive sensor 50 is located can also be called a light-transmitting hole. Of course, in some embodiments, the second display area A2 may be a shape other than rectangular, such as circular or elliptical.

[0062] In related technologies, the size (pitch) of the pixel circuits (including the first pixel circuit 10 and the second pixel circuit 20) and the first light-emitting element 30 are the same. For example, generally, the width is about 30 to 32 microns (μm) and the length is about 60 to 65 microns (μm). In the embodiments of this application, the width of the pixel circuits in the second direction is reduced relative to the width of the first light-emitting element 30 by compressing each pixel circuit along the second direction X2 (e.g., the direction in which the gate lines extend, also called the transverse direction) in order to provide sufficient space for arranging the second pixel circuits 20 without reducing the number of pixels in the first display area A1. Alternatively, the width of the first light-emitting element 30 in the second direction is increased relative to the width of the pixel circuits by stretching the first light-emitting element 30 along the second direction. Thus, assuming that the size of the base substrate 01 is the same, many areas can be provided within the first display area A1, and correspondingly, a second pixel circuit 20 for driving the second light-emitting element 40 located within the second display area A2 can be provided in these many areas.

[0063] For example, the difference between the width of the pixel circuit and the width of the first light-emitting element 30 is approximately 4 μm. Taking the example of a compressed pixel circuit with a width difference of 4 μm, Figure 7 is a layout diagram of the pixel circuit configuration before and after compression (i.e., the related technology and the embodiment of this application). Referring to Figure 7, the pixel circuit may include a drive structure and a switching unit B1 for connecting to the anode of the light-emitting element, and the size of the switching unit B1 can represent the size of the pixel circuit. The size of both the pixel circuit and the light-emitting element before compression is 1 to 100 μm in width and 2 to 200 μm in height, while the size of the light-emitting element after compression does not change, the height of the pixel circuit does not change, but the width decreases by 1 to 20 μm. In this way, there is one or more additional compressed pixel circuits for each row of compressed pixel circuits, and by adopting this design for the entire screen, full-screen compression is achieved. Here, these additional rows are selected to connect the second light-emitting element 40 in the second display area A2 and control the second light-emitting element 40 to emit light. In some embodiments, it is preferable to use an additional row of pixel circuits near the periphery of the second display area A2 as a second pixel circuit 20 for connecting the second light-emitting element 40. In this way, normal display can be ensured without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to achieve normal display.

[0064] Referring to Figure 3, the width of the pixel circuit can be defined as the length of the orthographic projection of the pixel circuit layout on the base substrate 01 in the second direction X2. The width of the first light-emitting element 30 refers to the length of the orthographic projection of the anode of the first light-emitting element 30 on the base substrate 01 in the second direction X2.

[0065] Referring to Figures 3 and 8, each first light-emitting element described in the embodiments of this application belongs to one subpixel in one pixel. For example, a red subpixel R, green subpixels G1 and G2, or a blue subpixel B. When determining the size of the anode of the first light-emitting element, it is generally possible to measure the width D10 of the pixel in the first direction X1 or the second direction X2, using one pixel as the period, and then divide the total width D10 of the pixel by the number of subpixels included in the pixel (for example, 4 as shown in Figure 8) for the width D01 of each first light-emitting element. Similarly, since each first light-emitting element is connected to correspond to one pixel circuit, it is possible to measure the width of each pixel circuit in the first direction X1 or the second direction X2, using each pixel circuit connected to one pixel as the period, and then divide the total width D0 of each pixel circuit by the number of subpixels included in the pixel.

[0066] As one option, referring to the pixel circuit shown in Figure 7, the pixel circuit described in the embodiment of this application may be a 7T1C structure, that is, including seven transistors and one capacitor. Figure 9 is a schematic diagram of the structure of a 7T1C pixel circuit, and Figure 10 is a layout diagram of the configuration of a 7T1C pixel circuit.

[0067] Referring here to the pixel circuits shown in Figures 9 and 10, the 7T1C pixel circuit 10 includes a drive transistor T1, a data write transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a memory capacity C1. The pixel circuit can be connected to a gate signal terminal Gate, a data signal terminal Data, reset signal terminals RST1, RST2, a light emission control signal terminal EM, a power terminal VDD, initial power terminals Vinit1, Vinit2, and a light-emitting element, the light-emitting element may also be connected to a power terminal VSS. The pixel circuit can be used to drive a connected light-emitting element to emit light in response to signals supplied from each connected signal terminal.

[0068] Furthermore, transistors can be classified into N-type transistors and P-type transistors depending on their characteristics. In the embodiments of this application, a P-type transistor will be used as an example for explanation. Based on the description and teaching of the embodiments in this application, a person skilled in the art can easily conceive, without any creative work, that at least some of the transistors in the pixel circuit structure in the embodiments of this application may be N-type transistors, that is, embodiments that employ N-type transistors or embodiments that combine N-type and P-type transistors, and these embodiments are also within the scope of protection of the embodiments of this application.

[0069] To further reflect the existence of multiple additional rows of pixel circuits after the pixel circuitry has been compressed, Figure 11 shows a schematic diagram of the structure of the first display area A1. Figure 12 is a schematic diagram of the substructure of Figure 4 (including only the pixel circuitry), and Figure 13 is a schematic diagram of the substructure of Figure 4 (including only the light-emitting element).

[0070] Referring to Figures 11 to 13, the width of the pixel circuit is smaller than the width of the light-emitting element. Thus, the second and ninth pixel circuits from left to right do not connect to the first light-emitting element 30 and belong to additional columns of the pixel circuit, which may be second pixel circuits 20 for connecting the second light-emitting element 40 in the second display area A2. Furthermore, each first light-emitting element 30 may include four types of anodes RG1BG2 and a switching unit B2 for connecting to the first pixel circuit 10. The switching unit B1 of the first pixel circuit 10 and the switching unit B2 of the first light-emitting element 30 are connected by a source-drain metal layer SD2. Alternatively, if the first pixel circuit 10 and the first light-emitting element 30 are connected, it is not necessary to provide an SD2 circuit for connection.

[0071] Furthermore, both at least one second pixel circuit 20 and at least one second light-emitting element 40 may have switching units, and if at least one second pixel circuit 20 is connected to at least one second light-emitting element 40 by a conductive wire L1, in practice, the conductive wire L1 may be connected to the switching unit of one second pixel circuit 20 and the switching unit of at least one second light-emitting element 40, respectively.

[0072] This allows the axis of the switching section of each second pixel circuit 20, arranged in the same row, to be parallel to the axis of the switching section of any of the second light-emitting elements 40, in order to ensure sufficient space for the conductive wire L1 to pass through, and the axis can extend along the second direction X2. In other words, in the same row in the row direction, the switching section of the second pixel circuit 20 and the switching section of the second light-emitting element 40 are located on the same straight line. Similarly, referring to Figures 11 to 13 above, in the same row, the switching section B1 of the first pixel circuit 10 and the switching section B2 of the first light-emitting element 30 may be located on the same straight line so that the wiring is aligned.

[0073] As one option, Figure 14 is a schematic diagram of yet another display panel structure according to an embodiment of the present application. As shown in Figure 14, the first display area A1 may include a first sub-display area A11 and a second sub-display area A12 arranged sequentially along a first direction X1. The first sub-display area A11 may include two symmetrical target sub-display areas A110, that is, the two target sub-display areas A110 have the same layout. The second display area A2 may include two third sub-display areas A21 arranged symmetrically along a second direction X2, that is, the two third sub-display areas A21 have the same layout. Here, one target sub-display area A110, the second display area A2, and the other target sub-display area A110 may be arranged sequentially along a second direction X2.

[0074] Based on the display panel shown in Figure 14, the left and right halves of the display panel have the same layout. Therefore, in the following embodiment, only the structure of the left half of the display panel is shown, namely one target sub-display area A110 and an adjacent third sub-display area A21 located in the left half. The right half is similar and is omitted from the description.

[0075] Furthermore, additional rows of the pixel circuits described in the embodiments of this application, i.e., a plurality of second pixel circuits 20, can be distributed and arranged in the first display area A1, and the arrangement positions can be flexibly adjusted as needed, as long as they ensure efficient connection with the second light-emitting element 40 and drive the second light-emitting element 40 to emit light reliably. For example, in the embodiments of this application, the arrangement positions of the second pixel circuits 20 will be schematically described below, taking as an example that a plurality of second pixel circuits 20 are distributed in the column direction, row direction and diagonal direction.

[0076] In one selectable embodiment, the second pixel circuit 20 extends along the column direction, and Figure 15 is a schematic diagram of yet another display panel structure according to an embodiment of the present application. Referring to Figures 14 and 15, the plurality of first pixel circuits 10 may include a plurality of columns of first pixel circuits 10 extending along a first direction X1, and the plurality of second pixel circuits 20 may include a plurality of columns of second pixel circuits 20 extending along the first direction X1.

[0077] Here, the multiple rows of the second pixel circuit 20 may be spaced apart from the multiple rows of the first pixel circuit 10. For example, there may be one row of the second pixel circuit 20 for every adjacent multiple rows of the first pixel circuit 10. In other words, adjacent multiple rows of the first pixel circuit 10 can be placed between two adjacent rows of the second pixel circuit 20.

[0078] One option is to place a first pixel circuit 10 with the same number of columns between any two adjacent columns of second pixel circuits 20, thereby ensuring uniformity of placement. For example, an adjacent eight-column first pixel circuit 10 can be placed between any two adjacent columns of second pixel circuits 20, or first pixel circuits 10 with different numbers of columns can be placed between any two adjacent columns of second pixel circuits 20.

[0079] For example, referring to the display panel shown in Figure 16, with the left boundary line between the third sub-display area A21 and the target sub-display area A110 as the starting position, the second, twelfth, and twentieth columns of pixel circuits to the left may all be the second pixel circuits 20. Note that the additional columns of the second pixel circuits 20 below the second display area A2 can be used as dummy columns and are not connected to the light-emitting elements.

[0080] In another optional embodiment, the second pixel circuit 20 does not extend along the column direction, and Figure 17 is a schematic diagram of yet another display panel structure according to an embodiment of the present application. As shown in Figure 17, the plurality of first pixel circuits 10 may include multiple rows of first pixel circuits 10 extending along a second direction X2, and the plurality of second pixel circuits 20 may include multiple rows of second pixel circuits 20 extending along the second direction X2.

[0081] As an option, the first direction X1 may intersect with the second direction X2. For example, if the first direction X1 and the second direction X2 are not perpendicular, the multiple second pixel circuits 20 can be arranged along the diagonal direction. If the first direction X1 and the second direction X2 are perpendicular, the multiple second pixel circuits 20 can be arranged along the row direction.

[0082] Here, the multiple rows of second pixel circuits 20 are spaced apart between the multiple rows of first pixel circuits 10. For example, the multiple second pixel circuits 20 shown in Figure 17 extend along the row direction, meaning that there is one row of second pixel circuits 20 for every adjacent multiple rows of first pixel circuits 10. In other words, multiple adjacent rows of first pixel circuits 10 can be placed between two adjacent rows of second pixel circuits 20. In all the following embodiments, the example will be that the multiple second pixel circuits 20 are arranged sequentially along the column direction.

[0083] Furthermore, an additional row of pixel circuits, i.e., a second pixel circuit 20, is connected to a second light-emitting element 40 by a conductive wire L1, and the number of layers of conductive wire L1 can be flexibly adjusted according to the radius of the light-transmitting hole. For example, Figure 18 is a schematic diagram of yet another display panel according to an embodiment of the present application. As shown in Figure 18, the display panel may include a conductive wire L11 (i.e., ITO1), a second conductive wire L12 (i.e., ITO2), and a third conductive wire L13 (i.e., ITO3).

[0084] Each third sub-display area A21 may contain k groups of light-emitting elements. Each group of light-emitting elements may contain multiple adjacent rows of second light-emitting elements 40, and the first to kth light-emitting elements may be arranged sequentially along a direction closer to the other third sub-display area. Correspondingly, each target sub-display area A110 contains k pixel circuit groups that correspond one-to-one with the k groups of light-emitting elements Z0. Each pixel circuit group may contain multiple adjacent rows of second pixel circuits 20, and the first to kth pixel circuit groups may be arranged sequentially along a direction away from the adjacent third sub-display area.

[0085] Here, k may be an integer greater than 0. For example, in the embodiments of this application, we will explain using the example where k is 4. As one option, each of the first to third light-emitting element groups Z01 to Z03 may include a second light-emitting element 40 with 12 rows. The fourth light-emitting element group Z04 may include a second light-emitting element 40 with 8 rows. Correspondingly, each of the first to third pixel circuit groups Z11 to Z13 may include a second pixel circuit 20 with 12 rows. The fourth pixel circuit group Z14 may include a second pixel circuit 20 with 8 rows.

[0086] In other words, in the display panel shown in Figure 18, in the third sub-display area A21, the second light-emitting elements 40 in the 1st row to the second light-emitting elements 40 in the 13th row (i.e., R1 to R13) belong to the first light-emitting element group Z01, the second light-emitting elements 40 in the 14th row to the second light-emitting elements 40 in the 26th row (i.e., R14 to P26) belong to the second light-emitting element group Z02, the second light-emitting elements 40 in the 27th row to the second light-emitting elements 40 in the 39th row (i.e., P27 to R39) belong to the third light-emitting element group Z03, and the second light-emitting elements 40 in the 40th row to the second light-emitting elements 40 in the 48th row (i.e., R40 to R48) belong to the fourth light-emitting element group Z04.

[0087] Correspondingly, in the target sub-display area A110, the second pixel circuits 20 in the 1st row to the second pixel circuits 20 in the 13th row (i.e., P1 to P13) belong to the first pixel circuit group Z11, the second pixel circuits 20 in the 14th row to the second pixel circuits 20 in the 26th row (i.e., P14 to P26) belong to the second pixel circuit group Z12, the second pixel circuits 20 in the 27th row to the second pixel circuits 20 in the 39th row (i.e., P27 to P39) belong to the third pixel circuit group Z13, and the second pixel circuits 20 in the 40th row to the second pixel circuits 20 in the 48th row (i.e., P40 to P48) belong to the fourth pixel circuit group Z14. Figure 18 does not show only the first pixel circuit 10 and the first light-emitting element 30.

[0088] As one option, in the embodiments of this application, each second light-emitting element 40 in each light-emitting element group is connected to each second pixel circuit 20 in a corresponding pixel circuit group by a first conductive wire L11, a second conductive wire L12 and / or a third conductive wire L13.

[0089] For example, as shown in Figure 19, each second light-emitting element 40 in the first light-emitting element group Z01 is connected to each second pixel circuit 20 in the first pixel circuit group Z11 by a first conductive wire L11 (in Figure 19, the first conductive wire L11 is shown as ITO1).

[0090] As shown in Figure 20, each second light-emitting element 40 in the second light-emitting element group Z02 is connected to each second pixel circuit 20 in the second pixel circuit group Z12 by a second conductive wire L12 (in Figure 20, the second conductive wire L12 is indicated as ITO2).

[0091] As shown in Figure 21, each second light-emitting element 40 in the third light-emitting element group Z03 is connected to each second pixel circuit 20 in the third pixel circuit group Z13 by a third conductive wire L13 (in Figure 21, the third conductive wire L13 is indicated as ITO3).

[0092] As shown in Figure 22, each second light-emitting element 40 in the fourth light-emitting element group Z04 is connected to each second pixel circuit 20 in the fourth pixel circuit group Z14 by a first conductive wire L11 (i.e., ITO1), a second conductive wire L12 (i.e., ITO2), and a third conductive wire L13 (i.e., ITO3).

[0093] For example, referring to Figure 22, the fourth sub-light-emitting group Z04 may include two first sub-light-emitting groups Z041, two second sub-light-emitting groups Z042, ​​and two third sub-light-emitting groups Z043, which are symmetrically arranged along the axis xx of the third sub-display area A21. Here, the number of rows of second light-emitting elements 40 included in each sub-light-emitting group may be the same or different. Furthermore, the first sub-light-emitting group Z041, the second sub-light-emitting group Z042, ​​and the third sub-light-emitting group Z043, which are arranged on the same side, are sequentially arranged along a direction away from the axis xx, and the axis xx extends along a second direction X2. The fourth pixel circuit group Z14 may include two first sub-pixel circuit groups Z141 that correspond one-to-one with two first sub-light-emitting groups Z041, two second sub-pixel circuit groups Z142 that correspond one-to-one with two second sub-light-emitting groups Z042, ​​and two third sub-pixel circuit groups Z143 that correspond one-to-one with two third sub-light-emitting groups Z043. The arrangement of the first sub-pixel circuit group Z141, the second sub-pixel circuit group Z142, and the third sub-pixel circuit group Z143, which are arranged on the same side, is the same as the arrangement of the sub-light-emitting groups.

[0094] Here, each second light-emitting element 40 in each first sub-light-emitting element group Z041 is connected to each second pixel circuit 20 in the corresponding first sub-pixel circuit group Z141 by a first conductive wire L11 (i.e., ITO1). Each second light-emitting element 40 in each second sub-light-emitting element group Z042 is connected to each second light-emitting element 40 in the corresponding second sub-pixel circuit group Z142 by a second conductive wire L12 (i.e., ITO2). Each second light-emitting element 40 in each third sub-light-emitting element group Z043 is connected to each second pixel circuit 20 in the corresponding third sub-pixel circuit group Z143 by a third conductive wire L13 (i.e., ITO3).

[0095] Figure 23 is a schematic diagram of the structure of a conductive wire according to an embodiment of this application. Figure 24 is a layout diagram of the configuration shown in Figures 19 to 21. Referring further to Figures 19 to 21, the first conductive wire L11 connected to each second light-emitting element 40 in the first light-emitting element group Z01, the second conductive wire L12 connected to each second light-emitting element 40 in the second light-emitting element group Z02, and the third conductive wire L13 connected to each second light-emitting element 40 in the third light-emitting element group Z03 may all include a first conductive wire segment La, a second conductive wire segment Lb, and a third conductive wire segment Lc.

[0096] Here, one end of the first conductive wire segment La is connected to the corresponding second light-emitting element 40, and the other end of the first conductive wire segment La is connected to one end of the second conductive wire segment Lb. The other end of the second conductive wire segment Lb is connected to one end of the third conductive wire segment Lc. The other end of the third conductive wire segment Lc is connected to the corresponding second pixel circuit 20. The first conductive wire segment La and the third conductive wire segment Lc extend along the first direction X1, and the second conductive wire segment Lb extends along the second direction X2, and the orthographic projection of the second conductive wire segment Lb onto the base substrate 01 at least partially overlaps with the orthographic projection of the second light-emitting element 40 onto the base substrate 01 (see Figure 24). That is, the first conductive wire L11, the second conductive wire L12, and the third conductive wire L13 can all be drawn out from the connected second light-emitting element 40 and extend laterally from the row direction to the second pixel circuit 20 in order to connect to the second pixel circuit 20.

[0097] As one option, to prevent interference between signals, the second conductive wire segment Lb included in the first conductive wire L11 can at least partially overlap with the second conductive wire segment Lb included in the third conductive wire L13. The second conductive wire segment Lb included in the first conductive wire L11 does not have to overlap with the second conductive wire segment Lb included in the second conductive wire L12, and the second conductive wire segment Lb included in the third conductive wire L13 does not have to overlap with the second conductive wire segment Lb included in the second conductive wire L12. The overlapping portion can be switched via vias.

[0098] Figure 24 schematically shows only the layout of the display panel for the first conductive wire L11, i.e., ITO1 wiring, connected to each second light-emitting element 40 in the first light-emitting element group Z01. The layout of the display panel for the second conductive wire L12 (i.e., ITO2 wiring) connected to each second light-emitting element 40 in the second light-emitting element group Z02 and the third conductive wire L13 (i.e., ITO3 wiring) connected to each second light-emitting element 40 in the third light-emitting element group Z03 can be directly referred to in the schematic diagram of the display panel shown in Figure 24, and will not be explained here.

[0099] As one option, Figure 25 is a schematic diagram of the structure of a conductive wire according to an embodiment of this application. As shown in Figure 25, the first conductive wire L11 connected to each second light-emitting element 40 in each first sub-light-emitting element group Z041, the second conductive wire L12 connected to each second light-emitting element 40 in each second sub-light-emitting element group Z042, ​​and the third conductive wire L13 connected to each second light-emitting element 40 in each third sub-light-emitting element group Z043 may include a fourth conductive wire segment Ld, a fifth conductive wire segment Le, a sixth conductive wire segment Lf, and a seventh conductive wire segment Lg.

[0100] Here, one end of the fourth conductive wire segment Ld is connected to the corresponding second light-emitting element 40, and the other end of the fourth conductive wire segment Ld is connected to one end of the fifth conductive wire segment Le. The other end of the fifth conductive wire segment Le is connected to one end of the sixth conductive wire segment Lf. The other end of the sixth conductive wire segment Lf is connected to one end of the seventh conductive wire segment Lg. The other end of the seventh conductive wire segment Lg is connected to the corresponding second pixel circuit 20. The fifth conductive wire segment Le and the seventh conductive wire segment Lg extend along the first direction X1, and the sixth conductive wire segment Lf extends along the second direction X2. The fourth conductive wire segment Ld is positioned between the row in which the connected second light-emitting element 40 is located and the adjacent row.

[0101] Figure 26 is a schematic diagram of yet another display panel according to an embodiment of this application, and Figure 27 is a schematic diagram of yet another display panel according to an embodiment of this application. Figure 28 is a simplified schematic diagram of the display panel shown in Figure 27. Referring to Figures 26 to 28, the fifth conductive wire segment Le included in the first conductive wire L11 (i.e., ITO1) is located within the region where the second to fourth light-emitting element groups Z02 to Z04 are located. The fifth conductive wire segment Le included in the second conductive wire L12 (i.e., ITO2) is located within the region where the third and fourth light-emitting element groups Z03 and Z04 are located. The fifth conductive wire segment Le included in the third conductive wire L13 (i.e., ITO3) is located within the region where the fourth light-emitting element group Z04 is located. The sixth conductive wire segment Lf on the side away from the second sub-display area A12 along the axis is located on the side of the second display area A2 away from the second sub-display area A12, and the sixth conductive wire segment Lf on the side closer to the second sub-display area A12 along the axis is located within the second display area A2 that is close to the second sub-display area A12.

[0102] In other words, the fifth conductive wire segment Le included in the first conductive wire L11 is drawn out from the connected second light-emitting element 40 in order to connect to the second pixel circuit 20, and extends along the column direction from the region where the second light-emitting elements 40 in columns R14 to R48 are located (i.e., the region where Z02 to Z04 are located) to the side of the third sub-display area A21 that is closer to the non-display area or the side of the third sub-display area A21 that is closer to the second sub-display area A12, and then can extend laterally along the row direction to the region where the corresponding second pixel circuit 20 is located. The fifth conductive wire segment Le, included in the second conductive wire L12, is drawn out from the connected second light-emitting element 40 to connect to the second pixel circuit 20, and extends along the column direction from the region where the second light-emitting elements 40 in columns P27 to R48 are located (i.e., the region where Z03 and Z04 are located) to the side of the third sub-display region A21 closer to the non-display region or the side of the third sub-display region A21 closer to the second sub-display region A12, and then can extend laterally along the row direction to the region where the corresponding second pixel circuit 20 is located. The fifth conductive wire segment Le, included in the third conductive wire L13, is drawn out from the connected second light-emitting element 40 to connect to the second pixel circuit 20, and extends along the column direction from the region where the second light-emitting elements 40 in columns R40 to R48 are located (i.e., the region where Z04 is located) to the side of the third sub-display area A21 closer to the non-display area or the side of the third sub-display area A21 closer to the second sub-display area A12, and then can extend laterally along the row direction to the region where the corresponding second pixel circuit 20 is located. Furthermore, the sixth conductive wire segment Lf included in each conductive wire located on the same side and extending along the row direction may or may not partially overlap.

[0103] Referring to Figures 26 and 27, the display panel further includes at least one row of dummy second pixel circuits 20, which are located in the target sub-display area A110. This row of dummy second pixel circuits 20 is also called a transition row, and this row of dummy second pixel circuits 20 is not connected to any light-emitting elements.

[0104] By providing a transition row, the gap between the second light-emitting element 40 in the first row and the second pixel circuit 20 connected to it is smaller than the gap between the second light-emitting element 40 in the last row and the second pixel circuit 20 connected to it. This avoids the problem of a large difference in illumination between the second light-emitting element 40 in the first row and the second light-emitting element 40 in the last row, further ensuring a better display effect.

[0105] Comparing Figure 26 and Figure 27, in the first light-emitting element group 01, the first conductive wire L11 (i.e., ITO1) connected to each second light-emitting element 40 arranged in adjacent rows may be positioned on the same upward side, or symmetrically on different sides. In the second light-emitting element group 01, the second conductive wire L12 (i.e., ITO2) connected to each second light-emitting element 40 arranged in adjacent rows may be positioned on the same upward side, or symmetrically on different sides. In the third light-emitting element group 01, the third conductive wire L13 (i.e., ITO1) connected to each second light-emitting element 40 arranged in adjacent rows may be positioned on the same upward side, or symmetrically on different sides. Of course, all of the above signal lines may also be positioned on the same downward side, and no further explanation is provided.

[0106] Figure 29 is a cross-sectional view of the display panel. Here, ITO1 represents the first conductive wire L11, ITO2 represents the second conductive wire L12, and ITO3 represents the third conductive wire L13. Anode refers to the anode of the light-emitting element, PLN refers to a flat layer, and the display panel shown in Figure 29 includes five flat layers PLN1 to PLN5, SD1 refers to the first source-drain metal layer, and SD2 refers to the second source-drain metal layer.

[0107] As one option, the display panel may include multiple metal layers, such as a first gate metal layer GATE1, a second gate metal layer GATE2, a first source-drain metal layer SD1, and a second source-drain metal layer SD2. The data cable DATA connected to each second pixel circuit 20 can be located on the same layer as any of the metal layers.

[0108] For example, referring to the display panel shown in Figure 30, along the direction away from the adjacent third sub-display area A21, in the second pixel circuits 20 from the 1st to the ith column within each target sub-display area A110, the data cables DATA connected to the second pixel circuits 20 located in odd-numbered columns may be located on the same layer as the first gate metal layer GATE1. The data cables DATA connected to the second pixel circuits 20 located in even-numbered columns may be located on the same layer as the second gate metal layer GATE2. The data cables DATA connected to the second pixel circuits 20 from the ith to the nth column may be located on the same layer as the first source-drain metal layer SD1. Here, i is an integer greater than 1 and less than n, and n is equal to the total number of columns in each target sub-display area A110. That is, the data cables DATA connected to the second pixel circuits 20 from the 1st to the ith column may be arranged alternately on the same layer as GATE1 and GATE2. The data cable DATA connected to the second pixel circuit 20 from column i to column n may be located on the same layer as SD1.

[0109] As one option, assuming that there are 48 columns of second light-emitting elements 40 in the third sub-display area A21, i may be 24, meaning there is one set for every 24 columns of second light-emitting elements 40. Correspondingly, that is, in columns 1 to 24, data cables DATA connected to odd-numbered columns may be located in the same layer as the first gate metal layer GATE1, data cables DATA connected to even-numbered columns in columns 1 to 24 may be located in the same layer as the second gate metal layer GATE2, and data cables DATA connected to columns 24 to 48 are all located in the same layer as the first source-drain metal layer SD1.

[0110] As one option, Figures 31 and 32 are layout diagrams of a configuration in which data cables DATA connected to the odd-numbered second pixel circuits 20 are arranged on the same layer as the first gate metal layer GATE1 at different locations. Figures 33 and 34 are layout diagrams of a configuration in which data cables DATA connected to the even-numbered second pixel circuits 20 are arranged on the same layer as the second gate metal layer GATE2 at different locations. Figures 35 and 36 are layout diagrams of a configuration in which data cables DATA connected to the i-th to n-th second pixel circuits 20 are arranged on the same layer as SD1 at different locations. Figures 37 and 38 are layout diagrams of the entire display panel arranged on the same layer as the first gate metal layer GATE1, the second gate metal layer GATE2, and SD1 at different locations. Figures 39 and 40 are layout diagrams including conductive wire L1 and data cable DATA.

[0111] Figure 41 is a schematic diagram of the data cable structure. Referring to the above data cable diagram, each data cable DATA connected to each second pixel circuit 20 may include a first data cable segment D11, a second data cable segment D12, and a third data cable segment D13.

[0112] Here, one end of the first data cable segment D11 may be connected to the corresponding metal layer, the other end to one end of the second data cable segment D12, the other end of the second data cable segment D12 may be connected to one end of the third data cable segment D13, and the other end of the third data cable segment D13 may be connected to the second pixel circuit 20.

[0113] Furthermore, the second data cable segment D12 extends along the first direction X1, and the second data cable segment D12 included in the data cable DATA located in the same layer as the first gate metal layer GATE1, the second data cable segment D12 included in the data cable DATA located in the same layer as the second gate metal layer GATE2, and the second data cable segment D12 included in the data cable DATA located in the same layer as the first source drain metal layer SD1 do not have to overlap each other. That is, each data cable DATA is switchable and pullable out from the metal layer at the boundary between the third sub-display area A21 and the second sub-display area A12, and in the third sub-display area A21 extends in the column direction from the display area to the non-display area, then extends in the row direction to the second pixel circuit 20 of the corresponding column, and is connected to the second pixel circuit 20.

[0114] Furthermore, referring to the display panel shown in Figure 42, in the second pixel circuit 20 of the same row, the data cable DATA connected to the second pixel circuit 20 located in the first sub-display area A11 may be different from the data cable DATA connected to the second pixel circuit 20 located in the second sub-display area A12. For example, the data cable DATA connected to the second pixel circuit 20 of one row is cut off at the boundary line between the first sub-display area A11 and the second sub-display area A12. In this way, the problem of mutual interference caused by signals supplied from the data cable can be avoided, and effective and reliable driving of the second light-emitting element 40 can be ensured.

[0115] Furthermore, referring to the display panel shown in Figure 43, the second source-drain metal layer SD2 covers the first gate metal layer GATE1, the second gate metal layer GATE2, and the first source-drain metal layer SD1. In this way, signal shielding can be achieved at the connection point between the drive transistor and the light-emitting element, thereby reducing signal crosstalk.

[0116] It can provide a certain shielding effect against the effects of parasitic capacitance on the conductive wire L1, ensuring good display effectiveness.

[0117] Based on the above, the embodiments of this application provide a display panel including a base substrate having a first display area and a second display area. Since the pixel circuit for driving the light-emitting elements in the second display area is arranged only in the first display area and not in the second display area, good light transmittance in the second display area is ensured. Correspondingly, the display effect of the display panel described in the embodiments of this application is good.

[0118] Figure 44 is a schematic diagram of the structure of a display device according to an embodiment of the present application. As shown in Figure 44, the display device may include an integrated circuit and a display panel 200 as shown in any of the above figures.

[0119] Here, the integrated circuit 100 is connected to the first pixel circuit and the second pixel circuit in the display panel 200 and is used to drive the first pixel circuit and the second pixel circuit to operate. For example, the drive circuit 100 is connected to each signal terminal connected to the pixel circuit and is used to supply a signal to each signal terminal.

[0120] Note that Figure 44 only shows the approximate location of the integrated circuit 100, and the integrated circuit 100 may be located to the right of the display panel 200, or it may be located on both the left and right sides of the display panel 200, or it may be located above and / or below the display panel 200.

[0121] As one option, the display device may be any product or component having a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet, a flexible display device, a television, or a display.

[0122] Those skilled in the art will see that, for the sake of explanatory convenience and brevity, the specific operating processes of the display board and display device described above can be understood by referring to the corresponding processes in the embodiments of the above method. Such explanations are omitted here.

[0123] The foregoing are merely selectable embodiments of this application and do not limit it. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. It has a first display area and a second display area, the first display area being a base substrate that at least partially surrounds the second display area, A plurality of first pixel circuits arranged in the first display area, a plurality of second pixel circuits arranged with intervals between the plurality of first pixel circuits, and a plurality of first light-emitting elements, A plurality of second light-emitting elements arranged in the second display area, A dummy second pixel circuit consisting of at least one row, Includes, The plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a first direction, The at least one row of dummy second pixel circuits is arranged in a target sub-display area close to the second display area, the at least one row of dummy second pixel circuits is arranged between two adjacent rows of first pixel circuits, the first display area includes a first sub-display area, and the first sub-display area includes two symmetrical target sub-display areas. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements, the orthographic projection of the at least one first pixel circuit onto the base substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element onto the base substrate, and at least one of the plurality of second pixel circuits is connected by conductive wires to at least one of the plurality of second light-emitting elements. Display panel.

2. The display panel according to claim 1, wherein the density of the plurality of second light-emitting elements is the same as the density of the plurality of first light-emitting elements.

3. The display panel according to claim 1, wherein the resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

4. Each of the first pixel circuits is connected to one of the first light-emitting elements. The orthographic projection of each of the first pixel circuits onto the base substrate at least partially overlaps with the orthographic projection of the connected first light-emitting element onto the base substrate. The display panel according to any one of claims 1 to 3.

5. The plurality of second pixel circuits include a plurality of rows of second pixel circuits extending along a first direction, The aforementioned multiple rows of second pixel circuits are arranged with gaps between the aforementioned multiple rows of first pixel circuits. The display panel according to any one of claims 1 to 3, wherein the same or different number of first pixel circuits are arranged between any two adjacent rows of the second pixel circuits.

6. The first display area includes a first sub-display area and a second sub-display area arranged sequentially along a first direction. One of the target sub-display areas, the second display area, and the other target sub-display area are arranged sequentially along the second direction. The display panel according to any one of claims 1 to 5.

7. The second display area includes two third sub-display areas arranged symmetrically along the second direction, and the display panel includes a first conductive wire, a second conductive wire, and a third conductive wire. Each of the third sub-display areas includes k groups of light-emitting elements, each of the light-emitting elements includes multiple adjacent rows of the second light-emitting elements, the first to the kth light-emitting elements are arranged sequentially along the direction toward the other third sub-display area, and k is an integer greater than 0. Each target sub-display area includes k pixel circuit groups corresponding one-to-one to the k light-emitting groups, each pixel circuit group includes multiple adjacent rows of second pixel circuits, the first to the kth pixel circuit groups are arranged sequentially along a direction away from adjacent third sub-display areas, and each second light-emitting element in each light-emitting group is connected to each second pixel circuit in a corresponding pixel circuit group by a first conductive wire, a second conductive wire, and / or a third conductive wire. The display panel according to claim 6.

8. The second light-emitting element in the first group of light-emitting elements is connected to the second pixel circuit in the first group of pixel circuits by the first conductive wire. The second light-emitting element in the second group of light-emitting elements is connected to the second pixel circuit in the second group of pixel circuits by the second conductive wire. The second light-emitting element in the third group of light-emitting elements is connected to the second pixel circuit in the third group of pixel circuits by the third conductive wire. The second light-emitting element in the fourth group of light-emitting elements is connected to the second pixel circuit in the fourth group of pixel circuits by the first conductive wire, the second conductive wire, and the third conductive wire. The display panel according to claim 7.

9. The first conductive wire connected to each of the second light-emitting elements in the first group of light-emitting elements, the second conductive wire connected to each of the second light-emitting elements in the second group of light-emitting elements, and the third conductive wire connected to each of the second light-emitting elements in the third group of light-emitting elements include a first conductive wire segment, a second conductive wire segment, and a third conductive wire segment. One end of the first conductive wire segment is connected to the corresponding second light-emitting element, and the other end of the first conductive wire segment is connected to one end of the second conductive wire segment. The other end of the second conductive wire segment is connected to one end of the third conductive wire segment. The other end of the third conductive wire segment is connected to the corresponding second pixel circuit. The first conductive wire segment and the third conductive wire segment extend along the first direction, the second conductive wire segment extends along the second direction, and the orthographic projection of the second conductive wire segment onto the base substrate at least partially overlaps with the orthographic projection of the second light-emitting element connected to the second conductive wire segment onto the base substrate. The display panel according to claim 8.

10. The display panel according to claim 9, wherein the second conductive wire segment included in the first conductive wire at least partially overlaps with the second conductive wire segment included in the third conductive wire, the second conductive wire segment included in the first conductive wire does not overlap with the second conductive wire segment included in the second conductive wire, and the second conductive wire segment included in the third conductive wire does not overlap with the second conductive wire segment included in the second conductive wire.

11. The fourth sub-light-emitting group includes two first sub-light-emitting groups, two second sub-light-emitting groups, and two third sub-light-emitting groups arranged symmetrically along the axis of the third sub-display area, each sub-light-emitting group including multiple adjacent rows of the second light-emitting elements, and the first, second, and third sub-light-emitting groups arranged on the same side are sequentially arranged along a direction away from the axis, the axis extending along the second direction, The fourth pixel circuit group includes two first sub-pixel circuit groups that correspond one-to-one with the two first sub-light-emitting groups, two second sub-pixel circuit groups that correspond one-to-one with the two second sub-light-emitting groups, and two third sub-pixel circuit groups that correspond one-to-one with the two third sub-light-emitting groups. Each second light-emitting element in each of the first sub-light-emitting element groups is connected by a first conductive wire to each second pixel circuit in the corresponding first sub-pixel circuit group; each second light-emitting element in each of the second sub-light-emitting element groups is connected by a second conductive wire to each second pixel circuit in the corresponding second sub-pixel circuit group; and each second light-emitting element in each of the third sub-light-emitting element groups is connected by a third conductive wire to each second pixel circuit in the corresponding third sub-pixel circuit group. The display panel according to claim 8.

12. The first conductive wire connected to each second light-emitting element in each of the first sub-light-emitting element groups, the second conductive wire connected to each second light-emitting element in each of the second sub-light-emitting element groups, and the third conductive wire connected to each second light-emitting element in each of the third sub-light-emitting element groups include a fourth conductive wire segment, a fifth conductive wire segment, a sixth conductive wire segment, and a seventh conductive wire segment. One end of the fourth conductive wire segment is connected to the corresponding second light-emitting element, and the other end of the fourth conductive wire segment is connected to one end of the fifth conductive wire segment. The other end of the fifth conductive wire segment is connected to one end of the sixth conductive wire segment. The other end of the sixth conductive wire segment is connected to one end of the seventh conductive wire segment. The other end of the seventh conductive wire segment is connected to the corresponding second pixel circuit. The fifth conductive wire segment and the seventh conductive wire segment extend along the first direction, the sixth conductive wire segment extends along the second direction, and the fourth conductive wire segment is positioned between the row in which the connected second light-emitting element is located and the adjacent row. The fifth conductive wire segment included in the first conductive wire is located within the region where the second to fourth light-emitting element groups are located, the fifth conductive wire segment included in the second conductive wire is located within the region where the third and fourth light-emitting element groups are located, the fifth conductive wire segment included in the third conductive wire is located within the region where the fourth light-emitting element group is located, the sixth conductive wire segment on the side away from the second sub-display area along the axis is located within the second display area away from the second sub-display area, and the sixth conductive wire segment on the side closer to the second sub-display area along the axis is located within the second display area close to the second sub-display area. The display panel according to claim 11.

13. It further contains multiple metal layers, The data cable connected to each of the second pixel circuits is arranged in the same layer as one of the metal layers. The plurality of metal layers include a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. The display panel according to any one of claims 7 to 12.

14. Along the direction away from the adjacent third sub-display area, in the second pixel circuits from the first to the ith column within each target sub-display area, data cables connected to the second pixel circuits located in odd-numbered columns are located in the same layer as the first gate metal layer, data cables connected to the second pixel circuits located in even-numbered columns are located in the same layer as the second gate metal layer, and data cables connected to the second pixel circuits from the ith to the nth column are located in the same layer as the first source-drain metal layer, where i is an integer greater than 1 and less than n, and n is equal to the total number of columns within each target sub-display area. The data cable connected to each of the second pixel circuits includes a first data cable segment, a second data cable segment, and a third data cable segment. One end of the first data cable segment is connected to the corresponding metal layer, the other end is connected to one end of the second data cable segment, the other end of the second data cable segment is connected to one end of the third data cable segment, and the other end of the third data cable segment is connected to the second pixel circuit. The second data cable segment extends along the first direction and is included in a data cable arranged in the same layer as the first gate metal layer, the second data cable segment is included in a data cable arranged in the same layer as the second gate metal layer, and the second data cable segment is included in a data cable arranged in the same layer as the first source drain metal layer, and these do not overlap each other. The display panel according to claim 13.

15. The display panel according to any one of claims 7 to 14, wherein in the second pixel circuit of the same row, the data cable connected to the second pixel circuit located in the first sub-display area is different from the data cable connected to the second pixel circuit located in the second sub-display area.

16. The display panel according to any one of claims 1 to 15, wherein in the plurality of first pixel circuits and the plurality of second pixel circuits, the width of any one pixel circuit is smaller than the width of any one of the first light-emitting elements.

17. The display panel according to any one of claims 1 to 16, wherein the conductive wire is a transparent conductive wire.

18. It includes an integrated circuit and a display panel, The display panel has a first display area and a second display area, the first display area includes a base substrate that at least partially surrounds the second display area, a plurality of first pixel circuits arranged in the first display area, a plurality of second pixel circuits spaced apart between the plurality of first pixel circuits, and a plurality of first light-emitting elements, a plurality of second light-emitting elements arranged in the second display area, and at least one row of dummy second pixel circuits, the plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a first direction, the at least one row of dummy second pixel circuits is arranged in a target sub-display area close to the second display area, the at least one row of dummy second pixel circuits is arranged between two adjacent rows of first pixel circuits, the first display area includes a first sub-display area, and the first sub-display area includes two symmetrical target sub-display areas. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements, the orthographic projection of the at least one first pixel circuit onto the base substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element onto the base substrate, and at least one of the plurality of second pixel circuits is connected by conductive wires to at least one of the plurality of second light-emitting elements. The integrated circuit is connected to the first pixel circuit and the second pixel circuit in the display panel and is used to drive the first pixel circuit and the second pixel circuit to operate. A display device characterized by the following features.

19. The display device according to claim 18, further comprising a photosensitive sensor, wherein the photosensitive sensor is located within a second display area of ​​the display panel.

20. The display device according to claim 19, wherein the second display area is rectangular, and the area of ​​the orthographic projection of the photosensitive sensor onto the base substrate is less than or equal to the area of ​​the inscribed circle of the second display area.

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