Receiver

Abstract

To provide an expected receiver capable of returning to a normal data signal in an early stage after an error occurs.SOLUTION: This receiver includes a special code detection circuit 2 for outputting a first correction value DET-COM, a byte alignment circuit 3 for executing byte alignment according to the first correction value DET-COM outputted from the special code detection circuit 2, and a decoder 4. The decoder 4 includes a data string generation circuit 41 for generating a plurality of data strings from an output signal of the byte alignment circuit 3, and a correction value generation circuit 43 for receiving a plurality of error signals obtained by performing error determination of the plurality of data strings outputted from the data string generation circuit 41, and generating a second correction value θK including information of data strings with no occurrence of errors. The byte alignment can be executed according to the second correction value θK even before receiving a special code.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a receiving apparatus.

Background Art

[0002] In an environment with a lot of external noise, such as inside an automobile, a data communication technology capable of improving electromagnetic compatibility (EMC) is required. In particular, with the sophistication of devices, the data communication volume is increasing, and there is a demand for a receiving apparatus that can receive data signals such as image data signals at high speed in an EMC environment.

[0003] For high-speed data transmission, serial data communication is used. Conventionally, for example, a serial data communication technology such as that disclosed in Patent Document 1 is known, and data reception using a control code is performed. Generally, a control code (K code) is used as a code indicating data different from the code (D code) related to the image data itself.

[0004] The symbol mapping method is a type of transmission coding method, and is a coding method in which an m-bit data character is mapped to n (m < n) bits to obtain a coded symbol. By taking advantage of the redundancy obtained by this expansion mapping of m bits to n bits, a control code that is not a code representing data can be generated. Among control codes, a delimiter symbol representing the head of serial data, for example, a comma character in the 8b / 10b method, is called a special code. That is, in the 8b10b coding method, which is one of the symbol mapping methods, comma characters (K28.1, K28.5, K28.7) are known as special codes. In this method, an image data receiving apparatus periodically (for example, at a rate of about one pixel per line included in one image) receives a special code. When the special code is received, the image data receiving apparatus performs byte alignment (byte boundary alignment) on the received image data signal. Patent Document 2 discloses a method of performing byte alignment.

Prior Art Documents

[0005] [Patent Document 1] International Publication No. 2012 / 049815 [Patent Document 2] U.S. Patent No. 8867683 [Overview of the project] [Problems that the invention aims to solve]

[0006] Conventional home image data receivers may produce distorted images when used in environments with significant external noise. If a single data point in a serial data signal is lost due to noise, an error occurs where the timing of subsequent data blocks (e.g., 10 bits) deviates from the normal value, resulting in image distortion. A lower frequency of special codes is preferable, as it increases the amount of image data that can be received per unit time. However, when byte alignment is performed in conjunction with the reception of special codes, the time required to recover from an error to a normal data signal (image) becomes longer. Therefore, there is a need for receivers that can recover to a normal data signal more quickly. [Means for solving the problem]

[0007] The first receiving device includes: a special code detection circuit that receives a data signal including a special code encoded using a symbol mapping method and outputs a first correction value corresponding to the position of the special code included in the data signal; a byte alignment circuit that receives the first correction value and the second correction value as inputs and performs byte alignment of the data signal according to the first correction value and the second correction value; a data sequence generation circuit that generates a plurality of data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit; a decoder that decodes and outputs a specific data sequence from the plurality of data sequences output from the data sequence generation circuit and performs error determination on the specific data sequence; a plurality of error detectors that perform error determination on each of the remaining data sequences other than the specific data sequence from the plurality of data sequences output from the data sequence generation circuit; and a correction value generation circuit that receives a plurality of error signals indicating the results of the error determination output from the decoder and the plurality of error detectors and generates a second correction value including information on data sequences without errors according to the plurality of input error signals.

[0008] In this receiving device, the first correction value corresponds to the position of a special code indicating normal timing. When the first correction value is received, the byte alignment circuit performs byte alignment. The second correction value contains information about data sequences that are error-free, based on multiple error signals. If an error occurs before the reception of the special code due to external noise, etc., the byte alignment of the data signal is performed according to the second correction value generated by the correction value generation circuit. This allows for an early return to a normal data signal, even before the reception of the special code. If the data signal is an image data signal, image distortion can be quickly resolved. This receiving device controls the byte alignment circuit by feeding back the second correction value generated by the correction value generation circuit to the preceding byte alignment circuit. Because it does not require many circuits, it can be implemented with a relatively small circuit size.

[0009] The second receiving device includes: a special code detection circuit that receives a data signal including a special code encoded using a symbol mapping method and outputs a first correction value corresponding to the position of the special code included in the data signal; a byte alignment circuit that performs byte alignment of the data signal according to the first correction value output from the special code detection circuit; a data sequence generation circuit that generates a plurality of data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit; a plurality of decoders that decode and determine the error of each of the plurality of data sequences output from the data sequence generation circuit; a correction value generation circuit that receives a plurality of error signals indicating the result of the error determination output from the plurality of decoders and generates a second correction value including information on data sequences without errors according to the plurality of error signals that were input; and a selection circuit that selects and outputs a data sequence corresponding to the second correction value from among the plurality of data sequences output from the plurality of decoders.

[0010] In this receiving device, the first correction value corresponds to the position of a special code indicating normal timing. When the first correction value is received, the byte alignment circuit performs byte alignment. The second correction value contains information about data sequences that are free of errors, based on multiple error signals. If an error occurs before the reception of the special code due to external noise, etc., the selection circuit selects and outputs a data sequence without byte alignment misalignment according to the second correction value generated by the correction value generation circuit. This allows for an early return to a normal data signal, even before the reception of the special code. If the data signal is an image data signal, image distortion can be quickly resolved.

[0011] The second receiving device is equipped with multiple decoders. The normal data signal is the data signal output by dividing the data sequence at the positions of normal blocks, while the error data signal is the data signal output by dividing the data sequence at the positions of blocks where errors occur. Both the normal data signal and the error data signal group are ready to output from the multiple decoders. This receiving device performs byte alignment of the data signal by selecting the normal data signal using a second correction value. Since this receiving device does not require feedback of the second correction value to the byte alignment circuit, the circuit structure is simplified, resulting in superior maintainability and robustness.

[0012] Furthermore, in the second receiving device, the byte alignment circuit outputs a notification signal indicating the completion of byte alignment. When this notification signal is input to the correction value generation circuit, the selection circuit selects and outputs a data sequence from the decoder with the default settings within the decoder. Even if there is no change in the second correction value, the selection circuit can output a correctly delimited data sequence by receiving the first correction value from the correction value generation circuit.

[0013] This disclosure The receiving device includes a special code detection circuit that receives a data signal encoded using a symbol mapping method and contains special codes, and outputs a first correction value corresponding to the position of the special codes contained in the data signal; a data sequence generation circuit that generates multiple data sequences from the data signal, each having a different delimiter position in the data sequence; a plurality of decoders that decode each of the plurality of data sequences output from the data sequence generation circuit and determine each of them to be error-free; a correction value generation circuit that receives a plurality of error signals indicating the results of the error determination output from the plurality of decoders, and generates a second correction value containing information on data sequences that do not have errors according to the plurality of error signals that were input; and a data sequence that selects and outputs a data sequence corresponding to the first correction value and the second correction value from among the plurality of data sequences output from the plurality of decoders. Bite alignment circuit It is equipped with the following.

[0014] In this receiving device, the first correction value corresponds to the position of a special code indicating normal timing. The second correction value contains information about data sequences that are error-free, based on multiple error signals. The byte alignment circuit selects and outputs data sequences corresponding to the first and second correction values ​​from among multiple data sequences output from multiple decoders. If an error occurs before the reception of a special code due to external noise, etc., the byte alignment circuit selects and outputs data sequences without byte alignment misalignment according to the second correction value generated by the correction value generation circuit. This allows for early recovery to a normal data signal, even before the reception of a special code. If the data signal is an image data signal, image distortion can be quickly resolved. This receiving device can achieve early recovery from byte alignment misalignment with a simple configuration.

[0015] The receiving device described above includes a deserializer that receives a serial data signal transmitted from the transmitting device, converts it into a parallel data signal, and inputs the data signal to the special code detection circuit. The deserializer can convert a serial data signal into a parallel data signal. [Effects of the Invention]

[0016] According to the receiving device of the present invention, even if an error occurs in the data signal, it is possible to quickly restore it to a normal data signal. [Brief explanation of the drawing]

[0017] [Figure 1] Figure 1 shows the circuit configuration of a transmitting and receiving system equipped with a first receiving device. [Figure 2] Figure 2 shows the circuit configuration of the special code detection circuit. [Figure 3] Figure 3 shows the data sequence generation circuit and the special code detection circuit. [Figure 4] Figure 4 shows an example of a data sequence generation circuit. [Figure 5] FIG. 5 is a diagram showing a byte alignment circuit of the first type. [Figure 6] FIG. 6 is a diagram showing a circuit configuration of a decoder with a correction value generation function. [Figure 7] FIG. 7 is a flowchart for explaining a phase correction procedure of an image data signal in the first receiving device. [Figure 8] FIG. 8 is a diagram for explaining the timing of byte alignment. [Figure 9] FIG. 9 is a diagram for explaining the states of a plurality of error signals. [Figure 10] FIG. 10 is a diagram showing a circuit configuration of a transmission / reception system including a second receiving device. [Figure 11] FIG. 11 is a diagram showing a byte alignment circuit of the second type. [Figure 12] FIG. 12 is a diagram showing a circuit configuration of a decoder with a correction value generation function. [Figure 13] FIG. 13 is a flowchart for explaining a phase correction procedure of an image data signal in the second receiving device. [Figure 14] FIG. 14 is a diagram for explaining the states of a plurality of error signals. [Figure 15] FIG. 15 is a timing diagram for explaining an example of the timing of data transmission / reception in the first receiving device. [Figure 16] FIG. 16 is a timing diagram for explaining an example of the timing of data transmission / reception in the second receiving device. [Figure 17] FIG. 17 is a diagram showing a circuit configuration of a transmission / reception system including a third receiving device. [Figure 18] FIG. 18 is a diagram showing a circuit configuration of a decoder with a correction value generation function. [Figure 19] FIG. 19 is a diagram showing a byte alignment circuit of the third type. [Figure 20] FIG. 20 is a diagram showing a circuit configuration of a transmission / reception system including an improved first receiving device. [Figure 21]Figure 21 shows the circuit configuration of a transceiver system equipped with an improved second receiver. [Figure 22] Figure 22 shows the circuit configuration of the transceiver system with the improved third receiver. [Modes for carrying out the invention]

[0018] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the attached drawings. In the description of the drawings, the same elements will be denoted by the same reference numerals, and redundant descriptions will be omitted. The present invention is not limited to these examples, but is indicated by the claims, and all modifications within the meaning and scope equivalent to the claims are intended to be included.

[0019] Figure 1 shows the circuit configuration of a transmitting and receiving system equipped with a first receiving device.

[0020] The transmission and reception system comprises a transmitting device TX and a receiving device RX.

[0021] The transmitter TX comprises an encoder 201 and a serializer 202. The encoder 201 receives a parallel data signal DATA-P(IN) as an image data signal, along with a signal FLAG-K(IN) corresponding to a control code (K code in 8b10b). This signal FLAG-K can also function as an identifier for the data type. The encoder 201 performs symbol mapping encoding. In this example, an 8-bit parallel data signal is input to the encoder 201, which is an 8b10b encoder. The encoder 201 outputs an encoded 10-bit parallel data signal DATA-P(EE). The parallel data signal DATA-P(EE) is input to the serializer 202. The serializer 202 converts the parallel data signal DATA-P(EE) into an encoded serial data signal DATA-S(E) and outputs it to the transmission line. The encoded serial data signal DATA-S(E) is transmitted from the transmitter TX and received by the receiver RX via the transmission line.

[0022] The receiving device RX comprises a deserializer 1, a special code detection circuit 2, a byte alignment circuit 3, and a decoder 4 with a correction value generation function.

[0023] Deserializer 1 converts the received serial data signal DATA-S(E) into a 10-bit parallel data signal DATA-P(E*). When converting a serial data signal to a parallel data signal, consecutive serial data is divided at equal intervals to generate blocks of data sequences. Deserializer 1 divides consecutive serial data into 10-bit blocks and outputs a temporary parallel data signal DATA-P(E*). In this way, the receiving device RX receives the data signal from the transmitting device TX as a serial data signal, converts it into a parallel data signal, and is equipped with a deserializer 1 that inputs this parallel data signal to the special code detection circuit 2 and the byte alignment circuit 3. Deserializer 1 can convert serial data signals into parallel data signals.

[0024] The special code detection circuit 2 receives a parallel data signal DATA-P(E*). The special code detection circuit 2 generates multiple data sequences (for example, 10 data sequences) shifted by one bit from the parallel data signal DATA-P(E*), compares each data sequence with a sequence of special codes (comma characters), and outputs a first correction value DET-COM containing information about the position (timing) of the special code if a data sequence matching the special code is detected. The first correction value DET-COM is used to correct the aforementioned data delimiter position (phase). The first correction value DET-COM contains information about the position (Xth data sequence) of the data sequence in which the special code was detected, for example, when multiple data sequences are generated.

[0025] The byte alignment circuit 3 receives the parallel data signal DATA-P(E*). The byte alignment circuit 3 corrects the delimiter positions of the temporary parallel data signal DATA-P(E*), i.e., performs byte alignment, according to the first correction value DET-COM. In the image data signal, special codes are embedded at the start and end of the blanking period, and the reception of actual image data starts from the bit following the time (t0) when the special code at the end is received. Similar to the special code detection circuit 2, the byte alignment circuit 3 generates multiple data sequences (for example, 10 data sequences) shifted by one bit each from the parallel data signal DATA-P(E*), and one of the data sequences is delimited at the correct position. If the position of the data sequence in which the special code was received by the special code detection circuit 2 is the Xth position, then the byte alignment circuit 3 also correctly delimited the Xth data sequence by the special code. The first correction value DET-COM instructs the byte alignment circuit 3 to use the position information that it is the Xth position. The byte alignment circuit 3 outputs a parallel data signal DATA-P(E) that has been byte-aligned based on the correct delimiter information.

[0026] After byte alignment is performed, external noise or other factors may cause the byte alignment to be performed at positions that are shifted from the correct delimiter positions (this is called "byte alignment misalignment").

[0027] "Byte alignment misalignment" refers to a condition in the receiving device where serial-to-parallel conversion is not performed on the correct data blocks. When noise is superimposed on the data, the recovery clock of the clock data recovery (CDR) circuit is shifted, causing a shift in the serial data acquisition timing of the receiving device, and resulting in an increase or decrease in the number of data points received. In this case, a discrepancy in the number of data points occurs between the transmitting and receiving devices, and the data boundary positions shift. Note that the difference in frequency between the transmission clock on the transmitting side and the recovery clock on the receiving side is called recovery clock misalignment. If the recovery clock of the receiving device is slower than the transmission clock on the transmitting device, it may not be possible to sample the transmitted (1-bit) data. Conversely, if the recovery clock is faster than the transmission clock on the transmitting device, the transmitted (1-bit) data may be sampled multiple times, which may increase the number of data points received by the receiving device. Thus, a difference between the number of data bits transmitted by the transmitting device and the number of data bits received by the receiving device causes "byte alignment misalignment."

[0028] In this receiving device, before receiving the next special code, byte alignment is performed again to restore the correct data signal as early as possible. In the first receiving device, the subsequent decoder 4 generates a second correction value θK. The second correction value θK, like the first correction value DET-COM, contains information about the position (Yth data sequence) of the data sequence separated at the correct position. When the byte alignment circuit 3 receives the second correction value θK, it performs byte alignment in the same way as when it receives the first correction value DET-COM, and outputs a parallel data signal DATA-P(E) that has been byte aligned based on the correct separation information.

[0029] The decoder 4 receives the parallel data signal DATA-P(E). The decoder 4 decodes the received parallel data signal DATA-P(E) and outputs the parallel data signal DATA-P(OUT) and the signal FLAG-K(OUT) which corresponds to the K code as a control code.

[0030] Furthermore, decoder 4 has a correction value generation function and generates a second correction value θK based on the received parallel data signal DATA-P(E). Like the byte alignment circuit 3, decoder 4 also generates multiple data sequences shifted by one bit at a time, and when decoding each data sequence, it identifies the position of the data sequence in which no error occurred (the Yth data sequence did not have an error). When byte alignment circuit 3 receives the second correction value θK, it determines that the Yth data sequence is separated at the correct position and performs byte alignment by outputting the signal for the Zth data sequence corresponding to the Yth sequence. Note that the Zth sequence is the X+Yth sequence, and if Z exceeds the maximum value of 10, that maximum value is subtracted. The structure of each circuit will be explained in detail below.

[0031] Figure 2 shows the circuit configuration of the special code detection circuit 2.

[0032] The special code detection circuit 2 comprises a data sequence generation circuit 21, a plurality of special code detection units 22, and a correction value generation circuit 23. The data sequence generation circuit 21 receives a parallel data signal DATA-P(E*). In this example, the data sequence generation circuit 21 generates 10 data sequences by shifting each bit from the parallel data signal DATA-P(E*). Each data sequence (DATA-ARRAY(0) to DATA-ARRAY(9)) is input to the corresponding special code detection unit 22(0) to 22(9). Each special code detection unit 22 also receives an 8b10b code and determines the position of the special code in the received data sequence. Known 8b10b special codes include the comma character (K28.1, K28.5, K28.7).

[0033] The special code detection units 22(0) to 22(9) each output special code detection signals COMMA-DET(0) to COMMA-DET(9) indicating whether the received data sequence contains a special code (comma character). The 10 special code detection signals COMMA-DET(0) to COMMA-DET(9) are input to the correction value generation circuit 23. If the Xth (X=5) special code detection signal indicates that a special code has been detected, for example, the sequence of special code detection signals will be (0,0,0,0,1,0,0,0,0,0). The correction value generation circuit 23 generates a first correction value DET-COM from the received sequence of special code detection signals, indicating that there is a special code at the Xth position. Since the first correction value DET-COM is input to the selection circuit of the byte alignment circuit 3, the data sequence of the special code detection signal can be used as is, as long as it is a signal that is appropriately synchronized with the parallel data signal DATA-P(E*) input to the byte alignment circuit 3.

[0034] Figure 3 shows the data sequence generation circuit and the special code detection circuit.

[0035] The data sequence generation circuit 21 combines the first data sequence (data D0~D9) and the second data sequence (D10~D19), which are input consecutively, to generate a data sequence consisting of 20 data points (D0~D19). Furthermore, it extracts a data sequence DATA-ARRAY(n) from the 20 data sequences, divided into groups of 10 data points (bits) (n=0~9). The nth data sequence and the (n+1)th data sequence are shifted by 1 bit (data point). The special code detection unit 22(n) is a logic circuit that compares the input data sequence (D(19-n)~D(10-n)) with a comma character data sequence (C0~C9). If they match, the level of the special code detection signal COMMA-DET(n) increases, allowing the location (timing) of the special code to be identified.

[0036] Figure 4 shows an example of a data sequence generation circuit.

[0037] The data sequence generation circuit 21 is equipped with 10 D flip-flops, each of which is input to the D terminal, representing 10 bits of data. When the first data sequence (data D0 to D9) is input, the rise edge of the sampling clock signal CLKφ is input to the clock terminal in synchronization with the input, the first data sequence is output to the Q terminal, and the 10-bit first data sequence is maintained by outputting from the lower terminal. Next, when the second data sequence (D10 to D19) is input to the data sequence generation circuit 21, the sampling clock signal CLKφ is not changed, and the 10-bit second data sequence is output from the upper terminal. In this manner, a 20-bit data sequence is generated, and this generation process is repeated thereafter.

[0038] Figure 5 shows a first type of bite alignment circuit 3.

[0039] The first type of byte alignment circuit 3 applied to the first receiving device comprises a data sequence generation circuit 31, a selection circuit 32, and a byte alignment determination circuit 33. The structure of the data sequence generation circuit 31 is the same as that of the data sequence generation circuit 21 described above, and outputs 10 data sequences (DATA-ARRAY(0) to DATA-ARRAY(9)) with phases shifted by one bit each. The selection circuit 32 performs byte alignment by outputting a data sequence corresponding to the information indicated by the input first correction value DET-COM and second correction value θK (the position of the data sequence separated at the correct position).

[0040] The first correction value DET-COM is generated depending on the timing of the reception of a special code (comma character) that is received periodically. When this is received, the byte alignment judgment circuit 33 inputs a first selection instruction signal (for example, a selection instruction signal to select the fifth data sequence (DATA-ARRAY(4))) to the selection circuit 32, which selects the error-free data sequence indicated by the information of the first correction value DET-COM. When the byte alignment judgment circuit 33 receives the second correction value θK, it inputs a second selection instruction signal to the selection circuit 32, which selects the error-free data sequence indicated by the information of the second correction value θK.

[0041] The byte alignment determination circuit 33 prioritizes the first selection instruction signal, which it generates in response to the reception of the first correction value DET-COM, over the second selection instruction signal, which it generates in response to the reception of the second correction value θK, and inputs it to the selection circuit 32. That is, if the byte alignment determination circuit 33 receives the first correction value DET-COM after receiving the second correction value θK, it stops the execution of byte alignment using the second correction value θK and outputs the first selection instruction signal.

[0042] In the first receiving device, the second correction value θK indicates the position of a data sequence where no errors have occurred. The second correction value θK is input to the byte alignment circuit 3, and byte alignment of the input data signal is performed according to the second correction value θK. The first receiving device controls the byte alignment circuit 3 by feeding back the second correction value θK generated by the correction value generation circuit. Since it does not require many circuits, it can have a relatively small circuit size.

[0043] Figure 6 shows the circuit configuration of the decoder 4 with a correction value generation function.

[0044] The decoder 4 includes a data sequence generation circuit 41, an 8b10b decoder 42(0) with error detection, a plurality of 8b10b error detectors 42E(1) to 42E(9), and a correction value generation circuit 43.

[0045] The structure of the data sequence generation circuit 41 is the same as that of the data sequence generation circuit 21 described above, and it outputs 10 data sequences (DATA-ARRAY(0) to DATA-ARRAY(9)) with phases shifted by one bit each. The decoder 4 has 10 channels through which these data sequences flow.

[0046] A typical 8b10b decoder has the functions of decoding the input signal, detecting errors during 8b10b conversion, and generating an identification signal FLAG-K(OUT) corresponding to the control code (K code). An 8b10b error detector can use some of the functions of the 8b10b decoder, but it may also be configured by removing unnecessary parts from the 8b10b decoder. An 8b10b decoder with error detection or an 8b10b error detector outputs an error signal ERROR(n), which is the result of determining whether there is an error in the input signal (in this example, n is an integer from 0 to 9). An error is determined to exist when a code error is detected or when a running disparity error is detected. Error detection may be performed in only one of these cases, or in both cases.

[0047] Ten error signals (ERROR(0) to ERROR(9)) are input to the correction value generation circuit 43. If the Yth error signal (Y=3) indicates that there is no error, for example, the sequence of error signals will be (1,1,0,1,1,1,1,1,1,1). The correction value generation circuit 43 generates a second correction value θK from the received sequence of error signals, indicating that there is no error at the Yth position. The second correction value θK may be generated, for example, by inverting the logic of the sequence of error signals and shifting the phase by the amount converted to input to the byte alignment circuit 3 so that a data sequence with correct delimiters is selected.

[0048] In the diagram, the first 8b10b decoder with error detection, 42(0), is positioned and outputs the decoded parallel data signal DATA-P(OUT) as well as the identification signal FLAG-K(OUT). However, it is not necessary to set the circuit that performs the decoding output as the first 8b10b decoder with error detection, 42(0); it may be set as a position corresponding to another channel in the data array. For example, the fifth 8b10b error detector 42E(4) or the sixth 8b10b error detector 42E(5) can also be used as the 8b10b decoder. In this case, the 8b10b decoder is located in the center of the data array channels, which has the advantage of increasing symmetry during data processing.

[0049] Figure 7 is a flowchart illustrating the phase correction procedure for the image data signal in the first receiving device.

[0050] The decoder 4 shown in Figure 6 detects whether an error has occurred in a specific channel (8b10b decoder 42(0) with error detection) that is currently being decoded and outputting data from 10 channels (data streams: DATA-ARRAY(0) to DATA-ARRAY(9)) (step S1). This can be determined by detecting the data stream of the error signal. If an error occurs in a specific channel, there is a channel that does not have an error, so that channel is selected (step S2). If an error occurs in the target channel currently being decoded, it means that the delimiter of the data stream in this channel is incorrect. There is a correct data stream with data delimiter at a position shifted in phase from this channel. The correction value generation circuit 43 selects the data stream with the correct delimiter, generates a second correction value θK corresponding to the selected channel, and outputs it (step S3). The byte alignment circuit 3 performs byte alignment according to the input second correction value θK (step S4). If byte alignment using the first correction value DET-COM is performed during the execution of this flow, the input to the decoder will become a data sequence with correct delimiters, thus resolving the error in the decoder. The execution of byte alignment using the second correction value θK will then be stopped, and the process will return to the state of step S1.

[0051] Figure 8 is a diagram illustrating the timing of bite alignment.

[0052] The timing of the encoded parallel data signal DATA-P(E) is shown. In the image data signal, the blanking start signal BS (comma character in the K code) is included at the start of the blanking period (D code), and the blanking end signal BE (comma character in the K code) is included at the end. The active period (D code) in which the image data is transmitted begins from the bit following the blanking end signal BE. At time t0 immediately after receiving the blanking end signal BE, byte alignment is performed using the first correction value DET-COM. Subsequently, if an error is detected at time t1 due to external noise, etc., during 8b10b decoding, byte alignment is performed at time t2 using the second correction value θK described above. Unless time t1 is immediately before time t3, the time for the next byte alignment using the first correction value DET-COM after the error occurred, time t2 is earlier than time t3, the time for the next byte alignment using the first correction value DET-COM after the error occurred. Therefore, this receiving device can quickly return to a normal image data signal even before receiving a special code.

[0053] Figure 9 is a diagram illustrating the states of multiple error signals.

[0054] Figure 6 shows a decoder 4 configured to constantly monitor multiple error signals ERROR(0) to ERROR(9). Suppose the first 8b10b decoder 42(0) with error detection in Figure 6 switches from a no-error state to an error state at time t1. In this case, for example, the error signal ERROR(1) output from the second 8b10b error detector 42E(1) changes to a no-error state immediately after time t1. The correction value generation circuit 43 generates a second correction value θK, inputs it to the byte alignment circuit 3, and byte alignment is performed at time t2. After that, the first 8b10b decoder 42(0) with error detection returns to a no-error state. Note that among the multiple channels, only one channel is error-free, while errors frequently occur in the other channels.

[0055] Figure 10 shows the circuit configuration of a transmitting and receiving system equipped with a second receiving device.

[0056] This transmission / reception system differs from the transmission / reception system shown in Figure 1 in the structure of the byte alignment circuit 3 and the decoder 4. Unlike the first type (Figure 5), this byte alignment circuit 3 (second type) does not receive a second correction value θK as input; instead, it outputs a notification signal DONE indicating the completion of byte alignment, which is input to the decoder 4. The other configurations of this transmission / reception system are the same as those shown in Figure 1.

[0057] Decoder 4 has multiple (sub)decoders internally, each corresponding to multiple channels, and the output signal of any of the (sub)decoders is the output signal with correctly delimited data. Therefore, if an error is detected in any of the (sub)decoders, the output of the decoder without the error is selected and output as the parallel data signal DATA-P(OUT).

[0058] Figure 11 shows a second type of bite alignment circuit.

[0059] The second type of byte alignment circuit 3 applied to the second receiving device differs from the first type of byte alignment circuit 3 (Figure 5) only in the function of the byte alignment determination circuit 33; the other configurations are identical. Similar to the first type, when the second type of byte alignment determination circuit 33 receives the first correction value DET-COM, it inputs a first selection instruction signal to the selection circuit 32 to select the corresponding error-free data sequence, and performs the same byte alignment as described above.

[0060] The second type of byte alignment determination circuit 33 inputs the first selection instruction signal to the selection circuit 32, and then outputs a notification signal (DONE) indicating that the byte alignment has been completed. The notification signal (DONE) is input to the decoder 4, which has a correction value generation function and is located in the subsequent stage.

[0061] Figure 12 shows the circuit configuration of the decoder 4 with a correction value generation function.

[0062] Decoder 4 comprises a data sequence generation circuit 41, 10 error-detection 8b10b decoders 42(0) to 42(9), a correction value generation circuit 43A, a first selection circuit 44, and a second selection circuit 45.

[0063] The structure of the data sequence generation circuit 41 is as described above, and it outputs 10 data sequences (DATA-ARRAY(0) to DATA-ARRAY(9)) with phases shifted by one bit each. The decoder 4 has 10 channels through which these data sequences flow.

[0064] The 10 error-detection 8b10b decoders 42(0) to 42(9) are general 8b10b decoders, each possessing the function of decoding the input signal, detecting errors during 8b10b conversion, and generating identification signals FLAG-K(0) to FLAG-K(9) corresponding to the control code (K code).

[0065] Each error-detecting 8b10b decoder 42(n) (where n is an integer from 0 to 9) outputs an output signal DATA(n) which decodes the input data sequence, an error signal ERROR(n) which determines whether or not there is an error, and an identification signal FLAG-K(n) which corresponds to the control code (K code). The error-detecting 8b10b decoder 42(n) outputs an error signal ERROR(n), which is the result of determining whether or not there is an error in the input signal (in this example, n is an integer from 0 to 9). An error is determined to exist when a code error is detected or when a running disparity error is detected. Error detection may be performed for only one of these cases, or for both cases.

[0066] Ten error signals (ERROR(0) to ERROR(9)) are input to the correction value generation circuit 43A. If the Yth error signal (Y=3) indicates that there is no error, for example, the data sequence of the error signal will be (1,1,0,1,1,1,1,1,1,1). The correction value generation circuit 43A generates a second correction value θK* from the received error signal sequence, indicating that there is no error at the Yth position. The second correction value θK* is, for example, obtained by inverting the logic of the error signal data sequence.

[0067] The first selection circuit 44 receives the decoded 10 output signals DATA(n). The first selection circuit 44 selects and outputs the output signal DATA(n) of the Y-th data sequence indicated by the second correction value θK* output from the correction value generation circuit 43A.

[0068] Ten identification signals, FLAG-K(n), are input to the second selection circuit 45. The second selection circuit 45 selects the identification signal FLAG-K(n) of the Yth data sequence indicated by the second correction value θK* output from the correction value generation circuit 43A, and outputs it as FLAG-K(OUT).

[0069] As explained above, this receiver RX is equipped with multiple 8b10b decoders 42(n) that decode multiple data sequences, and the second correction value θK* indicates a data sequence without errors. By selecting the data signal decoded from the data sequence indicated by the second correction value θK* and outputting it as a parallel data signal DATA-P(OUT), byte alignment of the data signal is performed. The receiver has multiple decoders prepared in advance.

[0070] A normal data signal is a data signal output by dividing the data sequence at the positions of normal blocks, and an error data signal is a data signal output by dividing the data sequence at the positions of blocks where errors occur. Multiple 8b10b decoders 42(n) are in a state where both normal data signals and error data signals can be output. This receiver performs byte alignment of the data signals by selecting normal data signals using a second correction value θK*. Since this receiver does not require feedback of the second correction value to the byte alignment circuit 3, the circuit structure is simplified, resulting in excellent maintainability and robustness.

[0071] Furthermore, when the byte alignment circuit 3 performs byte alignment using the first correction value DET-COM generated in synchronization with the special code detection, it inputs a notification signal DONE indicating the completion of byte alignment to the correction value generation circuit 43A of the decoder 4. After the byte alignment is performed, the first selection circuit 44 selects and outputs a parallel data signal DATA-P(OUT) that has been delimited at the correct timing. When the notification signal DONE indicating the completion of byte alignment is input to the correction value generation circuit 43A, it can be determined that the system is in the default alignment state (a state in which normal byte alignment synchronized with the special code detection has been performed and the correct delimiters have been made). If, in the initial settings, there is a specific channel (any of DATA-ARRAY(0) to DATA-ARRAY(9)) that is set to output the correct parallel data signal DATA-P(OUT) in this state, then that specific channel should be selected. In other words, in this case, the second correction value θK* is a signal that instructs the first selection circuit 44 and the second selection circuit 45 to select the data signal output from the 8b10b decoder 42 corresponding to a specific channel.

[0072] Figure 13 is a flowchart illustrating the phase correction procedure for the image data signal in the second receiving device.

[0073] The decoder 4 shown in Figure 12 detects whether an error has occurred in a specific channel (e.g., error-detection-equipped 8b10b decoder 42(0)) that is currently being decoded and outputting data from 10 channels (data streams: DATA-ARRAY(0) to DATA-ARRAY(9)) (step S11). This can be determined by detecting the data stream of the error signal. If an error occurs in a specific channel, there is a channel that does not have an error. If an error occurs in the target channel currently being decoded, it means that the data stream delimiter for this channel is incorrect and that the data stream delimiter with a phase shift is correct. Therefore, the correction value generation circuit 43A generates and outputs a second correction value θK* indicating the channel without errors (step S12). The first selection circuit 44 performs byte alignment by selecting and outputting the data signal without errors according to the input second correction value θK* (step S13). When byte alignment is performed using the first correction value DET-COM, the correction value generation circuit 43A receives the DONE notification signal indicating the completion of byte alignment, and regardless of which step is being performed, the decoder that was initially selected (the default decoder selected when the data signal DATA-P(E) has correct data delimiters and there are no errors) is selected, and the process transitions to step S11.

[0074] Figure 14 is a diagram illustrating the states of multiple error signals.

[0075] Figure 12 shows a decoder 4 configured to constantly monitor multiple error signals ERROR(0) to ERROR(9). Suppose the first 8b10b decoder 42(0) with error detection in Figure 12 switches from a no-error state to an error state at time t1. In this case, for example, the error signal ERROR(1) output from the second 8b10b decoder 42(1) changes to a no-error state immediately after time t1. The correction value generation circuit 43A generates a second correction value θK*, and at time t2, byte alignment is performed. Subsequently, the output signal of the second 8b10b decoder 42(1) is selected as the no-error output signal and output. Note that among the multiple channels, only one channel is error-free, while errors frequently occur in the other channels.

[0076] Figure 15 is a timing diagram illustrating an example of the timing of data transmission and reception in the first receiving device.

[0077] On the transmitting device TX side, an 8-bit parallel data signal DATA-P(IN)hex (hexadecimal representation) or DATA-P(IN)bin (binary representation) is input. This is converted to a 10-bit encoded parallel data signal DATA-P(EE), and then transmitted as a serialized serial data signal DATA-S(E).

[0078] On the receiving device RX side, the serial data signal DATA-S(E) is received, deserialized, converted into a parallel data signal DATA-P(E*), and then byte-aligned parallel data signal DATA-P(E) is generated. Subsequently, data sequences DATA-ARRAY(0) to DATA-ARRAY(9) flowing through 10 channels are generated. The parallel data signal DATA-P(OUT)bin (binary representation) or DATA-P(OUT)hex (hexadecimal representation) is output from the decoder.

[0079] If an error (NG) is detected in the parallel data signal DATA-P(OUT)hex (hexadecimal representation) after 8b10b encoding, for example, due to a code error, this output signal will have an undefined value. Code errors are detected by an 8b10b decoder with error detection. For example, if an error (ERROR) occurs in the first data sequence (DATA-ARRAY(0)) and the second data sequence (DATA-ARRAY(1)) is normal (OK), then, as described above, byte alignment using the second correction value θK is performed at time t2. In this case, the error in the subsequent first data sequence (DATA-ARRAY(0)) is resolved, and it can return to a normal (OK) state.

[0080] Figure 16 is a timing diagram illustrating an example of the timing of data transmission and reception in the second receiving device.

[0081] On the transmitting device TX side, an 8-bit parallel data signal DATA-P(IN)hex (hexadecimal representation) or DATA-P(IN)bin (binary representation) is input. This is converted to a 10-bit encoded parallel data signal DATA-P(EE), and then transmitted as a serialized serial data signal DATA-S(E).

[0082] On the receiving device RX side, the serial data signal DATA-S(E) is received, deserialized, converted into a parallel data signal DATA-P(E*), and then byte-aligned parallel data signal DATA-P(E) is generated. Subsequently, data sequences DATA-ARRAY(0) to DATA-ARRAY(9) flowing through 10 channels are generated. The parallel data signal DATA-P(OUT)bin (binary representation) or DATA-P(OUT)hex (hexadecimal representation) is output from the decoder.

[0083] If an error (NG) is detected in the parallel data signal DATA-P(OUT)hex (hexadecimal representation) after 8b10b encoding, for example, due to a code error, this output signal will have an undefined value. If the currently selected data sequence is the first data sequence (DATA-ARRAY(0)) (selected decoder output: DATA(0)), and an error (ERROR) occurs in this data sequence, but the second data sequence (DATA-ARRAY(1)) is determined to be normal (OK), then, as described above, byte alignment using the second correction value θK* is performed at time t2. In this case, the output of the second data sequence (DATA-ARRAY(1)) (selected decoder output: DATA(1)) is selected, and the system can return to a normal (OK) state.

[0084] Figure 17 shows the circuit configuration of a transmitting and receiving system equipped with a third receiving device.

[0085] This transmission / reception system differs from the transmission / reception system shown in Figure 1 in the structure and arrangement of the decoder 4 and the byte alignment circuit 3. Other components of this transmission / reception system are the same as those shown in Figure 1.

[0086] Decoder 4 has multiple (sub)decoders internally corresponding to multiple channels, and the output signal of any of the (sub)decoders is the output signal with correctly delimited data. Therefore, if an error is detected in any of the (sub)decoders, a second correction value θK* is output to select the output of the decoder that does not have an error. Decoder 4 also outputs multiple parallel data signals DATA-P(M) decoded from the input signal, and multiple identification signals FLAG-K(M).

[0087] The byte alignment circuit 3 (third type) is located after the decoder 4. The byte alignment circuit 3 receives multiple parallel data signals DATA-P(M) (e.g., 10 sequences of 8 bits each) and multiple identification signals FLAG-K(M) (e.g., 10 bits) output from the decoder 4. Each input signal is selected using a first correction value DET-COM and a second correction value θK to ensure correct data separation. These signals are then output as the parallel data signal DATA-P(OUT) and the identification signal FLAG-K(OUT), resulting in byte alignment of the input parallel data signals.

[0088] Figure 18 shows the circuit configuration of the decoder 4 with a correction value generation function.

[0089] Decoder 4 comprises a data sequence generation circuit 41, 10 error-detection 8b10b decoders 42(0) to 42(9), and a correction value generation circuit 43A. In this example, decoder 4 is located immediately after deserializer 1, so it receives the parallel data signal DATA-P(E*) before byte alignment is performed.

[0090] The structure and function of the data sequence generation circuit 41 and the 8b10b decoders 42(0) to 42(9) with error detection are the same as the corresponding circuits in the decoder 4 of the second receiver (see Figure 12).

[0091] The 10 error-detection 8b10b decoders 42(0) to 42(9) are general 8b10b decoders, each possessing the function of decoding the input signal, detecting errors during 8b10b conversion, and generating identification signals FLAG-K(0) to FLAG-K(9), respectively.

[0092] Each error-detecting 8b10b decoder 42(n) (where n is an integer from 0 to 9) outputs an output signal DATA(n) which decodes the input data sequence, an error signal ERROR(n) which determines whether or not there is an error, and an identification signal FLAG-K(n) which corresponds to the control code (K code). The error-detecting 8b10b decoder 42(n) outputs an error signal ERROR(n), which is the result of determining whether or not there is an error in the input signal (in this example, n is an integer from 0 to 9). An error is determined to exist when a code error is detected or when a running disparity error is detected. Error detection may be performed for only one of these cases, or for both cases.

[0093] Ten error signals (ERROR(0) to ERROR(9)) are input to the correction value generation circuit 43A. For example, if the Yth error signal (Y=3) indicates that there is no error, the data sequence of the error signal will be (1,1,0,1,1,1,1,1,1,1,1). The correction value generation circuit 43A generates a second correction value θK* from the received error signal sequence, indicating that there is no error at the Yth position. The second correction value θK* is, for example, obtained by inverting the logic of the error signal data sequence.

[0094] Figure 19 shows a third type of bite alignment circuit 3.

[0095] This bite alignment circuit 3 includes a bite alignment determination circuit 33, a first selection circuit 34, and a second selection circuit 35.

[0096] The byte alignment determination circuit 33 receives a first correction value DET-COM and a second correction value θK*. When the byte alignment determination circuit 33 receives the first correction value DET-COM, it generates a first selection instruction signal to select an error-free data sequence (e.g., the Xth element) and inputs this to the first selection circuit 34 and the second selection circuit 35. When the byte alignment determination circuit 33 receives the second correction value θK*, it generates a second selection instruction signal to select an error-free data sequence (e.g., the Yth element) and inputs this to the first selection circuit 34 and the second selection circuit 35. The byte alignment determination circuit 33 prioritizes the first selection instruction signal generated in response to the reception of the first correction value DET-COM over the second selection instruction signal generated in response to the reception of the second correction value θK*, and inputs this to the first selection circuit 34 and the second selection circuit 35. In other words, if the byte alignment determination circuit 33 receives the first correction value DET-COM after receiving the second correction value θK*, it stops performing byte alignment using the second correction value θK* (selection of error-free data signals) and performs byte alignment using the first correction value DET-COM (selection of error-free data signals).

[0097] The first selection circuit 34 receives 10 output signals DATA(n) decoded by the preceding decoder 4. The first selection circuit 34 selects an error-free data sequence DATA(n) according to the first selection instruction signal generated from the first correction value DET-COM, or the second selection instruction signal generated from the second correction value θK*, and outputs it as a parallel data signal DATA-P(OUT).

[0098] The second selection circuit 35 receives 10 identification signals FLAG-K(n) decoded by the preceding decoder 4. The second selection circuit 35 selects a signal FLAG-K(n) corresponding to an error-free channel according to the first selection instruction signal generated from the first correction value DET-COM, or the second selection instruction signal generated from the second correction value θK*, and outputs it as the identification signal FLAG-K(OUT).

[0099] Furthermore, the serializer 202 of the transmitter TX may be equipped with a pre-emphasis circuit (amplifier) ​​that amplifies the high-frequency components of the transmitted signal. The deserializer 1 of the receiver RX may be equipped with an adaptive equalizer that automatically amplifies high-frequency components that are attenuated according to the characteristics of the transmission line. This suppresses signal quality degradation during signal transmission and allows the transmission speed of symbol-mapping data to preferably be 4 Gbit / s or more over one pair of differential lines, and the transmission distance to be 10 m or more. In addition, flexible flat cables (FFCs) can be used for the serial data signal transmission line.

[0100] Next, we will describe a transmitting and receiving system equipped with a receiving device that is an improved version of the first to third receiving devices described above.

[0101] Figure 20 shows the circuit configuration of a transmitting and receiving system with an improved first receiving device.

[0102] The transmitter TX shown in the figure includes, in addition to the first receiver shown in Figure 1, a packer PC, a symbol generation circuit SG, and a multiplexer MUX.

[0103] The packer PC receives, for example, video signals DATA-IN for each RGB channel and a sink signal SYNC-IN. The packer PC generates a byte clock signal from the pixel clock signal of the video signal, and uses the byte clock signal to perform packet processing of the video signal, generating packet signals that will be the video signal within the active period (ACTIVE). The packer PC also performs packet processing of signals corresponding to the blank start (BS) period, blank end (BE) period, and blank (BP) period from the sink signal SYNC-IN, generating packet signals corresponding to each period. Each packet signal is an 8-bit parallel data signal, but it is also possible to process N times the number of 8-bit parallel data signals (where N is a natural number).

[0104] The symbol generation circuit SG receives the data enable signal DE-IN and generates and outputs an identification signal FLAG-K(IN) corresponding to the control code (K code) from the data enable signal DE-IN. The signal FLAG-K(IN) contains information indicating the BS period, BE period, and BP period. For example, the BS period can be set immediately after the falling edge of the data enable signal DE-IN, and the blank end BE period can be set immediately before the rising edge.

[0105] The multiplexer MUX receives multiple signals output from the packer PC and an identification signal FLAG-K(IN), and outputs an 8×N bit parallel data signal, which is a composite of these signals, to the encoder 201. The multiplexer MUX also receives an identification signal FLAG-K(IN) that contains information about the BS period, BE period, and BP period, and can operate using this signal. For example, during the active period, the multiplexer MUX can output a video signal containing image information, and during the BS period, BE period, and BP period, it can output signals generated from the sync signal SYNC-IN corresponding to each period.

[0106] Encoder 201 is an 8b10b encoder that receives an 8-bit parallel data signal PATA-P(IN) output from the multiplexer MUX, encodes it into a 10-bit parallel data signal, and outputs it. This parallel data signal can also be processed as a parallel data signal that is N times the number of bits of the 10-bit parallel data signal. Encoder 201 also receives an identification signal FLAG-K(IN) corresponding to the control code (K code) output from the symbol generation circuit SG, and can optimize the encoding operation according to the type of signal. A serializer 202 is placed downstream of encoder 201 and outputs a serial data signal DATA-S(E). The serializer 202 may also be equipped with a pre-emphasis circuit (amplifier) ​​that amplifies high-frequency components.

[0107] The first receiver RX shown in the figure includes, in addition to the first receiver shown in Figure 1, a symbol detection circuit SD, a demultiplexer DMUX, an amp-packer UP, and a data enable signal generation circuit DE.

[0108] The deserializer 1 of the receiver RX receives the serial data signal DATA-D(E). The deserializer 1 may be equipped with an adaptive equalizer. A special code detection circuit 2, a byte alignment circuit 3, and a decoder 4 are arranged downstream of the deserializer 1. The structure and operation of these are as described with respect to the first receiver (Figure 1), but the parallel data signal output from these circuits can also be a parallel data signal that is N times the number of bits of the 10-bit parallel data signal.

[0109] A symbol detection circuit SD is located downstream of decoder 4, followed by a data enable signal generation circuit DE. A demultiplexer DMUX is also located downstream of decoder 4. The symbol detection circuit SD receives a parallel data signal DATA-P (OUT) and an identification signal FLAG-K (OUT). The symbol detection circuit SD detects information corresponding to the BS period, BE period, and BP period from the received signals, and inputs the symbol detection signal containing the detected information to the demultiplexer DMUX and the data enable signal generation circuit DE.

[0110] The Unpacker UP (Unpacker) is located after the Demultiplexer DMUX. The Demultiplexer DMUX has the function of reconstructing the video signals for each RGB channel and the sync signal from the received parallel data signal DATA-P (OUT). In order to reconstruct the sync signal, the output terminal of the input parallel data signal can be switched according to each period (BS period, BE period, BP period) indicated by the symbol detection signal output from the symbol detection circuit SD. The parallel data signals separated from each output terminal according to the active period, BS period, BE period, and BP period are input to the Unpacker UP.

[0111] The unpacker UP generates a pixel clock signal from the parallel data signal received from the demultiplexer DEMUX, and uses the pixel clock signal to unpack the 8-byte packet signal, reconstructing the video signal DATA-OUT and the sync signal SYNC-OUT for each RGB channel, and outputting them.

[0112] The data enable signal generation circuit DE generates and outputs the data enable signal DE-OUT according to each period (BS period, BE period, BP period) indicated by the symbol detection signal output from the symbol detection circuit SD. Note that the parallel data signals output from decoder 4, demultiplexer DMUX, and unpacker UP can also be parallel data signals that are N times the number of the 8-bit parallel data signal.

[0113] Figure 21 shows the circuit configuration of a transceiver system equipped with an improved second receiver.

[0114] The transmitter TX shown in the figure is the same as the transmitter shown in Figure 20. The second receiver RX shown in the figure is a circuit that adds a symbol detection circuit SD, a demultiplexer DMUX, an amp-packer UP, and a data enable signal generation circuit DE to the second receiver shown in Figure 10.

[0115] The deserializer 1 of the receiver RX receives the serial data signal DATA-D(E). The deserializer 1 may be equipped with an adaptive equalizer. Following the deserializer 1 are a special code detection circuit 2, a byte alignment circuit 3, and a decoder 4. Their structure and operation are as described with respect to the second receiver (Figure 10). The parallel data signals output from the deserializer 1 and the byte alignment circuit 3 can be N times the number of a 10-bit parallel data signal. The parallel data signal output from the decoder 4 can also be N times the number of an 8-bit parallel data signal.

[0116] Following decoder 4 are a symbol detection circuit SD, a data enable signal generation circuit DE, a demultiplexer DMUX, and an ampucker UP. The structure and operation of these components are identical to those shown in Figure 20.

[0117] Figure 22 shows the circuit configuration of the transceiver system with the improved third receiver.

[0118] The transmitter TX shown in the figure is the same as the transmitter shown in Figure 20. The second receiver RX shown in the figure is a circuit that adds a symbol detection circuit SD, a demultiplexer DMUX, an amp-packer UP, and a data enable signal generation circuit DE to the third receiver shown in Figure 17.

[0119] The deserializer 1 of the receiver RX receives the serial data signal DATA-D(E). The deserializer 1 may be equipped with an adaptive equalizer. Following the deserializer 1 are a special code detection circuit 2, a decoder 4, and a byte alignment circuit 3. Their structure and operation are as described with respect to the third receiver (Figure 17). The parallel data signal output from the decoder 4 is 8 × n bits (n=10 in Figure 19). The parallel data signal DATA-P(OUT) output from the byte alignment circuit 3 can also be a parallel data signal that is N times the number of bits of the 8-bit parallel data signal.

[0120] Following decoder 4 are a symbol detection circuit SD, a data enable signal generation circuit DE, a demultiplexer DMUX, and an ampucker UP. The structure and operation of these components are identical to those shown in Figure 20.

[0121] As explained above, the first receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) encoded using a symbol mapping method and containing a special code, and outputs a first correction value DET-COM corresponding to the position of the special code contained in this data signal; a byte alignment circuit 3 that receives the first correction value DET-COM and the second correction value θK as inputs and performs byte alignment of the data signal according to the first and second correction values; a data sequence generation circuit 41 that generates multiple data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit 3; and an output from the data sequence generation circuit 41. The system comprises a decoder 42(0) that decodes and outputs a specific data sequence from among multiple data sequences and performs error detection on the specific data sequence; multiple error detectors 42E(1) to 42E(9) that perform error detection on each of the remaining data sequences other than the specific data sequence from the multiple data sequences output from the data sequence generation circuit 41; and a correction value generation circuit 43 that receives multiple error signals ERROR(0) to (9) indicating the result of the error detection output from the decoder 42(0) and the multiple error detectors 42E(1) to 42E(9), and generates a second correction value θK that includes information on data sequences that do not have errors, according to the multiple error signals that have been input.

[0122] In this receiving device, the first correction value DET-COM corresponds to the position of a special code indicating normal timing. When the first correction value DET-COM is received, byte alignment is performed by the byte alignment circuit 3. The second correction value θK contains information about data sequences that are error-free, based on multiple error signals. If an error occurs before the reception of the special code due to external noise, etc., byte alignment of the data signal is performed according to the second correction value generated by the correction value generation circuit 43. This allows for an early return to a normal data signal, even before the reception of the special code. If the data signal is an image data signal, image distortion can be quickly resolved. This receiving device controls the byte alignment circuit by feeding back the second correction value generated by the correction value generation circuit to the preceding byte alignment circuit. Because it does not require many circuits, it can be implemented with a relatively small circuit size.

[0123] The second receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) encoded using a symbol mapping method and containing special codes, and outputs a first correction value DET-COM corresponding to the position of the special codes contained in the data signal; a byte alignment circuit 3 that performs byte alignment of the data signal according to the first correction value DET-COM output from the special code detection circuit 2; a data sequence generation circuit 41 that generates multiple data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit 3; and an output from the data sequence generation circuit 41. The system comprises: multiple decoders 42(0) to 42(9) that decode and determine the error of each of the multiple data sequences; a correction value generation circuit 43A that receives multiple error signals ERROR(0) to (9) indicating the result of the error determination output from the multiple decoders 42(0) to 42(9) and generates a second correction value θK* that includes information on data sequences that do not have errors, according to the input error signals; and a selection circuit (44) that selects and outputs a data sequence corresponding to the second correction value θK* from among the multiple data sequences output from the multiple decoders 42(0) to 42(9).

[0124] In this receiving device, the first correction value DET-COM corresponds to the position of a special code indicating normal timing. When the first correction value DET-COM is received, the byte alignment circuit 3 performs byte alignment. The second correction value θK* contains information about data sequences that are free of errors, based on multiple error signals. If an error occurs before the reception of a special code due to external noise, etc., the selection circuit 44 selects and outputs data sequences without byte alignment misalignment according to the second correction value θK* generated by the correction value generation circuit 43A. This allows for early recovery to a normal data signal, even before the reception of a special code. If the data signal is an image data signal, image distortion can be quickly resolved. Furthermore, this receiving device can achieve early recovery from byte alignment misalignment with simple modifications from existing technology.

[0125] The second receiving device is equipped with multiple decoders. The normal data signal is the data signal output by dividing the data sequence at the positions of normal blocks, while the error data signal is the data signal output by dividing the data sequence at the positions of blocks where errors occur. Both the normal data signal and the error data signal group are ready to output from the multiple decoders. This receiving device performs byte alignment of the data signal by selecting the normal data signal using a second correction value. Since this receiving device does not require feedback of the second correction value to the byte alignment circuit, the circuit structure is simplified, resulting in superior maintainability and robustness.

[0126] Furthermore, in the second receiving device, the byte alignment circuit outputs a notification signal DONE indicating the completion of byte alignment. When the notification signal DONE is input to the correction value generation circuit 43, the selection circuit 44 selects and outputs a data sequence from the decoder with the default settings within the decoder. Even if there is no change in the second correction value θK*, the selection circuit 44 can output a correctly delimited data sequence when the correction value generation circuit 43 receives the first correction value DET-COM.

[0127] The third receiving device includes a special code detection circuit 2 that receives a data signal DATA-P(E*) encoded using a symbol mapping method and containing a special code, and outputs a first correction value DET-COM corresponding to the position of the special code contained in the data signal; a data sequence generation circuit 41 that generates multiple data sequences from the data signal, each with different delimiter positions in the data sequence; a plurality of decoders 42(0) to 42(9) that decode each of the plurality of data sequences output from the data sequence generation circuit 41 and determine each of them to be an error; a correction value generation circuit 43A that receives a plurality of error signals ERROR(0) to (9) indicating the result of the error determination output from the plurality of decoders 42(0) to 42(9), and generates a second correction value θK containing information on data sequences that do not have errors according to the plurality of input error signals; and a byte alignment circuit 3 that selects and outputs a data sequence from a plurality of data sequences DATA(0) to DATA(9) output from the plurality of decoders 42(0) to 42(9) that corresponds to the first correction value DET-COM and the second correction value θK*.

[0128] In this receiving device, the first correction value DET-COM corresponds to the position of a special code indicating normal timing. The second correction value θK* contains information about data sequences that are free of errors, based on multiple error signals. The byte alignment circuit 3 selects and outputs data sequences corresponding to the first correction value DET-COM and the second correction value θK* from among multiple data sequences output from multiple decoders. If an error occurs before the reception of a special code due to external noise, etc., the byte alignment circuit selects and outputs data sequences without byte alignment misalignment according to the second correction value θK* generated by the correction value generation circuit 43A. This allows for early recovery to a normal data signal, even before the reception of a special code. If the data signal is an image data signal, image distortion can be quickly resolved. This receiving device can achieve early recovery from byte alignment misalignment with a simple configuration.

[0129] The receiving device described above includes a deserializer 1 that receives the serial data signal DATA-S transmitted from the transmitting device, converts it into a parallel data signal, and inputs it as a data signal DATA-P(E*) to the special code detection circuit 2. The deserializer can convert the serial data signal into a parallel data signal.

[0130] In the receiving device described above, byte alignment is performed not only by relying on special codes but also by using transmission code errors. Taking advantage of the redundant characteristics of the symbol mapping method, transmission code errors are detected on the receiving side. If the deserialized data is a block of incorrect data, the likelihood of deviating from DC balance and run-length rules increases, so if a byte alignment misalignment occurs, the error can be detected. By arranging transmission code error detectors longer than the code length and monitoring all possible blocks of parallel data during parallel conversion, the correct data delimiter can be detected, and byte alignment can be performed again before receiving special codes.

[0131] In the above configuration, 10 data sequences were prepared for simultaneous observation, but configurations using two or more sequences for detection are also possible. In the above configuration, when the data width (code length) is 10 bits, a data sequence was generated by concatenating 20 bits of data, but detection can also be performed with a data width of 11 bits (code length + simultaneously observed data sequences - 1) or more. In error detection, it is acceptable to determine that an error has occurred when a single error is detected, or to determine that an error has occurred and perform byte alignment only when several errors occur consecutively. Furthermore, in the above, channels deemed to be error-free were identified, but it is also acceptable to determine that the channel with the lowest error frequency among all channels is error-free. In the above configuration, bit shifting can only be adjusted in one direction, forward or backward, using the second correction value θK (or θK*). However, by shifting the parallel data signal DATA-P, which is the output of the byte alignment circuit, or by increasing the data width (code length) from 20 bits (when 10 bits were used) to 21 bits or more, it becomes possible to adjust the byte alignment in both directions using the second correction value θK (or θK*).

[0132] Furthermore, in the first receiving device, since the output of the 8b10b decoder is fixed, decoders not connected to the output can be configured as error detection units only. Although there is a feedback circuit, the circuit area can be made relatively smaller compared to the second receiving device. On the other hand, in the second receiving device, a selection circuit is placed at the output of the 8b10b decoder, and the feedback circuit for byte alignment can be omitted, resulting in a simpler configuration and superior maintainability and robustness. Bite alignment deviations caused by external noise can be corrected without waiting for a special code (comma character). As a result, noise can be suppressed to the pixel level, improving video display, and especially when transmitting image data signals to display devices of mobile devices such as automobiles, it can improve driver convenience. [Explanation of Symbols]

[0133] 1...Deserializer, 2...Special code detection circuit, 3...Byte alignment circuit, 4...Decoder, 21...Data sequence generation circuit, 22...Special code detection unit, 23...Correction value generation circuit, 31...Data sequence generation circuit, 32...Selection circuit, 41...Data sequence generation circuit, 42...8b10b decoder, 42E...8b10b error detector, 43,43A...Correction value generation circuit, 44...First selection circuit, 45...Second selection circuit, 201...Encoder, 202...Serializer, ERROR...Error signal, RX...Receiver, TX...Transmitter.

Claims

1. A special code detection circuit receives a data signal containing special codes encoded using a symbol mapping method and outputs a first correction value corresponding to the position of the special codes contained in the data signal. A byte alignment circuit receives the first correction value and the second correction value as inputs and performs byte alignment of the data signal according to the first correction value and the second correction value, A data sequence generation circuit generates multiple data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit, A decoder that decodes and outputs a specific data sequence from among the multiple data sequences output from the data sequence generation circuit, and also performs error detection on the specific data sequence. Multiple error detectors that determine each of the remaining data sequences other than the specific data sequence output from the data sequence generation circuit to be an error, A correction value generation circuit receives a plurality of error signals indicating the result of the error determination output from the decoder and a plurality of error detectors, and generates a second correction value that includes information on data sequences in which no errors have occurred, in accordance with the plurality of input error signals. Equipped with, A receiving device characterized by the following features.

2. Receive a data signal containing special codes encoded using a symbol mapping method. A special code detection circuit outputs a first correction value corresponding to the position of the special code contained in this data signal, A byte alignment circuit that performs byte alignment of the data signal according to the first correction value output from the special code detection circuit, A data sequence generation circuit generates multiple data sequences with different delimiter positions in the data sequence from the output signal of the byte alignment circuit, Multiple decoders that decode and determine the error of each of the multiple data sequences output from the data sequence generation circuit, A correction value generation circuit receives multiple error signals indicating the results of the error determination output from multiple decoders, and generates a second correction value that includes information on data sequences in which no errors occurred, in accordance with the multiple error signals that were input. A selection circuit that selects and outputs a data sequence corresponding to the second correction value from among a plurality of data sequences output from a plurality of decoders, Equipped with, A receiving device characterized by the following features.

3. The system further includes a deserializer that receives a serial data signal transmitted from a transmitting device, converts it into a parallel data signal, and inputs the resulting data signal to the special code detection circuit. The receiving device according to claim 1 or 2, characterized by the features described above.

4. The aforementioned bite alignment circuit is, Output a notification signal indicating that the byte alignment process is complete. When the notification signal is input to the correction value generation circuit, The selection circuit selects and outputs a data sequence from the decoder with the default setting among the decoders. The receiving device according to feature 2.

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