Error detection device and capture analysis method

Abstract

The present invention provides an error detection device and a capture analysis method that can capture data from very short blocks of signals transmitted by an object under test during link training. [Solution] The error detection device 100 includes a block designation unit 21 that designates one block from among the blocks of the test signal, a PPG 11 that transmits the test signal to the object under test during link training, an error detection unit 15 that outputs a synchronization establishment signal that is turned on during the period when the designated block included in the signal under test is detected, a trigger generation unit 16 that generates a trigger signal to start capturing the signal under test at the timing of the rising edge of the synchronization establishment signal, a capture unit 18 that captures data of the signal under test including at least a part of the designated block in response to the trigger signal, and a display control unit 22 that controls the display of the captured data of the signal under test on a display screen.

Description

Technical Field

[0001] The present invention relates to an error detection device and a capture analysis method.

Background Art

[0002] In the standards of high-speed serial buses such as PCIe (Registered Trademark) (Peripheral Component Interconnect Express), a sequence operation for controlling a link state management mechanism (Link Training and Status State Machine: LTSSM) and switching the state of a device is essential. By sending a plurality of prescribed data patterns (hereinafter referred to as "sequence blocks") to a device in the correct order, it becomes possible to arbitrarily change the state of the device.

[0003] For example, in PCIe, the state transition diagram of LTSSM is as shown in FIG. 9, and states such as L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery are defined.

[0004] In addition, a conventional error detection device for detecting an error in a measured signal controls the LTSSM of PCIe Gen (Generation) 1 to 6 by rapidly switching and outputting sequence blocks defined by the standard from a pulse pattern generator (PPG), and has a function (sequence pattern function) of transitioning to a specific state. Note that the patterns for causing the device under test (DUT) to transition states are defined by the standard, and the error detection device can output patterns from the PPG by combining the output order of those patterns by the sequence pattern function.

[0005] In patterns that transition LTSSM to a specific state, patterns such as EIEOS (Electrical Idle Exit Ordered Set), which is used for synchronization detection, and SKP OS (Skip Ordered Set), which is used to prevent data loss or duplication, are inserted at regular intervals within the sequence block. Errors in such sequence blocks can be detected by the error rate measuring device disclosed in Patent Document 1.

[0006] Incidentally, with the adoption of the PAM (Pulse Amplitude Modulation) 4 signal in PCIe Gen6, the previously taken-for-granted error-free operation is no longer possible, and error correction by FEC (Forward Error Correction) has become essential. Therefore, the importance of a capture analysis function that captures the measured signal and displays it on a screen is increasing. One example of a technology that can perform a capture analysis function is the error rate measurement device disclosed in Patent Document 2. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 7132964 [Patent Document 2] Patent No. 7579368 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, conventional error rate measurement devices, such as those disclosed in Patent Documents 1 and 2, have the problem of not being able to capture short sequence blocks during link training. Specifically, with conventional error rate measurement devices, when attempting to capture a desired sequence block, a human being must visually determine the timing and initiate the capture operation. However, it is practically impossible to initiate the capture operation for sequence blocks during link training, which have a transmission time of only a few tens of milliseconds.

[0009] The present invention has been made to solve the above-mentioned conventional problems, and aims to provide an error detection device and a capture analysis method that can capture data of very short blocks of segments contained in the signal transmitted by the object under test during link training. [Means for solving the problem]

[0010] To solve the above problems, the present invention provides an error detection device (100) that transmits a test signal to an object under test (200) equipped with a link state management mechanism, receives a signal under test that is reflected back from the object under test in conjunction with the transmission of the test signal, and detects errors in the signal under test, comprising: a block designation unit (21) that designates one block as a designated block from among a plurality of blocks constituting the test signal; a pattern generation unit (11) that transmits the test signal to the object under test during link training; and a synchronization detection unit that detects the synchronization pattern included in the designated block of the signal under test and outputs a synchronization detection signal indicating that the synchronization pattern has been detected. The system comprises a detection unit (13), an error detection unit (15) that detects the designated block after the synchronization detection unit outputs the synchronization detection signal and outputs a synchronization establishment signal that is ON during the period in which the designated block is detected, a trigger generation unit (16) that generates a trigger signal to start capturing the signal under measurement at the timing of the rising edge of the synchronization establishment signal, a capture unit (18) that captures data of the signal under measurement, including at least a part of the designated block, in response to the trigger signal, and a display control unit (22) that controls the display of the data of the signal under measurement captured by the capture unit on a display screen (60).

[0011] With this configuration, the error detection device according to the present invention automatically starts capturing the signal under test during the period in which it detects a specified block included in the signal under test. This allows it to capture data from a specified block during link training, where the transmission time from the object under test is very short. This makes it possible to analyze errors in sequence blocks over very short intervals.

[0012] Furthermore, the error detection device according to the present invention may be configured such that the display control unit displays the data of the signal under measurement captured by the capture unit, divided by the data length of a specific pattern included in the synchronization pattern.

[0013] With this configuration, the error detection device according to the present invention displays the captured data of the signal under measurement in sections of a specific pattern length, making it possible to display a specific pattern within the capture range in an easy-to-understand manner.

[0014] Furthermore, the error detection device according to the present invention may be configured such that the pattern generation unit is capable of generating the test signal encoded using one of the following encoding methods: 8b / 10b encoding, 128b / 130b encoding, or 1b / 1b encoding. If the test signal is encoded using the 8b / 10b encoding method, the specific pattern is K28.5(COM). If the test signal is encoded using the 128b / 130b encoding method or the 1b / 1b encoding method, the specific pattern is EIEOSQ (Electrical Idle Exit Ordered Set Sequence).

[0015] Furthermore, the capture analysis method according to the present invention is a capture analysis method that uses an error detection device (100) which transmits a test signal to an object under test (200) equipped with a link state management mechanism, receives a signal under test that is reflected back from the object under test in conjunction with the transmission of the test signal, and detects errors in the signal under test, comprising: a block designation step (S1) which designates one block as a designated block from among a plurality of blocks constituting the test signal; a pattern generation step (S3) which transmits the test signal to the object under test during link training; and a synchronization detection step (S3) which detects the synchronization pattern included in the designated block of the signal under test and outputs a synchronization detection signal indicating that the synchronization pattern has been detected. The configuration includes: 4, S5) a synchronization establishment step (S6, S8) which, after the synchronization detection signal is output by the synchronization detection step, detects the designated block and outputs a synchronization establishment signal that is ON during the period in which the designated block is detected; a trigger generation step (S9) which generates a trigger signal to start capturing the signal under measurement at the timing of the rising edge of the synchronization establishment signal; a capture step (S10) which captures data of the signal under measurement, including at least a part of the designated block, in response to the trigger signal; and a display control step (S11) which controls the display of the data of the signal under measurement captured by the capture step on the display screen (60). [Effects of the Invention]

[0016] The present invention provides an error detection device and a capture analysis method that can capture data from very short blocks of signals transmitted by an object under test during link training. [Brief explanation of the drawing]

[0017] [Figure 1] This is a block diagram showing the configuration of an error detection device according to an embodiment of the present invention. [Figure 2] This is a time chart diagram of the test signal, the signal under measurement, and the synchronization establishment signal. [Figure 3]It is a diagram showing an example of a pattern setting screen. [Figure 4] It is a diagram showing an example of a capture setting screen. [Figure 5] It is a diagram showing an example of a capture display screen for an 8b / 10b encoding method. [Figure 6] It is a diagram showing an example of a capture display screen for a 128b / 130b encoding method. [Figure 7] It is a diagram showing an example of a capture display screen for a 1b / 1b encoding method. [Figure 8] It is a flowchart showing the processing of a capture analysis method using an error detection device according to an embodiment of the present invention. [Figure 9] It is a diagram showing the state transition of LTSSM.

Mode for Carrying Out the Invention

[0018] Hereinafter, embodiments of an error detection device and a capture analysis method according to the present invention will be described with reference to the drawings.

[0019] The error detection device according to the present invention is a device that transmits a test signal to a DUT equipped with LTSSM, receives the measured signal reflected from the DUT along with the transmission of this test signal, and detects an error (error) in the measured signal.

[0020] As shown in FIG. 1, the error detection device 100 according to the present embodiment includes a PPG 11, an error detector (ED) 12, a control unit 20, a storage unit 30, a display unit 31, and an operation unit 32.

[0021] The DUT 200 is equipped with LTSSM, and a sequence block for transitioning LTSSM to each state as shown in FIG. 9, for example, is input as a test signal from the PPG 11 as a pattern generation unit described later. Examples of the standards corresponding to the DUT 200 include PCIe Gen1 to 6.

[0022] The storage unit 30 is composed of memory such as RAM (Random Access Memory) and stores data of specific patterns included in the test signal, data of the measured signal captured by the capture unit 18 (described later), and error detection results from the error detection unit 15 (described later). The storage unit 30 also stores sequence blocks transmitted from the PPG 11 in advance in file units.

[0023] As shown in Figure 1, ED12 includes a synchronization detection unit 13, a reference generation unit 14, an error detection unit 15, a trigger generation unit 16, and a capture unit 18. ED12 is configured, for example, by an FPGA (Field Programmable Gate Array).

[0024] PPG11 transmits a sequence block (hereinafter simply referred to as "block") to DUT200 as a test signal during link training, which is used to transition DUT200's LTSSM to any desired state. PPG11 can also generate test signals encoded using one of the following encoding methods: 8b / 10b, 128b / 130b, or 1b / 1b.

[0025] As shown in Figure 2, the test signal consists of multiple serial blocks (for example, #2~#6, #8~#12, #14~#18 in the figure). The data content of each block of the test signal transmitted from PPG11 can be set on the pattern setting screen 42, which will be described later.

[0026] Figure 2 is a time chart of the test signal, the signal under test, and the synchronization establishment signal output from the error detection unit 15, when block #15 is specified by the block designation unit 21, which will be described later. The ON state of the synchronization establishment signal indicates that synchronization has been established for the designated block of the signal under test, and the OFF state of the synchronization establishment signal indicates that synchronization has been lost for the designated block of the signal under test. In other words, in the example shown in Figure 2, a pulse-like synchronization establishment signal with a width of t2-t1 is output from the error detection unit 15 to the trigger generation unit 16 during the period when synchronization of the designated block is established (time t1-t2 in the figure).

[0027] The synchronization detection unit 13 has the function of detecting the synchronization pattern included in the designated block of the signal under measurement, which is specified by the block designation unit 21 described later. The synchronization detection unit 13 outputs a synchronization detection signal indicating that a synchronization pattern has been detected before the above-mentioned time t1 (for example, several μs before). The synchronization pattern consists of, for example, the first 64 bits of a specific pattern included in the designated block of the signal under measurement and a known pattern that follows it.

[0028] The trigger generation unit 16 has the function of generating a trigger signal to start capturing the signal under measurement. For example, the trigger generation unit 16 outputs a trigger signal of the type selected by the "Trigger" input box 56 in the capture setting screen 52, which will be described later.

[0029] For example, when "Sync Mode Capture" is selected in the "Capture Mode" input box 53 and "Match Pattern" is selected in the "Trigger" input box 56, the trigger generation unit 16 generates a trigger signal to start capturing the measured signal at the rising edge of the synchronization establishment signal, after the synchronization detection signal has been output.

[0030] In this embodiment, if the test signal is a PCIe Gen1 or Gen2 compliant signal encoded using the 8b / 10b encoding method, the COM pattern K28.5(COM), where the K code is K28.5, can be used as the specific pattern. If the test signal is a PCIe Gen3 or Gen5 compliant signal encoded using the 128b / 130b encoding method, or if the test signal is a PCIe Gen6 compliant signal encoded using the 1b / 1b encoding method, EIEOSQ can be used as the specific pattern.

[0031] The capture unit 18 has a RAM area that sequentially updates and stores the data of the signal under test received by the ED12 from the DUT200. This RAM area has a capacity of, for example, about 8M bits. The capture unit 18 has a function to capture the data of the signal under test that is temporarily stored in the RAM area in response to a trigger signal output from the trigger generation unit 16. The data of the signal under test captured by the capture unit 18 (hereinafter also referred to as "capture data") includes at least a portion of the data of a designated block and is stored in the storage unit 30 by the control unit 20.

[0032] The reference generation unit 14 has the function of generating a reference signal that is identical to the specified block of the signal under test and synchronized with the specified block of the signal under test, triggered by the rising edge of the synchronization detection signal output from the synchronization detection unit 13.

[0033] The error detection unit 15 has the function of detecting errors in the signal under test and calculating the error rate of the signal under test by sequentially comparing the data of the reference signal output from the reference generation unit 14 with the signal under test. These results are stored in the storage unit 30 by the control unit 20.

[0034] The error detection unit 15 outputs an error detection signal to the capture unit 18, indicating that an error has been detected in the signal being measured. This makes it possible to highlight the bit or symbol containing the error on the capture display screen 60, which will be described later.

[0035] Furthermore, the error detection unit 15 detects a designated block included in the signal under measurement after the synchronization detection unit 13 outputs a synchronization detection signal, and outputs a synchronization establishment signal that is ON during the period in which the designated block is detected.

[0036] If the error detection unit 15 fails to detect the specified block after outputting the synchronization detection signal, it outputs a resynchronization request signal to the synchronization detection unit 13, causing the synchronization detection unit 13 to detect the synchronization pattern again.

[0037] The error detection unit 15 switches the synchronization establishment signal from the off state to the on state when the error rate of the signal under test falls below a predetermined value. This switch from the off state to the on state occurs, for example, a few microseconds after the specified block of the signal under test is input to the error detection unit 15. The error detection unit 15 then switches the synchronization establishment signal from the on state to the off state when the error rate of the signal under test exceeds a predetermined value. In the example in Figure 2, the synchronization establishment signal turns off when the data of block #16 begins to be input to the error detection unit 15.

[0038] The display unit 31 consists of various setting screens and display screens, as well as display devices such as an LCD (Liquid Crystal Display) that displays a GUI (Graphical User Interface) such as soft keys.

[0039] The operation unit 32 is for receiving user input and consists of, for example, operation knobs, various keys, switches, and buttons provided on the main body of the error detection device 100, as well as a user interface such as a touch panel, mouse, or keyboard for operating the GUI of the display unit 31.

[0040] The control unit 20 is composed of a control device such as a computer, which includes a CPU (Central Processing Unit), GPU (Graphics Processing Unit), ROM (Read Only Memory), RAM, and HDD (Hard Disk Drive). The control software controls the display unit 31 and the operation unit 32, as well as the PPG 11 and ED 12. The control software has a GUI and processes user input in the operation unit 32 and displays information to the user in the display unit 31.

[0041] Furthermore, the control unit 20 includes a block designation unit 21 and a display control unit 22.

[0042] The block designation unit 21 has the function of designating one block as the designated block from among multiple blocks that constitute the signal under measurement. For example, as shown in Figure 2, one block #15 can be designated as the designated block by the block designation unit 21 from among multiple blocks #2 to #6, #8 to #12, and #14 to #18 of the signal under measurement. The designation of a designated block by the block designation unit 21 can be done, for example, by entering the file name of the file containing the data of the desired block in the "File Name" input box 57 of the capture setting screen 52, which will be described later, as shown in Figure 4.

[0043] The display control unit 22 has the function of displaying various information necessary for capturing the signal under measurement, as well as data of the signal under measurement captured by the capture unit 18, on the display unit 31.

[0044] Figure 3 shows the pattern setting screen 42 displayed by the display unit 31 when the "Pattern" tab 41a is pressed by the operation unit 32 in the screen selection tab 41 of the PPG setting screen 40 displayed by the display unit 31.

[0045] The pattern setting screen 42 includes an input box 43 for "Specification," a soft key 44 for "Transmit," and a sequence block display area 45.

[0046] The "Specification" input box 43 displays PCIe Gen1 to 6 as a pull-down menu, allowing you to select the desired standard in this input box 43. In the pattern setting screen 42 in Figure 3, an example is shown where "PCIe6," which indicates PCIe Gen6, is selected.

[0047] The "Transmit" soft key 44 is a soft key used to instruct the start of transmission of a test signal from the PPG11.

[0048] The sequence block display area 45 is configured to display the data content of each block of the test signal transmitted from the PPG11 in a changeable manner.

[0049] Figure 4 shows the capture settings screen 52 displayed by the display unit 31 when the "Capture" tab 51a is pressed by the operation unit 32 in the screen selection tab 51 of the ED setting screen 50 displayed by the display unit 31.

[0050] The capture settings screen 52 includes an input box 53 for "Capture Mode," a soft key 54 for "Capture," an input box 55 for "Capture Area," an input box 56 for "Trigger," and an input box 57 for "File Name."

[0051] The input box 53 for "Capture Mode" displays options such as "Sync Mode Capture" and "Raw Data Capture" in a pull-down menu format, allowing you to select one of the modes using this input box 53. Figure 4 shows an example where "Sync Mode Capture" is selected in the capture settings screen 52.

[0052] "Sync Mode Capture" is a mode that checks for errors in the signal being measured, and requires the synchronization establishment signal to be ON. "Raw Data Capture" is a mode that does not check for errors in the signal being measured, and does not require the synchronization establishment signal to be ON.

[0053] The "Capture" soft key 54 is a soft key used to instruct the trigger generation unit 16 to generate a trigger signal. The "Capture" soft key 54 can be pressed whether the synchronization establishment signal is on or off. However, the timing at which the trigger generation unit 16 generates the trigger signal changes depending on the settings in the "Trigger" input box 56, which will be described later.

[0054] The input box 55 for "Capture Area" displays a pull-down menu with options such as "After the Trigger," "Around the Trigger," and "Before the Trigger," allowing you to select one of these capture areas using this input box 55. Figure 4 shows an example where "Around the Trigger" is selected in the capture settings screen 52.

[0055] "After the Trigger" instructs the capture unit 18 to capture the signal under test from the moment the trigger signal is generated by the trigger generation unit 16. "Around the Trigger" instructs the capture unit 18 to capture the signal under test before and after the moment the trigger signal is generated by the trigger generation unit 16. "Before the Trigger" instructs the capture unit 18 to capture the signal under test before the moment the trigger signal is generated by the trigger generation unit 16.

[0056] The "Trigger" input box 56 displays a pull-down menu with options such as "Sync Gain," "Error Detect," "Manual," "Match Pattern," and "External Trigger" as the types of trigger signals generated by the trigger generation unit 16. One of these trigger signals can be selected using this input box 56. Figure 4's capture settings screen 52 shows an example where "Match Pattern" is selected.

[0057] "Sync Gain" is a trigger signal generated by the trigger generation unit 16 at the timing when the error detection unit 15 detects a specified block of the signal under measurement, that is, at the rising edge of the synchronization establishment signal. If the "Capture" soft key 54 is pressed while the synchronization establishment signal is already ON, the trigger generation unit 16 immediately generates a trigger signal. Note that "Sync Gain" can only be selected when "Sync Mode Capture" is selected in the "Capture Mode" input box 53.

[0058] "Error Detect" is a trigger signal generated by the trigger generation unit 16 at the rising edge of the error detection signal, which indicates that the error detection unit 15 has detected an error in the signal under measurement during the period when the synchronization establishment signal is ON. Note that "Error Detect" can only be selected when "Sync Mode Capture" is selected in the "Capture Mode" input box 53.

[0059] "Manual" is a trigger signal generated by the trigger generation unit 16 at the timing of the rising edge of the manual input signal indicating that the user has pressed the "Capture" soft key 54.

[0060] "Match Pattern" is a trigger signal generated by the trigger generation unit 16 after the synchronization detection signal is turned ON.

[0061] "External Trigger" is a trigger signal generated by the trigger generation unit 16 at the timing of the rising edge of an external signal.

[0062] The "File Name" input box 57 allows you to enter the filename of the file containing the data of the block you want to designate from among the multiple blocks that make up the signal under measurement. Figure 4 shows an example where the filename of the data for block #15 in Figure 3, "PCIe6_RECOVERY_EQUALIZATION_PHASE1_TS0_EC01", has been entered. Note that all the data for all the blocks shown in Figure 3 are different.

[0063] Figures 5 to 7 show the capture display screen 60 displayed by the display unit 31. Since PCIe sequence blocks use different encoding methods depending on their Gen, the capture display screen 60 displays the capture according to the Gen.

[0064] Figure 5 shows the captured display screen 60 when the test signal is a PCIe Gen1 or Gen2 compliant signal encoded using the 8b / 10b encoding method.

[0065] In the left-hand area of ​​the capture display screen 60 in Figure 5, a data display area 61 is provided for displaying the captured data from the capture unit 18. The data display area 61 displays the captured data, divided by the data length of a specific pattern included in the synchronization pattern.

[0066] At this time, the display control unit 22 searches for a specific pattern corresponding to the PCIe Gen in the captured data, and based on the searched specific pattern, displays the captured data in the data display area 61, divided by the data length of the specific pattern. Furthermore, if the beginning and end of the captured data are less than the data length of the specific pattern, the display control unit 22 discards that data before displaying the captured data in the data display area 61.

[0067] In the right-hand area of ​​the capture display screen 60 in Figure 5, the "Viewer Mode" used for debugging purposes is displayed. In the "Notation" input box 63 of "Viewer Mode," "Bin," "Hex (Byte)," "Symbol (PAM4)," etc. are displayed as pull-down menus for the notation of the data to be displayed on the capture display screen 60, and one of these notations can be selected in this input box 63.

[0068] The "LSB First" radio button 64a and the "MSB First" radio button 64b allow the user to select whether to display the captured data in the data display area 61 in reverse order relative to the order in which the data was received by the ED12, or to display the captured data in the data display area 61 in the same order relative to the order in which the data was received by the ED12.

[0069] Below "Viewer Mode" on the capture display screen 60, "Error - Raw Signal" is displayed. In "Error - Raw Signal," checkboxes 65 (65a, 65b, 65c) are displayed to color-code the bits that had errors in the data display area 61 according to their transition state.

[0070] Specifically, checking the "INS" checkbox 65a will display bits or symbols with insertion errors (changing from 0 to 1) in red, and checking the "OMI" checkbox 65b will display bits or symbols with omission errors (changing from 1 to 0) in yellow. Additionally, when "Hex (Byte)" or "Symbol (PAM4)" is selected in the "Notation" input box 63, checking the "INS / OMI" checkbox 65c will display symbols with both insertion and omission errors in blue.

[0071] In Figure 5, "Bin" is selected in the "Notation" input box 63 of "Viewer Mode," so the data display area 61 displays the captured data in multiple rows, with the vertical axis representing the address and the horizontal axis representing the bits.

[0072] The specific patterns shown in the data display area 61 of Figure 5 are the COM(+) "0011111010" enclosed in thick border A and the COM(-) "1100000101" enclosed in thick border B, and the entire data within the data display area 61 is divided by the 10-bit data length of the COM pattern.

[0073] Figure 6 shows the captured display screen 60 when the test signal is a PCIe Gen3 to Gen5 compliant signal encoded using the 128b / 130b encoding method. In the captured display screen 60 of Figure 6, the same reference numerals are used for components that are the same as those in Figure 5, and their descriptions are omitted.

[0074] In Figure 6, "Hex (Byte)" is selected in the "Notation" input box 63 of "Viewer Mode". Therefore, the data display area 61 displays the captured data in multiple rows, with the vertical axis representing the address and the horizontal axis representing the header and 8-bit symbols.

[0075] The specific pattern shown in the data display area 61 of Figure 6 is the EIEOSQ pattern, enclosed in a thick border C, and the entire data is separated by a 2-bit header and a 128-bit data length for the EIEOSQ pattern. The EIEOSQ pattern is "00FF_00FF_00FF_00FF_00FF_00FF_00FF_00FF" for PCIe Gen3, "0000_FFFF_0000_FFFF_0000_FFFF_0000_FFFF" for PCIe Gen4, and "0000_0000_FFFF_FFFF_0000_0000_FFFF_FFFF" for PCIe Gen5. Figure 6 shows the EIEOSQ pattern for PCIe Gen5 as an example.

[0076] Figure 7 shows the captured display screen 60 when the test signal is a PCIe Gen6 compliant signal encoded using the 1b / 1b encoding method. In the captured display screen 60 of Figure 7, the same reference numerals are used for components that are the same as those in Figure 5, and their descriptions are omitted.

[0077] In Figure 7, "Symbol (PAM4)" is selected in the "Notation" input box 63 of "Viewer Mode". Therefore, the data display area 61 displays the captured data in multiple rows, with the vertical axis representing the address and the horizontal axis representing 2-bit symbols.

[0078] The specific pattern shown in the data display area 61 of Figure 7 is the EIEOSQ pattern, enclosed in a thick border D, and the entire data is divided into 128-bit segments, which is the data length of the EIEOSQ pattern. In PCIe Gen6, the EIEOSQ pattern is "0000_0000_0000_0000_FFFF_FFFF_FFFF_FFFF".

[0079] Below, an example of the capture analysis method using the error detection device 100 of this embodiment will be described with reference to the flowchart in Figure 8. Note that explanations that overlap with the above-described explanation of the configuration of the error detection device 100 will be omitted as appropriate.

[0080] First, the user makes various settings necessary for capturing the signal under measurement, such as setting the test signal standard, the specified block for the test signal, and the type of trigger signal, on the pattern setting screen 42 and the capture setting screen 52 (block specification step S1). When the test signal standard is set in step S1, a specific pattern corresponding to the standard is also set at the same time.

[0081] Next, the user presses the "Capture" soft key 54 on the capture settings screen 52 (step S2). As a result, the error detection unit 15 starts waiting for the specified block set in the "File Name" input box 57.

[0082] Next, when the user presses the "Transmit" soft key 44 on the pattern setting screen 42, the PPG11 starts transmitting a test signal (pattern generation step S3).

[0083] Next, if the synchronization detection unit 13 detects a synchronization pattern included in the specified block of the signal under measurement (synchronization detection step S4: YES), the process of step S5 is executed.

[0084] In step S5, the synchronization detection unit 13 outputs a synchronization detection signal indicating that a synchronization pattern has been detected (synchronization detection step S5).

[0085] Next, the error detection unit 15 determines whether or not the specified block has been detected (synchronization establishment step S6). For example, if the number of errors in 10,000 bits of data consecutive to the synchronization pattern is 10 or less, the error detection unit 15 determines that the specified block has been detected (step S6: YES), and the process in step S8 is executed. If the specified block is not detected in the synchronization establishment step S6 (step S6: NO), the process in step S7 is executed.

[0086] In step S7, the error detection unit 15 outputs a resynchronization request signal to the synchronization detection unit 13. As a result, the process in step S4 is executed again.

[0087] In step S8, the error detection unit 15 outputs a synchronization establishment signal that is ON during the period in which the specified block is detected (synchronization establishment step S8).

[0088] Next, the trigger generation unit 16 generates a trigger signal at the timing of the rising edge of the synchronization establishment signal (trigger generation step S9).

[0089] Next, when the capture unit 18 receives the trigger signal from the trigger generation unit 16, it captures data of the signal under measurement, including at least a portion of the specified block, in the capture area set in the input box 55 of "Capture Area" on the capture setting screen 52 (capture step S10).

[0090] Next, the display control unit 22 displays the data of the measured signal captured in the capture step S10 on the capture display screen 60 (display control step S11).

[0091] As described above, the error detection device 100 according to this embodiment automatically starts capturing the signal under test during the period in which it detects a specified block included in the signal under test. Therefore, it can capture data of a specified block during link training, when the transmission time from the DUT 200 is very short. This makes it possible to analyze errors in sequence blocks over very short intervals.

[0092] Furthermore, the error detection device 100 according to this embodiment divides the captured data of the signal under measurement into sections based on a specific pattern length and displays it, making it possible to display a specific pattern within the capture range in an easy-to-understand manner. [Explanation of Symbols]

[0093] 11 PPG (Pattern Generation Unit) 12 ED 13 Synchronization detection unit 14. Reference Generation Unit 15 Error detection unit 16 Trigger generation unit 18 Capture section 20 Control Unit 21 Block designation section 22 Display Control Unit 30 Storage section 31 Display section 32 Operation section 60 Capture display screen (display screen) 100 Error detection device 200 DUTs (samples to be measured)

Claims

1. An error detection device (100) that transmits a test signal to an object under test (200) equipped with a link state management mechanism, receives a signal under test that is reflected back from the object under test in conjunction with the transmission of the test signal, and detects an error in the signal under test, A block designation unit (21) that designates one block as a designated block from among a plurality of blocks that constitute the test signal, A pattern generation unit (11) transmits the aforementioned test signal to the object under test during link training, A synchronization detection unit (13) detects the synchronization pattern included in the designated block of the signal under measurement and outputs a synchronization detection signal indicating that the synchronization pattern has been detected, After the synchronization detection unit outputs the synchronization detection signal, the error detection unit (15) detects the designated block and outputs a synchronization establishment signal that is ON during the period in which the designated block is detected, A trigger generation unit (16) generates a trigger signal to start capturing the signal under measurement at the timing of the rising edge of the synchronization establishment signal, A capture unit (18) captures data of the signal under measurement, including at least a portion of the designated block, in response to the trigger signal. An error detection device comprising a display control unit (22) that controls the display of the data of the signal to be measured, captured by the capture unit, on a display screen (60).

2. The error detection device according to claim 1, characterized in that the display control unit displays the data of the signal to be measured, captured by the capture unit, divided by the data length of a specific pattern included in the synchronization pattern.

3. The pattern generation unit is capable of generating the test signal encoded using one of the following encoding methods: 8b / 10b encoding, 128b / 130b encoding, or 1b / 1b encoding. If the test signal is encoded using the 8b / 10b encoding method, the specific pattern is K28.5 (COM), The error detection device according to claim 2, characterized in that, when the test signal is a signal encoded using a 128b / 130b encoding method or a 1b / 1b encoding method, the specific pattern is EIEOSQ.

4. A capture analysis method using an error detection device (100) that transmits a test signal to an object under test (200) equipped with a link state management mechanism, receives a signal under test that is reflected back from the object under test in conjunction with the transmission of the test signal, and detects errors in the signal under test, wherein A block designation step (S1) is performed to designate one block as a designated block from among the multiple blocks that constitute the test signal, A pattern generation step (S3) in which the test signal is transmitted to the object under test during link training, A synchronization detection step (S4, S5) detects the synchronization pattern included in the designated block of the signal under measurement and outputs a synchronization detection signal indicating that the synchronization pattern has been detected, After the synchronization detection signal is output by the synchronization detection step, the synchronization establishment step (S6, S8) detects the designated block and outputs a synchronization establishment signal that is ON during the period in which the designated block is detected, A trigger generation step (S9) is performed to generate a trigger signal for starting the capture of the signal under measurement at the timing of the rising edge of the synchronization establishment signal, A capture step (S10) in which data of the signal to be measured, including at least a portion of the designated block, is captured in response to the trigger signal, A capture analysis method characterized by including a display control step (S11) for displaying the data of the signal to be measured captured in the capture step on a display screen (60).

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