Projection device and method for controlling the projection device

Abstract

To prevent the occurrence of contradiction in display caused by a shift of optical paths.SOLUTION: A projection apparatus includes a display panel that includes a plurality of OLEDs emitting rays of light in a predetermined direction, and an optical path shift element that shifts optical paths of the rays of light emitted from the light-emitting devices. In a light-emission sub frame L_f1, the display panel turns on the plurality of OLEDs, in a vertical scanning retrace period Vblnk, it turns off the plurality of OLEDs, and in a light-emission sub frame L_f2, it turns on the plurality of OLEDs. In the light-emission sub frames L_f1 and L_f2, the optical path shift element fixes the optical paths, and in vertical scanning retrace period Vblnk, it shifts the optical paths.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] The present invention relates to, for example, a projection device and a control method for a projection device.

Background Art

[0002] In a projection device that enlarges and projects the display image of a display panel onto a screen or the like, a technique of shifting the optical path of light emitted from the display panel by an optical path shift element is known (see, for example, Patent Documents 1 and 2). By this technique, it is possible to allow a user to visually recognize an image in which the resolution of the display panel is pseudo-increased.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a display panel, line sequential driving is mainstream, and the display content is switched every writing of a scanning line. On the other hand, according to the shift of the optical path by the optical path shift element, the entire image is shifted. For this reason, for example, when writing is being executed near the center of the screen and the optical path is shifted, the upper half of the screen is after the switching of the display content, while the lower half of the screen is before the switching of the display content, so that the image before the switching and the image after the switching are visually recognized mixedly. In addition, in a configuration in which the optical path is shifted after the completion of horizontal scanning, in order to secure a period for visually recognizing the image after switching, it is necessary to complete the writing of all scanning lines in a short time, which causes insufficient writing.

Means for Solving the Problems

[0005] A projection apparatus according to one aspect of the present disclosure includes a display panel including a plurality of light-emitting elements that emit light in a predetermined direction, and an optical path shift element that shifts the optical path of the light emitted from the plurality of light-emitting elements, wherein the display panel emits light in accordance with the shift of the optical path. [Brief explanation of the drawing]

[0006] [Figure 1] This is a diagram showing the configuration of the projection device according to the first embodiment. [Figure 2] This is a perspective view showing the configuration of a display panel applied to a projection system. [Figure 3] These are examples of panel pixels and sub-panel pixels in a projection system. [Figure 4] This block diagram shows the electrical configuration of a projection device. [Figure 5] This is a diagram showing the frame configuration in a projection device. [Figure 6] This diagram shows the correspondence between input pixels and panel pixels. [Figure 7] This figure shows the relationship between each subframe and the optical path shift. [Figure 8] This is a diagram showing projected pixels by a projection device. [Figure 9] This diagram shows the number of projected pixels visible in one frame (F). [Figure 10] This is a block diagram showing the electrical configuration of the display panel. [Figure 11] This diagram shows the pixel circuit in a display panel. [Figure 12] This is a timing chart showing the control signals for the optical path shift element. [Figure 13] This is a timing chart showing the operation of display panels and other components. [Figure 14] This is a timing chart showing the operation of display panels and other components. [Figure 15] This figure shows the equivalent circuit of the pixel circuit in the first embodiment. [Figure 16] This is a diagram for explaining the image to be projected. [Figure 17] This is a diagram for explaining the improvement of display quality according to an embodiment. [Figure 18] This is a diagram showing the pixel circuit of a display panel according to a second embodiment. [Figure 19] This is a timing chart showing the operation of a display panel or the like. [Figure 20] This is a timing chart showing the operation of a display panel or the like. [Figure 21] This is a diagram showing the equivalent circuit of the pixel circuit in the second embodiment. [Figure 22] This is an example of panel pixels and sub-panel pixels in a projection device according to a third embodiment. [Figure 23] This is a diagram showing the configuration of a projection device according to a fourth embodiment. [Figure 24] This is a diagram showing the projection pixels of a projection device. [Figure 25] This is a diagram showing the projection pixels visually recognized in one frame F. [Figure 26] This is a timing chart showing the control signal or the like of an optical path shift element according to a modification. [Figure 27] This is a timing chart showing the operation of a display panel according to a first comparative example. [Figure 28] This is a timing chart showing the operation of a display panel according to a second comparative example.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, a display panel according to an embodiment of the present invention will be described with reference to the drawings. In each figure, the dimensions and scales of each part are appropriately different from the actual ones. In addition, since the embodiments described below are preferred specific examples, various technically preferable limitations are imposed. However, the scope of the present invention is not limited to these embodiments unless there is a description to specifically limit the present invention in the following description.

[0008] <First Embodiment> Figure 1 is a diagram showing the configuration of a projection device 1 according to the first embodiment, and Figure 2 is a perspective view showing the configuration of a display panel 10 applied to the projection device 1. This projection device 1 enlarges and projects a color image created by the display panel 10 onto a screen Scr. The display panel 10 is equipped with a light-emitting element, and the projection device 1 does not require a separate light source and can be miniaturized. Furthermore, the projection device 1 can display high-resolution color images using an optical path shift element 20. The display panel 10 is a microdisplay that creates a color image. In this embodiment, a single-panel display panel with an OLED light-emitting element is used as the display panel 10. OLED stands for Organic Light Emitting Diode. In the display panel 10, multiple pixel circuits and drive circuits for driving these pixel circuits are formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but other semiconductor substrates may also be used.

[0009] As shown in Figure 1, the light emitted from the display panel 10 enters the optical path shift element 20. The projection lens 34 projects the projected image Img, which has passed through the optical path shift element 20, onto the screen Scr, enlarging it. The optical path shift element 20 shifts the light emitted from the display panel 10. More specifically, the optical path shift element 20 can shift the projected image Img onto the screen Scr in the left-right and up-down directions, as viewed from the screen Scr, which is the projection surface, according to the control described later.

[0010] For the sake of clarity, it is necessary to distinguish between the pixels of the projected image Img onto the screen Scr and the pixels displayed by the display panel 10. Therefore, in this explanation, the pixels of the projected image Img onto the screen Scr will be referred to as projected pixels, and the pixels displayed by the display panel 10 will be referred to as panel pixels. In the diagram, the X direction refers to the left direction when viewing the projected image Img on the screen Scr, the Y direction refers to the downward direction when viewing the projected image Img on the screen Scr, and the Z direction refers to the direction of emission by the projection lens 34.

[0011] As shown in Figure 2, the display panel 10 is housed in a frame-shaped case 192 having an opening 191. One end of an FPC board 194 is connected to the display panel 10. FPC stands for Flexible Printed Circuits. Multiple terminals 196 are provided on the other end of the FPC board 194. These multiple terminals 196 are connected to the video processing circuit, which will be described next.

[0012] In the first embodiment, the X direction is the horizontal direction of the display pixels in the display panel 10 and coincides with the direction of the scanning lines, and the Y direction is the vertical direction of the display pixels and coincides with the direction of the data lines. In this embodiment, the Z direction coincides with the direction of light emission from the OLED.

[0013] Figure 3 shows the configuration of panel pixels 11 in the display panel 10. As shown in this figure, one panel pixel 11 is composed of a red sub-panel pixel 11R, a green sub-panel pixel 11G, and a blue sub-panel pixel 11B. In the display panel 10, the panel pixels 11 are approximately square in shape when viewed from above, and are arranged with a pitch p in the X direction (horizontal direction) and Y direction (vertical direction). Furthermore, the symbol 11b represents the centroid of the panel pixel 11. In Figure 3, the centroid 11b is the central position of the panel pixel 11, and also the central position of the green sub-panel pixel 11G. As will be explained in more detail later, the panel pixels 11 in the display panel 10 are arranged in a matrix with m rows and n columns. m and n are both integers of 2 or greater.

[0014] Figure 4 is a block diagram showing the electrical configuration of the projection device 1. As shown in the figure, the projection device 1 includes the display panel 10 and optical path shift element 20 described above, as well as an image processing circuit 40.

[0015] The video processing circuit 40 receives video data Vde-in from the host device 5, synchronized with the synchronization signal Sync. The video data Vde-in is data indicating the image to be displayed on the projection device 1, and in detail, it specifies the gradation level of the color image in one frame of the image, for example, using 8 bits each for red (R), green (G), and blue (B). For the sake of explanation, the pixels of the color image indicated by the video data Vde-in will be referred to as input pixels. The Sync synchronization signal includes a vertical synchronization signal that instructs the start of vertical scanning in the video data Vid-in, a horizontal synchronization signal that instructs the start of horizontal scanning, and a clock signal that indicates the timing of one pixel in the video data Vid-in.

[0016] In this embodiment, the arrangement of display pixels specified by the video data Vde-in is twice as large in the vertical direction and twice as large in the horizontal direction compared to the arrangement of panel pixels in the display panel 10. Specifically, the input pixels are arranged in a vertical (2m) row × horizontal (2n) column configuration.

[0017] In this embodiment, the four input pixels specified in the video data Vde-in are represented by one panel pixel in the display panel 10. Therefore, we will first explain the specific method for achieving this.

[0018] In this embodiment, in order to make the projected image visible at a resolution higher than the resolution of the panel pixels, the optical path shift element 20 shifts the optical path (position of the projected pixels) emitted from the display panel 10. Specifically, when displaying an image of one frame using video data Vde-in, the period for displaying that one frame is divided into four subframes, and the position of the projected pixels is shifted for each subframe. Due to this shift, one panel pixel appears as if four input pixels are being displayed in one frame (four subframes).

[0019] Figure 5 is a diagram illustrating the relationship between frames and subframes in this embodiment. As shown in this figure, in this embodiment, one frame F is divided into four subframes, and these four subframes are assigned the symbols f1, f2, f3, and f4 in chronological order. As will be described later, f1, f2, f3, and f4 correspond to the shift positions (1), (2), (3), and (4) of the projected pixels, respectively. The duration of frame F is 16.7 milliseconds, assuming the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz. In this case, the duration of subframes f1 to f4 is 4.17 milliseconds each.

[0020] This section explains the relationship between the input pixels, whose grayscale level is specified in the video data Vde-in, the panel pixels of the display panel 10, and the position of the projected pixels shifted by the optical path shift element 20. As mentioned above, the optical path shift element 20 shifts the projected image Img onto the screen Scr in the left-right and up-down directions. For convenience, the amount of this shift will be explained in terms of the size of the projected pixels or panel pixels on the screen Scr.

[0021] The left column in Figure 6 shows a portion of the video data Vde-in. The right column in Figure 6 shows the pixel array corresponding to the input pixel array in the left column. In the arrangement of input pixels for the video data Vde-in shown in Figure 6, for convenience, the following codes are assigned to each row: A1-A6 in the first row, B1-B6 in the second row, C1-C6 in the third row, D1-D6 in the fourth row, E1-E6 in the fifth row, and F1-F6 in the sixth row. In the arrangement of panel pixels 11 in Figure 6, for convenience, the first row is assigned codes a1 to a3, the second row b1 to b3, and the third row c1 to c3. Figure 6 shows that, among the array of input pixels shown in the video data Vde-in, the four 2x2 input pixels indicated by the thick border are represented by a single panel pixel 11.

[0022] Figure 7 shows how, in projection device 1, the panel pixels 11 of the display panel 10 shift and display which input pixels, indicated by the video data Vde-in, to which position. In detail, Figure 7 shows which of the nine panel pixels 11 in the right column of Figure 6 are shifted to which positions in subframes f1 to f4 for display. The optical path shift element 20 is controlled to shift the optical path to the first to fourth optical paths in subframes f1 to f4. Figure 7 shows that the optical path is shifted to the first to fourth optical paths and the image is projected to positions (1) to (4).

[0023] The first row of Figure 7 shows that in subframe f1, panel pixel 11 represents the odd-numbered row and odd-numbered column input pixels with hatching from the 2x2 input pixels corresponding to panel pixel 11 at position (1). For example, panel pixel 11 at position a1 represents input pixel A1 by projecting it onto position (1) on screen Scr. The optical path is the first optical path. When we say that panel pixel 11 represents input pixel A1, it means that the RGB OLEDs contained in panel pixel 11 each emit light with a brightness corresponding to the gradation level of input pixel A1 specified in the video data Vde-in.

[0024] The second row of Figure 7 shows that in subframe f2, panel pixel 11 represents the hatched input pixels in even rows and odd columns of the 2x2 input pixels corresponding to panel pixel 11 at position (2). For example, panel pixel 11 at position a1 projects and represents input pixel B1 at position (2). Position (2) is the position obtained by shifting position (1) in the Y direction by half the pitch p (p / 2). The optical path is the second optical path.

[0025] The third row of Figure 7 shows that in subframe f3, panel pixel 11 represents the hatched input pixels in even rows and even columns of the 2x2 input pixels corresponding to panel pixel 11 at position (3). For example, panel pixel 11 at position a1 projects and represents input pixel B2 at position (3). Position (3) is the position obtained by shifting position (2) in the X direction by half the pitch p (p / 2). The optical path is the third optical path.

[0026] The fourth row of Figure 7 shows that in subframe f4, panel pixel 11 represents the odd-row, even-column input pixels with hatching among the 2x2 input pixels corresponding to panel pixel 11 at position (4). For example, panel pixel 11 at position a1 projects and represents input pixel A2 at position (4). Position (4) is the position obtained by shifting position (3) by half the pitch p (p / 2) in the opposite direction in the Y direction. The optical path is the fourth optical path. When transitioning from subframe f4 to the next subframe f1, the projected pixel shifts from position (4) by half the pitch p in the opposite direction in the X direction and returns to position (1). The optical path returns to the first optical path by the optical path shift element 20.

[0027] Focusing on the centroid 11b of the panel pixel 11, the centroid 11b shifts sequentially by half the pitch p at positions (1) to (4). Therefore, when viewed through subframes f1 to f4, the centroids 11b are arranged with a pitch of p / 2 in the Y and X directions, as shown in Figure 9. Figure 8 shows the arrangement of projected pixels in the display panel 10 of Figure 3, where the centroid 11b of the panel pixel 11 is projected at position (1), for example, by the optical path shift element 20. In Figure 8, the centroid 11b projected at position (1) is shown as a black circle, and arrows indicate how some of the projected pixels are shifted to positions (2) to (4). Figure 9 shows the appearance of the centroid 11b of the projected pixels that are projected at positions (1) to (4) in one frame F. Therefore, even though the panel pixels 11 of the display panel 10 are arranged in m rows vertically and n columns horizontally, the shift by the optical path shift element 20 makes it appear as if the projected pixels are arranged in 2m rows vertically and 2n columns horizontally. In other words, in this embodiment, the resolution of the display panel 10 is effectively increased to a total of four times its original resolution (twice vertically and twice horizontally).

[0028] Figures 8 and 9 show examples where the shift amount in the X and Y directions is half the pitch p. Similar arrays can generally have a shift amount of {k + (p / 2)}, where k is a non-negative integer. For example, the shift amount may be set to 3 / 2 times the pitch p by setting k to "1", or the shift amount may be set to 5 / 2 times the pitch p by setting k to "2". However, it should be noted that if k is set too large, the shift amount by the optical path shift element 20 will become large, which will require more time for the shift, or the optical path shift element 20 will need to be made faster.

[0029] Returning to the explanation in Figure 4, the video processing circuit 40 divides the video data Vde-in supplied from the host device 5 into subframes f1 to f4 and supplies them to the display panel 10 as video data Vid. More specifically, the video processing circuit 40 temporarily stores the video data Vde-in, and then, from the stored video data Vde-in, reads out the video data Vde-in corresponding to the input pixels corresponding to each subframe f1 to f4 and supplies it to the display panel 10 as video data Vid. The video processing circuit 40 outputs a control signal Ctr for controlling the drive of the display panel 10 for each subframe f1 to f4. Furthermore, the video processing circuit 40 outputs control signals Psh_X and Psh_Y for controlling the optical path shift element 20 for each subframe f1 to f4.

[0030] Figure 10 shows the electrical configuration of the display panel 10. As shown in this figure, the display panel 10 is broadly composed of a control circuit 50, a data signal output circuit 60, and a scan line drive circuit 120.

[0031] In the display panel 10, m rows of scan lines 12 are provided along the X direction in the figure, and (3n) columns of data lines 14 are provided along the Y direction and in such a way that they are electrically isolated from each other by the scan lines 12.

[0032] To distinguish between rows in scan line 12, the rows are referred to as 1, 2, 3, ..., (m-1), and m rows in the diagram, starting from the top. Note that, to describe scan line 12 generally without specifying a row, an integer i (between 1 and m) is sometimes used to refer to the i-th row. Furthermore, to distinguish the columns in data line 14, they are referred to as columns 1, 2, 3, ..., (3n-2), (3n-1), and (3n) from left to right in the diagram. Note that data line 14 is grouped into groups of three columns. To explain the groups in a general way, if we use an integer j between 1 and n (inclusive), then the j-th group from the left contains data line 14 with a total of three columns: (3j-2), (3j-1), and (3j).

[0033] Pixel circuits 110R, 110G, and 110B are provided in correspondence with scan lines 12 arranged in m rows and data lines 14 arranged in (3n) columns. Specifically, pixel circuit 110R is provided in correspondence with the intersection of the i-th row scan line 12 and the (3j-2)-th column data line 14. Pixel circuit 110G is provided in correspondence with the intersection of the i-th row scan line 12 and the (3j-1)-th column data line 14. Pixel circuit 110B is provided in correspondence with the intersection of the i-th row scan line 12 and the (3j)-th column data line 14. The display area 100 is the region where the pixel circuits 110R, 110G, and 110B are arranged in a vertical m row × horizontal (3n) column configuration.

[0034] Pixel circuit 110R emits red light, pixel circuit 110G emits green light, and pixel circuit 110B emits blue light. Therefore, subpanel pixel 11R is represented by pixel circuit 110R, subpanel pixel 11G is represented by pixel circuit 110G, and subpanel pixel 11B is represented by pixel circuit 110B. Note that the pixel circuits 110R, 110B, and 110G are circuits that represent the sub-panel pixels 11R, 11G, and 11B, respectively, and therefore strictly speaking should be called sub-pixel circuits. However, for convenience in this explanation, we will refer to them as pixel circuits.

[0035] The control circuit 50 controls each part based on the video data Vid and control signal Ctr supplied from the video processing circuit 40. The control circuit 50 generates various control signals, the details of which will be described later as appropriate. As mentioned above, the video data Vde-in specifies the gradation level of the input pixels for each RGB channel, for example, using 8 bits. However, the brightness characteristics specified by the gradation level do not necessarily match the brightness characteristics of the OLED contained in the panel pixels 11. Therefore, the control circuit 50 upconverts each of the 8 bits of RGB in the video data Vde-in to, for example, 10 bits in this embodiment, in order to cause the OLED to emit light at the brightness corresponding to the gradation level specified in the video data Vde-in, and outputs it as video data Vdata that specifies the brightness of the RGB OLED. For such upconversion, a lookup table is used which stores in advance the correspondence between the 8 bits of the input video data Vid-in and the 10 bits of the output video data Vdata for each RGB.

[0036] Although not shown in Figure 4, the control circuit 50 also supplies a common control signal Enb to all pixel circuits 110R, 110G, and 110B.

[0037] The scan line driving circuit 120 is a circuit for driving the pixel circuits 110R, 110G, and 110B, which are arranged in m rows (3n columns), one row at a time, according to the control of the control circuit 50. Specifically, the scan line driving circuit 120 supplies scan signals Scan(1), Scan(2), ..., Scan(m-1), and Scan(m) to the scan lines 12 of the 1st, 2nd, 3rd, ..., (m-1), and mth rows in order. Generally, the scan signal supplied to the scan line 12 of the ith row is denoted as Scan(i). Note that in Figure 10, to avoid complicating the drawing, one scan line 12 is shown as a single line; however, in reality, there are "2" scan lines per line. That is, in reality, the scan signals Scan_a(i) and Scan_b(i) are supplied to the two scan lines 12 corresponding to the i-th line.

[0038] The data signal output circuit 60 is a circuit that outputs a data signal of voltage corresponding to the grayscale level to the pixel circuits 110R, 110G, and 110B located in the row selected by the scan line drive circuit 120. Specifically, the data signal output circuit 60 latches one row of video data Vdata supplied from the control circuit 50, converts the latched row of video data Vdata into an analog data signal, and outputs it as a data signal to the corresponding data line 14. The potentials of data lines 14 in columns 1, 2, 3, ..., (3n-2), (3n-1), and 3n are denoted as Vd(1), Vd(2), V(3), ..., Vd(3n-2), Vd(3n-1), and Vd(3n), respectively. Furthermore, in this explanation, the reference for zero voltage is the logic level L level (ground potential), but except for the voltage between two points (threshold voltage), the terms potential and voltage are not strictly distinguished in this explanation. Also, in this explanation, a power source refers to a voltage or potential that is approximately constant over time.

[0039] The electrical configurations of pixel circuits 110R, 110G, and 110B are identical. Therefore, the electrical configurations of pixel circuits 110R, 110G, and 110B will be explained using pixel circuit 110R, located in row i (3j-2), as a representative example.

[0040] Figure 11 is a circuit diagram showing the electrical configuration of the pixel circuit 110R located in row i (3j-2) column. As shown in the figure, the pixel circuit 110R includes an OLED 130, p-channel MOS-type transistors 121, 122a, 122b, 123a, 123b, and 124, and capacitive elements C1a and C1b. MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0041] The i-th row pixel circuits 110R, 110G, and 110B are supplied with a scan signal Scan_a(i) via one of the two scan lines 12 corresponding to the i-th row, 12a, and a scan signal Scan_b(i) is supplied via the other scan line 12b.

[0042] The OLED130 is a light-emitting device in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 has both light reflectivity and light transmittance. In the OLED130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, and white light is produced.

[0043] When considering the pixel circuits 110R, 110G, and 110B individually, the generated white light resonates in an optical resonator composed of a reflective layer and a semi-reflective / semi-transparent layer (not shown), and is emitted at resonant wavelengths set to correspond to the colors red, green, and blue, respectively. A color filter corresponding to the respective color is provided in the Z direction, which is the direction of light emission from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being visible. The optical resonator is not shown.

[0044] In the i-row (3j-2) column pixel circuit 110R, for transistor 122a, the source node is connected to the data line 14 of the (3j-2) column, the drain node is connected to one end of the capacitive element C1a and the source node of transistor 123a, and the gate node is connected to the scan line 12a. For transistor 122b, the source node is connected to the data line 14 of the j column, the drain node is connected to one end of the capacitive element C1b and the source node of transistor 123b, and the gate node is connected to the scan line 12b. The other end of the capacitive element C1a and the other end of the capacitive element C1b are connected to the power supply wiring 116 to which a high power supply potential ELvdd is supplied.

[0045] In transistor 123a, the gate node is connected to control line 13a to which the selection signal Sel_a is supplied. In transistor 123b, the gate node is connected to control line 13b to which the selection signal Sel_b is supplied. The drain nodes of transistor 123a and transistor 123b are connected to the gate node g of transistor 121.

[0046] In transistor 121, the source node s is connected to the power supply wiring 116, and the drain node d is connected to the source node of transistor 124. In transistor 124, the control signal Enb is supplied to the gate node, and the drain node is connected to the pixel electrode 131 of OLED 130. In OLED 130, a low power supply potential ELvss is supplied to the common electrode 133 via the power supply wiring 118.

[0047] In this explanation, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, including, for example, in a semiconductor substrate, connections between two or more elements that are not direct but are connected via different wiring layers and contact holes.

[0048] Figure 12 is a timing chart illustrating the operation of the optical path shift element 20. The video processing circuit 40 supplies control signals Psh_Y and Psh_X to the optical path shift element 20 to shift the projected image Img on the screen Scr in the Y and X directions, respectively. In detail, the control signal Psh_Y shifts the position of the projected image Img relative to the screen Scr in the Y direction, and the control signal Psh_X shifts the position of the projected image Img in the X direction. Control signals Psh_Y and Psh_X take voltages of -A or +A, respectively. The optical path changes to one of four optical paths depending on the voltage of the control signals Psh_Y or Psh_X. If there is no change in the voltage of the control signals Psh_Y and Psh_X, the optical path is maintained. Here, if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is -A, then the projected image Img is at position (1) on the screen Scr. For convenience, let's assume that the coordinates Pps_Y and Pps_X of a projection pixel in the projected image Img at position (1) (for example, the projection pixel at the top left corner of display area 100) are both zero. The optical path in this case is the first optical path.

[0049] When the voltage of the control signal Psh_Y changes to +A, the position of the projected pixel shifts in the Y direction by half the pitch p, and the coordinate position Pps_Y becomes p / 2. When the voltage of the control signal Psh_X changes to +A, the position of the projected pixel shifts in the X direction by half the pitch p, and the coordinate position Pps_X becomes p / 2.

[0050] Therefore, the projected pixel will be at position (1) if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is -A, and at position (2) if the voltage of the control signal Psh_Y is +A and the voltage of the control signal Psh_X is -A. Furthermore, it will be at position (3) if the voltage of the control signal Psh_Y is +A and the voltage of the control signal Psh_X is +A, and at position (4) if the voltage of the control signal Psh_Y is -A and the voltage of the control signal Psh_X is +A.

[0051] Furthermore, even if the control signals Psh_Y and Psh_X change to voltage -A or +A, the position of the projected pixel (projected image Img) shifted by the optical path shift element 20 is not immediately determined, but is delayed by a period t1. In other words, the position of the projected pixel stabilizes after a period t1 has elapsed since the voltage of the control signal Psh_Y or Psh_X changed.

[0052] Furthermore, the control circuit 50 outputs the following control signal Enb in response to the output changes of the control signals Psh_Y and Psh_X from the video processing circuit 40. That is, the control circuit 50 outputs a control signal Enb that is at an H level during period t2 which includes the above period t1, and at an L level during other periods.

[0053] Figures 13 and 14 are timing charts illustrating the operation of projection device 1. As described above, one frame F is composed of four subframes f1 to f4, each corresponding to the first to fourth periods. In this embodiment, from the perspective of data writing, the subframe consists of write subframes W_f1 to W_f4 for writing data signals to the pixel circuits 110R, 110G, and 110B, and the vertical scan retrace period Vblnk. In addition, in this embodiment, from the perspective of light emission, the subframe consists of light emission subframes L_f1 to L_f4 for supplying current based on the voltage of the written data signal to the OLED 130, and the vertical scan retrace period Vblnk. In detail, the writing subframes W_f1 to W_f4 are periods for writing data signals corresponding to subframes f1 to f4 to the pixel circuits 110R, 110G, and 110B in order, while the light-emitting subframes L_f1 to L_f4 are periods for supplying current based on the voltage of the data signals written in the writing subframes W_f1 to W_f4 to the OLED 130 to cause it to emit light. In this embodiment, the first to fourth periods correspond to the write subframes W_f1 to Wf4, or the light emission subframes L_f4, L_f1 to L_f3, respectively. The vertical scan retrace period Vblnk corresponds to the blackout period.

[0054] In this embodiment, the periods of the write subframes W_f1 to W_f4 coincide with the periods of the light-emitting subframes L_f4 and Lf1 to L_f3, respectively. Furthermore, writing refers to the operation of holding the voltage of the data signal in the capacitive element C1a or C1b.

[0055] In the write subframes W_f1 and W_f3, the scan signals Scan_a(1), Scan_a(2), ..., Scan_a(m-1), and Scan_a(m) are sequentially set to an exclusive L level for every horizontal scan period H. In the write subframes W_f2 and W_f4, the scan signals Scan_b(1), Scan_b(2), ..., Scan_b(m-1), and Scan_b(m) are sequentially set to an exclusive L level for every horizontal scan period H.

[0056] In this embodiment, the period from when the scan signal Scan_a(1) changes to an L level in the write subframe W_f1 (or W_f3) until the scan signal Scan_a(m) changes to an H level, and the period from when the scan signal Scan_b(1) changes to an L level in the write subframe W_f2 (or W_f4) until the scan signal Scan_b(m) changes to an H level, are sometimes referred to as the vertical effective scan period. Furthermore, the vertical scan retrace period Vblnk is the period outside the vertical effective scan period, specifically the period from when the scan signal Scan_a(m) changes to a high level in write subframe W_f1 (or W_f3) until the scan signal Scan_b(1) changes to a low level in write subframe W_f2 (or W_f4), and the period from when the scan signal Scan_b(m) changes to a high level in write subframe W_f2 (or W_f4) until the scan signal Scan_a(1) changes to a low level in write subframe W_f3 (or W_f1).

[0057] In this embodiment, the control signal Enb is at an L level during the vertical effective scanning period, which is the light emission subframes L_f2, L_f3, L_f4, and L_f1, and at an H level during the vertical scanning retrace period, which is the other period. The vertical scanning retrace period corresponds to the period t2 described above.

[0058] Furthermore, the control signal Psh_Y to the optical path shift element 20 becomes -A when the write subframe W_f4 finishes, and becomes +A when the write subframe W_f2 finishes. The control signal Psh_X becomes -A when the write subframe W_f1 finishes, and becomes +A when the write subframe W_f3 finishes. Although not shown in Figures 13 and 14, after the voltage of the control signal Psh_Y or Psh_X changes at the start of the vertical scanning retrace period, the optical path shift by the optical path shift element 20 is completed by the start of the next vertical effective scanning period, and this state is maintained, stabilizing the position of the projected pixels.

[0059] In the first embodiment, in the write subframes W_f1 and W_f3 (light-emitting subframes L_f4 and L_f2), the selection signal Sel_a is at a high level and the selection signal Sel_b is at a low level, and in the write subframes W_f2 and W_f4 (light-emitting subframes L_f1 and L_f3), the selection signal Sel_a is at a low level and the selection signal Sel_b is at a high level. Furthermore, during the vertical scan retrace period after write subframes W_f1 and W_f3, the selection signal Sel_b changes from L to H level earlier in time, and the selection signal Sel_a changes from H to L level later in time. During the vertical scan retrace period after write subframes W_f2 and W_f4, the selection signal Sel_a changes from L to H level earlier in time, and the selection signal Sel_b changes from H to L level later in time.

[0060] The operation of projection device 1 in the write subframe W_f1 will be described. In the write subframe W_f1, the following three operations are primarily performed: In detail, in the write subframe W_f1, firstly, the input pixels in odd-numbered rows and odd-numbered columns of the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in are stored as video data Vdata in the capacitive elements C1a of the pixel circuits 110R, 110G, and 110B. In the writing subframe W_f1, secondly, the projection pixel is shifted to position (4) by the optical path shift element 20. The optical path is shifted to the fourth optical path. In the write subframe W_f1, or light-emitting subframe L_f4, thirdly, an operation is performed to supply current to the OLED130 according to the voltage held in the capacitive element C1b of the pixel circuits 110R, 110G, and 110B.

[0061] To elaborate on the first operation, in the writing subframe W_f1, the video processing circuit 40 outputs the input pixels in odd rows and odd columns of the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in supplied from the host device 5 as video data Vid. Note that the input pixels in odd rows and odd columns of the input pixels arranged in a vertical (2m) x horizontal (2n) grid are the input pixels that are hatched in the first row (subframe f1) of Figure 7.

[0062] In the write subframe W_f1, the control circuit 50 converts the video data Vde-in into video data Vdata line by line and outputs it in accordance with the timing when the scan signals Scan_a(1) to Scan_a(m) sequentially become low. Furthermore, in the written subframe W_f1, for example, during the period when the scan signal Scan_a(i) is at a low level, the data signal output circuit 60 converts the gradation levels of the subpanel pixels 11R, 11G, and 11B in rows i, column 1 to row i(3n), indicated by the video data Vdata, into analog potentials Vd(1) to Vd(3n) and outputs them as data signals to the data lines 14 in columns 1 to (3n). In the case of the (3j-2) column, the data signal output circuit 60 converts the gradation level corresponding to the sub-panel pixel 11R in row i (3j-2) of the video data Vdata into an analog signal potential Vd(3j-2) and outputs it as a data signal to the data line 14 in the (3j-2) column. Note that the gradation level corresponding to subpanel pixel 11R in row i (3j-2) refers to the gradation level obtained by converting the 8-bit gradation level corresponding to the R component of the input pixel in the (2i-1) row and j column of the input pixels arranged in a vertical (2m) x horizontal (2n) grid to a 10-bit gradation level.

[0063] When the scanning signal Scan_a(i) is at a low level, transistor 122a is turned on in the pixel circuit 110 at row i (3j-2). During the period when the scanning signal Scan_a(i) is at a low level, the scanning signal Scan_b(i) is at a high level, so transistor 122b is turned off in the pixel circuit 110 at row i (3j-2)j column.

[0064] Therefore, the data signal with potential Vd(3j-2) is held in the capacitive element C1a via the data line 14 in the (3j-2)th column and the transistor 122a in the pixel circuit 110R in the i-th row (3j-2) column. Here, we have described the pixel circuit 110R in row i and column (3j-2), but the same applies to the pixel circuits 110R, 110G, and 110B in the other columns of row i besides column (3j-2), and the data signal is held in the capacitive element C1a.

[0065] In this explanation, the "on state" of a switching element or transistor refers to a low-impedance state where the terminals of the switching element, or the source node and drain node of a transistor, are electrically closed. Conversely, the "off state" of a switching element or transistor refers to a high-impedance state where the terminals of the switching element, or the source node and drain node, are electrically open.

[0066] In the write subframe W_f1, even if it is not the i-th row, the scan signals Scan_a(1) to Scan(m) sequentially become L level exclusively, so that the data signal is held in the capacitive element C1a in all pixel circuits 110R, 110G, and 110B.

[0067] To elaborate on the second operation, after the write subframe W_f4, the video processing circuit 40 sets the control signal Psh_Y to voltage -A and the control signal Psh_X to voltage +A. As a result, in the light emission subframe L_f4, the projected pixels are shifted to position (4) and are stable. The optical path is shifted to the fourth optical path and maintains that state.

[0068] To elaborate on the third operation, in the write subframe W_f1, the selection signal Sel_a is at a high level and the selection signal Sel_b is at a low level. As a result, in all pixel circuits 110R, 110G, and 110B, transistor 123a is in the off state and transistor 123b is in the on state. Therefore, in all pixel circuits 110R, 110G, and 110B, one end of the capacitive element C1b is electrically connected to the gate node g of transistor 121 via transistor 123b, and the voltage held by the capacitive element C1b is applied between the gate node and source node of transistor 121. Furthermore, in the write subframe W_f1 (light emission subframe L_f4), the control signal Enb is at a low level, so transistor 124 is turned ON.

[0069] Therefore, in the light-emitting subframe L_f4, in all pixel circuits 110R, 110G, and 110B, the transistor 121 supplies a current to the OLED 130 corresponding to the voltage between the gate node and source node, i.e., the grayscale level of the pixel. The voltage held in the capacitive element C1b is based on the data signal supplied via the data line 14 in the writing subframe W_f4 of the previous frame. Therefore, in the light-emitting subframe L_f4, each OLED 130 in all pixel circuits 110R, 110G, and 110B emits light with a brightness corresponding to the subpanel pixels 11R, 11G, and 11B of subframe f4. The projected pixels resulting from this light emission are then visible at position (4) on the screen Scr.

[0070] The operation of projection device 1 in write subframe W_f2 is the same as in write subframe W_f1, except for the following point. Specifically, in the first case of the write subframe W_f2, the video processing circuit 40 outputs the input pixels in even rows and odd columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns of the video data Vde-in as video data Vdata; second case of the video processing circuit 40 setting the control signal Psh_Y to voltage -A and the control signal Psh_X to voltage -A to set the projected pixels by the optical path shift element 20 to position (1); and third case of the control circuit 50 setting the selection signal Sel_a to L level and the selection signal Sel_b to H level. Thus, the operation in the write subframe W_f2 differs from the operation in the write subframe W_f1. The optical path is shifted to the first optical path and that state is maintained.

[0071] In the written subframe W_f2, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the input pixels in even rows and odd columns among the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in is held in the capacitive element C1b, while a current corresponding to the voltage held in the capacitive element C1a (the voltage written in subframe Wf_1) is supplied to the OLED130. Therefore, in the writing subframe W_f2 (emitting subframe L_f1), each OLED 130 in all pixel circuits 110R, 110G, and 110B emits light with a brightness corresponding to the subpanel pixels 11R, 11G, and 11B of subframe f1, and the projected pixels resulting from this emission are visible at position (1) on the screen Scr.

[0072] The operation of projection device 1 in write subframe W_f3 is the same as in write subframe W_f1, except for the following point. Specifically, in the first case, in the writing subframe W_f2, the video processing circuit 40 outputs input pixels in even rows and even columns of the input pixels arranged in vertical (2m) rows × horizontal (2n) columns in the video data Vde-in as video data Vdata; and second, the video processing circuit 40 sets the projection pixels by the optical path shift element 20 to position (2) by setting the control signal Psh_Y to voltage +A and the control signal Psh_X to voltage -A. Thus, the operation in the writing subframe W_f3 differs from the operation in the writing subframe W_f1. The optical path is shifted to the second optical path, and that state is maintained.

[0073] In the writing subframe W_f3, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the input pixels in even rows and even columns among the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in is held in the capacitive element C1a, while a current corresponding to the voltage held in the capacitive element C1b (the voltage written in subframe Wf_2) is supplied to the OLED130. Therefore, in the writing subframe W_f3 (emitting subframe L_f2), each OLED 130 in all pixel circuits 110R, 110G, and 110B emits light with a brightness corresponding to the subpanel pixels 11R, 11G, and 11B of subframe f2, and the projected pixels resulting from this emission are visible at position (2) on the screen Scr.

[0074] The operation of projection device 1 in write subframe W_f4 is the same as in write subframe W_f1, except for the following point. Specifically, in the first case of the write subframe W_f4, the video processing circuit 40 outputs the input pixels in odd rows and even columns of the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in as video data Vdata; second case of the video processing circuit 40 setting the control signal Psh_Y to voltage +A and the control signal Psh_X to voltage +A to set the projected pixels by the optical path shift element 20 to position (3); and third case of the control circuit 50 setting the selection signal Sel_a to L level and the selection signal Sel_b to H level. Thus, the operation in the write subframe W_f3 differs from the operation in the write subframe W_f1. The optical path is shifted to the third optical path and that state is maintained.

[0075] In the writing subframe W_f4, in all pixel circuits 110R, 110G, and 110B, the voltage of the data signal corresponding to the input pixels in odd rows and even columns among the input pixels arranged in a vertical (2m) x horizontal (2n) grid in the video data Vde-in is held in the capacitive element C1b, while a current corresponding to the voltage held in the capacitive element C1a (the voltage written in subframe Wf_3) is supplied to the OLED130. Therefore, in the writing subframe W_f4 (emitting subframe L_f3), each OLED 130 in all pixel circuits 110R, 110G, and 110B emits light with a brightness corresponding to the subpanel pixels 11R, 11G, and 11B of subframe f3, and the projected pixels resulting from this emission are visible at position (3) on the screen Scr.

[0076] The pixel circuits 110R, 110G, and 110B of the display panel 10 in the projection device 1 according to the first embodiment can be understood as having the configuration shown in Figure 15, for example, of the pixel circuit 110R. Transistors 122a and 122b in Figure 11 can be understood as a first selector 122, as shown in Figure 15. Specifically, in write subframes W_f1 and W_f3, when scan line 12a is selected and the scan signal Scan_a(i) is at a low level, the first selector 122 electrically connects one end of the capacitive element C1a to the data line 14 of the (3j-2) column, and in write subframes W_f2 and W_f4, when scan line 12b is selected and the scan signal Scan_b(i) is at a low level, it electrically connects one end of the capacitive element C1b to the data line 14 of the (3j-2) column.

[0077] Furthermore, transistors 123a and 123b in Figure 11 can be understood as a second selector 123, as shown in Figure 15. In detail, the second selector 123 electrically connects one end of the capacitive element C1b to the gate node g of transistor 121 if, in the write subframes W_f1 and W_f3, the selection signal Sel_a is at a high level and the selection signal Sel_b is at a low level, and electrically connects one end of the capacitive element C1a to the gate node g of transistor 121 if, in the write subframes W_f2 and W_f4, the selection signal Sel_a is at a low level and the selection signal Sel_b is at a high level.

[0078] Specifically, transistor 121 is an example of a driving transistor, transistor 122a is an example of a first switching element, transistor 122b is an example of a second switching element, transistor 123a is an example of a third switching element, and transistor 123b is an example of a fourth switching element. Furthermore, capacitive element C1a is an example of a first capacitive element, and capacitive element C1b is an example of a second capacitive element.

[0079] Next, we will explain how the degradation of display quality is suppressed in the image projected by the projection device 1 according to this embodiment.

[0080] Figure 16 shows the display area 100. Top represents the top edge of the display area 100, i.e., the first row; Mid represents the middle of the display area 100, i.e., the (m / 2)th row; and Btm represents the bottom edge of the display area 100, i.e., the mth row.

[0081] Figure 27 illustrates the decrease in display quality in the first comparative example. In the first comparative example, a scan line is selected for each horizontal scanning period H, a data signal is written, and line sequential driving is shown where the brightness corresponds to the written data signal. Note that Wr indicates the timing of the data signal writing, and L indicates the brightness state corresponding to the written data signal. In the first comparative example, if the optical path shift element is configured to shift the optical path at the writing timing of the intermediate Mid of the display area 100, the panel pixels of the intermediate Mid will be visible with the brightness of the subframe at the position shifted by the shift element, while the panel pixels of the upper Top and lower Btm will be visible with the brightness spanning the preceding and succeeding subframes at the position shifted by the optical path shift element. Therefore, in the first comparative example, the panel pixels located at the upper edge (Top) and lower edge (Btm) are not properly visible at the positions shifted by the optical path shift element, resulting in a decrease in display quality due to inconsistencies in the display at the shifted positions.

[0082] Figure 28 is a diagram illustrating the decrease in display quality in the second comparative example. In the second comparative example, the horizontal scanning period H is shortened, that is, the time for writing the data signal is shortened, and the vertical scanning retrace period is extended accordingly. The extended vertical scanning retrace period is then adjusted to match the period during which the position shifted by the optical path shift element stabilizes. In the second comparative example, as in the first comparative example, the panel pixels at the top, middle, and bottom edges are viewed almost equally at the positions shifted by the optical path shift element. Therefore, it is considered that the deterioration of display quality caused by inconsistencies in display at the shifted positions is suppressed. However, in the second comparative example, since the time required to write the data signal is shortened, a situation may occur where the voltage of the data signal is not sufficiently written to the capacitive element, which can easily lead to a decrease in display quality due to insufficient writing.

[0083] Figure 17 is a diagram illustrating how the deterioration of display quality is suppressed in the first embodiment. As described above, in the first embodiment, for example, in the write subframe W_f1, data signals are sequentially written to the capacitive element C1a at each horizontal scanning period H, while a current corresponding to the voltage written to the capacitive element C1b is simultaneously supplied to the OLED130. In the next write subframe W_f2, data signals are sequentially written to the capacitive element C1b at each horizontal scanning period H, while a current corresponding to the voltage written to the capacitive element C1a is simultaneously supplied to the OLED130. Therefore, in the first embodiment, sufficient time is secured for writing the data signal, and no inconsistencies in the display at the shift position occur, thus suppressing a decrease in display quality.

[0084] <Second Embodiment> Next, the projection apparatus 1 according to the second embodiment will be described. In the second embodiment, the configuration of the pixel circuits 110R, 110G, and 110B in the display panel 10 differs from that of the first embodiment. Therefore, the differences between the second embodiment and the pixel circuits 110R, 110G, and 110B will be mainly described. In the second embodiment, the pixel circuits 110R, 110G, and 110B are configured to compensate for the threshold voltage of the transistor 121 that controls the current flowing through the OLED 130. Furthermore, in the second embodiment as well, the electrical configurations of the pixel circuits 110R, 110G, and 110B are the same, so the explanation will be based on the pixel circuit 110R located in row i (3j-2).

[0085] Figure 18 is a circuit diagram showing the electrical configuration of the pixel circuit 110R in the display panel 10 of the projection device 1 according to the second embodiment. Compared to the pixel circuit 110R shown in Figure 11, the pixel circuit 110R shown in Figure 18 has the addition of a capacitive element C2 and p-channel MOS type transistors 125 and 126. In Figure 18, the drain nodes of transistors 123a and 123b are connected to the drain node of transistor 125 and one end of the capacitive element C2. The other end of the capacitive element C2 is connected to the gate node g of transistor 121 and the drain node of transistor 126. For transistor 125, the source node is connected to the power supply wiring 116, and the gate node is supplied with the control signal Yb. For transistor 126, the source node is connected to the drain node d of transistor 121, and the gate node is supplied with the control signal Ya. The control signals Ya and Yb are supplied from the control circuit 50 to all pixel circuits 110R, 110G, and 110B in common.

[0086] Figures 19 and 20 are timing charts illustrating the operation of the projection apparatus 1 according to the second embodiment. The control signals Ya and Yb reach a low level after the completion of the write subframes W_f1 to W_f4. More specifically, after the completion of the write subframes W_f1 to W_f4, control signal Yb reaches a low level first, followed by control signal Ya reaching a low level. After control signal Ya reaches a low level, control signal Yb reaches a high level first, followed by control signal Ya reaching a low level.

[0087] Furthermore, in the second embodiment, as in the first embodiment, in the write subframes W_f1 and W_f3 (light-emitting subframes L_f4 and L_f2), the selection signal Sel_a is at the H level and the selection signal Sel_b is at the L level, and in the write subframes W_f2 and W_f4 (light-emitting subframes L_f1 and L_f3), the selection signal Sel_a is at the L level and the selection signal Sel_b is at the H level. However, the timing at which the selection signals Sel_a and Sel_b change to the H level is the end timing of the write subframes W_f1 to W_f4 (light-emitting subframes L_f1 to L_f4). Also, the timing at which the selection signals Sel_a and Sel_b change to the L level is after the control signal Ya changes to the H level and before the end of the vertical scan retrace period Vblnk.

[0088] When the control signal Yb reaches a low level at the end of the write subframes W_f1 to W_f4, transistor 125 turns on, and one end of the capacitive element C2 becomes the power supply potential ELvdd. Next, when the control signal Ya reaches the L level, transistor 126 turns on, and the drain node and gate node of transistor 121 are connected, i.e., it enters a diode connection state. As a result, the voltage between the gate node g and source node s of transistor 121 converges to the threshold voltage of transistor 121, and this threshold voltage is held by the capacitive element C2. When the control signal Yb reaches a high level, transistor 125 turns off, and when the control signal Ya reaches a high level, transistor 126 turns off.

[0089] Just before the end of the vertical scan retrace period Vblnk, the selection signal Sel_b becomes low, and transistor 123b turns on, so that capacitive elements C1b and C2 are in series between the power supply wiring 116 and the gate node g of transistor 121. Therefore, in the light-emitting subframe L_f2 (or L_f4) after the end of the vertical scan retrace period Vblnk, a threshold voltage is added to the voltage corresponding to the grayscale level supplied in the previous write subframe W_f2 (or W_f4), and this added voltage is applied to the gate node g of transistor 121. Furthermore, after the vertical scanning retrace period Vblnk ends, when the light-emitting subframe L_f3 (or L_f1) begins, transistor 123a turns ON, and capacitive elements C1a and C2 become series between the power supply wiring 116 and the gate node g of transistor 121. For this reason, in the light-emitting subframe L_f3 (or L_f1), a threshold voltage is added to the voltage corresponding to the grayscale level supplied in the previous write subframe W_f3 (or W_f1), and this added voltage is applied to the gate node g of transistor 121.

[0090] Thus, according to the second embodiment, the threshold voltage of transistor 121 is held in capacitive element C2 during each vertical scan retrace period Vblnk. In the subsequent light-emitting subframe, when transistor 123b is turned on, the threshold voltage (holding voltage of capacitive element C2) is added to the voltage corresponding to the grayscale level supplied in the previous writing subframe (holding voltage of capacitive element C1b), and this added voltage is applied to the gate node g of transistor 121. At the same time, when transistor 122a is turned on, the voltage corresponding to the grayscale level is held in capacitive element C1a. On the other hand, in the light-emitting subframe after the vertical scan retrace period Vblnk, when transistor 123a is turned on, a threshold voltage (holding voltage of capacitive element C2) is added to the voltage corresponding to the grayscale level supplied in the previous write subframe (holding voltage of capacitive element C1a), and this added voltage is applied to the gate node g of transistor 121. At the same time, when transistor 122b is turned on, a voltage corresponding to the grayscale level is held in capacitive element C1b. In the second embodiment, these operations are performed alternately and repeatedly.

[0091] In the second embodiment, as in the first embodiment, in the light-emitting subframes L_f1 to L_f4, when the position of the projected pixels is stable, the transistors 121 of all pixel circuits 110R, 110G, and 110B simultaneously supply current to the OLED 130. Furthermore, according to the second embodiment, in each of the light-emitting subframes L_f1 to L_f4, the transistor 121 supplies a current to the OLED 130 according to the gradation level while the threshold voltage is compensated, thus enabling high-quality display with less variation for each pixel circuit 110R, 110G, and 110B. Therefore, in the second embodiment, sufficient time is secured for writing the data signal, and no inconsistencies in the display at the shift position occur, thus suppressing a decrease in display quality and enabling high-quality display with compensated threshold voltage.

[0092] The pixel circuits 110R, 110G, and 110B of the display panel 10 in the projection device 1 according to the second embodiment can be understood as having the configuration shown in Figure 21, for example, of the pixel circuit 110R. As shown in Figure 21, transistor 126 functions as a switching element that electrically short-circuits the gate node g and drain node d of transistor 121, thereby putting transistor 121 into a diode connection state, when the control signal Ya is at an L level during the vertical scan retrace period Vblnk. In other words, transistor 126 is an example of a sixth switching element.

[0093] Furthermore, the capacitive element C2 holds the threshold voltage of transistor 121 when transistors 125 and 126 are turned on. The capacitive element C2, which holds the threshold voltage, is electrically interposed between one end of the capacitive element C1b and the gate node g of transistor 121 if the selection signal Sel_a is at a high level and the selection signal Sel_b is at a low level in the light-emitting subframe L_f2 (or L_f4), and between one end of the capacitive element C1a and the gate node g of transistor 121 if the selection signal Sel_a is at a low level and the selection signal Sel_b is at a high level in the light-emitting subframe L_f1 (or L_f3). In other words, the capacitive element C2 is an example of a third capacitive element. In this explanation, "electrically interposed" refers to an insertion between two or more elements when viewed as an electrical circuit.

[0094] <Third Embodiment> Next, the projection apparatus 1 according to the third embodiment will be described. In the third embodiment, the arrangement of sub-panel pixels in the display panel 10 differs from that of the first or second embodiment.

[0095] Figure 22 shows the configuration of the panel pixels 11 of the display panel 10 in the third embodiment. As shown in the figure, in the third embodiment, the green sub-panel pixels in the panel pixels 11 are divided into two. Specifically, the panel pixels 11 consist of a total of four pixels: one red sub-panel pixel 11R, two green sub-panel pixels 11G1 and 11G2, and one blue sub-panel pixel 11B. These four sub-panel pixels are arranged in a 2x2 square grid, with the green sub-panel pixels 11G1 and 11G2 located diagonally opposite each other in the 2x2 square grid, the red sub-panel pixel 11R located in one of the remaining two spaces, and the blue sub-panel pixel 11B located in the other of the remaining two spaces.

[0096] In this arrangement of sub-panel pixels 11R, 11G1, 11G2, and 11B, the centroid 11b of the panel pixel 11 is the center of the diagonal in a 2x2 square arrangement. In such an arrangement, adjacent sub-panel pixels in the X or Y direction always have different colors. Therefore, since color filters of the same color do not align in the X or Y direction, the differences in viewing angle characteristics between red, green, and blue sub-panel pixels can be reduced.

[0097] Although not specifically shown in the diagram, the pixel electrodes 131 are common to both sub-panel pixels 11G1 and 11G2. Therefore, when the pixel electrode 131, which is common to sub-panel pixels 11G1 and 11G2, makes contact with the data line 14 near the centroid 11b, the arrangement of the data line 14 becomes the same as that of the first embodiment shown in Figure 10.

[0098] Therefore, as shown in Figures 8 and 9, in the third embodiment, if, for example, the image is projected onto position (1) in subframe f1, onto position (2) in subframe f2, onto position (3) in subframe f3, and onto position (4) in subframe f4, the centroid 11b of the panel pixel 11 is sequentially shifted by half the pitch p. As a result, if we look at subframes f1 through f4, the centroid 11b becomes half the pitch p / 2 in both the Y and X directions, so the resolution is effectively quadrupled.

[0099] In the third embodiment, one of the sub-panel pixels 11G1 or 11G2 may be replaced with a sub-panel pixel of a different color from red, green, and blue, such as a white sub-panel pixel, to express high brightness, or it may be replaced with a yellow sub-panel pixel, for example, to expand the reproducible color gamut.

[0100] <Fourth Embodiment> Next, the projection device 1A according to the fourth embodiment will be described. In the projection devices according to the first to third embodiments, the display panel 10 was a so-called single-chip type, in which red sub-panel pixels 11R, green sub-panel pixels 11G (G1, G2), and blue sub-panel pixels 11B were provided. In contrast, the fourth embodiment is a so-called three-chip type, in which a display panel 10 is provided for each of the red, green, and blue colors, and images of these colors are combined and output.

[0101] Figure 23 shows the configuration of the projection device 1A according to the third embodiment. In the figure, display panel 10R emits a modulated image of the red component in the 6 o'clock direction. Display panel 10G emits a modulated image of the green component in the 9 o'clock direction. Display panel 10B emits a modulated image of the blue component in the 12 o'clock direction. The dichroic prism 36 reflects the modulated red component image from display panel 10R in the 9 o'clock direction in the diagram, transmits the modulated green component image from display panel 10G in the 9 o'clock direction in the diagram, and reflects the modulated blue component image from display panel 10B in the 9 o'clock direction in the diagram.

[0102] As a result, the dichroic prism 36 synthesizes the modulated image of the red component, the modulated pixels of the green component, and the modulated image of the blue component, and emits them in the 9 o'clock direction (Z direction) in the figure. The optical path shift element 20 can shift the combined light from the dichroic prism 36 by control of the image processing circuit 40.

[0103] Figure 24 shows the arrangement of projected pixels when the projection pixel is projected to position (1) by the optical path shift element 20. In the fourth embodiment, since the subpanel pixels of each color are combined to form a projected pixel, there is no concept of a centroid 11b as in the first to third embodiments, and one color is represented by one projection pixel itself, which is shown as a circle in the figure. In Figure 24, the width (maximum diameter) of the projection pixel is denoted as W. Note that in Figure 24, arrows indicate in some parts how the projection pixel is shifted to positions (2) to (4). Figure 25 shows the appearance of the projected pixel as it is projected to positions (1) to (4) in one frame F.

[0104] In the examples shown in Figures 24 and 25, the fourth embodiment is an example where k is set to "1" and the shift amount is 3 / 2 times the pitch p. Therefore, in the fourth embodiment, when a projected pixel is projected to position (1) in subframe f1, to position (2) in subframe f2, to position (3) in subframe f3, and to position (4) in subframe f4, the projected pixel is sequentially shifted by 3 / 2 times the pitch p. As a result, when viewed from subframe f1 to f4, the projected pixels are arranged with half the pitch p / 2 in both the Y and X directions, so the resolution is effectively quadrupled. Furthermore, if the pitch p / 2 of the projected pixels, which are pseudo-arranged by the shift, is made smaller than the maximum diameter w of the projected pixels, the pseudo-arranged projected pixels will not overlap. As a result, a clear image without overlap can be pseudo-visualized.

[0105] In the examples in Figures 24 and 25, k is set to "1" and the shift amount is 3 / 2 times the pitch p, but k may also be set to "0" and the shift amount may be 1 / 2 times the pitch p. Alternatively, k may be set to "2", "3", "4", ... and the shift amounts may be 5 / 2 times, 7 / 2 times, 9 / 2 times, ... In other words, as mentioned above, k can be any integer greater than or equal to "0".

[0106] <Application examples, variations> The first and second embodiments (hereinafter referred to as "embodiments, etc.") exemplified above can be modified in various ways. Specific examples of modifications that can be applied to the embodiments are given below. Two or more embodiments arbitrarily selected from the following examples may be merged to the extent that they do not contradict each other.

[0107] In the embodiment, the control signal Enb was set to L level, i.e., the OLED130 was made to emit light during the period when the scanning signals Scan_a(1) to Scan_a(m) sequentially become L level, and during the period when the scanning signals Scan_b(1) to Scan_b(m) sequentially become L level, i.e., the entire vertical effective scanning period. This configuration is not limited to this one; the light emission period during which the control signal Enb is at an L level can also be narrowed to shorten the light emission period of the OLED 130. With such a configuration, the light emission period of the OLED 130 is shortened, and the display characteristics of the display panel 10 become closer to the so-called impulse response, thereby reducing the afterimage effect in video display. In addition, dark gradation levels can be expressed even darker by the pixel circuit 110. Furthermore, when a portion of the vertically effective scanning period is designated as the light emission period, this light emission period may be shifted forward in time, backward in time, or made intermittent.

[0108] To improve the responsiveness of the optical path shift, the optical path shift element 20 may be driven in overdrive mode. Specifically, as shown in Figure 26, when the video processing circuit 40 changes the voltages of the control signals Psh_Y and Psh_X, it sets the voltage to be excessively swung in the direction of the change, and immediately after that, sets the voltage to a voltage corresponding to the amount of shift. For example, when the image processing circuit 40 changes the projection pixel from position (1) to position (2), it sets the voltage of the control signal Psh_Y to a voltage (A+α) that is excessively α in the direction of the change, and immediately after that, it sets the voltage to +A. Also, for example, when the image processing circuit 40 changes the projection pixel from position (4) to position (1), it sets the voltage of the control signal Psh_X to a voltage (-A-α) that is excessively α in the direction of the change, and immediately after that, it sets the voltage to -A. By driving the optical path shift element 20 in overdrive mode in this way, the responsiveness of the optical path shift is improved, so the period during which the projected pixel stabilizes at one of positions (1) to (4) is extended. As a result, the duration of the light emission subframes L_f1 to L_f4 can be extended.

[0109] In the embodiments described above, the optical path shift element 20 was configured to shift the projected pixels in the X and Y directions, but it may also be configured to shift the projected pixels in a direction along either the X or Y axis. For example, if the projected pixels are shifted by a shift amount of {k+(p / 2)} in the X direction, and the projected pixels are shifted to two different positions, the resolution of the display panel 10 can be effectively doubled horizontally for better viewing. Alternatively, the optical path may be shifted diagonally rather than in the X or Y direction.

[0110] The subpanel pixel arrangement is not limited to the arrangements shown in Figures 3 and 22; for example, a delta arrangement where the red, green, and blue subpanel pixels are arranged in a triangle may also be used. Even with a delta arrangement, the resolution can be artificially increased by shifting the amount by {k + (p / 2)}. The shift trajectory may also be a triangle.

[0111] In the display panel 10 according to the embodiment, the transistor 124 is provided between the transistor 121 and the OLED 130, but the position in which the transistor 124 is provided is not limited to the above-mentioned space. The function of the transistor 124 is to interrupt the path through which the current controlled by the transistor 121 flows to the OLED 130, so it is acceptable to have a configuration in which the transistors 121 and 124 are connected in series between the power supply wiring 116 and 118. Note that the transistor 124 is an example of a fifth switching element.

[0112] Furthermore, in the display panel 10, transistors 124 are provided in the pixel circuits 110R, 110G, and 110B, and the ON state of transistor 124 causes transistor 121 to supply current to the OLED 130. However, in the first embodiment, since the light emission period of all OLEDs 130 is the same, for example, a power supply circuit (not shown) may be configured to supply a power potential ELvdd to the power supply wiring 116 in accordance with the light emission period.

[0113] In the embodiments, OLED130 was used as an example of a light-emitting element, but other light-emitting elements may be used. For example, LEDs (Light Emitting Diodes), mini-LEDs, micro-LEDs, etc., may be used as light-emitting elements.

[0114] The channel types of transistors 121, 122a, 122b, 123a, 123b, 124, 125, and 126 are not limited to the embodiment. Furthermore, these transistors, with the exception of transistor 121, may be replaced with transmission gates as appropriate.

[0115] <Note> From the above description, preferred embodiments of this disclosure can be understood, for example, as follows. For the sake of ease of understanding each embodiment, the reference numerals in the drawings are conveniently included in parentheses below, but this does not mean that the present invention is limited to the illustrated embodiments.

[0116] A projection device (1) according to one embodiment (embodiment 1) includes a display panel (10) which includes a plurality of light-emitting elements (130) that emit light in a predetermined direction, and an optical path shift element (20) which shifts the optical path of the light emitted from the plurality of light-emitting elements (130), wherein the display panel (20) emits light in accordance with the shift of the optical path. According to Embodiment 1, since light is emitted in accordance with the shift of the optical path, no inconsistencies in the display occur.

[0117] A projection device (1) according to a specific embodiment 2 of embodiment 1 includes a video processing circuit (40) that supplies video data to a display panel (10) and outputs a control signal to an optical path shift element (20), wherein the video processing circuit (40) uses the display panel (10) to light up a plurality of light-emitting elements (130) in a first period (e.g., L_f1), to turn off the plurality of light-emitting elements (130) in a second period (Vblnk) after the first period (L_f1), to light up the plurality of light-emitting elements (130) in a third period (L_f2) after the second period (Vblnk), and uses the optical path shift element (20) to fix the optical path in the first period (L_f1) and the third period (L_f2), and to shift the optical path in the second period (Vblnk). Note that the emission subframe L_f1 is an example of the first period, the vertical scan retrace period Vblnk is an example of the second period, and the emission subframe L_f2 is an example of the third period.

[0118] In the projection apparatus (1) according to specific embodiment 3 of embodiment 2, if the pitch of the projected pixels visible when the optical path is fixed is p, then the amount of optical path shift in the second period (Vblnk) is k + (p / 2), where k is a non-negative integer. According to embodiment 3, the pseudo-resolution can be increased by the projected pixels that are visible in the first period (Lf_1) and the third period (Lf_3).

[0119] In the projection device (1) according to a specific embodiment 4 of embodiment 3, the display panel (10) is equipped with panel pixels composed of sub-panel pixels that emit red, green, and blue light, and the pitch of the projection pixels corresponds to the pitch of the centroids of the panel pixels.

[0120] In the projection apparatus (1) according to specific embodiment 5 of embodiment 2, the optical path shift element (20) shifts the optical path of the composite light of multiple subpanel pixels, and if the pitch of the projected pixels visible when the optical path is fixed is p and the maximum diameter of the projected pixels is w, then the amount of optical path shift in the second period (VBlnk) is k + (p / 2), where k is a non-negative integer, and w <p / 2である。 According to embodiment 5, while avoiding overlap of projected pixels before and after the shift, the pseudo-resolution can be increased by the projected pixels visible in the first period (Lf_1) and the third period (Lf_3).

[0121] The projection device (1) according to embodiment 1 can be conceptualized as an embodiment (6) of the control method for the projection device (1). More specifically, the control method for the projection apparatus (1) according to embodiment 6 is a control method for a projection apparatus including a display panel (10) including a plurality of light-emitting elements (130) that emit light in a predetermined direction, and an optical path shift element (20) that shifts the optical path of the light emitted from the plurality of light-emitting elements (130), wherein in a first period (Lf_1), the display panel (10) lights up the plurality of light-emitting elements (130) and the optical path shift element (20) fixes the optical path; in a second period (Vblnk) after the first period (Lf_1), the display panel (10) turns off the plurality of light-emitting elements (130) and the optical path shift element (20) shifts the optical path; and in a third period (Lf_2) after the second period (Vblnk), the display panel (10) lights up the plurality of light-emitting elements (130) and the optical path shift element (20) fixes the optical path. According to embodiment 6, the optical path is fixed during the first period (L_f1) and third period (L_f2) when the light-emitting element (130) is lit, and the optical path shifts during the second period (Vblnk) when the light-emitting element (130) is turned off, so no inconsistency in the display occurs. [Explanation of symbols]

[0122] 1, 1A...Projection device, 10...Display panel, 12...Scan line, 14...Data line, 100...Display area, 110R, 110G, 110B...Pixel circuit, 116...Power supply wiring (high-level power supply wiring), 118...Power supply wiring (low-level power supply wiring), 121...Transistor (drive transistor), 122a...Transistor (first switching element), 122b...Transistor (second switching element), 123a...Transistor (third switching element), 123b...Transistor (fourth switching element), 124...Transistor (fifth switching element), 126...Transistor (sixth switching element), C1a...Capacitance element (first capacitance element), C1b...Capacitance element (first capacitance element), C2...Capacitance element (third capacitance element).

Claims

1. A display panel having a plurality of pixel circuits provided corresponding to the intersection of data lines and a plurality of scan lines, including a light-emitting element that emits light in a predetermined direction, a first selector, a second selector, a first capacitive element, a second capacitive element, a drive transistor capable of supplying a current to the light-emitting element according to the voltage of the gate node, and a switching element disposed between the light-emitting element and the drive transistor, which supplies a current output from the drive transistor to the light-emitting element according to a control signal, An optical path shift element that shifts the optical path of light emitted from the light-emitting elements of the plurality of pixel circuits for each unit period from the first unit period to the nth unit period (where n is an integer of 2 or more) included in one frame period, A video processing circuit that supplies video data to the display panel and outputs a control signal to the optical path shift element, Equipped with, In the odd-numbered unit periods included in the aforementioned one frame period, The aforementioned video processing circuit selects the plurality of scan lines in order, When a scan line corresponding to that pixel circuit is selected from the plurality of scan lines, the first selector electrically connects one end of the first capacitive element to the data line. The second selector in the first pixel circuit electrically connects one end of the second capacitive element to the gate node. In an even-numbered period included in the aforementioned one frame period, The aforementioned video processing circuit selects the plurality of scan lines in order, When one of the plurality of pixel circuits has selected a scan line corresponding to that pixel circuit from among the plurality of scan lines, the first selector electrically connects one end of the second capacitive element to the data line. The second selector in the first pixel circuit electrically connects one end of the first capacitive element to the gate node. The display panel turns off during the vertical scan retrace period after all of the multiple scan lines have been selected, and illuminates during periods other than the vertical scan retrace period. The optical path shifting element performs the optical path shift during the vertical scanning retrace period. Projection device.

2. If the pitch of the projected pixels visible when the optical path is fixed is p, The amount of the optical path shift during the vertical scanning retrace period k + (p / 2) And, k is a non-zero integer. The projection apparatus according to claim 1.

3. Each of the display panels comprises panel pixels composed of sub-panel pixels that emit red, green, and blue light, The pitch of the projection pixels corresponds to the pitch of the centroids of the panel pixels. The projection apparatus according to claim 2.

4. The optical path shifting element shifts the optical path of the combined light of multiple subpanel pixels. When the optical path is fixed, the pitch of the projected pixels visible is p. If the maximum diameter of the aforementioned projection pixel is w, The amount of the optical path shift during the vertical scanning retrace period k + (p / 2) And, k is a non-zero integer, w < p / 2 The projection apparatus according to claim 1.

5. A display panel having a plurality of pixel circuits provided corresponding to the intersection of data lines and a plurality of scan lines, including a light-emitting element that emits light in a predetermined direction, a first selector, a second selector, a first capacitive element, a second capacitive element, a drive transistor capable of supplying a current to the light-emitting element according to the voltage of the gate node, and a switching element disposed between the light-emitting element and the drive transistor, which supplies a current output from the drive transistor to the light-emitting element according to a control signal, An optical path shift element that shifts the optical path of light emitted from the light-emitting elements of the plurality of pixel circuits for each unit period from the first unit period to the nth unit period (where n is an integer of 2 or more) included in one frame period, A video processing circuit that supplies video data to the display panel and outputs a control signal to the optical path shift element, A control method for a projection device comprising: In the odd-numbered unit periods included in the aforementioned one frame period, The aforementioned video processing circuit selects the plurality of scan lines in order, When a scan line corresponding to that pixel circuit is selected from the plurality of scan lines, the first selector electrically connects one end of the first capacitive element to the data line. The second selector in the first pixel circuit electrically connects one end of the second capacitive element to the gate node. In an even-numbered period included in the aforementioned one frame period, The aforementioned video processing circuit selects the plurality of scan lines in order, When one of the plurality of pixel circuits has selected a scan line corresponding to that pixel circuit from among the plurality of scan lines, the first selector electrically connects one end of the second capacitive element to the data line. The second selector in the first pixel circuit electrically connects one end of the first capacitive element to the gate node. The display panel turns off during the vertical scan retrace period after all of the multiple scan lines have been selected, and illuminates during periods other than the vertical scan retrace period. The optical path shifting element shifts the optical path during the vertical scanning retrace period. A method for controlling a projection device.

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