Shift register circuit and its driving method, gate driving circuit, display device

Abstract

SOLUTION: A shift register circuit (RS) includes a noise elimination control sub-circuit (20) and a noise elimination sub-circuit (30), wherein the noise elimination control sub-circuit (20) is configured to generate an alternating voltage signal from voltage of a first voltage terminal (VSS) and a signal from a second clock signal terminal (CB1) in response to a signal from a first clock signal terminal (CK1), and rectify the alternating voltage signal and then output the signal to a first noise elimination control node (PD-ox), so that voltage of the first noise elimination control node (PD-ox) is maintained to be voltage that enables the noise elimination sub-circuit (30) to be started, and the noise elimination sub-circuit (30) is configured to continuously be started under the control of the voltage of the first noise elimination control node (PD-ox), so as to eliminate noise from a scanning signal output terminal (Oput).EFFECT: A shift register circuit is provided which solves the problem that screen display becomes unstable.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] This application claims priority based on a Chinese patent application with application number 202010356184.0 filed on April 29, 2020, and all of its content is incorporated herein by reference.

[0002] The present disclosure relates to the field of display technologies, and particularly to a shift register circuit, its control method, a gate driving circuit, and a display device.

Background Art

[0003] With the progress of display technologies, semiconductor device technologies, which are the core of display devices, have also made great progress. As a type of current-emitting device, an Organic Light Emitting Diode (OLED) can emit light spontaneously, has characteristics such as fast response, wide viewing angle, and can be fabricated on a flexible substrate, so its application to high-performance display devices has been increasing.

Summary of the Invention

Means for Solving the Problems

[0004] In a first aspect, a shift register circuit is provided. The shift register circuit includes a noise removal control sub-circuit and a noise removal sub-circuit. Here, the noise removal control sub-circuit is coupled to a first voltage terminal, a first clock signal terminal, a second clock signal terminal, and a first noise removal control node. The noise removal control sub-circuit generates an alternating voltage signal from the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to the signal of the first clock signal terminal, rectifies the alternating voltage signal, and outputs the signal to the first noise removal control node, thereby maintaining the voltage of the first noise removal control node at a voltage that turns on the noise removal sub-circuit. The noise removal sub-circuit is coupled to the first noise removal control node and a scan signal output terminal. The noise removal sub-circuit is configured to perform noise removal on the scan signal output terminal in response to the voltage of the first noise removal control node being a voltage that turns on the noise removal sub-circuit.

[0005] In some embodiments, the noise removal control sub-circuit includes a first on-control sub-circuit and a second on-control sub-circuit. Here, the first on-control sub-circuit is coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and a second noise removal control node, and outputs the voltage of the first voltage terminal to the second noise removal control node periodically in response to the signal of the first clock signal terminal, and adjusts the voltage of the second noise removal control node periodically based on the signal of the second clock signal terminal, thereby configuring the second noise removal control node to be supplied with an alternating voltage signal. The second on-control sub-circuit is coupled to the first noise removal control node and the second noise removal control node, and is configured to rectify the alternating voltage signal and output the signal to the first noise removal control node in response to the alternating voltage signal supplied by the second noise removal control node.

[0006] In some embodiments, the first ON control subcircuit includes a first transistor and a first capacitor, and / or the second ON control subcircuit includes a second transistor and a second capacitor. The control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the second noise rejection control node. The first terminal of the first capacitor is coupled to the second clock signal terminal, and the second terminal of the first capacitor is coupled to the second noise rejection control node. The control electrode of the second transistor is coupled to the second noise rejection control node, the first electrode of the second transistor is coupled to the first noise rejection control node, and the second electrode of the second transistor is coupled to the second noise rejection control node. The first terminal of the second capacitor is coupled to the first signal terminal, and the second terminal of the second capacitor is coupled to the first noise rejection control node.

[0007] In some embodiments, the noise suppression control subcircuit is further coupled to a cascaded signal output terminal and a second signal terminal, and is further configured to control the noise suppression subcircuit to be turned off based on the signal at the second signal terminal in response to the voltage at the cascaded signal output terminal.

[0008] In some embodiments, the noise suppression control subcircuit includes a first ON control subcircuit, a second ON control subcircuit, and an OFF control unit. The first ON control subcircuit is coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and the second noise suppression control node, and is configured to periodically output the voltage of the first voltage terminal to the second noise suppression control node in response to the signal of the first clock signal terminal, and to periodically adjust the voltage of the second noise suppression control node based on the signal of the second clock signal terminal, thereby supplying an alternating voltage signal to the second noise suppression control node. The second ON control subcircuit is coupled to the first noise suppression control node and the second noise suppression control node, and is configured to rectify the alternating voltage signal supplied by the second noise suppression control node and output the signal to the first noise suppression control node in response to the alternating voltage signal. The OFF control unit is coupled to the cascade signal output terminal and the second signal terminal, and further includes a third transistor and a fourth transistor. The control electrode of the third transistor is coupled to the cascade signal output terminal, the first electrode of the third transistor is coupled to the second signal terminal, and the second electrode of the third transistor is coupled to the second noise reduction control node. The control electrode of the fourth transistor is coupled to the cascade signal output terminal, the first electrode of the fourth transistor is coupled to the second signal terminal, and the second electrode of the fourth transistor is coupled to the first noise reduction control node.

[0009] In some embodiments, the first ON control subcircuit further includes a fifth transistor. The first terminal of the first capacitor is coupled to the second clock signal terminal via the fifth transistor. The control electrode of the fifth transistor is coupled to the scan signal output terminal, the first electrode of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the first terminal of the first capacitor.

[0010] In some embodiments, the first signal terminal is coupled to the first voltage terminal or the first clock signal terminal.

[0011] In some embodiments, the noise reduction subcircuit includes a sixth transistor. The control electrode of the sixth transistor is coupled to the first noise reduction control node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the scan signal output terminal.

[0012] In some embodiments, the shift register circuit further includes an input subcircuit and an output subcircuit. Here, both the input subcircuit and the denoising subcircuit are coupled to a cascade signal output terminal, the input subcircuit is further coupled to an output subcircuit, and the denoising control subcircuit is configured to control the voltage at the cascade signal output terminal to turn the denoising subcircuit on or off, and is further configured to transmit an on signal to the output subcircuit. The output subcircuit is further coupled to the second voltage terminal or a fifth clock signal terminal, and the output subcircuit is further coupled to the scan signal output terminal. The output subcircuit is configured to transmit the signal at the second voltage terminal or the fifth clock signal terminal to the scan signal output terminal in response to an on signal transmitted from the input subcircuit.

[0013] In some embodiments, the input subcircuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third capacitor, an eleventh transistor, a fourth capacitor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The control electrode of the seventh transistor is coupled to the third clock signal terminal, the first electrode of the seventh transistor is coupled to the input signal terminal, and the second electrode of the seventh transistor is coupled to the first node.

[0014] The control electrode of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the third clock signal terminal, and the second electrode of the eighth transistor is connected to the second node.

[0015] The control electrode of the ninth transistor is coupled to the third clock signal terminal, the first electrode of the ninth transistor is coupled to the first voltage terminal, and the second electrode of the ninth transistor is coupled to the second node.

[0016] The control electrode of the 10th transistor is coupled to the 2nd node, the 1st electrode of the 10th transistor is coupled to the 2nd voltage terminal, and the 2nd electrode of the 10th transistor is coupled to the cascade signal output terminal.

[0017] The first terminal of the third capacitor is connected to the second node, and the second terminal of the third capacitor is connected to the first electrode and second voltage terminal of the tenth transistor.

[0018] The control electrode of the 11th transistor is coupled to the 3rd node, the 1st electrode of the 11th transistor is coupled to the 4th clock signal terminal, and the 2nd electrode of the 11th transistor is coupled to the cascade signal output terminal.

[0019] The first terminal of the fourth capacitor is connected to the third node, and the second terminal of the fourth capacitor is connected to the second electrode of the eleventh transistor and the cascade signal output terminal.

[0020] The control electrode of the 12th transistor is coupled to the first voltage terminal, the second electrode of the 12th transistor is coupled to the third node, and the first electrode of the 12th transistor is coupled to the first node.

[0021] The control electrode of the 13th transistor is coupled to the 4th clock signal terminal, the 1st electrode of the 13th transistor is coupled to the 1st node, and the 2nd electrode of the 13th transistor is coupled to the 4th node.

[0022] The control electrode of the 14th transistor is coupled to the second node, the first electrode of the 14th transistor is coupled to the second voltage terminal, and the second electrode of the 14th transistor is coupled to the fourth node.

[0023] The output subcircuit includes a 15th transistor. The control electrode of the 15th transistor is coupled to the cascade signal output terminal or the third node, the first electrode of the 15th transistor is coupled to the second voltage terminal or the fifth clock signal terminal, and the second electrode of the 15th transistor is coupled to the scan signal output terminal.

[0024] In some embodiments, the second signal terminal is coupled to the second voltage terminal, or the second signal terminal is coupled to the second node.

[0025] In some embodiments, the third clock signal terminal is coupled to the first clock signal terminal, and the fourth clock signal terminal is coupled to the second clock signal terminal.

[0026] In a second embodiment, a gate drive circuit is provided. The gate drive circuit includes a plurality of cascaded shift register circuits. The shift register circuit is the shift register circuit described in any one of the embodiments described above.

[0027] In a third embodiment, a display device is provided. The display device includes a plurality of gate lines and the gate drive circuit described in the second embodiment. Each shift register circuit in the gate drive circuit is coupled to at least one gate line.

[0028] In some embodiments, the scan signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one gate line.

[0029] In some embodiments, the plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines, the scan signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one first gate line, and the cascade signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one second gate line.

[0030] A fourth embodiment provides a method for driving a shift register circuit as described in any one of the above embodiments. The driving method includes, in the holding stage, a noise reduction control subcircuit of the shift register circuit generating an alternating voltage signal from the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to the signal of the first clock signal terminal, rectifying the generated alternating voltage signal and outputting the signal to the first noise reduction control node, thereby holding the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit, and the noise reduction subcircuit performing noise reduction on the scan signal output terminal in response to the voltage of the first noise reduction control node being a voltage that turns on the noise reduction subcircuit.

[0031] In some embodiments, the driving method further includes, where the shift register circuit further includes an input subcircuit and an output subcircuit, the input subcircuit and the noise reduction control subcircuit are both coupled to a cascade signal output terminal, and in the input stage, the input subcircuit controls the voltage at the cascade signal output terminal to a first control voltage in response to a signal at a third clock signal terminal coupled thereto, thereby causing the noise reduction control subcircuit to turn on the noise reduction subcircuit and transmit an ON signal to the output subcircuit; and in the output stage, the input subcircuit controls the voltage at the cascade signal output terminal to a second control voltage, thereby causing the noise reduction control subcircuit to turn off the noise reduction subcircuit and continuing to transmit an ON signal to the output subcircuit. In a fifth embodiment, a shift register circuit is provided, comprising a first transistor, a first capacitor, a second transistor, a second capacitor, and a sixth transistor. The control electrode of the first transistor is coupled to a first clock signal terminal, the first electrode of the first transistor is coupled to a first voltage terminal, and the second electrode of the first transistor is coupled to a second noise suppression control node. The first terminal of the first capacitor is coupled to a second clock signal terminal, and the second terminal of the first capacitor is coupled to the second noise suppression control node. The control electrode of the second transistor is coupled to the second noise suppression control node, the first electrode of the second transistor is coupled to the first noise suppression control node, and the second electrode of the second transistor is coupled to the second noise suppression control node. The first terminal of the second capacitor is coupled to a first signal terminal, and the second terminal of the second capacitor is coupled to the first noise suppression control node. The control electrode of the sixth transistor is coupled to the first noise suppression control node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the scan signal output terminal. In some embodiments, the shift register circuit further includes a third transistor and a fourth transistor. The control electrode of the third transistor is coupled to the cascade signal output terminal, the first electrode of the third transistor is coupled to the second signal terminal, and the second electrode of the third transistor is coupled to the second noise reduction control node. The control electrode of the fourth transistor is coupled to the cascade signal output terminal, the first electrode of the fourth transistor is coupled to the second signal terminal, and the second electrode of the fourth transistor is coupled to the first noise reduction control node. [Brief explanation of the drawing]

[0032] To more clearly explain the technical concepts in this disclosure, the following is a brief description of the accompanying drawings that may be used in some embodiments of this disclosure. Obviously, the drawings in the following description are merely accompanying drawings for some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these. Furthermore, the drawings in the following description can be considered schematic diagrams and do not limit the actual dimensions of the products, the actual processes of the methods, the actual sequences of signals, etc., relating to the embodiments of this disclosure.

[0033] [Figure 1A] This is a diagram showing the configuration of a display panel according to an embodiment of the present disclosure.

[0034] [Figure 1B] This is a gate drive architecture diagram of a display panel according to an embodiment of the present disclosure.

[0035] [Figure 2] This is a diagram showing the configuration of a pixel circuit related to the relevant technology.

[0036] [Figure 3] This is a partial diagram of a shift register circuit related to the relevant technology.

[0037] [Figure 4] This is a partial drive sequence diagram of a shift register circuit related to the relevant technology.

[0038] [Figure 5] This figure shows the output noise of a shift register circuit related to the relevant technology.

[0039] [Figure 6] This is a diagram showing the configuration of a shift register circuit according to an embodiment of the present disclosure.

[0040] [Figure 7] This is a configuration diagram of another shift register circuit according to an embodiment of the present disclosure.

[0041] [Figure 8] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0042] [Figure 9] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0043] [Figure 10] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0044] [Figure 11] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0045] [Figure 12] This is a drive sequence diagram of a shift register circuit according to an embodiment of the present disclosure.

[0046] [Figure 13] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0047] [Figure 14] This is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0048] [Figure 15] This is a drive sequence diagram of a shift register circuit according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0049] The following describes, with reference to the drawings, some of the technical concepts in the embodiments of this disclosure clearly and completely. It is clear that the embodiments described are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments relating to this disclosure are all within the scope of protection of this disclosure.

[0050] Unless otherwise required by context, throughout this specification and the claims, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted as having an open, inclusive meaning, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that a particular feature, structure, material, or property relating to that embodiment or example is included in at least one embodiment or example of this disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any particular feature, structure, material, or property described may be included in any one or more embodiments or examples in any suitable manner.

[0051] Hereafter, the terms “First” and “Second” are used solely for descriptive purposes and should not be understood as implicitly indicating the relative importance of any technical feature or the number of such features expressed or implied. Therefore, features limited by “First” and “Second” may include one or more such features, either expressly or implicitly. In the description of the embodiments of this disclosure, unless otherwise specified, “multiple” means two or more.

[0052] In describing some embodiments, the terms “coupled,” “connected,” and related expressions may be used. For example, in describing some embodiments, the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other. Also, for example, in describing some embodiments, the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact with each other. However, the terms “coupled” or “communicatively coupled” may also indicate that two or more components are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to those described herein.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and both include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0054] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, the term "when" is optionally interpreted, depending on the context, to mean "when," "on the occasion of," "in response to the determination of," or "in response to the detection of." Similarly, depending on the context, the phrases "when it is determined" or "[the described condition or event] is detected" are optionally interpreted to mean "when it is determined," "in response to the determination of," "[the described condition or event] is detected," or "[the described condition or event] is detected."

[0056] In this specification, the use of “applicable to…” or “configured to…” means open and inclusive language that does not exclude devices applied to or configured to perform additional tasks or steps.

[0057] Furthermore, the use of “based on” implies that a process, step, calculation, or other action performed “on the basis” of one or more of the aforementioned conditions or values ​​may, in fact, be based on exceeding additional conditions or values, thus being open and inclusive.

[0058] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the mean value within an acceptable range of deviation of a particular value, where the acceptable range of deviation is determined taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., limitations of the measurement system) as considered by those skilled in the art.

[0059] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape from the drawings may be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, exemplary embodiments should be interpreted as including not only the shapes of the regions illustrated herein, but also variations in shape due to manufacturing, etc. For example, etching regions shown as rectangles typically have curved characteristics. Therefore, the regions shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of the regions in the apparatus, nor are they intended to limit the scope of the exemplary embodiments.

[0060] Some embodiments of this disclosure provide display devices. A display device means a product having an image display function, and exemplary such a display device may be a television, a mobile phone, a computer, a notebook computer, a tablet, a personal digital assistant (PDA), an in-vehicle computer, a display, a sign, a digital photo frame, a laser printer with a display function, a telephone, a digital camera, a portable video recorder, a viewfinder, a monitor, a navigation device, a vehicle, a large-area wall, a home appliance, an information inquiry device (e.g., business inquiry devices and monitors for departments such as e-government, banks, hospitals, and power companies). A display device includes a frame, a display panel provided within the frame, a circuit board, an integrated circuit (IC), and other electronic components.

[0061] The above-mentioned display panel may be a liquid crystal display panel (LCD), an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro-LED (including miniLED or microLED) display panel, etc., and this disclosure does not specifically limit it.

[0062] The following embodiments of this disclosure will be described using the case where the display panel is an OLED display panel as an example.

[0063] As shown in Figure 1A, the display panel 100 includes a display area AA (Active Area) and a peripheral area BB located on at least one side of the display area AA. Figure 1A shows that the peripheral area BB encircles the display area AA.

[0064] The display panel 100 includes a plurality of subpixels P of multiple colors located in the display area AA, and the plurality of subpixels include at least a first color subpixel, a second color subpixel, and a third color subpixel, and the first, second, and third colors may be the three primary colors (for example, red, green, and blue).

[0065] For the sake of explanation, this disclosure will describe the case in which the above-mentioned multiple subpixels P are arranged in a matrix. In this case, subpixels P arranged in a row in the horizontal direction X are called subpixels of the same row, and subpixels P arranged in a column in the vertical direction Y are called subpixels of the same column.

[0066] As shown in Figure 1B, each sub-pixel P is provided with a pixel circuit (also called a pixel driving circuit) S containing multiple transistors (Figure 1B shows two transistors). This pixel circuit S is coupled to a light-emitting element L and is used to drive the light-emitting element L to emit light. Here, pixel circuits S located in the same row are connected to the same gate line GL (i.e., coupled), and pixel circuits S located in the same column are connected to the same data line DL (Data Line). Furthermore, the arrangement of the multiple sub-pixels P depends on the arrangement of the pixel circuits S in the multiple sub-pixels P, regardless of the position of the light-emitting element L in the sub-pixels P.

[0067] The transistors included in the pixel circuit S may all be N-type transistors, or all be P-type transistors, or may include both N-type and P-type transistors, and can be designed according to actual requirements.

[0068] Furthermore, the pixel circuit S may include at least one of low-temperature polysilicon (LTPS) transistors and oxide transistors. For example, the transistors in the pixel circuit S may all be LTPS transistors, or all be oxide transistors, or it may include both LTPS transistors and oxide transistors simultaneously.

[0069] In some embodiments, the voltage controlling the brightness of subpixels changes over time due to the leakage current of the transistors in the pixel circuit S. Therefore, to maintain the brightness fluctuations of the subpixels within an appropriate range, it is still necessary to refresh the data when displaying still images. To reduce power consumption when displaying still images, it is effective to lower the refresh frequency. However, since it is necessary to maintain display quality while lowering the refresh frequency, it is necessary to reduce the leakage rate of the transistors in the pixel circuit S. Oxide semiconductors have ultra-low leakage characteristics, so by using oxide transistors in the pixel circuit S, leakage of the transistors in the pixel circuit S can be reduced during the process in which the display panel displays the screen. Low-temperature polysilicon has high carrier mobility. When using LTPS transistors in the pixel circuit S, the response speed of the transistors can be significantly improved, thereby ensuring the charging speed of the subpixels. Furthermore, since the source and drain of the LTPS transistor are formed by automatic alignment using an ion implantation method, the parasitic capacitance generated between the gate and source and drain is significantly smaller than that of amorphous silicon transistors, and the capacitive coupling effect is also significantly reduced. To reduce transistor leakage in pixel circuits while ensuring fast sub-pixel charging and low parasitic capacitance, a low-temperature polycrystalline oxide (LTPO) process may be employed, combining the advantages of LTPS and oxide. For example, the pixel circuit S may include both LTPS transistors and oxide transistors. For instance, the pixel circuit S may include a P-type LTPS transistor and an N-type oxide transistor.

[0070] Continuing to refer to Figures 1A and 1B, the display device may further include a gate drive circuit 01 and a data drive circuit 02. Exemplarily, the gate drive circuit 01 may be located in the peripheral region BB of the display panel 100, for example, on the side located at one end of the gate line GL in the peripheral region BB (for example, the left side of the peripheral region BB in Figure 1A). Exemplarily, the data drive circuit 02 may be located in the peripheral region BB of the display panel 100. For example, the data drive circuit 02 may be located on the side located at one end of the data line DL in the peripheral region BB (for example, the lower side of the peripheral region BB in Figure 1A). This drives the pixel circuit S in the display panel 100 and further drives the light-emitting element L to emit light, thereby displaying the color to be displayed on the corresponding sub-pixel P.

[0071] In some embodiments, the gate drive circuit 01 may be a gate drive IC bonded to the array substrate (also called a drive backplane) of the display panel 100. In some other embodiments, the gate drive circuit 01 may be a GOA (Gate Driver on Array) circuit and may be included in the display panel 100. In this case, the gate drive circuit 01 is directly integrated into the array substrate of the display panel 100. Providing the gate drive circuit 01 on the array substrate reduces the manufacturing cost of the display panel 100 compared to bonding it to the array substrate using a gate drive IC, and also allows for a narrower bezel width of the display device. In the following embodiments, the case where the gate drive circuit 01 is a GOA circuit will be used as an example.

[0072] Figures 1A and 1B show an example of one-sided driving, where the gate drive circuit 01 is provided on only one side of the peripheral region BB of the display panel 100, and each gate line GL is driven row by row from one side. In some other embodiments, gate drive circuits may be installed along the two sides in the extending direction of the gate line GL in the peripheral region BB of the display panel 100, and each gate line GL may be driven row by row from both sides simultaneously by the two gate drive circuits, i.e., both-sided driving. In some other embodiments, gate drive circuits may be installed along the two sides in the extending direction of the gate line GL in the peripheral region BB of the display panel 100, and each gate line GL may be driven row by row from both sides alternately by the two gate drive circuits, for example, one gate drive circuit may drive the odd-numbered rows of gate line GL and the other gate drive circuit may drive the even-numbered rows of gate line GL, i.e., alternating driving. The following embodiments of this disclosure will all be described using one-sided driving as an example.

[0073] In some embodiments of this disclosure, as shown in Figure 1B, the gate drive circuit 01 includes N stages (where N is a positive integer) of cascaded shift register circuits (RS1, RS2, ..., RS(N)), and each of the N stages of cascaded shift register circuits (RS1, RS2, ..., RS(N)) is connected in a one-to-one correspondence with N gate lines (G1, G2, ..., G(N)).

[0074] For example, the circuit structure of each stage of the shift register circuits (RS1, RS2, ..., RS(N)) may be the same, and each stage of the shift register circuits (RS1, RS2, ..., RS(N)) is connected sequentially so that each stage of the shift register circuits outputs an on voltage (active level in the scanning signal, also called a high level). This enables scanning of multiple gate lines on the display panel row by row and charges the subpixels of each row coupled to the gate lines.

[0075] For example, as shown in Figure 1B, the first stage shift register circuit of the gate drive circuit 01 is denoted as RS(i) (where i=1,2,...,N). The shift register circuit RS(i) includes a scan signal output terminal Output (in the following description and diagrams, Output will be abbreviated as Oput). This outputs a gate scan signal to the gate line GL connected to the scan signal output terminal Oput.

[0076] Each stage of the gate drive circuit 01's shift register circuit RS(i) is further provided with a signal input terminal Input (abbreviated as Iput in the diagram and the following description) to supply a start signal to each stage of the shift register circuit RS(i).

[0077] Furthermore, each stage of the gate drive circuit 01's shift register circuit RS(i) further includes a cascade signal output terminal GP, which can be connected to the next stage shift register circuit. This allows the cascade signal to be transmitted to the next stage shift register circuit as a start signal for that next stage shift register circuit.

[0078] Based on this, the cascaded configuration of each stage of the shift register circuit RS(i) in the gate drive circuit 01 may be as follows.

[0079] The signal input terminal Iput of the first-stage shift register circuit RS1 is connected to the start signal terminal STV, and the signal input terminal Iput of any other stage shift register circuit RS(i), excluding the first-stage shift register circuit RS1, is connected to the cascade signal output terminal GP of the shift register circuit RS(i-1) located in the preceding stage.

[0080] Based on the above cascade configuration, the scan signal output terminal Oput of each stage's shift register circuit RS(i) is coupled to at least one gate line GL.

[0081] In some embodiments, for example, if the pixel circuit S includes not only a P-type LTPS transistor but also an N-type oxide transistor, the cascade signal output terminal GP may be connected to the P-type transistor in the pixel circuit S via a gate line to transmit a signal (which may be called a control signal) to the P-type transistor and control the on / off state of the P-type transistor.

[0082] Based on this, the connection relationships between each stage of the shift register circuits (RS1, RS2, ..., RS(N)) in the gate drive circuit 01 and the multiple gate lines GL can be as follows.

[0083] Each pixel circuit in the same row may be coupled to at least two gate lines, including at least one first gate line and at least one second gate line. The scan signal output terminal Oput of each shift register circuit in the gate drive circuit is coupled to at least one first gate line, and the cascade signal output terminal GP of each shift register circuit in the gate drive circuit is coupled to at least one second gate line. Here, the gate line coupled to the scan signal output terminal Oput and the gate line coupled to the cascade signal output terminal GP are not the same line, so to make them easier to distinguish, the gate line coupled to the scan signal output terminal Oput is referred to as the first gate line, and the gate line coupled to the cascade signal output terminal GP is referred to as the second gate line.

[0084] Referring to the 7T1C pixel circuit shown in Figure 2, the control method for an LTPO type pixel circuit will be explained using this pixel circuit as an example. As shown in Figure 2, the pixel circuit S' includes seven transistors D1 to D7 and one capacitor Cst. Here, transistors D3 and D4 are N-type transistors, for example, N-type oxide transistors, and transistors D2 and D7 are P-type transistors, for example, P-type LTPS transistors. Then, in any of the pixel circuits S' in row i, transistors D3 and D4 can be coupled to the scan signal output terminal Oput(i) of this stage and the scan signal output terminal Oput(i-1) of the previous stage, respectively, via two first gate lines, and transistors D2 and D7 can be coupled to the cascade signal output terminal GP(i) of this stage and the cascade signal output terminal GP(i-1) of the previous stage, respectively, via two second gate lines.

[0085] The shift register circuit controls the oxide transistor and LTPS transistor in the LTPO-type pixel circuit via the first and second gate lines, respectively, and can significantly improve the response time of this control process.

[0086] In some related technologies, in the process of driving one row of gate lines within one frame period, a single-stage shift register circuit first outputs an on-voltage (also called an active voltage or operating voltage) in the scan signal to the gate line coupled to it, turning on one row of subpixels coupled to this gate line. This stage is called the output stage. Subsequently, this stage of the shift register circuit outputs an off-voltage (also called a non-operating voltage) in the scan signal to the gate line coupled to it, ensuring that the subpixels coupled to this gate line are turned off. That is, it enters the holding stage. However, in the holding stage, the noise at the scan signal output terminal coupled to the gate line in the shift register circuit is large, resulting in an unstable display on the display device.

[0087] The inventors of this disclosure have found through their investigation that one of the causes of the above problem is as follows:

[0088] As shown in Figures 3 and 4, Figure 3 shows a partial circuit configuration of the shift register circuit RS' in the related technology, and Figure 4 shows the partial drive sequence of this shift register circuit RS'. In Figure 3, 30' is a noise reduction subcircuit, and this noise reduction subcircuit 30' includes transistor T03.

[0089] In the driving process of one gate line, at output stage P2', the potential of the cascade signal output terminal GP is low, transistor T04 turns on, and the scan signal output terminal Oput outputs a high level, i.e., outputs a scan signal. Transistor T02 turns on, and the potential of node PD-ox' is high, which causes transistor T03 in the noise reduction subcircuit 30' to turn off.

[0090] During the holding phase P3', in period P31', the potential of the clock signal terminal CK1 is low, transistor T01 is on, and the potential of node PD-ox' is low V SS +|V th | is (where V th (This is the threshold voltage of transistor T01). As a result, transistor T03 in the noise reduction subcircuit 30' turns on, and the potential of the scan signal output terminal Oput becomes a low potential V SS +|V th This results in a | shape, and the scan signal output terminal Oput is reset.

[0091] During the holding phase P3', in period P32', the potential of the clock signal terminal CK1 is high, so transistor T01 is off. Also, the potential of the cascade signal output terminal GP is high, so transistor T02 is off. Therefore, the potential of node PD-ox' is floating. The potential of the clock signal terminal CB1 becomes low, and due to the coupling effect of capacitor C01, the potential of node PD_ox' is further pulled down. Transistor T03 in the noise reduction subcircuit 30' is further turned on, the potential of the scan signal output terminal Oput becomes low, and a further reset of the scan signal output terminal Oput is achieved.

[0092] During the period P33' of the holding stage P3', the potential of the clock signal terminal CK1 is at a low level, but PD_ox' is also at a low level. Also, since the threshold voltage V th of the PMOS (Positive-channel Metal Oxide Semiconductor) transistor is generally a negative value, the gate-source voltage difference V gs >V th of the transistor T01. V gs <V th In this case, since the PMOS transistor is on, at this time, the transistor T01 is off. Also, since the potential of the cascade signal output terminal GP is at a high level and the transistors T02 and T04 are also off, the potentials of the node PD-ox' and the scan signal output terminal Oput are in a floating state. The potential of the clock signal terminal CB1 is at a high level. Due to the coupling effect of the capacitor C01, the potential of the node PD_ox' is slightly pulled up, whereby the transistor T03 in the noise removal sub-circuit 30' is off and the noise removal of the scan signal output terminal Oput cannot be performed.

[0093] Thus, since the clock signals CK1 and CB1 alternately become high level and low level, thereafter, the periods P32' and P33' alternately appear. Therefore, in the holding stage, in a period that is almost close to half (that is, the period P33' of the holding stage P3'), the noise removal sub-circuit 30' cannot perform noise removal of the scan signal output terminal Oput. As a result, when it is disturbed, the shift register circuit RS' cannot perform noise removal in a timely manner in the holding stage P3', and there is a possibility that a large amount of noise will occur at the scan signal output terminal Oput. As shown in FIG. 5, as a result of the simulation test, in the holding stage P3', the noise of the scan signal output terminal Oput can reach 2V.

[0094] Some embodiments of this disclosure provide a shift register circuit that solves the problem of unstable screen display due to high noise at the scan signal output terminal coupled to the gate line in the shift register circuit during the holding phase. As shown in Figure 6, the shift register circuit RS includes a noise reduction control subcircuit 20 and a noise reduction subcircuit 30.

[0095] Here, the noise suppression control subcircuit 20 is coupled to the first voltage terminal VSS, the first clock signal terminal CK1, the second clock signal terminal CB1, and the first noise suppression control node PD-ox. The noise suppression control subcircuit 20 is configured to rectify the charge at the first voltage terminal VSS to the first noise suppression control node PD-ox under the control of the signal at the first clock signal terminal CK1. By doing so, the voltage at the first noise suppression control node PD-ox can be adjusted (pulled up or pulled down) to maintain the voltage at which the noise suppression subcircuit 30 is turned on. Specifically, the noise suppression control subcircuit 20 is configured to generate an alternating voltage signal (in other words, an oscillation signal) from the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1 in response to the signal of the first clock signal terminal CK1, rectify the generated alternating voltage signal and output the signal to the first noise suppression control node PD-ox, and maintain the voltage of the first noise suppression control node PD-ox at a voltage that turns on the noise suppression subcircuit 30. For example, the voltage of the first noise suppression control node PD-ox can be gradually changed (gradually pulled up or pulled down) until, for example, a steady state is reached.

[0096] Here, an alternating voltage signal refers to a signal whose voltage magnitude changes periodically. For example, an alternating voltage signal may be a signal in which high and low voltages appear alternately, such as a square wave signal. Here, the duration of the high voltage and the duration of the low voltage within one period may be the same or different. Furthermore, the amplitude value of the alternating voltage signal may be kept constant; for example, the high voltages and low voltages may be equal across multiple periods.

[0097] Rectification refers to outputting an alternating voltage signal as a DC voltage signal. In embodiments of this disclosure, the DC voltage signal is defined in comparison to the alternating voltage signal and may be a signal whose voltage does not change over time. It may also include a signal whose amplitude (voltage) gradually increases or decreases over time, and this signal can eventually reach a steady state (i.e., the voltage no longer changes). For example, the DC voltage signal may include multiple periods, where the magnitude of the voltage in each period is constant, and the voltage in any period is higher than the voltage in the previous period, or the voltage in any period is lower than the voltage in the previous period.

[0098] The aforementioned "voltage to turn on the noise reduction subcircuit 30" refers to the voltage at which the noise reduction subcircuit 30 can be operated, and this voltage should be understood to depend specifically on the type of transistor included in the noise reduction subcircuit 30. For example, if the transistor included in the noise reduction subcircuit 30 is P-type, this voltage is a low-level voltage, and if the transistor included in the noise reduction subcircuit 30 is N-type, this voltage is a high-level voltage. The noise reduction subcircuit 30 is coupled to the first noise reduction control node PD-ox and the scan signal output terminal Oput. The noise reduction subcircuit 30 is configured to perform noise reduction on the scan signal output terminal Oput in response to the voltage of the first noise reduction control node being the voltage to turn on the noise reduction subcircuit.

[0099] In the shift register circuit RS described above, the noise reduction control subcircuit 20, under the control of the signal from the first clock signal terminal CK1, adjusts the voltage of the first noise reduction control node PD-ox to stabilize based on the received signal (which may include, for example, the signal from the first voltage terminal VSS and the signal from the second clock signal terminal CB1), that is, it can stabilize the voltage of the first noise reduction control node PD-ox to a voltage (high level or low level) that turns on the noise reduction subcircuit 30. The noise reduction control subcircuit 20 outputs the adjusted voltage to the noise reduction subcircuit 30 and controls it to maintain the state in which the noise reduction subcircuit 30 remains on, thereby enabling the noise reduction subcircuit 30 to continuously output a stable non-operating voltage and continue to perform noise reduction on the scan signal output terminal Oput, thereby improving the stability of the screen display.

[0100] In some embodiments, as shown in Figure 7, the noise suppression control subcircuit 20 includes an ON control unit 21 and an OFF control unit 22. Here, the ON control unit 21 is coupled to a first voltage terminal VSS, a first clock signal terminal CK1, a second clock signal terminal CB1, and a first noise suppression control node PD-ox. The ON control unit 21 is configured to rectify the charge at the first voltage terminal VSS and the charge at the second clock signal terminal CB1 to the first noise suppression control node PD-ox under the control of the signal at the first clock signal terminal CK1. By doing so, the voltage at the first noise suppression control node PD-ox can be maintained at a voltage that turns on the noise suppression subcircuit 30 by pulling up or pulling down the voltage at the first noise suppression control node PD-ox.

[0101] Specifically, the ON control unit 21 responds to the signal at the first clock signal terminal CK1 by generating an alternating voltage signal from the voltage at the first voltage terminal VSS and the signal at the second clock signal terminal CB1, rectifies the generated alternating voltage signal, and outputs the signal to the first noise reduction control node PD-ox, thereby maintaining the voltage at the first noise reduction control node PD-ox at a voltage that turns on the noise reduction subcircuit 30. Exemplarily, the ON control unit 21 may be coupled to the second noise reduction control node PD-ox-i, in which case the generated alternating voltage signal is the signal at the second noise reduction control node PD-ox-i.

[0102] Here, the first voltage terminal VSS is configured to transmit, for example, a DC low-level signal. For example, this first voltage terminal VSS is grounded. In some embodiments, as shown in Figure 8, the ON control unit 21 of the noise suppression control subcircuit 20 includes a first ON control subcircuit 211 and a second ON control subcircuit 212.

[0103] Here, the first ON control subcircuit 211 is coupled to the first clock signal terminal CK1, the second clock signal terminal CB1, the first voltage terminal VSS, and the second noise reduction control node PD-ox-i. In response to the signal from the first clock signal terminal CK1, it periodically outputs the voltage from the first voltage terminal VSS to the second noise reduction control node PD-ox-i, and based on the signal from the second clock signal terminal CB1, it periodically adjusts the voltage of the second noise reduction control node PD-ox-i, thereby supplying an alternating voltage signal to the second noise reduction control node PD-ox-i.

[0104] For illustrative purposes, referring to Figure 8, the first ON control subcircuit 211 includes a first transistor T1 and a first capacitor C1.

[0105] Here, the control electrode of the first transistor T1 is coupled to the first clock signal terminal CK1, the first electrode of the first transistor T1 is coupled to the first voltage terminal VSS, and the second electrode of the first transistor T1 is coupled to the second noise reduction control node PD-ox-i.

[0106] The first terminal of the first capacitor C1 is connected to the second clock signal terminal CB1, and the second terminal of the first capacitor C1 is connected to the second noise suppression control node PD-ox-i.

[0107] For example, when the first transistor T1 is turned on by signal control of the first clock signal terminal CK1, the voltage at the first voltage terminal VSS is transmitted to the second noise suppression control node PD-ox-i via the first transistor T1. When the first transistor T1 is turned off by signal control of the first clock signal terminal CK1, the voltage at the first voltage terminal VSS cannot be transmitted to the second noise suppression control node PD-ox-i, but the voltage at the second noise suppression control node PD-ox-i can be further adjusted in response to the signal at the second clock signal terminal CB1 and by the coupling effect of the first capacitor C1. For example, when the first transistor T1 is turned on by signal control of the first clock signal terminal CK1, the second clock signal terminal CB1 outputs a low level. When the first transistor T1 is turned off by signal control of the first clock signal terminal CK1, the second clock signal terminal CB1 outputs a high level, thereby pulling up the voltage at the second noise suppression control node PD-ox-i. The first clock signal terminal CK1 controls the signal, which periodically switches the first transistor T1 on and off. The second clock signal terminal CB1 periodically adjusts the voltage of the second noise suppression control node PD-ox-i. Through the combined action of these two, the voltage of the second noise suppression control node PD-ox-i becomes an alternating voltage.

[0108] The second ON control subcircuit 212 is coupled to the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i, and rectifies this alternating voltage signal and outputs the signal to the first noise reduction control node, thereby maintaining the voltage of the first noise reduction control node PD-ox at a voltage that turns on the noise reduction subcircuit 30.

[0109] For illustrative purposes, referring to Figure 8, the second ON control subcircuit 212 includes a second transistor T2 and a second capacitor C2.

[0110] Here, the control electrode of the second transistor T2 is coupled to the second noise reduction control node PD-ox-i, the first electrode of the second transistor T2 is coupled to the first noise reduction control node PD-ox, and the second electrode of the second transistor T2 is coupled to the second noise reduction control node PD-ox-i.

[0111] The first terminal of the second capacitor C2 is connected to the first clock signal terminal ST, and the second terminal of the second capacitor C2 is connected to the first noise suppression control node PD-ox.

[0112] For example, the alternating voltage signal supplied by the second noise suppression control node PD-ox-i can turn on the second transistor T2. When the first transistor T1 is turned on, it transmits the voltage at the first voltage terminal VSS to the second noise suppression control node PD-ox-i. At this time, since there is no coupling effect of the first capacitor C1, the charge on its second terminal does not change. On the other hand, when the first transistor T1 is turned off, it is not possible to transmit the voltage at the first voltage terminal VSS to the second noise suppression control node PD-ox-i. At this time, due to the coupling effect of the first capacitor C1, the voltage at the second terminal of the first capacitor C1 is pulled down by the second clock signal terminal CB1, so the amount of charge on the second terminal of the first capacitor C1 is smaller than the amount of charge on the second terminal of the second capacitor C2. Then, the charge on the second terminal of the second capacitor C2 can be transmitted to the second terminal of the first capacitor C1 via the second transistor T2. Furthermore, because the above process cycles periodically, the charge on the second terminal of the second capacitor C2 is constantly transmitted to the second terminal of the first capacitor C1. As a result, the charge on the second terminal of the second capacitor C2 gradually decreases and eventually stabilizes at a fixed value. For example, the voltage at the second terminal of the first capacitor C1 stabilizes at the same value as the charge on the second terminal of the first capacitor C1 when it is pulled down by the second clock signal terminal CB1. In addition, the voltage of the first noise suppression control node PD-ox coupled to the second capacitor C2 stabilizes at a fixed voltage, and this fixed voltage keeps the noise suppression subcircuit 30 on.

[0113] In the shift register circuit RS according to the embodiment of this disclosure, the first noise reduction control node PD-ox, the second noise reduction control node PD-ox-i, the cascade signal output terminal GP, and the first node n1, second node n2, third node n3, and fourth node n4 described later do not represent actual existing components, but rather represent connection points of related electrical connections in the circuit diagram. In other words, these nodes are nodes that equivalently represent connection points of related electrical connections in the circuit diagram. The first signal terminal (also called a constant voltage signal terminal) ST may be coupled to the first voltage terminal VSS or the first clock signal terminal CK1.

[0114] For example, when the first signal terminal ST is coupled to the first voltage terminal VSS, the first terminal of the second capacitor C2 is connected to the first voltage terminal VSS. This allows the second capacitor C2 to provide voltage stabilization to the first noise suppression control node PD-ox, preventing leakage from occurring in the first noise suppression control node PD-ox.

[0115] For example, when the first signal terminal ST is coupled to the first clock signal terminal CK1, the first terminal of the second capacitor C2 is connected to the first clock signal terminal CK1. This allows the second capacitor C2 to stabilize the voltage of the first noise suppression control node PD-ox. In addition, when the voltage of the signal at the first clock signal terminal CK1 changes, the second capacitor C2 can further adjust the voltage of the first noise suppression control node PD-ox, quickly stabilizing the voltage of the first noise suppression control node PD-ox to a potential that can turn on the noise suppression sub-circuit 30, which is advantageous in improving the noise suppression speed of the noise suppression sub-circuit 30. For example, if the potential that turns on the noise suppression sub-circuit 30 is low, when the voltage of the signal at the first clock signal terminal CK1 decreases, the second capacitor C2 can further pull down the potential of the first noise suppression control node PD-ox, which is advantageous in improving the noise suppression speed of the noise suppression sub-circuit 30.

[0116] The first transistor T1, first capacitor C1, second transistor T2, and second capacitor C2 included in the ON control unit 21 described above form a charge pump structure. Due to the voltage regulation effect of the charge pump structure, the voltage of the first noise suppression control node PD-ox stabilizes to a voltage that can turn on the noise suppression subcircuit 30. This ensures that the noise suppression subcircuit 30 remains on during the holding phase of the driving process of one row of gate lines, and continues to perform noise suppression on the scan signal output terminal Oput.

[0117] In some embodiments, the off-control unit 22 of the noise suppression control subcircuit 20 is coupled to the cascade signal output terminal GP, the second signal terminal (also called the control signal terminal) CN, the first noise suppression control node PD-ox, and the second noise suppression control node PD-ox-i. The off-control unit 22 is configured to control the noise suppression subcircuit 30 by transmitting the signal from the second signal terminal CN to the first noise suppression control node PD-ox in response to the voltage of the cascade signal output terminal GP.

[0118] For illustrative purposes, continuing to refer to Figure 8, the off-control unit 22 includes a third transistor T3 and a fourth transistor T4.

[0119] Here, the control electrode of the third transistor T3 is coupled to the cascade signal output terminal GP, the first electrode of the third transistor T3 is coupled to the second signal terminal CN, and the second electrode of the third transistor T3 is coupled to the second noise reduction control node PD-ox-i.

[0120] The control electrode of the fourth transistor T4 is coupled to the cascade signal output terminal GP, the first electrode of the fourth transistor T4 is coupled to the second signal terminal CN, and the second electrode of the fourth transistor T4 is coupled to the first noise reduction control node PD-ox.

[0121] The second signal terminal CN may be coupled to the second voltage terminal VDD or the second node n2. Here, for example, the second voltage terminal VDD is configured to transmit a DC high-level signal. For example, the voltage value of this DC high-level signal is greater than the voltage value of the DC low-level signal transmitted from the first voltage terminal VSS. Here, the second node n2 is one of the nodes in the input subcircuit 10, which will be described later, and for example, the voltage of this node is high at the output stage and low at the holding stage during the driving process of one row of gate lines.

[0122] For example, when the second signal terminal CN is coupled to the second voltage terminal VDD, in the output stage, the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage at the cascade signal output terminal GP, and the voltages of the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i are both at the voltage of the second voltage terminal VDD, i.e., at a high level. As a result, the noise reduction subcircuit 30 remains off in the output stage and does not affect the output of the scan signal at the scan signal output terminal Oput. In the holding stage, since the third transistor T3 and the fourth transistor T4 remain off under the control of the voltage at the cascade signal output terminal GP, the high level of the second signal terminal CN has almost no effect on the voltages of the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i.

[0123] As an example, if the third transistor T3 and the fourth transistor T4 are both P-type transistors, and the second signal terminal CN is coupled to the second node n2, the voltage at the second node n2 is high during the output phase and low during the hold phase. Therefore, during the output phase, the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage at the cascade signal output terminal GP, and the voltages at the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i are both at the voltage at the second node n2, i.e., high levels. As a result, the noise reduction subcircuit 30 remains off during the output phase and does not affect the output of the scan signal at the scan signal output terminal Oput. During the hold phase, the third transistor T3 and the fourth transistor T4 remain off under the control of the voltage at the cascade signal output terminal GP, so the voltage at the second signal terminal CN is low. This is advantageous in reducing the leakage of the third transistor T3 and the fourth transistor T4, thereby reducing the influence of the leakage of the third transistor T3 and the fourth transistor T4 on the voltage of the first noise suppression control node PD-ox, and speeding up the voltage adjustment speed of the first noise suppression control node PD-ox. As a result, the voltage of the first noise suppression control node PD-ox can reach a stable voltage value in a shorter time, and further improves the noise suppression speed of the noise suppression subcircuit 30.

[0124] In some embodiments, as shown in Figure 9, the first ON control subcircuit 211 further includes a fifth transistor T5. The first terminal of the first capacitor C1 is coupled to the second clock signal terminal CB1 via the fifth transistor T5. The control electrode of the fifth transistor T5 is coupled to the scan signal output terminal Oput, the first electrode of the fifth transistor T5 is coupled to the second clock signal terminal CB1, and the second electrode of the fifth transistor T5 is coupled to the first terminal of the first capacitor C1.

[0125] Taking the case where the fifth transistor T5 is a P-type transistor as an example, the control electrode of the fifth transistor T5 is coupled to the scanning signal output terminal Oput. Therefore, in the output stage, the fifth transistor T5 is turned off under the control of the high-level signal output from the scanning signal output terminal Oput, thereby disconnecting the connection between the second clock signal terminal CB1 and the first capacitor C1, and preventing the potential change of the second clock signal terminal CB1 from affecting the first capacitor C1. This eliminates the coupling effect of the first capacitor C1 on the potential change of the second clock signal terminal CB1, and also eliminates the resulting influence on the potential of the second noise reduction control node PD-ox-i.

[0126] In some embodiments, as shown in Figure 11, the noise reduction subcircuit 30 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is coupled to the first noise reduction control node PD-ox, the first electrode of the sixth transistor T6 is coupled to the first voltage terminal VSS, and the second electrode of the sixth transistor T6 is coupled to the scan signal output terminal Oput.

[0127] In the above embodiment, during the holding phase, the noise reduction control subcircuit 20 can maintain the voltage of the first noise reduction control node PD-ox at a stable voltage that turns on the noise reduction subcircuit 30. As a result, the sixth transistor T6 of the noise reduction subcircuit 30 remains on. This allows the voltage of the first voltage terminal VSS to be continuously transmitted to the scan signal output terminal Oput, ensuring that noise reduction is continuously performed on the scan signal output terminal Oput.

[0128] In some embodiments, as shown in Figure 10, the shift register circuit RS further includes an input sub-circuit 10 and an output sub-circuit 40.

[0129] Both the input subcircuit 10 and the noise reduction control subcircuit 20 are coupled to the cascade signal output terminal GP, and the noise reduction control subcircuit is configured to control the voltage of the cascade signal output terminal GP in order to turn the noise reduction subcircuit on or off. The input subcircuit 10 is further coupled to the output subcircuit 40 and is configured to transmit an ON signal to the output subcircuit 40.

[0130] For example, in the output stage, the input subcircuit 10 can control the voltage at the cascade signal output terminal GP to a voltage that turns on the off control unit 22. In response to the voltage at the cascade signal output terminal GP, the off control unit 22 turns off the noise reduction subcircuit 30 by transmitting the signal at the second signal terminal CN to the first noise reduction control node PD-ox, ensuring that the output of the scan signal at the scan signal output terminal Oput is not affected. In the holding stage, the input subcircuit 10 can keep the noise reduction subcircuit 30 turned on by the action of the on control unit 21 by controlling the voltage at the cascade signal output terminal GP to a voltage that turns off the off control unit 22.

[0131] Furthermore, the input sub-circuit 10 is connected to the input signal terminal Iput, the third clock signal terminal CK3, the fourth clock signal terminal CB3, the first voltage terminal VSS, and the second voltage terminal VDD. Under the control of the signal from the third clock signal terminal CK3, the input sub-circuit 10 can also write the signal from the input signal terminal Iput. Also, under the control of the voltage from the first voltage terminal VSS, it transmits an ON signal to the output sub-circuit 40 according to the written signal.

[0132] Here, as an example, the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 may be the same as the signal transmitted by the first clock signal terminal CK1. For example, the third clock signal terminal CK3 is coupled to the first clock signal terminal CK1. The signal transmitted by the fourth clock signal terminal CB3 may be the same as the signal transmitted by the second clock signal terminal CB1. For example, the fourth clock signal terminal CB3 is coupled to the second clock signal terminal CB1. In this case, as shown in Figure 13, the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 may be considered to be coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, respectively.

[0133] For example, the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 is different from the signal transmitted by the first clock signal terminal CK1, and the signal transmitted by the fourth clock signal terminal CB3 is different from the signal transmitted by the second clock signal terminal CB1. That is, as shown in Figure 10, the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are different from the first clock signal terminal CK1 and the second clock signal terminal CB1 coupled to the noise suppression control sub-circuit 20. In other words, the input sub-circuit 10 and the noise suppression control sub-circuit 20 are controlled by different groups of clock signals. This enables independent control of each of the input sub-circuit 10 and the noise suppression control sub-circuit 20, and further ensures effective control of the voltage of the first noise suppression control node PD-ox by the noise suppression control sub-circuit 20. In addition, the falling edge of the signal at the first clock signal terminal CK1 can be matched with the rising edge of the signal at the fourth clock signal terminal CB3 and the falling edge of the signal at the scan signal output terminal Oput. In this way, it is possible to reset the voltage of the scan signal output terminal Oput in a timely manner after outputting a scan signal from the scan signal output terminal Oput.

[0134] The output subcircuit 40 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2. Figure 10 shows that the output subcircuit 40 is coupled to the fifth clock signal terminal CK2. The output subcircuit 40 is further coupled to the scan signal output terminal Oput. The output subcircuit 40 is configured to transmit the signal from the second voltage terminal VDD or the fifth clock signal terminal CK2 to the scan signal output terminal Oput in response to the ON signal transmitted from the input subcircuit 10, thereby scanning the gate line coupled to the scan signal output terminal Oput.

[0135] Exemplary, referring to Figure 11, the input subcircuit 10 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third capacitor C3, an eleventh transistor T11, a fourth capacitor C4, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0136] Here, the control electrode of the seventh transistor T7 is coupled to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is coupled to the input signal terminal Iput, and the second electrode of the seventh transistor T7 is coupled to the first node n1.

[0137] The control electrode of the 8th transistor T8 is coupled to the 1st node n1, the 1st electrode of the 8th transistor T8 is coupled to the 3rd clock signal terminal CK3, and the 2nd electrode of the 8th transistor T8 is coupled to the 2nd node n2.

[0138] The control electrode of the ninth transistor T9 is coupled to the third clock signal terminal CK3, the first electrode of the ninth transistor T9 is coupled to the first voltage terminal VSS, and the second electrode of the ninth transistor T9 is coupled to the second node n2.

[0139] The control electrode of the 10th transistor T10 is connected to the second node n2, the first electrode of the 10th transistor T10 is connected to the second voltage terminal VDD, and the second electrode of the 10th transistor T10 is connected to the cascade signal output terminal GP.

[0140] The first terminal of the third capacitor C3 is connected to the second node n2, and the second terminal of the third capacitor C3 is connected to the first electrode and second voltage terminal VDD of the tenth transistor T10.

[0141] The control electrode of the 11th transistor T11 is coupled to the 3rd node n3, the 1st electrode of the 11th transistor T11 is coupled to the 4th clock signal terminal CB3, and the 2nd electrode of the 11th transistor T11 is coupled to the cascade signal output terminal GP.

[0142] The first terminal of the fourth capacitor C4 is connected to the third node n3, and the second terminal of the fourth capacitor C4 is connected to the second electrode of the eleventh transistor T11 and the cascade signal output terminal GP.

[0143] The control electrode of the 12th transistor T12 is coupled to the first voltage terminal VSS, the second electrode of the 12th transistor T12 is coupled to the third node n3, and the first electrode of the 12th transistor T12 is coupled to the first node n1.

[0144] The control electrode of the 13th transistor T13 is coupled to the 4th clock signal terminal CB3, the first electrode of the 13th transistor T13 is coupled to the 1st node n1, and the second electrode of the 13th transistor T13 is coupled to the 4th node n4.

[0145] The control electrode of the 14th transistor T14 is coupled to the second node n2, the first electrode of the 14th transistor T14 is coupled to the second voltage terminal VDD, and the second electrode of the 14th transistor T14 is coupled to the fourth node n4.

[0146] Based on the above embodiment, the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 is the same as the signal transmitted by the first clock signal terminal CK1, and the signal transmitted by the fourth clock signal terminal CB3 is the same as the signal transmitted by the second clock signal terminal CB1. That is, when the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, respectively, as shown in Figure 14, the control electrode of the seventh transistor T7 included in the input sub-circuit 10 is coupled to the first clock signal terminal CK1, the first electrode of the eighth transistor T8 is coupled to the first clock signal terminal CK1, the control electrode of the ninth transistor T9 is coupled to the first clock signal terminal CK1, and the control electrode of the thirteenth transistor T13 is coupled to the second clock signal terminal CB1. Furthermore, the connection relationship between the other electrodes of the above transistors and the other transistors included in the input sub-circuit 10 can be seen by referring to the above embodiment corresponding to Figure 11.

[0147] Illustratively, continuing to refer to Figure 11, the output subcircuit 40 includes a 15th transistor T15. The control electrode of the 15th transistor T15 is coupled to the cascade signal output terminal GP or the third node n3 (Figure 11 shows the case where the control electrode of the 15th transistor T15 is coupled to the third node n3), the first electrode of the 15th transistor T15 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2 (Figure 11 shows the case where the control electrode of the 15th transistor T15 is coupled to the fifth clock signal terminal CK2), and the second electrode of the 15th transistor T15 is coupled to the scan signal output terminal Oput.

[0148] The transistor used in the shift register circuit RS according to the embodiment of this disclosure may be a thin-film transistor (TFT), a field-effect transistor (FET), or another switching element having the same characteristics. In the embodiment of this disclosure, a thin-film transistor will be described as an example.

[0149] The control electrode of each thin-film transistor used in the shift register circuit RS is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. The source and drain of the thin-film transistor may be structurally symmetrical, so there may be no structural distinction between the source and drain. In other words, the first and second electrodes of the thin-film transistor in the embodiments of this disclosure may be structurally indistinguishable. Exemplarily, when the thin-film transistor is a P-type transistor, the first electrode of the thin-film transistor is the source and the second electrode is the drain. Exemplarily, when the thin-film transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0150] In the shift register circuit RS according to the embodiments of this disclosure, the example will be described using the case where the thin-film transistor is a P-type transistor. However, the embodiments of this disclosure include, but are not limited to, the above case. For example, one or more thin-film transistors in the shift register circuit RS according to the embodiments of this disclosure may be N-type transistors, and each electrode of the thin-film transistor of the selected type should be connected accordingly with reference to the respective electrodes of the thin-film transistor in the embodiments of this disclosure, and the corresponding voltage terminals should provide the corresponding high-level voltage or low-level voltage.

[0151] In the embodiments of this disclosure, the specific implementation configurations of the input subcircuit 10, noise suppression control subcircuit 20, noise suppression subcircuit 30, and output subcircuit 40 are not limited to those described above, and any implementation configuration for any application, such as a common connection configuration well known to those skilled in the art, may be used, as long as appropriate functionality can be ensured. The above examples are not intended to limit the scope of protection of this disclosure. In actual applications, those skilled in the art may choose to use or not use one or more of the above circuits as appropriate, and various combinations and variations of the above circuits will not deviate from the principles of this disclosure and will not be described further here.

[0152] Furthermore, in the embodiments of this disclosure, the capacitors (for example, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in Figure 11) may be capacitor elements individually manufactured by a process step, or they may be realized by manufacturing dedicated capacitor electrodes, for example, and each capacitor electrode of the capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc. The capacitor may be the parasitic capacitance between transistors, or it may be realized by the transistor itself and other devices and wiring, or it may be realized by the parasitic capacitance between the wiring of the circuit itself.

[0153] Based on the configuration of the shift register circuit RS according to the above embodiment, some embodiments of this disclosure provide a method for driving the shift register circuit RS.

[0154] As shown in Figures 10 and 12, the driving process of one row of gate lines includes an input stage P1, an output stage P2, and a holding stage P3.

[0155] If the shift register circuit RS includes an input subcircuit 10, a noise reduction control subcircuit 20, a noise reduction subcircuit 30, and an output subcircuit 40, at the input stage P1, the input subcircuit 10 controls the voltage at the cascade signal output terminal GP to a first control voltage, causing the noise reduction control subcircuit 20 to turn on the noise reduction subcircuit 30. Here, the first control voltage is the voltage at which the cascade signal output terminal GP can turn on the noise reduction subcircuit 30 by controlling the noise reduction control subcircuit 20. For example, the first control voltage is equal to the voltage output by the second voltage terminal. As a result, the noise reduction control subcircuit 20 turns on the noise reduction subcircuit 30 by controlling the voltage at the first noise reduction control node PD-ox to a voltage that turns on the noise reduction subcircuit 30. The input subcircuit 10 also transmits an ON signal to the output subcircuit 40. For example, the input sub-circuit 10 writes the signal to the input signal terminal Iput under the control of the signal from the third clock signal terminal CK3, and the output sub-circuit 40 is turned on by the written signal from the input signal terminal Iput.

[0156] In output stage P2, the input sub-circuit 10 controls the voltage at the cascade signal output terminal GP to a second control voltage, causing the noise suppression control sub-circuit 20 to turn off the noise suppression sub-circuit 30. Here, the second control voltage is the voltage at which the cascade signal output terminal GP can turn off the noise suppression sub-circuit 30 by controlling the noise suppression control sub-circuit 20. For example, the second control voltage is equal to the voltage output by the first voltage terminal. As a result, the noise suppression control sub-circuit 20 controls the voltage at the first noise suppression control node PD-ox to a voltage that turns off the noise suppression sub-circuit 30. The input sub-circuit 10 also continues to transmit an ON signal to the output sub-circuit 40.

[0157] For example, in the output stage, the output sub-circuit 40, under the control of this ON signal, can transmit the signal from the second voltage terminal VDD or the fifth clock signal terminal CK2 (Figure 10 shows the case where the output sub-circuit 40 is coupled to the fifth clock signal terminal CK2) to the scan signal output terminal Oput, thereby scanning the gate line coupled to the scan signal output terminal Oput.

[0158] In holding stage P3, the noise reduction control subcircuit 20 responds to the signal at the first clock signal terminal CK1 by generating an alternating voltage signal from the voltage at the first voltage terminal VSS and the signal at the second clock signal terminal CB1, rectifying the generated alternating voltage signal and outputting the signal to the first noise reduction control node PD-ox, thereby maintaining the voltage at the first noise reduction control node PD-ox at a voltage that turns on the noise reduction subcircuit 30. The noise reduction subcircuit 30 remains on under the control of the voltage at the first noise reduction control node PD-ox and performs noise reduction on the scan signal output terminal Oput.

[0159] For illustrative purposes, the following will explain in detail the specific operation process in the driving process of one row of gate lines in the shift register circuit RS shown in Figure 11, with reference to Figure 12. In the following explanation, we will use the example where each transistor in the shift register circuit RS is a P-type transistor (without considering the effect of the transistor threshold voltage), the voltage transmitted by the first voltage terminal VSS is a low-level voltage, and the voltage transmitted by the second voltage terminal VDD is a high-level voltage.

[0160] Furthermore, the following description will use as an example the case in which the control electrode of the 15th transistor T15 is coupled to the 3rd node n3 and the first electrode of the 15th transistor T15 is coupled to the 5th clock signal terminal CK2. In some other embodiments, the control electrode and the first electrode of the 15th transistor T15 may be coupled to other nodes or signal terminals. For example, the control electrode of the 15th transistor T15 may be coupled to the cascade signal output terminal GP, and the first electrode of the 15th transistor T15 may be coupled to the 2nd voltage terminal VDD.

[0161] As shown in Figure 12, the driving process of one gate line includes at least an input stage P1, an output stage P2, and a holding stage P3. Here, the holding stage P3 includes at least a first holding period P31 and a second holding period P32.

[0162] For illustrative purposes, in the following explanation, "0" represents a low level and "1" represents a high level.

[0163] At input stage P1, Iput=0, CK1=0, CB1=1, CK2=0, CK3=0, and CB3=1.

[0164] In this case, the seventh transistor T7 is turned on under the control of the low-level signal at the third clock signal terminal CK3, and the input signal terminal Iput outputs a low-level signal to the first node n1. The eighth transistor T8 is turned on under the control of the low-level voltage at the first node n1, and the ninth transistor T9 is turned on under the control of the low-level signal at the third clock signal terminal CK3. Therefore, the voltage at the second node n2 is a low-level voltage.

[0165] The 10th transistor T10 is turned on under the control of the low-level voltage of the second node n2 and the high-level voltage V of the second voltage terminal VDD. DD This is transmitted to the cascade signal output terminal GP via the 10th transistor T10. The 12th transistor T12 turns on under the control of the first voltage terminal VSS and transmits the low-level voltage of the first node n1 to the control electrodes of the third node n3 and the 11th transistor T11, turning on the 11th transistor T11. Thereafter, the 11th transistor T11 transmits the high-level signal of the fourth clock signal terminal CB3 to the cascade signal output terminal GP. Thus, the voltage at the cascade signal output terminal GP is the high-level voltage V DD That is the case.

[0166] At this time, the fourth capacitor C4 is charged, the voltage at one end connected to its third node n3 is a low-level voltage, and the voltage at the other end connected to the first electrode of the eleventh transistor T11 is a high-level voltage, and the writing of the signal to be transmitted to the input signal terminal Iput is realized.

[0167] The third transistor T3 and the fourth transistor T4 are both turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0168] The first transistor T1 is turned on under the control of a low-level signal output from the first clock signal terminal CK1, and the voltage of the second noise rejection control node PD-ox-i is the low-level voltage V SS The second transistor T2 controls the low-level voltage V of the second noise rejection control node PD-ox-i. SS Under its control, the voltage of the first noise rejection control node PD-ox is set to a low-level voltage V SS This causes the sixth transistor T6 to turn on, and the voltage at the scan signal output terminal Oput becomes a low-level voltage V. SS Thus, noise reduction for the scan signal output terminal Oput is achieved by the noise reduction subcircuit 30.

[0169] Furthermore, the 14th transistor T14 controls the low-level voltage V at the second node n2. SS It turns on under the control of the 14th transistor T14, which transmits the high-level voltage of the second voltage terminal VDD coupled to its first electrode to the 4th node n4. At this time, the 13th transistor T13 turns off under the control of the high-level signal of the 4th clock signal terminal CB3. As a result, the voltage at the 4th node n4 becomes the high-level voltage V DD That is the case.

[0170] The 15th transistor T15 is turned on under the control of the low-level voltage of the 3rd node n3, and the low-level voltage output from the 5th clock signal terminal CK2 is transmitted to the scan signal output terminal Oput via the 15th transistor T15. As a result, a low-level scan signal is output from the scan signal output terminal Oput.

[0171] At output stage P2, Iput=1, CK1=1, CB1=0, CK2=1, CK3=1, and CB3=0.

[0172] In this case, the seventh transistor T7 is turned off under the control of the high-level signal at the third clock signal terminal CK3, and the voltage at the first node n1 remains at a low level. The eighth transistor T8 is turned on under the control of the low-level voltage at the first node n1, and the high-level signal at the third clock signal terminal CK3 is transmitted to the second node n2 via the eighth transistor T8. The ninth transistor T9 is turned off under the control of the high-level signal at the third clock signal terminal CK3. Therefore, the voltage at the second node n2 is at a high level.

[0173] The 10th transistor T10 is turned off under the control of the high-level voltage at the 2nd node n2. The 12th transistor T12 is turned on under the control of the 1st voltage terminal VSS, transmitting the low-level voltage at the 1st node n1 to the control electrodes of the 3rd node n3 and the 11th transistor T11, which then turns on the 11th transistor T11. As a result, the 11th transistor T11 transmits the low-level signal at the 4th clock signal terminal CB3 to the cascade signal output terminal GP. Therefore, the voltage at the cascade signal output terminal GP is a low-level voltage.

[0174] At this time, the voltage at one end of the fourth capacitor C4, which is coupled to the first electrode of the eleventh transistor T11, is a low-level voltage. The voltage of the low-level signal at the fourth clock signal terminal CB3 is V SS , the voltage of the high-level signal is V DD Therefore, the voltage at one end of the fourth capacitor C4, which is coupled to the first electrode of the eleventh transistor T11, is the V of the input stage P1. DD From V SS The voltage drops to V DD -V SS Therefore, due to the capacitive bootstrap effect of the fourth capacitor C4, the voltage at the third node n3 coupled to the other terminal of the fourth capacitor C4 is further increased to V DD -V SS Pulled down in minutes, the voltage of the third node n3 is the same as the V of the input stage P1. SS From 2V SS -V DD Descending.

[0175] The 15th transistor T15 is turned on under the control of the low-level voltage of the 3rd node n3, and the high-level voltage output from the 5th clock signal terminal CK2 is transmitted to the scan signal output terminal Oput via the 15th transistor T15. As a result, a high-level scan signal is output from the scan signal output terminal Oput, enabling scanning of the gate line.

[0176] The third transistor T3 and the fourth transistor T4 are both turned on under the control of the low-level voltage of the cascade signal output terminal GP. Then, the signal from the second signal terminal CN is transmitted to the second noise reduction control node PD-ox-i via the third transistor T3 and to the first noise reduction control node PD-ox via the fourth transistor T4. Since the second signal terminal CN is the second voltage terminal VDD or the second node n2 (where the voltage at output stage P2 of the second node n2 is a high-level voltage), the voltages at both the second noise reduction control node PD-ox-i and the first noise reduction control node PD-ox are high-level voltages. As a result, the sixth transistor T6 is turned off and does not affect the output of a high-level scan signal from the scan signal output terminal Oput.

[0177] At this time, the first transistor T1 is turned off under the control of a high-level signal output from the first clock signal terminal CK1, and the second transistor T2 is also turned off under the control of a high-level voltage from the second noise reduction control node PD-ox-i.

[0178] Furthermore, the 14th transistor T14 is turned off under the control of the high-level voltage at the second node n2. The 13th transistor T13 is turned on under the control of the low-level signal at the fourth clock signal terminal CB3. Therefore, the voltage at the fourth node n4 is equal to the voltage at the first node n1, i.e., it is a low-level voltage.

[0179] During the first retention period P31 of retention stage P3, Iput=1, CK1=0, CB1=1, CK2=0, CK3=0, and CB3=1.

[0180] In this case, the seventh transistor T7 is turned on under the control of the low-level signal of the third clock signal terminal CK3, and the high-level signal of the input signal terminal Iput is transmitted to the first node n1 via the seventh transistor T7. This raises the voltage at the first node n1 to a high-level voltage. The eighth transistor T8 is turned off under the control of the high-level voltage at the first node n1. The ninth transistor T9 is turned on under the control of the low-level signal of the third clock signal terminal CK3, and the low-level signal of the first signal terminal VSS is transmitted to the second node n2 via the ninth transistor T9. This raises the voltage at the second node n2 to a low-level voltage VSS. SS I'll do that.

[0181] The 10th transistor T10 is turned on under the control of the low-level voltage of the 2nd node n2, and the high-level voltage of the 2nd voltage terminal VDD is transmitted to the cascade signal output terminal GP via the 10th transistor T10. The 12th transistor T12 is turned on under the control of the 1st voltage terminal VSS, and transmits the high-level voltage of the 1st node n1 to the control electrodes of the 3rd node n3 and the 11th transistor T11, and the 11th transistor T11 is turned off. Therefore, the voltage at the cascade signal output terminal GP is a high-level voltage.

[0182] At this time, both the third transistor T3 and the fourth transistor T4 are turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0183] The first transistor T1 is turned on under the control of a low-level signal output from the first clock signal terminal CK1. Then, the voltage at the second noise rejection control node PD-ox-i becomes the low-level voltage V SS Therefore, the voltage at one end of the first capacitor C1 connected to the second noise suppression control node PD-ox-i is the low-level voltage V. SS Therefore, the voltage at one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the voltage of the high-level signal at the second clock signal terminal CB1. The voltage of the high-level signal output from the second clock signal terminal CB1 is called the high-level voltage V. DDTherefore, the voltage at one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the high-level voltage V DD That is the case.

[0184] The second transistor T2 controls the low-level voltage V of the second noise rejection control node PD-ox-i. SS Under its control, the voltage of the first noise rejection control node PD-ox is set to a low-level voltage V SS This causes the sixth transistor T6 to turn on, and the voltage at the scan signal output terminal Oput becomes a low-level voltage V. SS Thus, noise reduction for the scan signal output terminal Oput is achieved by the noise reduction subcircuit 30.

[0185] Furthermore, the 14th transistor T14 controls the low-level voltage V at the second node n2. SS It is turned on under the control of the 14th transistor T14. The high-level voltage V of the second voltage terminal VDD coupled to its first electrode DD This is transmitted to the fourth node n4. At this time, the 13th transistor T13 is turned off under the control of the high-level signal of the fourth clock signal terminal CB3. As a result, the voltage at the fourth node n4 becomes the high-level voltage V DD That is the case.

[0186] The 15th transistor T15 is turned off under the control of the high-level voltage at the 3rd node n3.

[0187] In the second holding stage P32 of holding stage P3, Iput=1, CK1=1, CB1=0, CK2=1, CK3=1, and CB3=0.

[0188] In this case, the seventh transistor T7 is turned off under the control of the high-level signal at the third clock signal terminal CK3, and the voltage at the first node n1 remains at a high level. The eighth transistor T8 is still turned off under the control of the high-level voltage at the first node n1. The ninth transistor T9 is turned off under the control of the high-level signal at the third clock signal terminal CK3, and the voltage at the second node n2 remains at a low level.

[0189] The 10th transistor T10 is turned on under the control of the low-level voltage of the 2nd node n2, and the high-level voltage of the 2nd voltage terminal VDD is transmitted to the cascade signal output terminal GP via the 10th transistor T10. The 12th transistor T12 is turned on under the control of the 1st voltage terminal VSS, and transmits the high-level voltage of the 1st node n1 to the control electrodes of the 3rd node n3 and the 11th transistor T11, and the 11th transistor T11 is turned off. Therefore, the voltage at the cascade signal output terminal GP is a high-level voltage.

[0190] At this time, both the third transistor T3 and the fourth transistor T4 are turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0191] The first transistor T1 is turned off under the control of the high-level signal output from the first clock signal terminal CK1, and the second noise reduction control node PD-ox-i is in a floating state. The voltage at one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the voltage of the low-level signal at the second clock signal terminal CB1, i.e., the low-level voltage V SS Therefore, the voltage at one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the V of the first holding period P31. DD From low-level voltage V SS The voltage drops to V SS -V DD That is the case.

[0192] Due to the coupling effect of the first capacitor C1, the voltage of the second noise suppression control node PD-ox-i is shifted, and the offset amount is:

number

number

[0193] At this time, the voltage of the first noise reduction control node PD-ox is the low-level voltage V SS Therefore, the voltage of the second noise reduction control node PD-ox-i is,

number

number

number

[0194] Subsequently, the signals from the first clock signal terminal CK1 and the second clock signal terminal CB1 alternate between high-level and low-level signals. That is, during the holding phase P3, the first holding period P31 and the second holding period P32 alternate. As a result, the coupling between the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i occurs multiple times, and the voltage is averaged multiple times. Ultimately, the voltage of the first noise reduction control node PD-ox stabilizes around a certain voltage. The voltage change of the first noise reduction control node PD-ox is as shown in the waveform in Figure 12. Consequently, the sixth transistor T6 remains on during the holding phase P3, continuously performing noise reduction on the scan signal output terminal Oput.

[0195] For example, if C1 is sufficiently large, PD-ox-i ≒ If it is considered to be C1 (C1 is C PD-ox-i If the proportion is relatively large (for example, it can be understood as being 90% or more), the numerical values ​​related to the above derivation process can be found in the following explanation.

[0196] Due to the coupling effect of the first capacitor C1, the voltage offset amount of the second noise rejection control node PD-ox-i is V SS -V DD Therefore, the voltage of the second noise reduction control node PD-ox-i is V during the first holding period P31. SS From V SS +(V SS -V DD ) = 2V SS -V DD Descend to this point.

[0197] At this time, the voltage of the first noise reduction control node PD-ox is the low-level voltage V SS Therefore, the voltage of the second noise reduction control node PD-ox-i is 2V SS -V DD Therefore, the second transistor T2 turns on, and about half of the charge flows from the first noise reduction control node PD-ox to the second noise reduction control node PD-ox-i. Thus, the voltage at the first noise reduction control node PD-ox is [(2V SS -V DD )+V SS ] / 2=(3V SS -V DD ) / 2, which means that the voltage of the first noise reduction control node PD-ox is V during the first holding period P31. SS from (3V SS -V DD ) / 2 will be selected from the dropdown menu.

[0198] Subsequently, the signals from the first clock signal terminal CK1 and the second clock signal terminal CB1 alternately become high-level and low-level signals, that is, in holding stage P3, the first holding period P31 and the second holding period P32 alternate. As a result, coupling between the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i occurs multiple times, and the voltage is averaged multiple times. Ultimately, the voltage of the first noise reduction control node PD-ox is 2V. SS -V DD It stabilizes in the vicinity. As a result, the sixth transistor T6 remains on during the holding phase P3, continuously performing noise reduction on the scan signal output terminal Oput.

[0199] Furthermore, during the second holding period P32, the 14th transistor T14 is turned on under the control of the low-level voltage of the second node n2. The 14th transistor T14 is turned on under the control of the high-level voltage V of the second voltage terminal VDD coupled to its first electrode. DD This is transmitted to the fourth node n4. At this time, the 13th transistor T13 is turned on under the control of the low-level signal of the fourth clock signal terminal CB3. As a result, the voltage at the fourth node n4 becomes the high-level voltage V DD Thus, the 13th transistor T13 and the 14th transistor T14 both control the second voltage terminal VDD to charge the first node n1, thereby maintaining the first node n1 at a high voltage level and ensuring that the 11th transistor T11 remains in the off state.

[0200] The 15th transistor T15 is turned off under the control of the high-level voltage at the 3rd node n3.

[0201] In some other embodiments, as shown in Figures 13 and 14, when the third clock signal terminal CK3 and the fourth clock signal terminal CB3, which are coupled to the input sub-circuit 10 of the shift register circuit RS, are coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, respectively, the drive sequence of this shift register circuit RS may be as shown in Figure 15, and the specific drive process of the circuit can be found in the previous explanation, so it will not be explained further here.

[0202] The foregoing describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could conceive of within the technical scope of the Disclosure are all included within the technical scope of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be governed by the scope of protection set forth in the claims.

Claims

1. A shift register circuit, It includes a noise reduction control subcircuit and a noise reduction subcircuit. The noise reduction control subcircuit is connected to the first voltage terminal, the first clock signal terminal, the second clock signal terminal, and the first noise reduction control node. The noise reduction control subcircuit is configured to generate an alternating voltage signal from the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to the signal of the first clock signal terminal, rectify the alternating voltage signal and output the signal to the first noise reduction control node, thereby maintaining the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit, so that the signal of the first clock signal terminal and the signal of the second clock signal terminal alternately become a high-level signal and a low-level signal. The noise reduction subcircuit is coupled to the first noise reduction control node and the scan signal output terminal. The noise reduction subcircuit is configured to perform noise reduction on the scan signal output terminal in response to the voltage of the first noise reduction control node. The noise reduction control subcircuit is, A first ON control subcircuit coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and the second noise suppression control node, the first ON control subcircuit is configured to periodically output the voltage of the first voltage terminal to the second noise suppression control node in response to the signal of the first clock signal terminal, and to supply an alternating voltage signal to the second noise suppression control node by adjusting the voltage of the second noise suppression control node based on the signal of the second clock signal terminal, A second ON control subcircuit coupled to the first noise reduction control node and the second noise reduction control node, the second ON control subcircuit is configured to rectify the alternating voltage signal supplied by the second noise reduction control node and output the signal to the first noise reduction control node, The second ON control subcircuit is a shift register circuit including a second transistor whose control electrode is coupled to the second noise rejection control node, whose first electrode is coupled to the first noise rejection control node, and whose second electrode is coupled to the second noise rejection control node.

2. The first ON control subcircuit is, The shift register circuit according to claim 1, comprising a first capacitor whose first terminal is coupled to the second clock signal terminal and whose second terminal is coupled to the second noise suppression control node.

3. The first ON control subcircuit is, The shift register circuit according to claim 2, further comprising a first transistor having a control electrode coupled to the first clock signal terminal, a first electrode coupled to the first voltage terminal, and a second electrode coupled to the second noise rejection control node.

4. The aforementioned noise reduction sub-circuit is The shift register circuit according to claim 1, comprising a sixth transistor whose control electrode is coupled to the first noise reduction control node, whose first electrode is coupled to the first voltage terminal, and whose second electrode is coupled to the scan signal output terminal.

5. The shift register circuit according to any one of claims 1 to 4, further comprising an output subcircuit coupled to a second voltage terminal or a fifth clock signal terminal, and further coupled to the scan signal output terminal, and configured to transmit the signal from the second voltage terminal or the fifth clock signal terminal to the scan signal output terminal in response to an ON signal transmitted from an input subcircuit.

6. The shift register circuit according to claim 5, further comprising an input subcircuit coupled to a cascade signal output terminal and the output subcircuit, the input subcircuit configured to control the voltage of the cascade signal output terminal and further configured to transmit an ON signal to the output subcircuit.

7. The aforementioned input sub-circuit is, A 10th transistor, in which a control electrode is connected to a second node, a first electrode is connected to the second voltage terminal, and a second electrode is connected to the cascade signal output terminal, The shift register circuit according to claim 6, comprising a third capacitor whose first terminal is connected to the second node and whose second terminal is connected to the first electrode and second voltage terminal of the tenth transistor.

8. A gate drive circuit including multiple cascaded shift register circuits, The shift register circuit is a gate drive circuit, wherein the shift register circuit is the shift register circuit described in any one of claims 1 to 4.

9. Multiple gate lines, A display device comprising the gate drive circuit described in claim 8, Each shift register circuit in the gate drive circuit is a display device connected to at least one gate line.

10. The display device according to claim 9, wherein the scanning signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one gate line.

11. A method for driving a shift register circuit according to any one of claims 1 to 4, During the holding stage, The noise reduction control subcircuit of the shift register circuit generates an alternating voltage signal from the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to the signal of the first clock signal terminal, rectifies the generated alternating voltage signal and outputs the signal to the first noise reduction control node, thereby maintaining the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit. A driving method comprising the noise reduction subcircuit performing noise reduction on a scan signal output terminal in response to the voltage of the first noise reduction control node being a voltage that turns on the noise reduction subcircuit.

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