Display panels and display devices

Abstract

To correct color shifting on a display panel.SOLUTION: An array substrate included in a display panel includes a substrate, a first conductive layer, an insulating layer, and a second conductive layer. The first conductive layer includes first and second signal lines. The second conductive layer includes third and fourth signal lines. The third and fourth signal lines transmit the same signal. The first and third signal lines are electrically connected in a first overlapping region. The second and fourth signal lines are electrically connected in a fourth overlapping region. The first and fourth signal lines are insulated. The second and third signal lines are insulated. Orthogonal projection to a substrate of each of the second and third overlapping regions is at least partially positioned within orthogonal projection to a substrate of one type of pixel aperture.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to a display panel and a display device.

Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) have advantages such as high image quality, low power consumption, thin body, and wide application range. Therefore, they are widely applied to various consumer electronic products such as mobile phones, TVs, notebook computers, and desktop computers, and have become the main display devices.

[0003] However, it is necessary to improve the performance of current OLED display products.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this application provide a display panel and a display device that can improve the color shift of the display panel and enhance the performance of the display panel.

Means for Solving the Problems

[0005] An embodiment of the first aspect of an embodiment of this application includes a substrate, a first conductive layer, an insulating layer, and a second conductive layer sequentially laminated on the substrate side. The first conductive layer includes a first signal line and a second signal line extending along a first direction. The second conductive layer includes a third signal line and a fourth signal line extending along a second direction. The first direction and the second direction intersect. The first signal line and the second signal line are arranged along the second direction. The third signal line and the fourth signal line are arranged along the first direction. Moreover, the third signal line and the fourth signal line transmit the same signal, and it is provided with an array substrate. Along the direction perpendicular to the substrate, there is a first overlap region between the first signal line and the third signal line, a second overlap region between the first signal line and the fourth signal line, a third overlap region between the second signal line and the third signal line, a fourth overlap region between the second signal line and the fourth signal line, the first signal line and the third signal line are electrically connected in the first overlap region, the first signal line and the fourth signal line are insulated in the second overlap region, and / or the second signal line and the third signal line are insulated in the third overlap region. The present invention provides a display panel in which the burlap region is insulated, the second signal line and the fourth signal line are electrically connected in the fourth overlap region, the orthographic projections of the first overlap region and the fourth overlap region onto the substrate are both located outside the orthographic projection of one type of pixel aperture onto the substrate, and the orthographic projections of the second overlap region and the third overlap region onto the substrate are both located at least partially within the orthographic projection of one type of pixel aperture onto the substrate, and the pixel aperture is located on the side of the array substrate toward the insulating layer.

[0006] According to an embodiment of a first aspect of the present invention, the pixel aperture includes a first pixel aperture, and the orthographic projections of the second overlap region and the third overlap region onto the substrate are each at least partially located within the orthographic projection of the first pixel aperture onto the substrate. Preferably, the orthographic projections of the first overlap region and the fourth overlap region onto the substrate are both located outside the orthographic projection of the first pixel aperture onto the substrate, and the first pixel aperture is used to house a blue light-emitting unit.

[0007] According to any of the embodiments of the first aspect of the present invention, the pixel aperture further includes a second pixel aperture, the first pixel aperture and the second pixel aperture are arranged alternately along the second direction, and the first pixel aperture and the second pixel aperture are further arranged alternately along the first direction, the first overlap region and the fourth overlap region are located between adjacent first pixel apertures and second pixel apertures along the second direction, Preferably, the second pixel aperture is used to house a red light-emitting unit.

[0008] According to any of the embodiments of the first aspect of the present invention, the plurality of first pixel apertures and second pixel apertures are arranged alternately along a second direction to form a first pixel row, wherein the first overlap region and the third overlap region are located in one of two adjacent first pixel rows, and the second overlap region and the fourth overlap region are located in the other first pixel row.

[0009] According to any of the embodiments of the first aspect of the present invention, the pixel aperture further includes a third pixel aperture, the plurality of the third pixel apertures arranged along the second direction to form a second pixel row, and the first pixel row and the second pixel row are arranged alternately along the first direction.

[0010] According to any of the embodiments of the first aspect of the present invention, two first pixel apertures and two second pixel apertures are provided on the periphery of the third pixel aperture, and the two first pixel apertures and two second pixel apertures are alternately distributed on the periphery of the third pixel aperture.

[0011] According to any of the embodiments of the first aspect of the present invention, the orthographic projection of the first signal line onto the substrate does not overlap with the orthographic projections of the second and third pixel apertures onto the substrate, and the orthographic projection of the first signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate along the first direction. Preferably, the orthographic projection of the second signal line onto the substrate does not overlap with the orthographic projections of the second and third pixel apertures onto the substrate, and the orthographic projection of the second signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate along the first direction. Preferably, the orthographic projection of the third signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the third signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction. Preferably, the orthographic projection of the fourth signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the fourth signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction.

[0012] According to any of the embodiments of the first aspect of the present invention, the first signal line and the fourth signal line are insulated in the second overlap region, and the second signal line and the third signal line are insulated in the third overlap region. Alternatively, the first signal line and the fourth signal line are insulated in the second overlap region, and the second signal line and the third signal line are electrically connected in the third overlap region. Alternatively, the first signal line and the fourth signal line are electrically connected in the second overlap region, and the second signal line and the third signal line are insulated in the third overlap region. Alternatively, the first signal line and the fourth signal line are insulated in a portion of the second overlap region and electrically connected in a portion of the preset second overlap region, and the second signal line and the third signal line are insulated in a portion of the third overlap region and electrically connected in a portion of the preset third overlap region. Preferably, the sum of the number of a portion of the preset second overlap region and the sum of the number of a portion of the preset third overlap region is half or one-quarter of the sum of the number of the second overlap region and the sum of the third overlap region.

[0013] According to any of the above embodiments of the first aspect of the present invention, the first conductive layer further includes a fifth signal line and a sixth signal line extending along the first direction, the second conductive layer further includes a seventh signal line and an eighth signal line extending along the second direction, the fifth signal line and the sixth signal line are arranged along the second direction, the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal.

[0014] According to any of the embodiments of the first aspect of the present invention, the third signal line and the fourth signal line are provided adjacent to each other along the first direction, the seventh signal line and the eighth signal line are provided adjacent to each other along the first direction, the fifth signal line is located between the adjacent first signal line and the second signal line, the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is provided between the fifth signal line and the sixth signal line.

[0015] According to any of the embodiments of the first aspect of the present invention, the pixel aperture includes a first pixel aperture, a second pixel aperture and a third pixel aperture, the first pixel aperture and the second pixel aperture are arranged alternately along the second direction, and the first pixel aperture and the second pixel aperture are further arranged alternately along the first direction, a plurality of the first pixel apertures and the second pixel apertures are arranged alternately along the second direction to form a first pixel row, a plurality of the third pixel apertures are arranged along the second direction to form a second pixel row, the first pixel row and the second pixel row are arranged alternately along the first direction, the orthographic projection of the fifth signal line onto the substrate does not overlap with the orthographic projection of the first pixel aperture and the second pixel aperture onto the substrate, and the orthographic projection of the first signal line onto the substrate passes through the orthographic projection of the third pixel aperture onto the substrate along the first direction. Preferably, the orthographic projections of the second overlap region and the third overlap region onto the substrate are each at least partially located within the orthographic projection of the first pixel aperture onto the substrate. Preferably, the first overlapping region and the fourth overlapping region are located between adjacent first and second pixel apertures along the second direction. Preferably, of two adjacent first pixel rows, the first overlap region and the third overlap region are located in one of the first pixel rows, and the second overlap region and the fourth overlap region are located in the other first pixel row. Preferably, the orthographic projection of the sixth signal line onto the substrate does not overlap with the orthographic projections of the first and second pixel apertures onto the substrate, and the orthographic projection of the sixth signal line onto the substrate passes through the orthographic projection of the third pixel aperture onto the substrate along the first direction. Preferably, the orthographic projection of the seventh signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the seventh signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction. Preferably, the orthographic projection of the eighth signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the eighth signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction.

[0016] According to any of the above embodiments of the first aspect of the present invention, the first signal line further includes a first extension, the first extension being connected to the second overlap region and arranged along the second overlap region and the second direction, at least a portion of the orthographic projection of the first extension onto the substrate lies outside the orthographic projection of the first pixel aperture onto the substrate, the first extension is electrically connected to the fourth signal line via a first through-hole, the orthographic projection of the first through-hole onto the substrate does not overlap with the orthographic projection of the first pixel aperture onto the substrate, Preferably, the fifth signal line includes a first partition region for accommodating the first extension, and at least a portion of the first extension is located in the first partition region.

[0017] According to any of the above embodiments of the first aspect of the present invention, the second signal line further includes a second extension, the second extension being connected to the third overlap region and aligned with the third overlap region and the second direction, at least a portion of the orthographic projection of the second extension onto the substrate lies outside the orthographic projection of the first pixel aperture onto the substrate, the second extension is electrically connected to the third signal line via a second through-hole, and the orthographic projection of the second through-hole on the substrate does not overlap with the orthographic projection of the first pixel aperture onto the substrate. Preferably, the sixth signal line includes a second partition region for accommodating the second extension, and at least a portion of the second extension is located within the second partition region.

[0018] According to any of the embodiments of the first aspect of the present invention, a fifth overlap region exists between the fifth signal line and the seventh signal line, a sixth overlap region exists between the fifth signal line and the eighth signal line, a seventh overlap region exists between the sixth signal line and the seventh signal line, an eighth overlap region exists between the sixth signal line and the eighth signal line, the fifth signal line and the seventh signal line are electrically connected in the fifth overlap region, the sixth signal line and the eighth signal line are electrically connected in the eighth overlap region, and / or the fifth signal line and the eighth signal line are electrically connected in the sixth overlap region, and the sixth signal line and the seventh signal line are electrically connected in the seventh overlap region.

[0019] According to any of the embodiments of the first aspect of the present invention, the third signal line has a first reset signal, and the seventh signal line has a second reset signal, Preferably, the system further includes a plurality of drive circuits electrically connected to at least one light-emitting unit, each including a first light-emitting control module, a first initialization module, and a second initialization module. The control terminal of the second initialization module is electrically connected to the first scanning signal line, the first terminal of the second initialization module is electrically connected to the second reset signal line, and the second terminal of the second initialization module is electrically connected to the first terminal of the first light emission control module. The control terminal of the first initialization module is electrically connected to the first scanning signal line, the first terminal of the first initialization module is electrically connected to the first reset signal line, and the second terminal of the first initialization module is electrically connected to the second terminal of the first light emission control module and the light emitting unit.

[0020] According to any of the embodiments of the first aspect of the present invention, it further includes a first high-level signal line located in the second conductive layer. The first high-level signal line extends along the second direction, and in the orthographic projection of the first high-level signal line onto the substrate, the portion located within the orthographic projections of the second pixel aperture and the first pixel aperture onto the substrate is symmetric with respect to a symmetry axis parallel to the second direction.

[0021] The embodiment of the second aspect of the present application further provides a display panel. The display panel includes an array substrate including a substrate, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer laminated along a direction away from the substrate. The array substrate includes a first type of transistor, a second type of transistor, and a capacitor, wherein the first semiconductor layer is used to form the source region, drain region, and channel region of the first type of transistor; the first metal layer is used to form the gate of the first type of transistor and the first plate of the capacitor; the second metal layer is used to form the bottom gate of the second type of transistor; the second semiconductor layer is used to form the source region, drain region, and channel region of the second type of transistor; the third metal layer is used to form the top gate of the second type of transistor; and the fourth metal layer is used to form the source electrode and drain electrode of the first type of transistor and the second type of transistor. A first signal line and a second signal line are formed in one of the first, second, third, and fourth metal layers, extending along a first direction, and the first and second signal lines are arranged along the second direction; a third signal line and a fourth signal line are formed in the fourth metal layer, extending along a second direction, and the third and fourth signal lines are arranged along the first direction, the first direction intersects with the second direction, and the third and fourth signal lines transmit the same signal. Along the direction perpendicular to the substrate, there is a first overlap region between the first signal line and the third signal line, a second overlap region between the first signal line and the fourth signal line, a third overlap region between the second signal line and the third signal line, and a fourth overlap region between the second signal line and the fourth signal line. The first signal line and the third signal line are electrically connected in the first overlap region, the first signal line and the fourth signal line are insulated in the second overlap region, and / or the second signal line and the third signal line are insulated in the third overlap region. The second signal line and the fourth signal line are electrically connected in the fourth overlap region. The orthographic projections of the first overlap region and the fourth overlap region onto the substrate are both located outside the orthographic projection of one type of pixel aperture onto the substrate, and the orthographic projections of the second overlap region and the third overlap region onto the substrate both have at least a part located within the orthographic projection of one type of the pixel aperture onto the substrate.

[0022] According to an embodiment of the second aspect of the present invention, a first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer, and the third signal line and the fourth signal line are formed on the fifth metal layer. The first signal line and the second signal line are formed in the first metal layer, the first signal line and the third signal line are electrically connected via a first via hole in the first overlap region, the second signal line and the fourth signal line are electrically connected via a second via hole in the fourth overlap region, and the first via hole and the second via hole penetrate the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the second metal layer, the first signal line and the third signal line are electrically connected via a first via hole in the first overlap region, the second signal line and the fourth signal line are electrically connected via a second via hole in the fourth overlap region, and the first via hole and the second via hole penetrate the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the fourth metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the third metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the fifth insulating layer and the sixth insulating layer. Preferably, the material of the first semiconductor layer includes a polysilicon semiconductor, and the material of the second semiconductor layer includes a metal oxide semiconductor.

[0023] According to any of the above embodiments of a second aspect of the present invention, the present invention further includes an emissive layer located on the array substrate side and an isolation structure, wherein the emissive layer includes an emissive unit, and the isolation structure includes a main body and an isolation opening opened in the main body, and the orthogonal projection of the emissive unit onto the array substrate is located within the orthogonal projection of the isolation opening onto the array substrate. Preferably, the main body includes a first isolation portion and a second isolation portion, the second isolation portion being located on the side of the first isolation portion away from the array substrate, and the orthogonal projection of the second isolation portion onto the array substrate covering the orthogonal projection of the first isolation portion onto the array substrate. Preferably, the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode, which are stacked in a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion.

[0024] Embodiments of a second aspect of this application further provide a display device including any of the display panels according to the first aspect of this application.

[0025] In the display panel according to this application, the signals in the first signal line and the third signal line are the same, and a first overlap region is formed at their intersection and electrically connected, thereby forming a mesh-like structure between the first signal line and the third signal line. Because the orthographic projection of the first overlap region onto the substrate and the orthographic projection of the pixel aperture onto the substrate do not overlap, electrical connection between the first signal line and the third signal line can be achieved in the first overlap region via a via hole. Since the via hole is not located within the pixel aperture region, the presence of the via hole does not cause display defects in the light-emitting unit corresponding to the pixel aperture due to the film layer above the via hole being non-flat. The signals in the second signal line and the fourth signal line are the same, and a fourth overlap region is formed at their intersection and electrically connected, thereby forming a mesh-like structure between the second signal line and the fourth signal line. The orthographic projection of the fourth overlap region onto the substrate and the orthographic projection of the pixel aperture onto the substrate do not overlap. That is, electrical connection between the second signal line and the fourth signal line is achieved in the fourth overlap region via a via hole, and since the via hole is not located within the pixel aperture region, the presence of the via hole does not cause display defects in the light-emitting unit corresponding to the pixel aperture due to the film layer above the via hole being non-flat. A second overlap region exists between the first and fourth signal lines, and a third overlap region exists between the second and third signal lines. The first and fourth signal lines are isolated in the second overlap region, and the second and third signal lines are isolated in the third overlap region. Since the orthographic projections of the second and third overlap regions onto the substrate are at least partially located within the orthographic projection of one type of pixel aperture onto the substrate, there is no need to provide via holes at the locations of the second and third overlap regions, and this does not affect the display yield of the light-emitting unit corresponding to the pixel aperture.The display panel described in this application achieves electrical connection between the first signal line and the third signal line, and electrical connection between the second signal line and the fourth signal line, and ensures that the orthographic projection of the via holes necessary for the electrical connection onto the substrate is located outside the orthographic projection onto the pixel aperture substrate. This improves the problem of color shift caused by the presence of via holes affecting the electrode flatness of the light-emitting unit within the pixel aperture, thereby improving the display quality of the display panel. [Brief explanation of the drawing]

[0026] To more clearly illustrate the technical concept of the embodiments of this application, the drawings that need to be used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only a few embodiments of this application, and those skilled in the art can obtain other drawings based on these without any creative work.

[0027] [Figure 1] This is a schematic diagram of the structure of a display panel according to an embodiment of this application. [Figure 2] This is a cross-sectional view along the line P-P' in Figure 1. [Figure 3] This is a magnified view of the Q region in Figure 1. [Figure 4] This is a magnified view of the Q region in Figure 1. [Figure 5] This is a magnified view of the Q region in Figure 1. [Figure 6] This is a magnified view of the Q region in Figure 1. [Figure 7] This is a magnified view of the Q region in Figure 1. [Figure 8] This is a magnified view of the Q region in Figure 1. [Figure 9] This is a magnified view of the Q region in Figure 1. [Figure 10] This is a magnified view of the Q region in Figure 1. [Figure 11] This is a magnified view of the Q region in Figure 1. [Figure 12] This is a magnified section of Figure 11. [Figure 13] This is a magnified view of the Q region in Figure 1. [Figure 14] This is a magnified view of a portion of Figure 13. [Figure 15] This is a circuit diagram of the drive circuit in the display panel according to an embodiment of this application. [Figure 16] This is a schematic diagram of the structure of a display panel according to an embodiment of this application. [Figure 17] This is a schematic diagram of the structure of a display device according to an embodiment of this application. [Explanation of Symbols]

[0028] 1 Display panel, 11 Array substrate, 110 Substrate, 111 First conductive layer, 1111 First signal line, 1112 Second signal line, 1113 Fifth signal line, 1114 Sixth signal line, 112 Second conductive layer, 1121 Third signal line, 1122 Fourth signal line, 1123 Seventh signal line, 1124 Eighth signal line, 12 First overlap region, 13 Second overlap region, 14 Third overlap region, 15 Fourth overlap region, 16 Pixel aperture, 161 First pixel aperture, 162 Second pixel aperture, 163 Third pixel aperture, 17 First extension, 18 Second extension, 19 Fifth overlap region, 20 Sixth overlap region, 21 Seventh overlap region, 22 Eighth overlap region, 23 First semiconductor layer, 24 First metal layer, 25 Second metal layer, 26 Second semiconductor layer, 27 Third metal layer, 28 Fourth metal layer, 29 Fifth metal layer, 30 First insulating layer, 31 Second insulating layer, 32 Third insulating layer, 33 Fourth insulating layer, 34 Fifth insulating layer, 35 Sixth insulating layer, 36 Light-emitting unit, 361 First electrode, 362 Light-emitting functional layer, 363 Second electrode, 37 Isolation structure, 371 First isolation section, 372 Second isolation section, 370 Isolation opening, 100 Drive module, 200 Data writing module, 300 Compensation module, 400 Memory module, 500 First light emission control module, 600 Second light emission control module, 700 First initialization module, 800 Second initialization module, 900 Third initialization module, Vref1 First reset signal line, Vref2 Second reset signal line, ELVDD First high-level signal line, ELVSS First low-level signal line, S1 First scan signal line, S2 Second scan signal line, S3 Third scan signal line, S4 Fourth scan signal line, EM Light emission control signal line, Data Data signal line, Vref3 Third reset signal line, 2 Display device. [Modes for carrying out the invention]

[0029] The following describes in detail the features and exemplary embodiments of each aspect of this application. Many specific details are provided in the following detailed description to provide a comprehensive understanding of this application. However, as will be apparent to those skilled in the art, this application can be implemented without requiring some of these specific details. The following description of embodiments is provided solely to illustrate examples of this application and to better understand it.

[0030] In this specification, relational terms such as "First" and "Second," etc., are merely used to distinguish one entity or operation from another and do not necessarily require or imply that such an actual relationship or order exists between these entities or operations. Furthermore, the terms "includes," "contains," or any other variation thereof are intended to cover non-exclusive inclusion, thereby meaning that a process, method, article, or device containing a set of elements includes not only those elements but also other elements not explicitly listed, or elements specific to such a process, method, article, or device. Unless further restrictions are found, an element limited by the phrase "contains" does not preclude the presence of other identical elements in a process, method, article, or device containing the element.

[0031] To better understand this application, the display panel and display device 2 according to the embodiment of this application will be described in detail below with reference to Figures 1 to 17.

[0032] Referring to Figures 1 to 3, an embodiment of the present application provides a display panel 1 including an array substrate 11, the array substrate 11 including a substrate 110 and a first conductive layer 111, an insulating layer, and a second conductive layer 112 sequentially laminated on the substrate 110 side, the first conductive layer 111 including a first signal line 1111 and a second signal line 1112 extending along a first direction x, the second conductive layer 112 including a third signal line 1121 and a fourth signal line 1122 extending along a second direction y, the first direction x and the second direction y intersect, the first signal line 1111 and the second signal line 1112 are arranged along the second direction y, the third signal line 1121 and the fourth signal line 1122 are arranged along the first direction x, and the third signal line 1121 and the fourth signal line 1122 transmit the same signal.

[0033] Along the direction perpendicular to the substrate 110, a first overlap region 12 exists between the first signal line 1111 and the third signal line 1121, a second overlap region 13 exists between the first signal line 1111 and the fourth signal line 1122, a third overlap region 14 exists between the second signal line 1112 and the third signal line 1121, and a fourth overlap region 15 exists between the second signal line 1112 and the fourth signal line 1122. The first signal line 1111 and the third signal line 1121 are electrically connected in the first overlap region 12, the first signal line 1111 and the fourth signal line 1122 are insulated in the second overlap region 13, and / or the second signal line 1112 and the third signal line 1121 are insulated in the third overlap region 14, and the second signal line 1112 and the fourth signal line 1122 are electrically connected in the fourth overlap region 15.

[0034] The orthographic projections of the first overlap region 12 and the fourth overlap region 15 onto the substrate 110 are both located outside the orthographic projection of the pixel aperture 16 onto the substrate 110, while the orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are both located at least partially within the orthographic projection of one type of pixel aperture 16 onto the substrate 110, and the pixel aperture 16 is located on the side of the array substrate 11 toward the insulating layer from the substrate 110.

[0035] In the above embodiment, the second conductive layer 112 is located on the side of the first conductive layer 111, and specifically, it may be located above the first conductive layer 111 or below the first conductive layer 111, but this application does not particularly limit it.

[0036] In the above embodiment, the first overlap region 12 is the region where the orthographic projections of the first signal line 1111 and the third signal line 1121 onto the substrate 110 overlap. The second overlap region 13 is the region where the orthographic projections of the first signal line 1111 and the third signal line 1121 onto the substrate 110 overlap. The third overlap region 14 is the region where the orthographic projections of the second signal line 1112 and the third signal line 1121 onto the substrate 110 overlap. The fourth overlap region 15 is the region where the orthographic projections of the second signal line 1112 and the fourth signal line 1122 onto the substrate 110 overlap.

[0037] The pixel aperture 16 is located on the side of the array substrate 11 away from the substrate 110 and toward the insulating layer, that is, on the side of the second conductive layer 112 away from the substrate 110, and the pixel aperture 16 is used to house and contain the light-emitting unit 36.

[0038] In the display panel 1 according to this application, the first signal line 1111 and the third signal line 1121 have the same signals and are electrically connected by forming a first overlap region 12 at their intersecting position, thereby forming a mesh-like structure between the first signal line 1111 and the third signal line 1121. Because the orthographic projection of the first overlap region 12 onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 do not overlap, an electrical connection between the first signal line 1111 and the third signal line 1121 can be achieved in the first overlap region 12 via a via hole. Since the via hole is not located within the area of ​​the pixel aperture 16, the presence of the via hole does not cause display defects in the light-emitting unit 36 ​​corresponding to the pixel aperture 16 due to the film layer above the via hole being non-flat.

[0039] The second signal line 1112 and the fourth signal line 1122 have the same signals, and a fourth overlap region 15 is formed at their intersection, electrically connecting them. This creates a mesh-like structure between the second signal line 1112 and the fourth signal line 1122. The orthographic projection of the fourth overlap region 15 onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 do not overlap. That is, electrical connection between the second signal line 1112 and the fourth signal line 1122 is achieved in the fourth overlap region 15 via a via hole, and since the via hole is not located within the area of ​​the pixel aperture 16, the presence of the via hole does not cause display defects in the light-emitting unit 36 ​​corresponding to the pixel aperture 16 due to the film layer above the via hole being non-flat.

[0040] A second overlap region 13 exists between the first signal line 1111 and the fourth signal line 1122, and a third overlap region 14 exists between the second signal line 1112 and the third signal line 1121. The first signal line 1111 and the fourth signal line 1122 are isolated in the second overlap region 13, and / or the second signal line 1112 and the third signal line 1121 are isolated in the third overlap region 14. The orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are such that at least a portion of each lies within the orthographic projection of one type of pixel aperture 16 onto the substrate 110. This eliminates the need to provide via holes at the locations of the second overlap region 13 and / or the third overlap region 14, thereby reducing the number of via holes and reducing the impact on the display yield of the light-emitting unit 36 ​​corresponding to the pixel aperture 16.

[0041] The display panel 1 according to this application achieves that the third signal line 1121 and the fourth signal line 1122 transmit the same signal, the first signal line 1111 and the third signal line 1121 are electrically connected, and the second signal line 1112 and the fourth signal line 1122 are electrically connected. Furthermore, the display panel 1 is configured such that most or all of the orthographic projection of the via holes necessary for the electrical connection onto the substrate 110 is located outside the orthographic projection of the pixel aperture 16 onto the substrate 110. This improves the problem of color shift caused by the presence of via holes affecting the electrode flatness of the light-emitting unit 36 ​​within the pixel aperture 16, thereby improving the display quality of the display panel 1.

[0042] In one feasible embodiment, as shown in Figure 4, the pixel aperture 16 includes a first pixel aperture 161, and the orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are each at least partially located within the orthographic projection of the first pixel aperture 161 onto the substrate 110.

[0043] Furthermore, the orthographic projections of the first overlap region 12 and the fourth overlap region 15 onto the substrate 110 are both located outside the orthographic projection of the first pixel aperture 161 onto the substrate 110.

[0044] In the above embodiment, the pixel aperture 16 is used to contain the light-emitting unit 36. The light-emitting unit 36 ​​may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit, with the blue light-emitting unit having the largest area and the most serious impact of its color shift on the yield of the display panel 1. The first pixel aperture 161 may be used to accommodate the blue light-emitting unit.

[0045] The orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are set so that at least a portion of each is located within the orthographic projection of the first pixel aperture 161 onto the substrate 110. Since there is no need to provide via holes at the locations of the second overlap region 13 and / or the third overlap region 14, the impact on the planarization of the upper film layer of the second overlap region 13 and / or the third overlap region 14 is reduced, the yield of the blue light-emitting units is guaranteed, and the problem of display defects in the blue light-emitting units corresponding to the first pixel aperture 161 caused by the upper film layer being uneven due to via holes can be improved.

[0046] On the other hand, because the first pixel aperture 161 is large, the orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are set so that at least a portion of each is located within the orthographic projection of the first pixel aperture 161 onto the substrate 110, thereby easily simplifying the difficulty of wiring and ensuring sufficient spacing between wires. In one feasible embodiment, the display panel 1 may further include a pixel definition layer for defining the pixel aperture 16, formed on the side of the first conductive layer 111 and the second conductive layer 112 that is further away from the substrate 110.

[0047] In one feasible embodiment, as shown in Figure 4, the pixel aperture 16 further includes a second pixel aperture 162, the first pixel aperture 161 and the second pixel aperture 162 are arranged alternately along a second direction y, and the first pixel aperture 161 and the second pixel aperture 162 are further arranged alternately along a first direction x, and the first overlap region 12 and the fourth overlap region 15 are located between adjacent first pixel apertures 161 and second pixel apertures 162 along the second direction y. That is, by providing via holes between the first pixel aperture 161 and the second pixel aperture 162 to realize electrical connections between a first signal line 1111 and a third signal line 1121, and via holes to realize electrical connections between a second signal line 1112 and a fourth signal line 1122, the adverse effects on different color light-emitting units 36 due to the non-flatness of the upper film layer caused by the via holes can be reduced, and the display effect can be improved.

[0048] Specifically, the second pixel aperture 162 may be used to house a red light-emitting unit.

[0049] In one feasible embodiment, as shown in Figure 4, a plurality of first pixel apertures 161 and second pixel apertures 162 are arranged alternately along a second direction y to form a first pixel row, where a first overlap region 12 and a third overlap region 14 are located in one of two adjacent first pixel rows, and a second overlap region 13 and a fourth overlap region 15 are located in the other first pixel row, thereby having in each pixel row one of the first overlap region 12 and the fourth overlap region 15 and one of the second overlap region 13 or the third overlap region 14, where electrical connection is achieved in the first overlap region 12 and the fourth overlap region 15, and isolation is achieved in the second overlap region 13 and / or the third overlap region 14. Accordingly, in the above embodiment, the first overlap region 12 and the fourth overlap region 15 for achieving electrical connection, and the second overlap region 13 and / or third overlap region 14 used for insulation are alternately provided along the first direction x and the second direction y, thereby improving the uniformity of the display panel 1.

[0050] In one feasible embodiment, as shown in Figure 4, the pixel aperture 16 further includes a third pixel aperture 163, the plurality of third pixel apertures 163 arranged along a second direction y to form a second pixel row, and the first and second pixel rows are arranged alternately along a first direction x.

[0051] In the above embodiment, the third pixel aperture 163 may be used to form a green light-emitting unit.

[0052] In one feasible embodiment, as shown in Figure 4, two first pixel apertures 161 and two second pixel apertures 162 are provided on the periphery of the third pixel aperture 163, and the two first pixel apertures 161 and two second pixel apertures 162 are alternately distributed on the periphery of the third pixel aperture 163. This pixel arrangement method can achieve a better light mixing effect.

[0053] In the above pixel arrangement method, the display panel 1 contains multiple virtual quadrilaterals C, which are arranged in a matrix. In each virtual quadrilateral C, two opposing vertices each coincide with the center of the first pixel aperture 161, and the other two opposing vertices each coincide with the center of the second pixel aperture 162.

[0054] In the above pixel arrangement scheme, the orthographic projection of the first signal line 1111 onto the substrate 110 does not overlap with the orthographic projections of the second pixel aperture 162 and the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the first signal line 1111 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 along the first direction x.

[0055] The orthographic projection of the second signal line 1112 onto substrate 110 does not overlap with the orthographic projections of the second pixel aperture 162 and the third pixel aperture 163 onto substrate 110, and the orthographic projection of the second signal line 1112 onto substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto substrate 110 along the first direction x.

[0056] The orthographic projection of the third signal line 1121 onto substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto substrate 110, and the orthographic projection of the third signal line 1121 onto substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto substrate 110 and the orthographic projection of the second pixel aperture 162 onto substrate 110 along the second direction y.

[0057] The orthographic projection of the fourth signal line 1122 onto substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto substrate 110, and the orthographic projection of the fourth signal line 1122 onto substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto substrate 110 and the orthographic projection of the second pixel aperture 162 onto substrate 110 along the second direction y.

[0058] In the above embodiment, the orthographic projection of the first signal line 1111 onto the substrate 110 does not overlap with the orthographic projections of the second pixel aperture 162 and the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the first signal line 1111 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 along the first direction x. The orthographic projection of the third signal line 1121 onto the substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the third signal line 1121 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 and the orthographic projection of the second pixel aperture 162 onto the substrate 110 along the second direction y.

[0059] The orthographic projection of one first signal line 1111 or one second signal line 1112 onto the substrate 110 can pass through the same virtual quadrilateral C, and the orthographic projection of the first signal line 1111 onto the substrate 110 does not overlap with the orthographic projections of the second pixel aperture 162 and the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the third signal line 1121 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 and the orthographic projection of the second pixel aperture 162 onto the substrate 110 along the second direction y, thereby passing through the first signal line 1111 The first overlap region 12, formed to overlap with the third signal line 1121, can be positioned between the second pixel aperture 162 and the first pixel aperture 161 along the second direction y, thereby preventing the orthographic projection of the first overlap region 12 onto the substrate 110 from overlapping with the orthographic projection of the pixel aperture 16 onto the substrate 110. By positioning the first signal line 1111 and the third signal line 1121 to be electrically connected at the location of the first overlap region 12, it is possible to prevent affecting the flatness of the electrodes of the light-emitting unit 36 ​​corresponding to the pixel aperture 16 and improve color shift.

[0060] In the above embodiment, the orthographic projection of the second signal line 1112 onto the substrate 110 does not overlap with the orthographic projections of the second pixel aperture 162 and the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the second signal line 1112 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 along the first direction x. The orthographic projection of the fourth signal line 1122 onto the substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto the substrate 110, and the orthographic projection of the fourth signal line 1122 onto the substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto the substrate 110 and the orthographic projection of the second pixel aperture 162 onto the substrate 110 along the second direction y.

[0061] The orthographic projection of one first signal line 1111 or one second signal line 1112 onto the substrate 110 can pass through the same virtual quadrilateral C orthographic projection onto the substrate 110, and the orthographic projection of the second signal line 1112 onto the substrate 110 does not overlap with the orthographic projection of the second pixel aperture 162 and the third pixel aperture 163 onto the substrate 110, but overlaps only with the orthographic projection of the first pixel aperture 161 onto the substrate 110, so that the orthographic projection of the fourth signal line 1122 onto the substrate 110 passes through the orthographic projections of the first pixel aperture 161 and the second pixel aperture 162 onto the substrate 110 along the second direction y, and then passes through the second signal line 1 The fourth overlap region 15 can be formed with 112, and the orthographic projection of the fourth overlap region 15 onto the substrate 110 is located between the orthographic projections of the second pixel aperture 162 and the first pixel aperture 161 onto the substrate 110, so that the orthographic projection of the fourth overlap region 15 onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 do not overlap. The second signal line 1112 and the fourth signal line 1122 are set to be electrically connected at the location of the second overlap region 13, thereby preventing an impact on the flatness of the electrodes of the light-emitting unit 36 ​​corresponding to the pixel aperture 16 and improving color shift.

[0062] In one feasible embodiment, as shown in Figure 4, the first signal line 1111 and the fourth signal line 1122 are insulated in the second overlap region 13, and the second signal line 1112 and the third signal line 1121 are insulated in the third overlap region 14.

[0063] In the above embodiment, since the signal lines in the second overlap region 13 and the third overlap region 14 are both insulated, in the display panel 1, the orthographic projections of the first overlap region 12 and the fourth overlap region 15 for electrical connection onto the substrate 110 are both located outside the pixel aperture 16. Since the signal lines in the second overlap region 13 and the third overlap region 14, where the orthographic projection onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 overlap, are both insulated, via holes for electrical connection can completely avoid the pixel aperture 16 region, the influence of via holes for electrical connection on the color shift of the light-emitting unit 36 ​​within the pixel aperture 16 can be minimized, and display quality can be improved.

[0064] In another feasible embodiment, as shown in Figure 5, the first signal line 1111 and the fourth signal line 1122 are isolated in the second overlap region 13, and the second signal line 1112 and the third signal line 1121 are electrically connected in the third overlap region 14. This increases the number of connection points between the second signal line 1112 and the third signal line 1121, and further improves the electrical connection effect between the second signal line 1112 and the third signal line 1121.

[0065] In another feasible embodiment, as shown in Figure 6, the first signal line 1111 and the fourth signal line 1122 are electrically connected in a second overlap region 13, and the second signal line 1112 and the third signal line 1121 are isolated in a third overlap region 14. This increases the number of connection points between the first signal line 1111 and the fourth signal line 1122, and further improves the electrical connection effect between the first signal line 1111 and the fourth signal line 1122.

[0066] In another feasible embodiment, as shown in Figures 7 and 8, the first signal line 1111 and the fourth signal line 1122 are isolated in a portion of the second overlap region 13 and electrically connected in a portion of the preset second overlap region 13, and the second signal line 1112 and the third signal line 1121 are isolated in a portion of the third overlap region 14 and electrically connected in a portion of the preset third overlap region 14. This increases the number of connection points between the first signal line 1111 and the fourth signal line 1122, and between the second signal line 1112 and the third signal line 1121, further improving the electrical connection effect between the second signal line 1112 and the third signal line 1121, and further improving the electrical connection effect between the first signal line 1111 and the fourth signal line 1122.

[0067] In the above embodiment, as shown in Figure 7, the sum of the number of pre-set second overlap regions 13 and pre-set third overlap regions 14 is half the sum of the number of second overlap regions 13 and third overlap regions 14, or, as shown in Figure 8, the sum of the number of pre-set second overlap regions 13 and pre-set third overlap regions 14 is one-quarter of the sum of the number of second overlap regions 13 and third overlap regions 14. Therefore, the number of connection points can be reduced by half or three-quarters, and the color misalignment problem can be improved to some extent.

[0068] In one feasible embodiment, as shown in Figure 9, the first conductive layer 111 further includes a fifth signal line 1113 and a sixth signal line 1114 extending along a first direction x, and the second conductive layer 112 further includes a seventh signal line 1123 and an eighth signal line 1124 extending along a second direction y, the fifth signal line 1113 and the sixth signal line 1114 are arranged along the second direction y, the seventh signal line 1123 and the eighth signal line 1124 are arranged along the first direction x, and the seventh signal line 1123 and the eighth signal line 1124 transmit the same signal.

[0069] In the above embodiment, the third signal line 1121 and the fourth signal line 1122 transmit the same signal and intersect with the first signal line 1111 and the second signal line 1112 to form a network for transmitting one type of signal, while the seventh signal line 1123 and the eighth signal line 1124 transmit the same signal and intersect with the fifth signal line 1113 and the sixth signal line 1114 to form a network for transmitting another type of signal.

[0070] In one feasible embodiment, as shown in Figure 9, the third signal line 1121 and the fourth signal line 1122 are provided adjacent to each other along the first direction x, the seventh signal line 1123 and the eighth signal line 1124 are provided adjacent to each other along the first direction x, the fifth signal line 1113 is located between the adjacent first signal line 1111 and the second signal line 1112, the sixth signal line 1114 is located between the adjacent first signal line 1111 and the second signal line 1112, and the first signal line 1111 or the second signal line 1112 is provided between the fifth signal line 1113 and the sixth signal line 1114.

[0071] In the above embodiment, by installing the third signal line 1121 and the fourth signal line 1122 adjacent to each other along the first direction x, and installing the seventh signal line 1123 and the eighth signal line 1124 adjacent to each other along the first direction x, it is possible to ensure insulation at the positions of the second overlap region 13 and the third overlap region 14, and to ensure that the third signal line 1121 and the fourth signal line 1122 are each formed in a mesh pattern.

[0072] In one feasible embodiment, as shown in Figure 9, the orthographic projection of the fifth signal line 1113 onto the substrate 110 does not overlap with the orthographic projections of the first pixel aperture 161 and the second pixel aperture 162 onto the substrate 110, and the orthographic projection of the first signal line 1111 onto the substrate 110 passes through the orthographic projection of the third pixel aperture 163 onto the substrate 110 along the first direction x.

[0073] The orthographic projection of the sixth signal line 1114 onto substrate 110 does not overlap with the orthographic projections of the first pixel aperture 161 and the second pixel aperture 162 onto substrate 110, and the orthographic projection of the sixth signal line 1114 onto substrate 110 passes through the orthographic projection of the third pixel aperture 163 onto substrate 110 along the first direction x.

[0074] The orthographic projection of the seventh signal line 1123 onto substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto substrate 110, and the orthographic projection of the seventh signal line 1123 onto substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto substrate 110 and the orthographic projection of the second pixel aperture 162 onto substrate 110 along the second direction y.

[0075] The orthographic projection of the eighth signal line 1124 onto substrate 110 does not overlap with the orthographic projection of the third pixel aperture 163 onto substrate 110, and the orthographic projection of the eighth signal line 1124 onto substrate 110 passes through the orthographic projection of the first pixel aperture 161 onto substrate 110 and the orthographic projection of the second pixel aperture 162 onto substrate 110 along the second direction y.

[0076] In the above embodiment, since neither the fifth signal line 1113 nor the sixth signal line 1114 passes through the first pixel aperture 161 or the second pixel aperture 162, the electrical connection positions of the fifth signal line 1113, the sixth signal line 1114, the seventh signal line 1123, and the eighth signal line 1124 can be set between the first pixel aperture 161 and the second pixel aperture 162, which are arranged along the second direction y, and this does not affect the light emission yield of the light-emitting unit 36 ​​within the pixel aperture 16.

[0077] In one feasible embodiment, as shown in Figure 9, a fifth overlap region 19 exists between the fifth signal line 1113 and the seventh signal line 1123, a sixth overlap region 20 exists between the fifth signal line 1113 and the eighth signal line 1124, a seventh overlap region 21 exists between the sixth signal line 1114 and the seventh signal line 1123, an eighth overlap region 22 exists between the sixth signal line 1114 and the eighth signal line 1124, and the fifth signal line 111 Signal line 3 and the seventh signal line 1123 are electrically connected in the fifth overlap region 19, signal line 6 and signal line 8 are electrically connected in the eighth overlap region 22, and / or signal line 5 and signal line 8 are electrically connected in the sixth overlap region 20, and signal line 6 and signal line 7 are electrically connected in the seventh overlap region 21.

[0078] In the above embodiment, as shown in Figure 9, the fifth overlap region 19, the sixth overlap region 20, the seventh overlap region 21, and the eighth overlap region 22 may all be electrically connected overlap regions. Alternatively, they may be overlap regions that are partially insulated and partially electrically connected, provided that the fifth signal line 1113, the eighth signal line 1124, the sixth signal line 1114, and the seventh signal line 1123 are arranged in a mesh pattern. Specifically, this may consist of one mesh pattern or two mesh patterns. Specifically, as shown in Figure 10, the fifth signal line 1113 and the seventh signal line 1123 are electrically connected in the fifth overlap region 19, the fifth signal line 1113 and the eighth signal line 1124 are isolated in the sixth overlap region 20, the sixth signal line 1114 and the seventh signal line 1123 are isolated in the seventh overlap region 21, and the sixth signal line 1114 and the eighth signal line 1124 are electrically connected in the eighth overlap region 22.

[0079] In one feasible embodiment, as shown in Figures 11 and 12, the first signal line 1111 further includes a first extension 17, the first extension 17 being connected to a second overlap region 13 and aligned with the second overlap region 13 along a second direction y, the orthographic projection of the first extension 17 onto the substrate 110 being at least partially outside the orthographic projection of the first pixel aperture 161 onto the substrate 110, the first extension 17 being electrically connected to a fourth signal line 1122 via a first through-hole, the orthographic projection of the first through-hole onto the substrate 110 not overlapping with the orthographic projection of the first pixel aperture 161 onto the substrate 110.

[0080] In the above embodiment, by providing a first through-hole in the first extension portion 17, an electrical connection between the first signal line 1111 and the fourth signal line 1122 can be achieved. Specifically, the first through-hole is formed in the first extension portion 17, and the first extension portion 17 is connected to the second overlap region 13, thereby increasing the overlap area between the first signal line 1111 and the fourth signal line 1122. The first extension portion 17 moves the position where the first signal line 1111 and the fourth signal line 1122 overlap to form the first through-hole outside the orthogonal projection onto the substrate 110 of the pixel aperture 16, thereby achieving an electrical connection between the first signal line 1111 and the fourth signal line 1122, and ensuring that the first through-hole does not affect the color shift of the light-emitting unit 36 ​​within the pixel aperture 16.

[0081] In the above embodiment, the fifth signal line 1113 includes a first partition region for accommodating the first extension 17, and at least a portion of the first extension 17 is located in the first partition region.

[0082] Because the distance between the fifth signal line 1113 and the first signal line 1111 is short, providing a first partition region on the fifth signal line 1113 provides the conditions for accommodating the first extension 17 and providing a first through hole in the first extension 17.

[0083] In one feasible embodiment, as shown in Figures 13 and 14, the second signal line 1112 further includes a second extension 18 connected to a third overlap region 14 and aligned with the third overlap region 14 along a second direction y, wherein the orthographic projection of the second extension 18 onto the substrate 110 is at least partially outside the orthographic projection of the first pixel aperture 161 onto the substrate 110, the second extension 18 is electrically connected to the third signal line 1121 via a second through-hole, and the orthographic projection of the second through-hole onto the substrate 110 does not overlap with the orthographic projection of the first pixel aperture 161 onto the substrate 110.

[0084] In the above embodiment, by providing a second through-hole in the second extension portion 18, electrical connection between the second signal line 1112 and the third signal line 1121 can be achieved. Specifically, the second through-hole is formed in the second extension portion 18, and the second extension portion 18 is connected to the third overlap region 14, thereby increasing the overlap area between the second signal line 1112 and the third signal line 1121. The second extension portion 18 moves the position where the second signal line 1112 and the third signal line 1121 overlap to form the second through-hole outside the orthogonal projection onto the substrate 110 of the pixel aperture 16, thereby achieving electrical connection between the second signal line 1112 and the third signal line 1121, and preventing the second through-hole from affecting the color shift of the light-emitting unit 36 ​​within the pixel aperture 16.

[0085] In the above embodiment, the sixth signal line 1114 includes a second partition region for accommodating the second extension 18, and at least a portion of the second extension 18 is located in the second partition region.

[0086] Because the distance between the sixth signal line 1114 and the second signal line 1112 is short, providing a second partition region in the sixth signal line 1114 provides the conditions for accommodating the second extension 18 and providing a second through-hole in the second extension 18.

[0087] In one feasible embodiment, the first high-level signal line is located in a second conductive layer 112, the first high-level signal line extending along a second direction y, and the portion of the orthographic projection of the first high-level signal line onto the substrate 110 that lies within the orthographic projections of the second pixel aperture 162 and the first pixel aperture 161 onto the substrate 110 is symmetric with respect to an axis of symmetry parallel to the second direction y.

[0088] This strengthens the symmetry of the first electrode 361 of the light-emitting unit 36, improving the color shift phenomenon and enhancing the display quality of the display panel 1.

[0089] In one feasible embodiment, the second conductive layer 112 is located on the side of the first conductive layer 111 away from the substrate 110.

[0090] In one feasible embodiment, the signals in the first signal line 1111 and the fifth signal line 1113 are different.

[0091] Specifically, the first signal line 1111 contains the first reset signal, meaning that the first signal line 1111, the second signal line 1112, the third signal line 1121, and the fourth signal line 1122 are all the first reset signal line Vref1, and the fifth signal line 1113 contains the second reset signal, meaning that the fifth signal line 1113, the sixth signal line 1114, the seventh signal line 1123, and the eighth signal line 1124 are all the second reset signal line Vref2.

[0092] Specifically, as shown in Figure 15, the drive circuit is electrically connected to at least one light-emitting unit 36, and the drive circuit includes a first light-emitting control module 500, a first initialization module 700, and a second initialization module 800. The control terminal of the second initialization module 800 is electrically connected to the first scan signal line S1, the first terminal of the second initialization module 800 is electrically connected to the second reset signal line Vref2, and the second terminal of the second initialization module 800 is electrically connected to the first terminal of the first light-emitting control module 500. The control terminal of the first initialization module 700 is electrically connected to the first scan signal line S1, the first terminal of the first initialization module 700 is electrically connected to the first reset signal line Vref1, and the second terminal of the first initialization module 700 is electrically connected to the second terminal of the first light-emitting control module 500 and the light-emitting unit 36. The control terminal of the first light emission control module 500 is electrically connected to the light emission control signal line EM, the first terminal of the first light emission control module 500 is electrically connected to the second initialization module 800, and the second terminal of the first light emission control module 500 is electrically connected to the first initialization module 700 and the light emission unit 36.

[0093] The drive circuit further includes a drive module 100, a data writing module 200, a compensation module 300, a storage module 400, a second light emission control module 600, and a third initialization module 900. The display panel 1 further includes a first high-level signal line ELVDD, a first low-level signal line ELVSS, a second scan signal line S2, a first scan signal line S1, a third scan signal line S3, a fourth scan signal line S4, a light emission control line EM, a data signal line Data, and a third reset signal line Vref3.

[0094] Here, the control terminal of the second light emission control module 600 is connected to the light emission control signal line EM, the first terminal of the second light emission control module 600 is connected to the first high-level signal line ELVDD and the first terminal of the storage module 400, and the second terminal of the second light emission control module 600 is connected to the second terminal of the data writing module 200 and the first terminal of the drive module 100.

[0095] The first terminal of the memory module 400 is connected to the first high-level signal line ELVDD and the first terminal of the second light emission control module 600, and the second terminal of the memory module 400 is connected to the first terminal of the compensation module 300 and the control terminal of the drive module 100.

[0096] The control terminal of the data writing module 200 is electrically connected to the second scan signal line S2, the first terminal of the data writing module 200 is electrically connected to the data signal line Data, and the second terminal of the data writing module 200 is connected to the first terminal of the drive module 100 and the second terminal of the second light emission control module 600.

[0097] The control terminal of the compensation module 300 is connected to the fourth scan signal line S4, the first terminal of the compensation module 300 is connected to the second terminal of the memory module 400 and the control terminal of the drive module 100, and the second terminal of the compensation module 300 is electrically connected to the first node N.

[0098] The control terminal of the drive module 100 is electrically connected to the second terminal of the memory module 400 and the first terminal of the compensation module 300. The first terminal of the drive module 100 is connected to the second terminal of the data writing module 200 and the second terminal of the second light emission control module 600. The second terminal of the drive module 100 is electrically connected to the first node N.

[0099] The control terminal of the first light emission control module 500 is electrically connected to the light emission control signal line EM, the first terminal of the first light emission control module 500 is electrically connected to the second initialization module 800 and the first node N, and the second terminal of the first light emission control module 500 is electrically connected to the first initialization module 700 and the light emission unit 36.

[0100] The control terminal of the second initialization module 800 is electrically connected to the first scanning signal line S1, the first terminal of the second initialization module 800 is electrically connected to the second reset signal line Vref2, and the second terminal of the second initialization module 800 is electrically connected to the first terminal and the first node N of the first light emission control module 500.

[0101] The control terminal of the first initialization module 700 is electrically connected to the first scan signal line S1, the first terminal of the first initialization module 700 is electrically connected to the first reset signal line Vref1, and the second terminal of the first initialization module 700 is electrically connected to the second terminal of the first light emission control module 500 and the light emission unit 36.

[0102] The control terminal of the third initialization module 900 is electrically connected to the third scan signal line S3, the first terminal of the third initialization module 900 is electrically connected to the third reset signal line Vref3, and the second terminal of the third initialization module 900 is electrically connected to the second terminal of the second initialization module 800 and the first node N.

[0103] The light-emitting unit 36 ​​includes a first electrode 361 and a second electrode 363, the first electrode 361 being electrically connected to a second terminal of the first initialization module 700 and a second terminal of the first light-emitting control module 500, and the second electrode 363 being electrically connected to a first low-level signal line ELVSS.

[0104] In the above embodiment, the first initialization module 700 is for resetting the first electrode 361 of the light-emitting unit 36, the second initialization module 800 is for resetting the second terminal of the drive module 100, and the third initialization module 900 is for resetting the control terminal of the drive module 100, thereby contributing to improved display quality.

[0105] This application further provides a display panel 1, as shown in Figure 16, the display panel 1 includes an array substrate 11, the array substrate 11 includes a substrate 110 and a first semiconductor layer 23, a first metal layer 24, a second metal layer 25, a second semiconductor layer 26, a third metal layer 27, a fourth metal layer 28, and a fifth metal layer 29, which are laminated along a direction away from the substrate 110.

[0106] Here, the array substrate 11 includes a first type transistor, a second type transistor, and a capacitor, the first semiconductor layer 23 is used to form the source region, drain region, and channel region of the first type transistor, the first metal layer 24 is used to form the gate of the first type transistor and the first plate of the capacitor, the second metal layer 25 is used to form the bottom gate of the second type transistor, the second semiconductor layer 26 is used to form the source region, drain region, and channel region of the second type transistor, the third metal layer 27 is used to form the top gate of the second type transistor, and the fourth metal layer 28 is used to form the source electrode and drain electrode of the first type transistor and the second type transistor.

[0107] A first signal line 1111 and a second signal line 1112 are formed in one of the first metal layer 24, the second metal layer 25, the fourth metal layer 28, and the third metal layer 27, extending along a first direction x, and the first signal line 1111 and the second signal line 1112 are arranged along a second direction y. A third signal line 1121 and a fourth signal line 1122 are formed in the fifth metal layer 29, extending along a second direction y, and the third signal line 1121 and the fourth signal line 1122 are arranged along the first direction x, the first direction x and the second direction y intersect, and the third signal line 1121 and the fourth signal line 1122 transmit the same signal.

[0108] Along the direction perpendicular to the substrate 110, there is a first overlap region 12 between the first signal line 1111 and the third signal line 1121, a second overlap region 13 between the first signal line 1111 and the fourth signal line 1122, a third overlap region 14 between the second signal line 1112 and the third signal line 1121, and a fourth overlap region 15 between the second signal line 1112 and the fourth signal line 1122. The first signal line 1111 and the third signal line 1121 are electrically connected in the first overlap region 12, and the first signal line 1111 and the fourth signal line 1122 are electrically connected in the second overlap region 13. The second signal line 1112 and the third signal line 1121 are insulated in the third overlap region 14, and the second signal line 1112 and the fourth signal line 1122 are electrically connected in the fourth overlap region 15, and the orthographic projections of the first overlap region 12 and the fourth overlap region 15 onto the substrate 110 are both located outside the orthographic projection of the pixel aperture 16 onto the substrate 110, and the orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are both located at least partially within the orthographic projection of one type of pixel aperture 16 onto the substrate 110.

[0109] In the display panel 1 according to this application, the first signal line 1111 and the third signal line 1121 have the same signals and are electrically connected by forming a first overlap region 12 at their intersecting position, thereby forming a mesh-like structure between the first signal line 1111 and the third signal line 1121. The orthographic projection of the first overlap region 12 onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 do not overlap, so that electrical connection between the first signal line 1111 and the third signal line 1121 can be achieved in the first overlap region 12 via a via hole. Since the via hole is not located within the area of ​​the pixel aperture 16, the presence of the via hole does not cause display defects in the light-emitting unit 36 ​​corresponding to the pixel aperture 16 due to the film layer above the via hole being non-flat.

[0110] The second signal line 1112 and the fourth signal line 1122 have the same signals and are electrically connected by a fourth overlap region 15 formed at their intersection, thereby forming a mesh-like structure between the second signal line 1112 and the fourth signal line 1122. The orthographic projection of the fourth overlap region 15 onto the substrate 110 and the orthographic projection of the pixel aperture 16 onto the substrate 110 do not overlap. That is, electrical connection between the second signal line 1112 and the fourth signal line 1122 is achieved in the fourth overlap region 15 via a via hole, and since the via hole is not located within the area of ​​the pixel aperture 16, the presence of the via hole does not cause display defects in the light-emitting unit 36 ​​corresponding to the pixel aperture 16 due to the film layer above the via hole being non-flat.

[0111] A second overlap region 13 exists between the first signal line 1111 and the fourth signal line 1122, and a third overlap region 14 exists between the second signal line 1112 and the third signal line 1121. The first signal line 1111 and the fourth signal line 1122 are isolated in the second overlap region 13, and / or the second signal line 1112 and the third signal line 1121 are isolated in the third overlap region 14. The orthographic projections of the second overlap region 13 and the third overlap region 14 onto the substrate 110 are such that at least a portion of each lies within the orthographic projection of one type of pixel aperture 16 onto the substrate 110. This eliminates the need to provide via holes at the locations of the second overlap region 13 and / or the third overlap region 14, thereby reducing the number of via holes and reducing the impact on the display yield of the light-emitting unit 36 ​​corresponding to the pixel aperture 16.

[0112] The display panel 1 according to this application achieves that the third signal line 1121 and the fourth signal line 1122 transmit the same signal, the first signal line 1111 and the third signal line 1121 are electrically connected, and the second signal line 1112 and the fourth signal line 1122 are electrically connected. Furthermore, the display panel 1 is configured such that most or all of the orthographic projection of the via holes necessary for the electrical connection onto the substrate 110 is located outside the orthographic projection of the pixel aperture 16 onto the substrate 110. This improves the problem of color shift caused by the presence of via holes affecting the electrode flatness of the light-emitting unit 36 ​​within the pixel aperture 16, thereby improving the display quality of the display panel 1.

[0113] Specifically, the material of the first semiconductor layer 23 includes a polysilicon semiconductor, and the material of the second semiconductor layer 26 includes a metal oxide semiconductor.

[0114] In the above embodiment, the second type of transistor is an oxide semiconductor transistor, and the second type of transistor may also be a double-gate transistor.

[0115] In the above embodiment, a first insulating layer 30 is formed between the first semiconductor layer 23 and the first metal layer 24, a second insulating layer 31 is formed between the first metal layer 24 and the second metal layer 25, a third insulating layer 32 is formed between the second metal layer 25 and the second semiconductor layer 26, a fourth insulating layer 33 is formed between the second semiconductor layer 26 and the third metal layer 27, a fifth insulating layer 34 is formed between the third metal layer 27 and the fourth metal layer 28, a sixth insulating layer 35 is formed between the fourth metal layer 28 and the fifth metal layer 29, and a third signal line 1121 and a fourth signal line 1122 are formed in the fifth metal layer 29.

[0116] In one feasible embodiment, a first signal line 1111 and a second signal line 1112 are formed in a first metal layer 24, the first signal line 1111 and a third signal line 1121 are electrically connected via a first via hole in a first overlap region 12, the second signal line 1112 and a fourth signal line 1122 are electrically connected via a second via hole in a fourth overlap region 15, and the first and second via holes penetrate a second insulating layer 31, a third insulating layer 32, a fourth insulating layer 33, a fifth insulating layer 34, and a sixth insulating layer 35.

[0117] In another feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed in the second metal layer 25, the first signal line 1111 and the third signal line 1121 are electrically connected via a first via hole in the first overlap region 12, the second signal line 1112 and the fourth signal line 1122 are electrically connected via a second via hole in the fourth overlap region 15, and the first and second via holes penetrate the third insulating layer 32, the fourth insulating layer 33, the fifth insulating layer 34, and the sixth insulating layer 35.

[0118] In another feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed in the fourth metal layer 28, the first signal line 1111 and the third signal line 1121 are electrically connected via a first via hole in the first overlap region 12, the second signal line 1112 and the fourth signal line 1122 are electrically connected via a second via hole in the fourth overlap region 15, and the first and second via holes penetrate the sixth insulating layer 35.

[0119] In another feasible embodiment, the first signal line 1111 and the second signal line 1112 are formed in the third metal layer 27, the first signal line 1111 and the third signal line 1121 are electrically connected via a first via hole in the first overlap region 12, the second signal line 1112 and the fourth signal line 1122 are electrically connected via a second via hole in the fourth overlap region 15, and the first and second via holes penetrate the fifth insulating layer 34 and the sixth insulating layer 35.

[0120] In one feasible embodiment, as shown in Figure 16, the array substrate 11 further includes a light-emitting layer and an isolation structure 37 located on one side, the light-emitting layer includes a light-emitting unit 36, and the isolation structure 37 includes a main body and an isolation opening 370 opened in the main body, the orthographic projection of the light-emitting unit 36 ​​onto the array substrate 11 is located within the orthographic projection of the isolation opening 370 onto the array substrate 11.

[0121] Specifically, the light-emitting unit 36 ​​includes a first electrode 361, a light-emitting functional layer 362, and a second electrode 363, which are stacked in a direction away from the substrate. In the above embodiment, the isolation structure 37 separates the second electrode 363 of the light-emitting unit 36 ​​from the light-emitting functional layer 362, thereby achieving mutual independence of different light-emitting units 36, improving the crosstalk problem between adjacent light-emitting units 36, and contributing to an improvement in the display quality of the display panel 1. At the same time, by adopting the isolation structure 37, it is not necessary to use a mask plate in the manufacturing process of the light-emitting units 36, and the spacing between the light-emitting units 36 can be reduced to improve the aperture ratio, while also saving costs.

[0122] Specifically, the isolation structure 37 includes a first isolation section 371 and a second isolation section 372, the second isolation section 372 being located on the side of the first isolation section 371 away from the substrate 110, and the orthographic projection of the second isolation section 372 onto the substrate 110 covering the orthographic projection of the first isolation section 371 onto the substrate 110.

[0123] In the above embodiment, a step is formed between the second isolation portion 372 and the first isolation portion 371 in the isolation structure 37, and the light-emitting functional layer 362 and the second electrode 363 are separated at the step, thereby realizing mutual independence between different light-emitting units 36. More preferably, the second electrode 363 is electrically connected to the first isolation portion 371, thereby contributing to realizing the transmission demand for the power signal required inside the second electrode 363.

[0124] Related technical proposals for isolation structures are described in Patent PCT / CN2023 / 134518, Patent 202310759370.2, Patent 202310740412.8, Patent 202310707209.0 and Patent 202311346196.5, the contents of which are incorporated into this application by reference.

[0125] This application further provides a display device 2, which includes a display panel 1 according to any of the embodiments of this application, as shown in Figure 17.

[0126] The color misalignment problem in the display device 2 is improved, resulting in enhanced display quality and contributing to a further improvement in the user experience.

[0127] The display device 2 may be a mobile terminal such as a mobile phone or laptop computer, a fixed terminal such as a television or computer display, or a wearable device such as a wristwatch, and is not particularly limited in this application.

[0128] As described above in the embodiments of this application, these embodiments do not detail all aspects, nor do they limit the invention to any particular embodiment. It is clear from the above description that many modifications and changes are possible. This specification selects and describes these embodiments specifically to better interpret the principles and practical applications of this application, thereby enabling those skilled in the art to make full use of this application and any modifications thereto. This application is limited only by the claims and all their scope and equivalents.

Claims

1. The array substrate comprises a substrate and a first conductive layer, an insulating layer, and a second conductive layer sequentially laminated on the substrate side, wherein the first conductive layer includes a first signal line and a second signal line extending along a first direction, and the second conductive layer includes a third signal line and a fourth signal line extending along a second direction, the first direction and the second direction intersect, the first signal line and the second signal line are arranged along the second direction, the third signal line and the fourth signal line are arranged along the first direction, and the third signal line and the fourth signal line transmit the same signal. Along the direction perpendicular to the substrate, a first overlap region exists between the first signal line and the third signal line, a second overlap region exists between the first signal line and the fourth signal line, a third overlap region exists between the second signal line and the third signal line, and a fourth overlap region exists between the second signal line and the fourth signal line, and the first signal line and the third signal line are electrically connected in the first overlap region. The first signal line and the fourth signal line are insulated in the second overlap region, and / or the second signal line and the third signal line are insulated in the third overlap region. The second signal line and the fourth signal line are electrically connected in the fourth overlap region, the orthographic projections of the first and fourth overlap regions onto the substrate are both located outside the orthographic projection of one type of pixel aperture onto the substrate, the orthographic projections of the second and third overlap regions onto the substrate are both located at least partially within the orthographic projection of one type of pixel aperture onto the substrate, and the pixel aperture is located on the side of the array substrate toward the insulating layer. A display panel characterized by having a first reset signal in the first signal line and the third signal line.

2. The pixel aperture includes a first pixel aperture, and the orthographic projections of the second overlap region and the third overlap region onto the substrate are each at least partially located within the orthographic projection of the first pixel aperture onto the substrate. The display panel according to claim 1, characterized in that the orthographic projections of the first overlap region and the fourth overlap region onto the substrate are both located outside the orthographic projection of the first pixel aperture onto the substrate, and the first pixel aperture is used to house a blue light-emitting unit.

3. The pixel aperture further includes a second pixel aperture, the first pixel aperture and the second pixel aperture are arranged alternately along the second direction, and the first pixel aperture and the second pixel aperture are further arranged alternately along the first direction, the first overlap region and the fourth overlap region are located between adjacent first pixel apertures and second pixel apertures along the second direction, The display panel according to claim 2, characterized in that the second pixel aperture is used to house a red light-emitting unit.

4. The display panel according to claim 3, characterized in that a plurality of the first pixel apertures and the second pixel apertures are arranged alternately along a second direction to form a first pixel row, and of two adjacent first pixel rows, the first overlap region and the third overlap region are located in one of the first pixel rows, and the second overlap region and the fourth overlap region are located in the other first pixel row.

5. The display panel according to claim 4, wherein the pixel aperture further includes a third pixel aperture, the plurality of third pixel apertures are arranged along the second direction to form a second pixel row, and the first pixel row and the second pixel row are arranged alternately along the first direction.

6. The display panel according to claim 5, characterized in that two first pixel apertures and two second pixel apertures are provided on the periphery of the third pixel aperture, and the two first pixel apertures and two second pixel apertures are alternately distributed on the periphery of the third pixel aperture.

7. The orthographic projection of the first signal line onto the substrate does not overlap with the orthographic projections of the second and third pixel apertures onto the substrate, and the orthographic projection of the first signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate along the first direction. The orthographic projection of the second signal line onto the substrate does not overlap with the orthographic projections of the second and third pixel apertures onto the substrate, and the orthographic projection of the second signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate along the first direction. The orthographic projection of the third signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the third signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction. The display panel according to claim 5, characterized in that the orthographic projection of the fourth signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the fourth signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction.

8. The first signal line and the fourth signal line are insulated in the second overlap region, and the second signal line and the third signal line are insulated in the third overlap region. Alternatively, the first signal line and the fourth signal line are insulated in the second overlap region, and the second signal line and the third signal line are electrically connected in the third overlap region. Alternatively, the first signal line and the fourth signal line are electrically connected in the second overlap region, and the second signal line and the third signal line are isolated in the third overlap region. Alternatively, the display panel according to claim 1, characterized in that the first signal line and the fourth signal line are insulated in a portion of the second overlap region and electrically connected in a portion of the preset second overlap region, the second signal line and the third signal line are insulated in a portion of the third overlap region and electrically connected in a portion of the preset third overlap region, and the sum of the number of the portion of the preset second overlap region and the portion of the preset third overlap region is half or one-quarter of the sum of the number of the second overlap region and the third overlap region.

9. The display panel according to claim 1, wherein the first conductive layer further includes a fifth signal line and a sixth signal line extending along the first direction, the second conductive layer further includes a seventh signal line and an eighth signal line extending along the second direction, the fifth signal line and the sixth signal line are arranged along the second direction, the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal.

10. The display panel according to claim 9, characterized in that the third signal line and the fourth signal line are provided adjacent to each other along the first direction, the seventh signal line and the eighth signal line are provided adjacent to each other along the first direction, the fifth signal line is located between the adjacent first signal line and the second signal line, the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is provided between the fifth signal line and the sixth signal line.

11. The pixel aperture includes a first pixel aperture, a second pixel aperture, and a third pixel aperture, the first and second pixel apertures are arranged alternately along the second direction, and the first and second pixel apertures are further arranged alternately along the first direction, a plurality of the first and second pixel apertures are arranged alternately along the second direction to form a first pixel row, a plurality of the third pixel apertures are arranged along the second direction to form a second pixel row, the first pixel row and the second pixel row are arranged alternately along the first direction, the orthographic projection of the fifth signal line onto the substrate does not overlap with the orthographic projection of the first and second pixel apertures onto the substrate, and the orthographic projection of the first signal line onto the substrate passes through the orthographic projection of the third pixel aperture onto the substrate along the first direction. The orthographic projections of the second overlap region and the third overlap region onto the substrate are both such that at least a portion of them lies within the orthographic projection of the first pixel aperture onto the substrate. The first overlap region and the fourth overlap region are located between the first and second pixel apertures adjacent to each other along the second direction. Of the two adjacent rows of the first pixel array, the first overlap region and the third overlap region are located in one of the first pixel arrays, and the second overlap region and the fourth overlap region are located in the other first pixel array. The orthographic projection of the sixth signal line onto the substrate does not overlap with the orthographic projections of the first and second pixel apertures onto the substrate, and the orthographic projection of the sixth signal line onto the substrate passes through the orthographic projection of the third pixel aperture onto the substrate along the first direction. The orthographic projection of the seventh signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the seventh signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction. The display panel according to claim 10, characterized in that the orthographic projection of the eighth signal line onto the substrate does not overlap with the orthographic projection of the third pixel aperture onto the substrate, and the orthographic projection of the eighth signal line onto the substrate passes through the orthographic projection of the first pixel aperture onto the substrate and the orthographic projection of the second pixel aperture onto the substrate along the second direction.

12. The first signal line further includes a first extension, the first extension being connected to the second overlap region and arranged along the second overlap region and the second direction, at least a portion of the orthographic projection of the first extension onto the substrate lies outside the orthographic projection of the first pixel aperture onto the substrate, the first extension is electrically connected to the fourth signal line via a first through-hole, the orthographic projection of the first through-hole onto the substrate does not overlap with the orthographic projection of the first pixel aperture onto the substrate, The display panel according to claim 11, wherein the fifth signal line includes a first partition area for accommodating the first extension, and at least a portion of the first extension is located in the first partition area.

13. The second signal line further includes a second extension, the second extension being connected to the third overlap region and aligned with the third overlap region and the second direction, at least a portion of the orthographic projection of the second extension onto the substrate lies outside the orthographic projection of the first pixel aperture onto the substrate, the second extension is electrically connected to the third signal line via a second through-hole, and the orthographic projection of the second through-hole on the substrate does not overlap with the orthographic projection of the first pixel aperture onto the substrate. The display panel according to claim 11, wherein the sixth signal line includes a second partition area for accommodating the second extension, and at least a portion of the second extension is located in the second partition area.

14. A fifth overlap region exists between the fifth signal line and the seventh signal line, a sixth overlap region exists between the fifth signal line and the eighth signal line, a seventh overlap region exists between the sixth signal line and the seventh signal line, and an eighth overlap region exists between the sixth signal line and the eighth signal line. The fifth signal line and the seventh signal line are electrically connected in the fifth overlap region, and the sixth signal line and the eighth signal line are electrically connected in the eighth overlap region. The display panel according to claim 9, characterized in that the fifth signal line and the eighth signal line are electrically connected in the sixth overlap region, and the sixth signal line and the seventh signal line are electrically connected in the seventh overlap region.

15. The seventh signal line has a second reset signal, The display panel is electrically connected to at least one light-emitting unit and further includes a plurality of drive circuits, including a first light-emitting control module, a first initialization module, and a second initialization module. The control terminal of the second initialization module is electrically connected to the first scan signal line, the first terminal of the second initialization module is electrically connected to the second reset signal line, and the second terminal of the second initialization module is electrically connected to the first terminal of the first light emission control module. The display panel according to claim 9, characterized in that the control terminal of the first initialization module is electrically connected to the first scan signal line, the first terminal of the first initialization module is electrically connected to the first reset signal line, and the second terminal of the first initialization module is electrically connected to the second terminal of the first light emission control module and the light emission unit.

16. The display panel according to claim 3, further comprising a first high-level signal line located in the second conductive layer, wherein the first high-level signal line extends along the second direction, and the portion of the first high-level signal line located in the second pixel aperture and the first pixel aperture in the orthographic projection onto the substrate is symmetric with respect to an axis of symmetry parallel to the second direction.

17. The present invention includes a substrate and an array substrate comprising a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are stacked along a direction away from the substrate. The array substrate includes a first type of transistor, a second type of transistor, and a capacitor, wherein the first semiconductor layer is used to form the source region, drain region, and channel region of the first type of transistor; the first metal layer is used to form the gate of the first type of transistor and the first plate of the capacitor; the second metal layer is used to form the bottom gate of the second type of transistor; the second semiconductor layer is used to form the source region, drain region, and channel region of the second type of transistor; the third metal layer is used to form the top gate of the second type of transistor; and the fourth metal layer is used to form the source electrode and drain electrode of the first type of transistor and the second type of transistor. A first signal line and a second signal line are formed in one of the first, second, third, and fourth metal layers, extending along a first direction, and the first and second signal lines are arranged along a second direction. A third signal line and a fourth signal line are formed in the fourth metal layer, extending along a second direction, and the third and fourth signal lines are arranged along the first direction, the first direction intersects with the second direction, and the third and fourth signal lines transmit the same signal. Along the direction perpendicular to the substrate, a first overlap region exists between the first signal line and the third signal line, a second overlap region exists between the first signal line and the fourth signal line, a third overlap region exists between the second signal line and the third signal line, and a fourth overlap region exists between the second signal line and the fourth signal line, and the first signal line and the third signal line are electrically connected in the first overlap region. The first signal line and the fourth signal line are insulated in the second overlap region, and / or the second signal line and the third signal line are insulated in the third overlap region. The second signal line and the fourth signal line are electrically connected in the fourth overlap region, the orthographic projections of the first and fourth overlap regions onto the substrate are both located outside the orthographic projection of one type of pixel aperture onto the substrate, and the orthographic projections of the second and third overlap regions onto the substrate are both located at least partially within the orthographic projection of one type of pixel aperture onto the substrate. A display panel characterized by having a first reset signal in the first signal line and the third signal line.

18. A first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer, and the third signal line and the fourth signal line are formed in the fifth metal layer. The first signal line and the second signal line are formed in the first metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the second metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the fourth metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the sixth insulating layer. Alternatively, the first signal line and the second signal line are formed in the third metal layer, the first signal line and the third signal line are electrically connected in the first overlap region via a first via hole, the second signal line and the fourth signal line are electrically connected in the fourth overlap region via a second via hole, and the first via hole and the second via hole penetrate the fifth insulating layer and the sixth insulating layer. The display panel according to claim 17, characterized in that the material of the first semiconductor layer includes a polysilicon semiconductor, and the material of the second semiconductor layer includes a metal oxide semiconductor.

19. The array substrate side further includes a light-emitting layer and an isolation structure, the light-emitting layer includes a light-emitting unit, the isolation structure includes a main body and an isolation opening opened in the main body, the orthographic projection of the light-emitting unit onto the array substrate is located within the orthographic projection of the isolation opening onto the array substrate, The main body includes a first isolation portion and a second isolation portion, the second isolation portion being located on the side of the first isolation portion away from the array substrate, and the orthographic projection of the second isolation portion onto the array substrate covering the orthographic projection of the first isolation portion onto the array substrate. The display panel according to claim 17, wherein the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode, which are stacked along a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion.

20. A display device characterized by comprising a display panel according to any one of claims 1 to 19.

Images