Photoelectric converters, photoelectric conversion systems, mobile devices, semiconductor substrates

Abstract

This photoelectric conversion device is characterized by comprising a pixel array having arranged therein a plurality of pixels that include first to third pixels and that each include photoelectric conversion units, and is characterized in that at least a portion of the pixels included in the pixel array outputs signals for use in focus detection, the first and second pixels are arranged along a first direction in a plan view from the upper surface of the pixel array, the first pixel is positioned away from the second pixel in the positive direction of the first direction, the first and third pixels are arranged along a second direction, the first and third pixels are connected to a first signal line, the second pixel is connected to a second signal line, the first signal line is connected to a first signal processing circuit, the second signal line is connected to a second signal processing circuit, the first and second signal processing circuits are arranged along the first direction, and the first signal processing circuit is positioned away from the second signal processing circuit in a direction having a negative-direction component of the first direction.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system including the photoelectric conversion device, a moving body, and a semiconductor substrate.

Background Art

[0002] A solid-state imaging device that reads out pixel signals using two signal processing circuits is disclosed in Patent Document 1.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the solid-state imaging device described in Patent Document 1, when performing horizontal addition of pixel signals, there are problems that the readout speed decreases or the signal processing becomes complicated. In particular, when pixels that output signals for focus detection are provided in the pixel array, a load for processing the focus detection signals occurs, so the problems of readout speed and signal processing complexity increase further.

[0005] The present case has been made in view of the above problems, and in a photoelectric conversion device that reads out pixel signals using two signal processing circuits, it suppresses a decrease in readout speed or complexity of signal processing in a photoelectric conversion device that can suitably perform analog or digital operations.

Means for Solving the Problems

[0006] One aspect of the present invention is a photoelectric conversion device comprising a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, wherein at least some of the pixels included in the pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens, the first pixel and the second pixel are arranged along a first direction in a plan view as seen from the top surface of the pixel array, and the first pixel is located in the first direction from the second pixel The pixels are positioned apart in the positive direction, the first and third pixels are arranged along the second direction, the first and third pixels are connected to a first signal line, the second pixel is connected to a second signal line, the first signal line is connected to a first signal processing circuit, the second signal line is connected to a second signal processing circuit, the first and second signal processing circuits are arranged along the first direction, and the first signal processing circuit is positioned apart from the second signal processing circuit in a direction having a negative component in the first direction.

[0007] Another aspect of the present invention is a photoelectric conversion device comprising a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each comprising a photoelectric conversion unit, wherein at least some of the pixels included in the pixel array are provided with a plurality of photoelectric conversion units for a single microlens, the first pixel and the second pixel are arranged along a first direction in a plan view as seen from the top surface of the pixel array, the first pixel is located away from the second pixel in the positive direction of the first direction, the first pixel and the third pixel are arranged along a second direction, the first pixel and the third pixel are connected to a first signal line, the second pixel is connected to a second signal line, the first signal line is connected to a first signal processing circuit, the second signal line is connected to a second signal processing circuit, the first signal processing circuit and the second signal processing circuit are arranged along the first direction, and the first signal processing circuit is located away from the second signal processing circuit in a direction having a component in the negative direction of the first direction.

[0008] A further aspect of the present invention is a semiconductor substrate laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, wherein at least some of the pixels included in the pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens, the first pixel and the second pixel are arranged along a first direction in a plan view as seen from the top surface of the pixel array, and the first pixel is positioned in front of the second pixel. The first and third pixels are positioned apart in the positive direction of the first direction, the first and third pixels are arranged along the second direction, the first and third pixels are connected to a first signal line, the second pixel is connected to a second signal line, the first signal line is connected to a first signal processing circuit, the second signal line is connected to a second signal processing circuit, the first and second signal processing circuits are arranged along the first direction, and the first signal processing circuit is positioned apart from the second signal processing circuit in a direction having a component in the negative direction of the first direction.

[0009] A further aspect of the present invention is a semiconductor substrate laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, wherein at least some of the pixels included in the pixel array have a plurality of photoelectric conversion units for one microlens, the first pixel and the second pixel are arranged along a first direction in a plan view as seen from the top surface of the pixel array, the first pixel is located away from the second pixel in the positive direction of the first direction, the first pixel and the third pixel are arranged along a second direction, the first pixel and the third pixel are connected to a first signal line, the second pixel is connected to a second signal line, the first signal line is connected to a first signal processing circuit, the second signal line is connected to a second signal processing circuit, the first signal processing circuit and the second signal processing circuit are arranged along the first direction, and the first signal processing circuit is located away from the second signal processing circuit in the negative direction of the first direction.

[0010] A further aspect of the present invention is a semiconductor substrate laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, wherein at least some of the pixels included in the pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens, and the semiconductor substrate has a first signal processing circuit and a second signal processing circuit, a connection part connected to the first signal processing circuit via a first signal line to the first pixel, a connection part connected to the second signal processing circuit via a second signal line to the second pixel, and an intersection part of the first signal line and the second signal line.

[0011] A further aspect of the present invention is a semiconductor substrate stacked on a semiconductor substrate having a pixel array in which a plurality of pixels including a first pixel and a second pixel are arranged, wherein at least some of the pixels included in the pixel array have a plurality of photoelectric conversion units for one microlens and have a first signal processing circuit and a second signal processing circuit, and the first pixel has a connection portion connected to the first signal processing circuit via a first signal line, the second pixel has a connection portion connected to the second signal processing circuit via a second signal line, and the intersection portion of the first signal line and the second signal line is also included.

[0012] A further aspect of the present invention is a semiconductor substrate laminated on a semiconductor substrate comprising a pixel array having a plurality of pixels including a first pixel, and a first signal line connected to the first pixel, wherein the semiconductor substrate has a first signal processing circuit and a second signal line, and the first pixel has a connection portion connected to the first signal processing circuit via the first signal line and the second signal line, and the first signal line and the second signal line intersect in a plan view of the pixel array viewed from above. [Effects of the Invention]

[0013] According to the present invention, in a photoelectric converter that can read out pixel signals using two signal processing circuits and suitably perform analog or digital calculations, it is possible to suppress a decrease in readout speed or complexity of signal processing.

Brief Description of the Drawings

[0014] [Figure 1] It is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 2] It is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 3] It is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 4] It is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 5] It is a schematic diagram of a photoelectric conversion device according to the second embodiment. [Figure 6] It is an equivalent circuit diagram of a pixel of a photoelectric conversion device according to the third embodiment. [Figure 7A] It is a schematic cross-sectional view of a photoelectric conversion device according to the third embodiment. [Figure 7B] It is a schematic cross-sectional view of a photoelectric conversion device according to the third embodiment. [Figure 7C] It is a schematic cross-sectional view of a photoelectric conversion device according to the third embodiment. [Figure 8] It is a schematic diagram of a pixel of a photoelectric conversion device according to the third embodiment. [Figure 9] It is a diagram showing the configuration of a photoelectric conversion system according to the fourth embodiment. [Figure 10A] It is a diagram showing the configuration and operation of a moving body according to the fifth embodiment. [Figure 10B] It is a diagram showing the configuration and operation of a moving body according to the fifth embodiment.

Modes for Carrying Out the Invention

[0015] Hereinafter, each embodiment will be described with reference to the drawings.

[0016] In each of the embodiments described below, as an example of a photoelectric conversion device, an imaging device will be mainly described. However, each embodiment is not limited to an imaging device and can also be applied to other examples of photoelectric conversion devices. For example, there are ranging devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light), and the like.

[0017] (First Embodiment) FIGS. 1, 2, and 3 are schematic views of a photoelectric conversion device according to the first embodiment.

[0018] The photoelectric conversion device shown in FIG. 1 includes pixels 10, a pixel array 20, vertical lines 30, 31, current sources 40, 41, ramp signal generation circuits 50, 51, comparators 60, 61. Further, it has a first memory 70, 71, a second memory 80, 81, counters 90, 91.

[0019] A plurality of pixels 10 are arranged in an array over a plurality of rows and columns in the pixel array 20.

[0020] In each column of the pixel array 20, vertical lines are arranged extending in the column direction (vertical direction in FIG. 1). The vertical lines are respectively connected to the pixels 10 arranged in the column direction and form a common signal line for these pixels 10.

[0021] The number of pixels 10 constituting the pixel array 20 is not particularly limited. For example, the pixel array 20 may be constituted by thousands of rows × thousands of columns of pixels 10 like a general digital camera, or may be constituted by a plurality of pixels 10 arranged in a single row.

[0022] The pixel signals read from the pixels 10 are input to the signal processing circuit via the vertical lines. The signal processing circuit includes a comparator that compares the pixel signals read from the pixels 10 with the reference signals output from the ramp signal generation circuits, a memory for holding signals, and the like. The pixel signals are sequentially output column by column via the signal processing circuit.

[0023] (Pixel composition) The configuration of the pixel 10 according to this embodiment will be described below.

[0024] Figure 2 shows an example of an equivalent circuit for pixel 10. Each of the pixels 10 has a photodiode 400, a transfer transistor 410, a floating diffusion 420, a source follower transistor 430, a selection transistor 440, a GND node 450, a reset transistor 455, and a power node 460.

[0025] Photodiode 400 is grounded at GND node 450. Photodiode 400 is connected to transfer transistor 410. A control signal is input to the gate of transfer transistor 410 from control signal line TX. Transfer transistor 410 has a common node with the gates of reset transistor 455 and source follower transistor 430, and this common node becomes floating diffusion 420. Both reset transistor 455 and source follower transistor 430 are connected to power node 460. A reset signal is input to the gate of reset transistor 455 from reset signal line RES. Source follower transistor 430 is connected to select transistor 440, and a select signal is input to the gate of select transistor 440 from select signal line SEL. Select transistor 440 is connected to vertical line 30.

[0026] (Function of each element) The functions of each element of the photoelectric conversion device according to this embodiment will be described.

[0027] The photodiode 400 converts incident light into photoelectric energy, generating an electric charge.

[0028] The charge photoelectrically converted by the photodiode 400 is transferred to the floating diffusion 420 via the transfer transistor 410, and converted into a signal voltage by the parasitic capacitance associated with the floating diffusion 420. This signal voltage is input to the gate of the source follower transistor 430 and output to the vertical line 30 via the selection transistor 440. The source follower transistor 430, together with the current source 40 in Figure 1, constitutes a source follower, and the signal voltage on the floating diffusion 420 is output to the vertical line 30 via the source follower.

[0029] The comparator 60 compares the signal of the vertical line 30 with the ramp signal output from the ramp signal generation circuit 50. At the timing when the comparator 60 changes, the first memory 70 receives the count signal from the counter 90. As a result, the signal of the pixel 10 is converted using AD conversion. The digital signal held in the first memory 70 is transferred to the second memory 80 and then output outside the chip. In this embodiment, an example using common counters 90 and 91 across multiple circuits is shown, but it is also common to supply a common count clock to each signal processing circuit and to provide a counter for each circuit corresponding to each vertical line. The present invention can also be applied in such a configuration.

[0030] (Element arrangement of the photoelectric converter according to this embodiment) Figure 3 is a schematic diagram showing an example of the element arrangement of the photoelectric conversion device according to this embodiment.

[0031] Figure 3 shows a photoelectric conversion device with a stacked structure having a pixel substrate 100 (first semiconductor substrate) and a circuit board 110 (second semiconductor substrate).

[0032] In this photoelectric converter, the pixel array 20 is arranged on the pixel substrate 100. Vertical lines 120-126 are signal lines (first signal lines) corresponding to the odd-numbered rows of the pixel array, and vertical lines 140-146 are signal lines (second signal lines) corresponding to the even-numbered rows of the pixel array. Hereafter, vertical lines 120-126 will be referred to as vertical line group 1, and vertical lines 140-146 as vertical line group 2.

[0033] The circuit board 110 has two signal processing circuits 200 and 210, which read out the signals of the pixels 10 included in the pixel array 20. The signal processing circuits 200 and 210 each have unit circuits 220 to 226 that read out the signals of vertical line group 1 and unit circuits 240 to 246 that read out the signals of vertical line group 2. Hereafter, unit circuits 220 to 226 will be referred to as signal processing circuit 1 (first signal processing circuit), and unit circuits 240 to 246 will be referred to as signal processing circuit 2 (second signal processing circuit).

[0034] Signal processing circuit 1 includes, for example, a current source 40, a first comparator 60, a first memory 70, and a second memory 80 as shown in Figure 1. Signal processing circuit 2 includes, for example, a current source 41, a second comparator 61, a first memory 71, and a second memory 81 as shown in Figure 1.

[0035] In the comparative example shown in Figure 3, the order in which the vertical lines on the pixel substrate 100 are arranged is different from the order in which the corresponding unit circuits are arranged on the circuit substrate 110.

[0036] (Comparative example of element arrangement) Figure 4 shows a comparative example of the element arrangement of a photoelectric converter.

[0037] Figures 3 and 4 show different wiring relationships between vertical line group 1 (vertical lines 120-126) and vertical line group 2 (vertical lines 140-146) and signal processing circuit 1 (unit circuits 220-226) and signal processing circuit 2 (unit circuits 240-246).

[0038] In the comparative example shown in Figure 4, the order in which the vertical lines are arranged on the pixel substrate 100 matches the order in which the unit circuits corresponding to the vertical lines are arranged on the circuit substrate 110.

[0039] Incidentally, in a typical photoelectric converter, the pixel signals read from vertical line group 1 and the pixel signals read from vertical line group 2 correspond to different colors. For example, the signal for a red pixel is read from vertical line group 1, while the signal for a green pixel is read from vertical line group 2. Each pixel is associated with a color by having a color filter that corresponds to a specific wavelength range of visible light, such as red, green, or blue, for each pixel. For example, the first pixel is provided with a first color filter corresponding to the first color, and the second pixel is provided with a second color filter corresponding to a second color that is different from the first color. Also, when adding the signals of pixels arranged horizontally, the pixels to be added may be shifted horizontally for red and green.

[0040] For example, consider the case where signals based on the charge generated by pixels in three horizontally aligned rows in Figure 4 are added together. Assume that the signals from unit circuits 220-222, which are part of signal processing circuit 1 that read signals from vertical lines 120-122 (vertical line group 1), are to be added together. At this time, the signals from unit circuits 241-243, which are part of signal processing circuit 1 that read signals from vertical lines 141-143 (vertical line group 2), are to be added together. In this case, the signal from vertical line 140 (vertical line group 2) is not to be added together.

[0041] As shown in Figure 4, when vertical line group 1 (vertical lines 120-126) is connected sequentially to signal processing circuit 1 (unit circuits 220-226), and vertical line group 2 (vertical lines 140-146) is connected to signal processing circuit 2 (unit circuits 240-246), the following problems arise.

[0042] In Figure 4, the unit circuits 241-243 of signal processing circuit 2, which processes the signals of vertical lines 141-143 of vertical line group 2 that are to be added, are distributed across two signal processing circuits 200 and 210. The same applies to the unit circuits 223-225 of signal processing circuit 1, which processes the signals of vertical lines 123-125 of vertical line group 1. In this case, when adding digital signals between the unit circuits, it becomes necessary to exchange signals between the two signal processing circuits 200 and 210, making the signal processing complicated. Furthermore, if, for example, a lateral wiring is provided to connect the unit circuits 241-243 of signal processing circuit 2 in order to add analog signals before AD conversion, the length of the wiring becomes long, and the processing speed decreases due to parasitic capacitance.

[0043] In Figure 3, the connections between vertical line group 1 (vertical lines 120-126) and signal processing circuit 1 (unit circuits 220-226) intersect with the connections between vertical line group 2 (vertical lines 140-146) and signal processing circuit 2 (unit circuits 240-246). In other words, in a plan view from the top of the pixel array, if, for example, the vertical lines included in vertical line group 1 are to the right of the vertical lines included in vertical line group 2, then the unit circuits included in signal processing circuit 1 are to the left of the unit circuits included in signal processing circuit 2. As a result, the unit circuits 241-243 of signal processing circuit 2, which process the signals of vertical lines 141-143 of vertical line group 2 that are to be added, are not distributed across two signal processing circuits 200 and 210. The same applies to the unit circuits 223-225 of signal processing circuit 1 that process the signals of vertical lines 123-125 of vertical line group 1 that are to be added when, for example, three rows of pixels are added horizontally.

[0044] In other words, the photoelectric converter according to this embodiment includes a pixel array in which a plurality of pixels are arranged, including a first pixel, a second pixel, and a third pixel. The first and second pixels are arranged along a first direction (along the rows) in a plan view from the top surface of the pixel array, and the first pixel is located away from the second pixel in the positive direction of the first direction. The first and third pixels are arranged along a second direction (along the columns), and the first and third pixels are connected to a first signal line, and the second pixel is connected to a second signal line. The first signal line is connected to a first signal processing circuit, and the second signal line is connected to a second signal processing circuit, and the first and second signal processing circuits are arranged along the first direction. The first signal processing circuit is located away from the second signal processing circuit in a direction having a negative component in the first direction.

[0045] To put it another way, the photoelectric converter according to this embodiment includes a pixel array in which a plurality of pixels are arranged, including a first pixel and a second pixel. The first pixel is connected to a first signal processing circuit via a first signal line, and the second pixel is connected to a second signal processing circuit via a second signal line. In a plan view of the pixel array from above, there is a portion where a third signal line, from the first signal line to the first signal processing circuit, intersects with the second signal line, and a fourth signal line, from the second signal line to the second signal processing circuit, intersects with the first signal line.

[0046] This configuration makes it possible to suppress a decrease in readout speed or complexity of signal processing when performing analog or digital horizontal summation in a solid-state imaging device that reads out pixel signals using two signal processing circuits, as demonstrated in this embodiment.

[0047] In Figures 3 and 4, the connections are schematically represented to clearly show the difference between the vertical lines and the unit circuits. Although not explicitly shown in Figures 3 and 4, known techniques such as TSV (through-silicon via) electrodes that penetrate between substrates and hybrid bonding are used at the connection points where signals are connected between substrates. For example, when the latter is used, the bonding surface will have a joint between the insulator of the pixel substrate 100 and the insulator of the circuit board 110, and a joint between the metal of the pixel substrate 100 and the metal of the circuit board 110.

[0048] Furthermore, although this embodiment describes a stacked configuration as an example, the structure of the photoelectric conversion device is not limited to this. The present invention can also be applied to a single-substrate photoelectric conversion device.

[0049] In the photoelectric converter shown in Figure 3, no signal processing circuits are located near the junction between signal processing circuits 200 and 210. However, vertical scanning circuits may be placed, for example, to drive the signal processing circuits located in each of the signal processing circuits 200 and 210.

[0050] The above description uses the analog summation of pixel signals as an example, but the arithmetic processing performed by the photoelectric converter according to this embodiment is not limited to summation. For example, it can be applied to any arithmetic processing performed on pixel signals read from vertical lines, such as edge detection by differential processing, calculations between AF signals, and correction processing using adjacent pixels. The same applies to the following embodiments.

[0051] (Second Embodiment) Figure 5 shows a schematic diagram of the photoelectric converter according to the second embodiment. Below, explanations common to the first embodiment will be omitted, and only the differences from Figure 3 will be described.

[0052] In the photoelectric converter shown in Figure 5, unlike in Figure 3, signal processing circuit 1 and signal processing circuit 2 are not arranged adjacent to each other in a mixed manner. Signal processing circuit 1 and signal processing circuit 2 are arranged to be separated from each other. This reduces parasitic capacitance between vertical lines 120-126 (vertical line group 1) and vertical lines 140-146 (vertical line group 2), thereby suppressing color mixing.

[0053] In Figure 5, joints 320-326 are substrate-to-substrate joints between vertical lines 120-126 of vertical line group 1 and unit circuits 220-226 of signal processing circuit 1. Joints 340-346 are substrate-to-substrate joints between vertical lines 140-146 of vertical line group 2 and unit circuits 240-246 of signal processing circuit 2. The connections 420-426 between vertical line group 1 (vertical lines 120-126) and signal processing circuit 1 (unit circuits 220-226), and the connections 440-446 between vertical line group 2 (vertical lines 140-146) and signal processing circuit 2 (unit circuits 240-246) have directional components that are opposite to each other. That is, when the connection direction is decomposed into x and y components, one connection points in the positive direction of the x component, and the other connection points in the negative direction. In other words, the positions on the substrate where the junctions 320-326 between the vertical line group 1 and the signal processing circuit 1 are located, and the positions on the substrate where the junctions 340-346 between the vertical line group 2 and the signal processing circuit 2 are located, are separated so as to be away from each other in the direction of the vertical line wiring. Alternatively, it can be said that the junctions 340-346 are arranged in a direction perpendicular to the direction in which the junctions 320-326 are aligned. Therefore, in a plan view of the pixel substrate from above, there is a portion where the third signal lines, the connections 420-426, which are connected to the first signal line, the vertical line group 1, on the pixel substrate intersect with the second signal line, the vertical line group 2.

[0054] This arrangement with intersections prevents, for example, when adding signals from three rows of pixels horizontally, the unit circuits 241-243 that process the signals of the vertical lines 141-143 to be added from spanning two signal processing circuits 200 and 210. The same applies to the unit circuits 223-225 that process the signals of the vertical lines 123-125 to be added.

[0055] Furthermore, when the positions on the substrate where the joints 320-326 are located and the positions on the substrate where the joints 340-346 are located are separated in the direction of the vertical wiring, both the signal processing circuit 1 and the signal processing circuit 2 are also arranged separately on the substrate, thereby suppressing color mixing.

[0056] To achieve this arrangement of joints, dummy circuits 227 and 247 are placed as needed to shift the position of the joints.

[0057] Therefore, in this embodiment, in a solid-state imaging device that reads out pixel signals using two signal processing circuits, it is possible to suppress a decrease in readout speed or complexity of signal processing when performing analog or digital horizontal summation.

[0058] Furthermore, in this embodiment, the connections 420-460 between vertical lines 120-126 and unit circuits 220-226, and the connections 440-446 between vertical lines 140-146 and unit circuits 240-246, are designed so as not to intersect. This makes it possible to suppress, for example, crosstalk between vertical lines 140-146 and vertical lines 140-146 via parasitic capacitance.

[0059] Furthermore, since the unit circuits 220-226 of signal processing circuit 1 and the unit circuits 240-246 of signal processing circuit 2 are arranged separately, the comparators 60 included in unit circuits 220-226 and the comparators 60 included in unit circuits 240-246 are also arranged separately. This makes it possible to suppress the occurrence of color mixing due to interference when the output of comparator 60 changes.

[0060] (Third embodiment) Figures 6 to 8 show schematic diagrams of the photoelectric converter according to the third embodiment. Hereafter, explanations common to the first and second embodiments will be omitted. This embodiment differs from the first and second embodiments in that each pixel 10 has multiple photoelectric converters and is configured to perform phase-difference detection type focus detection. Aside from this point and the matters described below, the explanations are substantially the same as those of the other embodiments and will therefore be omitted.

[0061] Figure 6 is a circuit diagram showing an example of the circuit for a 2x1 pixel 10 in a pixel array 20.

[0062] Pixel 10 includes photodiodes 400-1 and 400-2, which are photoelectric conversion units, transfer transistors 410-1 and 410-2, a charge conversion unit C1, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. Transfer transistor 410-1 is located in the electrical path between the node to which the charge conversion unit C1, reset transistor 455, and amplification transistor 430 are connected, and photodiode 400-1. Transfer transistor 410-2 is located in the electrical path between the node to which the charge conversion unit C1, reset transistor 455, and amplification transistor 430 are connected, and photodiode 400-2. The charge conversion unit C1 is also called the floating diffusion unit (FD unit). The reset transistor 455 and the amplification transistor 430 are supplied with a power supply voltage VDD. The selection transistor 440 is located in the electrical path between the amplification transistor 430 and the vertical output line 30. The amplification transistor 430 can be said to be electrically connected to the vertical output line 30 via the selection transistor 440. The charge conversion unit C1 includes a stray diffusion capacitance provided in the semiconductor substrate and parasitic capacitance in the electrical path from the transfer transistor 440 to the amplification transistor 430 via the stray diffusion capacitance. Signals RES, Tx_A, and SEL are signals supplied from a vertical scanning circuit (not shown).

[0063] As shown in Figure 7A, photodiodes 400-1 and 400-2 are positioned corresponding to one microlens ML. In other words, photodiodes 400-1 and 400-2 are positioned to receive light transmitted through one microlens ML. This enables focus detection using a phase difference detection method.

[0064] Furthermore, another photodiode may be placed between photodiodes 400-1 and 400-2 in Figure 7A. This is an example of a configuration in which three or more photodiodes are arranged corresponding to one microlens. By individually reading the signals from the photodiode placed between photodiodes 400-1 and 400-2, further functionality can be achieved. For example, by providing a photodiode with a smaller area than photodiodes 400-1 and 400-2, it is possible to reduce sensitivity and obtain an image with increased gradation for high-luminance signals. In addition, the signal from the photodiode placed between photodiodes 400-1 and 400-2 can be read at a different timing than when the signals from photodiodes 400-1 and 400-2 are read. This makes it possible to generate images with increased temporal resolution.

[0065] Note that the pixel configuration in this embodiment is not limited to the configurations shown in Figures 6 and 7A. A single microlens ML may include three or more photoelectric conversion units. For example, Figures 7B and 7C show a configuration in which four photoelectric conversion units, specifically four photodiodes 400-1 to 400-4, are provided as four photoelectric conversion units, which is an example of a configuration with three or more photoelectric conversion units for a single microlens ML. A transfer transistor is provided corresponding to each of the photodiodes 400-1 to 400-4, and gates 4101 to 410-4 are the gate electrodes of the corresponding transfer transistors. In Figure 7B, gates G1 and G3 transfer charge to the pixel readout circuit R1. Gates 410-2 and 410-4 transfer charge to the pixel readout circuit R2. Capacitive elements C1, as shown in Figure 15, are provided in each of the pixel readout circuits R1 and R2. The reset transistor 455, the amplification transistor 430, and the selection transistor 440 shown in Figure 15 may be provided in each of the pixel readout circuits R1 and R2, or they may be provided in either the pixel readout circuit R1 or R2.

[0066] Figure 7C shows a configuration in which gates 410-1 to 410-4 are arranged to transfer charge to a single capacitive element C1. This embodiment can also be suitably implemented in this configuration.

[0067] Furthermore, a configuration was described in which light is incident on both photodiodes 400-1 and 400-2, which are provided in correspondence with a single microlens ML. As another example, one of the photodiodes 400-1 and 400-2 may be shielded from light, and light may be incident on the other. In this case, for some pixels 10, light is incident on one of the photodiodes 400-1 and 400-2, and for other some pixels 10, light is incident on the other of the photodiodes 400-1 and 400-2. Even with this configuration, focus detection using a phase difference detection method can be performed by reading the signals from some pixels 10 and other some pixels 10. The read signals are used for focus detection by a detection unit provided on a circuit board, for example.

[0068] Note that all pixels 10 arranged in the pixel array may have the configuration shown in Figure 6, but other examples are also possible. At least some of the pixels 10 may have the configuration shown in Figure 6, and some other pixels may have the configuration shown in Figure 2. Even in such a case, focus detection can be performed using the signals of the pixels having the configuration shown in Figure 6.

[0069] Furthermore, an example of the bonding configuration of the pixel substrate 100 and the circuit board 110 in this embodiment is shown in Figure 8.

[0070] A first layer CFL is provided between the microlens ML and the pixel substrate 100. The first layer CFL is provided with an anti-reflective coating, a color filter, etc. The first structural layer CFL may also include a stationary charge film disposed on the first surface (incident surface) of the pixel substrate 100.

[0071] Photodiodes 400-1 and 400-2 are provided on the pixel substrate 100. Transfer transistor gates 410-1 and 410-2 are arranged on the second surface of the pixel substrate 100. The gates of other transistors are also arranged on the second surface of the pixel substrate 100 (not shown).

[0072] A second structural layer L1 and a third structural layer L2 are arranged between the pixel substrate 100 and the circuit board 110. The second structural layer L1 has multiple wiring layers and multiple interlayer insulating films. The multiple wiring layers are shown as wiring layers M1 and M2. The second structural layer L1 also has a first conductive portion MB11. The first conductive portion MB11 is connected to the wiring layer M2 by multiple interlayer connection portions TH1 and TH2.

[0073] The third structural layer L2 also comprises multiple wiring layers and multiple interlayer insulating films. One of the multiple wiring layers is shown as a wiring layer M21. The third structural layer L2 also has a second conductive part MB21. Electrical conductivity is achieved by the contact between the first conductive part MB11 and the second conductive part MB21. A joint BD1 is formed by the first conductive part MB11 and the second conductive part MB21. A first insulating film is formed on the surface on which the conductive part MB11 is provided. A second insulating film is formed on the surface on which the conductive part MB21 is provided. The insulating film provided on the surface on which the conductive part MB11 is provided and the insulating film provided on the surface on which the conductive part MB21 is provided are joined to each other. In other words, at the joint surface between the second structural layer L1 and the third structural layer L2, there is a joint between the conductive part MB11 and the conductive part MB21, and a joint between the insulating film contained in the second structural layer L1 and the insulating film contained in the third structural layer L2. The insulating film contained in the second structural layer L1 and the insulating film contained in the third structural layer L2 are films containing silicon and oxygen. The second conductive part MB21 is connected to the wiring layer M21 by a plurality of interlayer connectors TH3 and TH4. The interlayer connectors TH1, TH2, TH3, and TH4 can be made of a conductive material, such as tungsten. The wiring layers M1, M2, and M21 can also be made of a conductive material, such as copper or aluminum. The first conductive part MB11 and the second conductive part MB21 that form the joint BD1 can also be made of a conductive material, such as copper.

[0074] The circuit board 110 is provided with a well area (WEL). The gate SG of each transistor is located between the circuit board 110 and the wiring layer.

[0075] Figure 8 shows several junction structures ST1 to ST4. Structure ST1, which includes the aforementioned junction BD1, is a structure in which one electrical node is formed by one first conductive part and one second conductive part. Structures ST2 to ST4 are structures in which one electrical node is formed by multiple junctions.

[0076] In structure ST2, one wire included in the second structural layer L1 is connected to multiple joints BD2 and BD3. On the other hand, one wire included in the third structural layer L2 is connected to joint BD2, and another wire is connected to joint BD3.

[0077] In structure ST3, one wire included in the second structural layer L1 is connected to joint BD4, and another wire is connected to joint BD5. Meanwhile, one wire included in the third structural layer L2 is connected to joints BD4 and BD5.

[0078] In structure ST4, one wiring included in the second structural layer L1 is connected to joints BD6 and BD7. On the other hand, one wiring included in the third structural layer L2 is connected to joints BD6 and BD7.

[0079] These structures ST1 to ST4 can be used interchangeably depending on the location of the photoelectric converter and the signal (voltage) to be transmitted.

[0080] For example, in a path that transmits power supply voltage, one of structures ST2 to ST4 is selected to reduce the resistance of the transmission path. On the other hand, in a path that transmits signals row by row or column by column of unit pixels 101, structure ST1 is selected because it is constrained by the row pitch or column pitch.

[0081] By using structures ST2 to ST4 for the joints, redundancy can be provided to the joints. Even if a joint failure occurs in the first joint among the multiple joints included in each of structures ST2 to ST4 due to substrate warping or the like, electrical conductivity can be maintained by the second joint.

[0082] Furthermore, the joints BD1-7 and the connected wiring also act as heat dissipation paths. Therefore, by providing longer wiring in areas where heat generation is high, heat can be effectively dissipated. Multiple interlayer connections TH1-TH4 are connected to each of the first conductive part MB11 and the second conductive part MB21. This has the effect of making it easier to dissipate heat compared to the case where each of the first conductive part MB11 and the second conductive part MB21 has only one interlayer connection.

[0083] In the configurations shown in Figures 7A to 7C, multiple photodiodes 400-1 and 400-2 are provided for one microlens. However, as shown in Figure 2, a single photodiode 400 may be provided for one microlens. By shielding a portion of this single photodiode, a phase-difference detection method for focus detection can be generated. In this case, light is incident only on a portion of the photodiode 400 for some pixels 10, and on the other portion of the photodiode 400 for other pixels 10. In other words, the position of the light-shielding film is made different for some pixels 10 and other pixels 10 so that the light incidence position of the photodiode is different. Even with this configuration, phase-difference detection method for focus detection can be performed by reading the signals from some pixels 10 and other pixels 10. In such a configuration, pixels 10 used for imaging rather than focus detection can be configured without a light-shielding film that shields a portion of the photodiode 400. In other words, the photodiode of pixel 10 that outputs the focus detection signal has a larger light-shielding area due to the light-shielding film than the photodiode of pixel 10 used for imaging. The signal read from this focus detection pixel is used for focus detection by a detection unit provided on the circuit board, for example. The matters described in this embodiment, including the configuration in Figures 6 and 7A to 7C, can be implemented in combination with other embodiments.

[0084] In this embodiment, the calculation processing performed by the photoelectric converter may, for example, only target pixel signals output from pixels other than those used for focus detection.

[0085] (Fourth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Figure 9. Figure 9 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0086] The photoelectric conversion device described in the first or second embodiment above is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 9 shows a block diagram of a digital still camera as an example of these.

[0087] The photoelectric conversion system illustrated in Figure 9 includes an imaging device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject onto the imaging device 1004. Furthermore, it includes an aperture 1003 for varying the amount of light passing through the lens 1002, and a barrier 1001 for protecting the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light onto the imaging device 1004. The imaging device 1004 is a photoelectric conversion device of any of the above embodiments, which converts the optical image formed by the lens 1002 into an electrical signal.

[0088] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing the output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as needed and outputs the image data. The signal processing unit 1007 may be formed on the semiconductor substrate on which the imaging device 1004 is mounted, or it may be formed on a semiconductor substrate separate from the imaging device 1004.

[0089] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system includes a recording medium 1012 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0090] Furthermore, the photoelectric conversion system includes an overall control / calculation unit 1009 that controls various calculations and the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the imaging device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system only needs to have at least the imaging device 1004 and the signal processing unit 1007 that processes the output signals output from the imaging device 1004.

[0091] The imaging device 1004 outputs an imaging signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The photoelectric conversion system uses this image data to generate an image.

[0092] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying a photoelectric conversion device (imaging device) of any of the above embodiments.

[0093] (Fifth embodiment) The photoelectric conversion system and mobile unit of this embodiment will be described using Figures 10A and 10B. Figures 10A and 10B show the configuration of the photoelectric conversion system and mobile unit of this embodiment.

[0094] Figure 10A shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is a photoelectric conversion device (imaging device) as described in any of the embodiments above. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0095] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 360 ​​and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control unit that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to a warning device 370 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 370 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0096] In this embodiment, the photoelectric conversion system 300 images the area around the vehicle, for example, the front or rear. Figure 10B shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 360 ​​sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0097] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0098] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0099] For example, examples in which some configurations of one embodiment are added to other embodiments, or in which some configurations of other embodiments are replaced, are also included as embodiments of the present invention.

[0100] Furthermore, the photoelectric conversion systems shown in the fourth and fifth embodiments above are merely examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 9, 10A, and 10B.

[0101] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0102] The present invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are attached to make the scope of the invention public. [Explanation of symbols]

[0103] 10 pixels 30 Vertical lines 31 Vertical lines 60 Comparators 61 Comparator

Claims

1. It comprises a pixel array including a first pixel, a second pixel, and a third pixel, each of which has multiple pixels including a photoelectric conversion unit, At least some of the pixels included in the aforementioned pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens. The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to the first signal line, The second pixel is connected to the second signal line, The third pixel is connected to the fifth signal line, The first signal line is connected to the first signal processing circuit. The second signal line is connected to the second signal processing circuit. The fifth signal line is connected to the third signal processing circuit. The first signal processing circuit, the second signal processing circuit, and the third signal processing circuit are arranged along the first direction, and the first signal processing circuit is located between the second signal processing circuit and the third signal processing circuit. A photoelectric converter characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

2. The aforementioned pixel array includes pixels that output signals used for imaging, The photoelectric conversion device according to claim 1, characterized in that the photoelectric conversion unit of a pixel that outputs a signal used for focus detection has a larger light-shielded area than the photoelectric conversion unit of a pixel that outputs a signal used for imaging.

3. The system comprises a pixel array in which multiple pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each of which is equipped with a photoelectric conversion unit. At least some of the pixels included in the aforementioned pixel array are equipped with multiple photoelectric conversion units for a single microlens, The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to the first signal line, The second pixel is connected to the second signal line, The third pixel is connected to the fifth signal line, The first signal line is connected to the first signal processing circuit. The second signal line is connected to the second signal processing circuit. The fifth signal line is connected to the third signal processing circuit. The first signal processing circuit, the second signal processing circuit, and the third signal processing circuit are arranged along the first direction, and the first signal processing circuit is located between the second signal processing circuit and the third signal processing circuit. A photoelectric converter characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

4. The first signal processing circuit includes a first comparator, The second signal processing circuit includes a second comparator. The first comparator is located away from the second comparator in the negative direction of the first direction. The photoelectric conversion device according to any one of claims 1 to 3.

5. The device comprises a pixel array in which multiple pixels are arranged, each including a first pixel, a second pixel, and a third pixel, and each of these pixels includes a photoelectric conversion unit. At least some of the pixels included in the aforementioned pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens. The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to a first signal processing circuit via a first signal line. The second pixel is connected to the second signal processing circuit via a second signal line. The third pixel is connected to the third signal processing circuit via a fifth signal line. In a plan view of the pixel array as seen from above, the third signal line, which extends from the first signal line to the first signal processing circuit, has a portion where it intersects with the second signal line. A photoelectric converter characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

6. The device comprises a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each of which is equipped with a photoelectric conversion unit. At least some of the pixels included in the aforementioned pixel array are equipped with multiple photoelectric conversion units for a single microlens, The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to a first signal processing circuit via a first signal line. The second pixel is connected to the second signal processing circuit via a second signal line. The third pixel is connected to the third signal processing circuit via a fifth signal line. In a plan view of the pixel array as seen from above, the third signal line, which extends from the first signal line to the first signal processing circuit, has a portion where it intersects with the second signal line. A photoelectric converter characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

7. The photoelectric converter according to claim 5 or 6, characterized in that, in the plan view, the fourth signal line from the second signal line to the second signal processing circuit has a portion where it intersects with the first signal line.

8. The pixel array, the first signal line, and the second signal line are provided on the first semiconductor substrate. The first signal processing circuit and the second signal processing circuit are provided on the second semiconductor substrate. The first signal line and the first signal processing circuit are connected via a first junction. The second signal line and the second signal processing circuit are connected via a second junction. The photoelectric conversion device according to any one of claims 5 to 7, characterized in that the third signal line between the first junction and the first signal processing circuit intersects the second signal line in the plan view.

9. The pixel array, the first signal line, and the second signal line are provided on the first semiconductor substrate. The first signal processing circuit and the second signal processing circuit are provided on the second semiconductor substrate. The first signal line and the first signal processing circuit are connected via a first junction. The second signal line and the second signal processing circuit are connected via a second junction. The third signal line between the first junction and the first signal processing circuit intersects the second signal line in the plan view. The photoelectric conversion device according to any one of claims 5 to 7, characterized in that the fourth signal line between the second junction and the second signal processing circuit intersects the first signal line in the plan view.

10. When the direction in which the first pixel and the second pixel are aligned is defined as the positive direction of the first direction, The position in which the first joint is located, The photoelectric conversion device according to claim 8 or 9, characterized in that the position where the second joint is located includes a component in the negative direction of the first direction when viewed from one side to the other.

11. The direction in which the first signal processing circuit and the second signal processing circuit are aligned is, The photoelectric conversion device according to claim 10, characterized in that it includes a component in a second direction perpendicular to the first direction.

12. The photoelectric conversion device according to any one of claims 8 to 11, characterized in that each of the first and second joints is formed including an electrode that penetrates the first semiconductor substrate and the second semiconductor substrate.

13. The insulator of the first semiconductor substrate and the insulator of the second semiconductor substrate are joined at the joint surface. The photoelectric conversion device according to any one of claims 8 to 12, characterized in that each of the first joint and the second joint is formed by joining the metal of the first semiconductor substrate and the metal of the second semiconductor substrate at the joint surface.

14. The photoelectric conversion device according to any one of claims 8 to 13, characterized in that a detection unit that performs focus detection using signals output by the plurality of photoelectric conversion units is provided on the second semiconductor substrate.

15. The first semiconductor substrate and the second semiconductor substrate are provided with a plurality of structural layers, including a first structural layer and a second structural layer. The first structural layer is disposed between the first semiconductor substrate and the second structural layer, and the second structural layer is disposed between the first semiconductor substrate and the second semiconductor substrate. The photoelectric conversion device according to any one of claims 8 to 14, characterized in that it comprises a joint formed by joining a first conductive portion included in the first structural layer and a second conductive portion included in the second structural layer.

16. Multiple interlayer connecting portions made of conductive material are connected to the first conductive portion. The photoelectric conversion device according to claim 15, characterized in that a plurality of interlayer connection portions made of a conductive material are connected to the second conductive portion.

17. It further has another joint, The photoelectric conversion device according to claim 15 or 16, characterized in that the other joint and the joint are connected to one wiring included in the first structural layer.

18. It further has another joint, The photoelectric conversion device according to any one of claims 15 to 17, characterized in that the other joint and the joint are connected to one wiring included in the second structural layer.

19. The pixel array includes a fourth pixel, The fourth pixel, the first pixel, the second pixel, and the third pixel are arranged in the positive direction of the first direction along the first direction in a plan view as seen from the top surface of the pixel array. The fourth pixel is connected to the sixth signal line, The sixth signal line is connected to the fourth signal processing circuit. The first signal processing circuit, the second signal processing circuit, the third signal processing circuit, and the fourth signal processing circuit are arranged along the first direction, and the second signal processing circuit is located between the first signal processing circuit and the fourth signal processing circuit. The photoelectric converter according to any one of claims 1 to 18, characterized in that it performs an arithmetic operation to generate another signal using the signal read from the second signal line and the signal read from the sixth signal line.

20. The photoelectric converter according to any one of claims 1 to 19, characterized in that the calculation process is an addition process.

21. The photoelectric conversion device according to any one of claims 1 to 20, characterized in that the first color filter covering the first pixel and the second color filter covering the second pixel correspond to different colors, and the third color filter covering the third pixel and the first color filter correspond to the same color.

22. A photoelectric conversion device according to any one of claims 1 to 21, A photoelectric conversion system characterized by having a signal processing unit that generates an image using the signal output by the aforementioned photoelectric conversion device.

23. A mobile body comprising a photoelectric converter according to any one of claims 1 to 21, A mobile body characterized by having a control unit that controls the movement of the mobile body using a signal output by the photoelectric converter.

24. A semiconductor substrate to be laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, At least some of the pixels included in the aforementioned pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens. The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to the first signal line, The second pixel is connected to the second signal line, The third pixel is connected to the fifth signal line, The first signal line is connected to the first signal processing circuit. The second signal line is connected to the second signal processing circuit. The fifth signal line is connected to the third signal processing circuit. The first signal processing circuit, the second signal processing circuit, and the third signal processing circuit are arranged along the first direction, and the first signal processing circuit is located between the second signal processing circuit and the third signal processing circuit. A semiconductor substrate characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

25. A semiconductor substrate to be laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, At least some of the pixels included in the aforementioned pixel array are equipped with multiple photoelectric conversion units for a single microlens, The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. The first pixel is connected to the first signal line, The second pixel is connected to the second signal line, The third pixel is connected to the fifth signal line, The first signal line is connected to the first signal processing circuit. The second signal line is connected to the second signal processing circuit. The fifth signal line is connected to the third signal processing circuit. The first signal processing circuit, the second signal processing circuit, and the third signal processing circuit are arranged along the first direction, and the first signal processing circuit is located between the second signal processing circuit and the third signal processing circuit. A semiconductor substrate characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

26. A semiconductor substrate to be laminated on a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, each including a first pixel, a second pixel, and a third pixel, each including a photoelectric conversion unit, At least some of the pixels included in the aforementioned pixel array are pixels that output a signal used for focus detection by partially shielding a photoelectric conversion unit provided for one microlens. The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. It has a first signal processing circuit, a second signal processing circuit, and a third signal processing circuit. A connection part connected to the first pixel and the first signal processing circuit via a first signal line, A connection portion connected to the second pixel and the second signal processing circuit via the second signal line, A connection part connected to the third pixel and the third signal processing circuit via a fifth signal line, Having an intersection of the first signal line and the second signal line, A semiconductor substrate characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

27. A semiconductor substrate to be stacked on a semiconductor substrate having a pixel array in which a plurality of pixels including a first pixel, a second pixel, and a third pixel are arranged, At least some of the pixels included in the aforementioned pixel array are equipped with multiple photoelectric conversion units for a single microlens, The first pixel, the second pixel, and the third pixel are arranged in a plan view from the top surface of the pixel array, along the first direction in the positive direction of the first direction. It has a first signal processing circuit, a second signal processing circuit, and a third signal processing circuit. A connection portion connected to the first pixel via a first signal line to the first signal processing circuit, A connection portion connected to the second pixel via a second signal line to the second signal processing circuit, A connection portion connected to the third pixel via a fifth signal line to the third signal processing circuit, Having an intersection of the first signal line and the second signal line, A semiconductor substrate characterized by performing an arithmetic operation to generate another signal using the signal read from the first signal line and the signal read from the fifth signal line.

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