Liquid crystal display device

Abstract

To provide a liquid crystal display device enabling reduction of sampling noise which occurs in the liquid crystal display device when sampling analog ramp waveforms.SOLUTION: In a display unit 6, a pixel circuit 60 is provided which includes a liquid crystal pixel 62 at each intersection of a plurality of column data lines D1-Dx and a plurality of row scan lines G1-Gy. A horizontal scanning circuit 4 applies, to the column data lines D1-Dx, a grayscale drive voltage corresponding to the grayscale of each pixel constituting each horizontal line of video data VDATA which is displayed on the display unit 6. A vertical scanning circuit 5 sequentially applies a row selection signal to the row scan lines G1-Gy in order to apply a grayscale drive voltage to the pixel circuit 60 of each pixel constituting each horizontal line. A digital signal processing unit 3 alternately repeats fixed value addition and subtraction in the horizontal direction with respect to the grayscale of each pixel constituting each horizontal line of the video data VDATA, thereby generating corrected video data SDATA and supplying the generated corrected video data SDATA to the horizontal scanning circuit 4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a liquid crystal display device.

Background Art

[0002] Patent Document 1 describes a liquid crystal display device that compares pixel data of each horizontal line with a count value by a counter and drives each liquid crystal pixel with an analog voltage obtained by sampling an analog ramp waveform at the timing when both match.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In this type of liquid crystal display device, sampling noise may occur when sampling an analog ramp waveform. In particular, as in the case where all pixels of one horizontal line have the same gradation, the larger the number of horizontally consecutive pixels having the same gradation, the greater the sampling noise generated.

[0005] An object of the present invention is to provide a liquid crystal display device capable of reducing sampling noise generated when sampling an analog ramp waveform to generate an analog voltage for driving each liquid crystal pixel.

Means for Solving the Problems

[0006] The present invention provides a liquid crystal display device comprising: a display unit provided with pixel circuits including liquid crystal pixels at each intersection of a plurality of column data lines and a plurality of row scan lines; a horizontal scanning circuit that applies a gradation drive voltage corresponding to the gradation of each pixel constituting each horizontal line of video data displayed on the display unit to the plurality of column data lines; a vertical scanning circuit that sequentially applies row selection signals to the plurality of row scan lines in order to apply the gradation drive voltage to the pixel circuit of each pixel constituting each horizontal line; and a digital signal processing unit that generates corrected video data by alternately adding and subtracting a fixed value in the horizontal direction to the gradation of each pixel constituting each horizontal line of the video data, and supplies it to the horizontal scanning circuit. [Effects of the Invention]

[0007] According to the liquid crystal display device of the present invention, sampling noise generated when sampling an analog ramp waveform to generate an analog voltage for driving each liquid crystal pixel can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the configuration of a liquid crystal display device according to one embodiment. [Figure 2] This is a timing diagram illustrating the operation of a liquid crystal display device according to one embodiment. [Figure 3] This block diagram shows a specific configuration example of the analog signal generation circuit 2 in Figure 1. [Figure 4] This block diagram shows a specific configuration example of the digital signal processing unit 3 in Figure 1. [Figure 5A] This figure partially shows the grayscale of two frames of video data input to a liquid crystal display device according to one embodiment. [Figure 5B] This figure partially shows the gradation of two frames of corrected video data corrected by the digital signal processing unit 3 in Figure 1. [Figure 6A]This figure shows the sampling noise that occurs when a liquid crystal display device according to one embodiment displays the corrected video data shown in Figure 5B. [Figure 6B] This figure shows the sampling noise that occurs when a liquid crystal display device according to one embodiment displays the video data shown in Figure 5A. [Modes for carrying out the invention]

[0009] Hereinafter, a liquid crystal display device according to one embodiment will be described with reference to the attached drawings. As shown in Figure 1, the liquid crystal display device 100 according to one embodiment includes a timing generation circuit 1, an analog signal generation circuit 2, a digital signal processing unit 3, a horizontal scanning circuit 4, a vertical scanning circuit 5, and a display unit 6. The horizontal scanning circuit 4 includes a shift register 41, a latch circuit 42, comparator circuits 441 to 44x, and selection circuits 451 to 45x.

[0010] The horizontal scanning circuit 4 is connected to the column data lines D1 to Dx of the display unit 6. Any column data lines D1 to Dx will be referred to as column data lines D. The vertical scanning circuit 5 is connected to the row scanning lines G1 to Gy of the display unit 6. Any row scanning lines G1 to Gy will be referred to as row scanning lines G.

[0011] The display unit 6 has x pixel circuits 60 arranged in a matrix in the horizontal direction and y pixel circuits 60 in the vertical direction. For example, x is 1920 and y is 1080. The pixel circuits 60 are provided at each intersection of x column data lines D1 to Dx and y row scan lines G1 to Gy. The comparator circuits 441 to 44x and selection circuits 451 to 45x are provided in a manner corresponding to the number of pixel circuits 60, which is the horizontal number of pixels in the display unit 6.

[0012] The pixel circuit 60 includes a pixel selection transistor 61 and a liquid crystal pixel 62. The pixel selection transistor 61 is composed of, for example, a thin-film transistor. The gate terminal of the pixel selection transistor 61 is connected to the row scan line G, and the drain terminal is connected to the column data line D. The liquid crystal pixel 62 is connected to the source terminal of the pixel selection transistor 61.

[0013] In Figure 1, the timing generation circuit 1 receives the clock CLK, the horizontal synchronization signal Hsync shown in Figure 2(a), and the vertical synchronization signal Vsync (not shown). The horizontal synchronization signal Hsync and the vertical synchronization signal Vsync are the horizontal and vertical synchronization signals of the video data VDATA shown in Figure 2(b). The timing generation circuit 1 generates the counter clock CCLK shown in Figure 2(g) based on the clock CLK, and the counter reset signal CRST with a horizontal period shown in Figure 2(h), and supplies them to the counter circuit 43.

[0014] Furthermore, the timing generation circuit 1 generates the selector reset signal SELRST shown in Figure 2(j) and supplies it to the selection circuits 451 to 45x. The timing generation circuit 1 generates the clock ACLK based on the clock CLK and supplies it to the analog signal generation circuit 2. The timing generation circuit 1 generates a horizontal periodic signal HS similar to the horizontal synchronization signal Hsync, and a row selection signal VST that is high for one horizontal period at the timing of the topmost horizontal line of each frame, and supplies them to the vertical scanning circuit 5.

[0015] In addition to the clock ACLK, the analog signal generation circuit 2 receives the horizontal synchronization signal Hsync and the frame synchronization signal FS as inputs. As shown in Figure 3, the analog signal generation circuit 2 includes a ramp waveform counter circuit 21, an inverter 22, a switch 23, and a D / A converter 24.

[0016] The ramp waveform counter circuit 21 receives the clock ACLK and the horizontal synchronization signal Hsync as inputs. The ramp waveform counter circuit 21 counts the clock ACLK for each horizontal line and generates a count value that increases in the positive direction as it approaches the right end from the left end of each horizontal line, and supplies this count value to the terminal Ta of the switch 23 and the inverter 22.

[0017] The inverter 22 inverts the input count value, generates a count value that increases in the negative direction as it approaches the right end from the left end of each horizontal line, and supplies it to the terminal Tb of the switch 23. The frame synchronization signal FS is input to the switch 23, and the switch 23 switches between the state of connecting to the terminal Ta and the state of connecting to the terminal Tb for each frame.

[0018] In the frame connected to the terminal Ta, the D / A converter 24 D / A-converts a count value that increases in the positive direction, and outputs an analog signal VREF1 shown in (m) of FIG. 2, which is a ramp waveform in which the analog value gradually increases as it approaches the right end from the left end of each horizontal line. In the frame connected to the terminal Tb, the D / A converter 24 D / A-converts a count value that increases in the negative direction, and outputs an analog signal VREF2 shown in (o) of FIG. 2, which is a ramp waveform in which the analog value gradually decreases as it approaches the right end from the left end of each horizontal line.

[0019] As shown in (m) of FIG. 2, the analog signal VREF1 increases in the positive direction from the voltage V0 to the voltage V1 within each horizontal period. As shown in (o) of FIG. 2, the analog signal VREF2 increases in the negative direction from the voltage V0 to the voltage -V1 within each horizontal period. The analog signal generation circuit 2 supplies the analog signal VREF1 or VREF2 that switches for each frame to the selection circuits 451 to 45x. Switching between the analog signals VREF1 and VREF2 for each frame is to reduce the burn-in of the liquid crystal pixels 62.

[0020] In FIG. 1, the video data VDATA, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync of the video data VDATA, and the system clock SCLK shown in (d) of FIG. 2 are input to the digital signal processing unit 3. The digital signal processing unit 3 generates corrected video data SDATA as described later based on the input video data VDATA, and supplies it to the shift register 41 of the horizontal scanning circuit 4.

[0021] As shown in Figure 4, the digital signal processing unit 3 includes a horizontal counter 31, a vertical counter 32, a frame counter 33, XNOR gates 34 and 35, multipliers 36 and 37, a switch 38, and an adder 39.

[0022] The horizontal counter 31 receives the system clock SCLK and the horizontal synchronization signal Hsync. The horizontal counter 31 generates a count value that increases as it approaches the right end from the left end of each horizontal line, and outputs the least significant bit of the count value, the value HCNT[0]. The value HCNT[0] alternates between the values ​​of 0 and 1 on a pixel-by-pixel basis.

[0023] The vertical counter 32 receives the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. The vertical counter 32 generates a count value that increases as it approaches the bottom edge from the top edge within each frame, and outputs the value VCNT[0], which is the least significant bit of the count value. The value VCNT[0] alternates between the value 0 and the value 1 on a line-by-line basis.

[0024] The XNOR gate 34 inverts the exclusive OR of the input values ​​HCNT[0] and VCNT[0] to output a value HVCNT[0] in which the values ​​0 and 1 alternate on a pixel-by-pixel and line-by-line basis.

[0025] The frame counter 33 receives the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. The frame counter 33 generates a count value that increases in value as the frames progress and outputs the value FCNT[0], which is the least significant bit of the count value. The value FCNT[0] alternates between the value 0 and the value 1 on a frame-by-frame basis.

[0026] The XNOR gate 35 inverts the exclusive OR of the input values ​​HVCNT[0] and FCNT[0] to output a selected signal AS in which the values ​​0 and 1 alternate on a pixel-by-pixel, line-by-line, and frame-by-frame basis.

[0027] A fixed value is input to multipliers 36 and 37. The fixed value is, for example, 1. Multiplier 36 multiplies the input value 1 by +1 and supplies it to terminal Ta of switch 38. Multiplier 37 multiplies the input value 1 by -1 and supplies it to terminal Tb of switch 38. For example, switch 38 is connected to terminal Ta when the selection signal AS is value 0, and to terminal Tb when it is value 1. Switch 38 outputs a value of +1 or -1 that alternates on a pixel-by-pixel, line-by-line, and frame-by-frame basis.

[0028] The adder 39 adds the output of switch 38 to the video data VDATA and outputs the corrected video data SDATA shown in Figure 2(c). The pixel position within the frame of the video data VDATA is represented as (m,n). m is a value from 1 to x, and the values ​​are 1, 2, 3, 4, ..., x from the left end to the right end of each horizontal line. n is a value from 1 to y, and the values ​​are 1, 2, 3, 4, ..., y from the top end to the bottom end of each frame. The pixel positions within the frame of the video data VDATA are represented as (1,1), (2,1), ...

[0029] For example, as shown in Figure 5A, suppose that in the three horizontal lines from the top edge of a frame f1, all pixels in each horizontal line are grayscale 3, and in the three horizontal lines from the top edge of the next frame f2, all pixels in each horizontal line are grayscale 3. In frame f1, suppose that the selection signal AS at pixel position (1,1) has a value of 1.

[0030] The gradation of each pixel position in the corrected video data SDATA at this time is as shown in Figure 5B. In frame f1, the gradation of pixel positions (1,1), (2,1), (3,1), (4,1), (5,1)... is 2, 4, 2, 4, 2, ... The gradation of pixel positions (1,2), (2,2), (3,2), (4,2), (5,2)... is 4, 2, 4, 2, 4, ... The gradation of pixel positions (1,3), (2,3), (3,3), (4,3), (5,3)... is 2, 4, 2, 4, 2, ...

[0031] In frame f2, the selection signal AS alternates, so the gradation of pixel positions (1,1), (2,1), (3,1), (4,1), (5,1)... in the corrected video data SDATA becomes 4, 2, 4, 2, 4,... The gradation of pixel positions (1,2), (2,2), (3,2), (4,2), (5,2)... becomes 2, 4, 2, 4, 2,... The gradation of pixel positions (1,3), (2,3), (3,3), (4,3), (5,3)... becomes 4, 2, 4, 2, 4,...

[0032] Returning to Figure 1, the system clock SCLK is input to the shift register 41 in addition to the correction video data SDATA. Based on the shift clock signal SCLK, the shift register 41 inputs the gradation data of the correction video data SDATA line by line and shifts it, holding one line's worth of gradation data. The latch circuit 42 is input to the latch signal SL shown in Figure 2(e). Based on the latch signal SL, the latch circuit 42 latches one line's worth of gradation data held in the shift register 41. The latch circuit 42 holds one line's worth of gradation data for one line's duration.

[0033] The counter circuit 43 counts the counter clock signal CCLK and outputs the count value QD shown in Figure 2(i). The counter circuit 43 resets the count value QD with a horizontal period by the counter reset signal CRST. If the video data VDATA is, for example, 12 bits and has 4096 gradations, the counter circuit 43 supplies count values ​​QD from 0 to 4095 for each line to the comparator circuits 441 to 44x.

[0034] Each of the comparator circuits 441 to 44x receives the grayscale data DL of each pixel in a line held by the latch circuit 42. Figure 2(f) shows the grayscale data DL input to one of the comparator circuits 441 to 44x. Here, we assume that one of the comparator circuits is comparator circuit 441. Comparator circuits 441 to 44x compare the grayscale data DL of each input pixel with the count value QD and output a match pulse signal AP when they match.

[0035] The matching pulse signal AP output by comparator circuits 441 to 44x when the grayscale data DL of frame f1 shown in Figure 5B is input will be referred to as matching pulse signal AP1, and the matching pulse signal AP output when the grayscale data DL of frame f2 is input will be referred to as matching pulse signal AP2.

[0036] In frame f1, the grayscale of pixel position (1,1) is 2, so the comparator circuit 441 outputs a matching pulse signal AP1 when the count value QD is 2, as shown in Figure 2(k). In frame f1, the grayscale of pixel position (1,2) is 4, so the comparator circuit 441 outputs a matching pulse signal AP1 when the count value QD is 4, as shown in Figure 2(k).

[0037] Similarly, comparator circuits 442 to 44x output a matching pulse signal AP1 when the count value QD is 2 if the input grayscale data DL has 2 grayscale levels, and output a matching pulse signal AP1 when the count value QD is 4 grayscale levels if the grayscale levels have 4 grayscale levels.

[0038] Each of the selection circuits 451 to 45x receives a matching pulse signal AP output from the comparator circuits 441 to 44x. Each of the selection circuits 451 to 45x also receives a selector reset signal SELRST and an analog signal VREF1 or VREF2 that switches each frame.

[0039] The selection circuit 451 samples the analog signal VREF1 at the timing when the comparator circuit 441 supplies a matching pulse signal AP1 corresponding to the pixel position (1,1) of frame f1, and outputs the analog voltage VID1 as the grayscale drive voltage VID. The selection circuit 451 samples the analog signal VREF1 at the timing when the comparator circuit 441 supplies a matching pulse signal AP1 corresponding to the pixel position (1,2) of frame f1, and outputs the analog voltage VID2 as the grayscale drive voltage VID.

[0040] Similarly, the selection circuits 452 to 45x each sample the analog signal VREF1 at the timing when the matching pulse signal AP1 is supplied from the comparator circuits 442 to 44x, and output the analog voltage VID1 or VID2 as the grayscale drive voltage VID.

[0041] In frame f2, the grayscale of pixel position (1,1) is 4, so the comparator circuit 441 outputs a matching pulse signal AP2 at the timing when the count value QD is 4, as shown in Figure 2(n). In frame f2, the grayscale of pixel position (1,2) is 2, so the comparator circuit 441 outputs a matching pulse signal AP2 at the timing when the count value QD is 2, as shown in Figure 2(n).

[0042] The selection circuit 451 samples the analog signal VREF2 at the timing when the comparator circuit 441 supplies a matching pulse signal AP2 corresponding to the pixel position (1,1) of frame f2, and outputs the analog voltage -VID2 as the grayscale drive voltage VID. The selection circuit 451 samples the analog signal VREF2 at the timing when the comparator circuit 441 supplies a matching pulse signal AP2 corresponding to the pixel position (1,2) of frame f2, and outputs the analog voltage -VID1 as the grayscale drive voltage VID.

[0043] Similarly, the selection circuits 452 to 45x each sample the analog signal VREF2 at the timing when the matching pulse signal AP2 is supplied from the comparator circuits 442 to 44x, and output the analog voltage -VID1 or -VID2 as the grayscale drive voltage VID.

[0044] The vertical scanning circuit 5 is composed of a shift register, which shifts the row selection signal VST downwards on the row scan line G each time the horizontal periodic signal HS is input. That is, when the vertical scanning circuit 5 displays an image on the liquid crystal pixel 62 of the pixel circuit 60 of the uppermost horizontal line of each frame, it applies the row selection signal VST to the row scan line G1, turning on the pixel selection transistor 61 connected to the row scan line G1. When the vertical scanning circuit 5 displays an image on the liquid crystal pixel 62 of the pixel circuit 60 of the second horizontal line of each frame, it applies the row selection signal VST to the row scan line G2, turning on the pixel selection transistor 61 connected to the row scan line G2.

[0045] In this way, the vertical scanning circuit 5 shifts the row scan line G, which is turned on by applying the row selection signal VST to the pixel selection transistor 61, downward each time the horizontal periodic signal HS is input.

[0046] In this manner, the horizontal scanning circuit 4 applies a gradation drive voltage VID corresponding to the gradation of each pixel constituting each horizontal line of the corrected video data SDATA displayed on the display unit 6 to multiple column data lines D. The vertical scanning circuit 5 sequentially applies row selection signals to multiple row scan lines G in order to apply the gradation drive voltage VID to the pixel circuit 60 of each pixel constituting each horizontal line.

[0047] Therefore, the display unit 6 applies a positive analog voltage VID1 or VID2, or a negative analog voltage -VID1 or -VID2, as a grayscale drive voltage VID corresponding to the grayscale of each pixel to the pixel selection transistor 61 of the selected row scan line G. As a result, the display unit 6 displays the image of each frame in grayscale.

[0048] When the liquid crystal display device 100 displays the corrected video data SDATA on the display unit 6, the gradation perceived by the user is integrated in the horizontal, vertical, and frame directions, resulting in a state equivalent to displaying the video data VDATA on the display unit 6.

[0049] Figure 6A shows the sampling noise Ns generated when the liquid crystal display device 100 displays the corrected video data shown in Figure 5B. In Figure 6A, the height of the sampling noise Ns is H2. Figure 6B shows the sampling noise Ns generated when the liquid crystal display device 100 displays the video data shown in Figure 5A, assuming that the liquid crystal display device 100 does not have a digital signal processing unit 3. In Figure 6B, the height of the sampling noise Ns is H1.

[0050] The liquid crystal display device 100 supplies corrected video data SDATA, which is obtained by correcting video data VDATA from the digital signal processing unit 3, to the horizontal scanning circuit 4. Therefore, the liquid crystal display device 100 can reduce the sampling noise Ns that occurs when sampling the analog signal VREF1 or VREF2, which is an analog ramp waveform.

[0051] The digital signal processing unit 3 may generate corrected video data SDATA by alternately adding and subtracting a fixed value in the horizontal direction to the gradation of each pixel constituting each horizontal line of the video data VDATA. Preferably, in addition to horizontal correction, the digital signal processing unit 3 generates corrected video data SDATA by alternately adding and subtracting a fixed value in the vertical direction to the gradation of each vertical pixel located at the same position in the horizontal direction of the video data VDATA.

[0052] In addition to horizontal and vertical correction, the digital signal processing unit 3 preferably generates corrected video data SDATA by alternately adding and subtracting a fixed value in the frame direction to the gradation of each pixel in multiple frames located at the same position in the horizontal and vertical directions of the video data VDATA. Multiple frames refer to at least two frames.

[0053] Incidentally, the digital signal processing unit 3 corrects the gradation of each pixel and generates corrected video data SDATA, regardless of whether the same gradation is consecutive in multiple pixels that make up the video data VDATA. For example, suppose the gradations of pixel positions (1,1), (2,1), (3,1), (4,1), (5,1)... in the video data VDATA are 3, 4, 5, 6, 7,... In this case, the corrected video data SDATA will have gradations of 2, 5, 4, 7, 6,... at pixel positions (1,1), (2,1), (3,1), (4,1), (5,1)...

[0054] Even in such cases, when the liquid crystal display device 100 displays the corrected video data SDATA on the display unit 6, the gradation perceived by the user is integrated in the horizontal, vertical, and frame directions, resulting in a state equivalent to displaying the video data VDATA on the display unit 6.

[0055] The present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0056] 1 Timing generation circuit 2. Analog signal generation circuit 3. Digital signal processing unit 4. Horizontal scanning circuit 5. Vertical scanning circuit 6 Display section 60-pixel circuit MOSFET1 Pixel Selection Transistor 62 LCD pixels D1~Dx Column Data Lines G1~Gy row scan lines

Claims

1. A display unit is provided with a pixel circuit including liquid crystal pixels at each intersection of multiple column data lines and multiple row scan lines. A horizontal scanning circuit that applies a grayscale driving voltage corresponding to the grayscale of each pixel constituting each horizontal line of video data displayed on the display unit to the plurality of column data lines, A vertical scanning circuit that sequentially applies row selection signals to the plurality of row scanning lines in order to apply the grayscale driving voltage to the pixel circuit of each pixel constituting each of the horizontal lines, A digital signal processing unit generates corrected video data by alternately adding and subtracting a fixed value to the grayscale of each pixel constituting each horizontal line of the video data in the horizontal direction, and supplies this corrected video data to the horizontal scanning circuit. A liquid crystal display device equipped with the following features.

2. The liquid crystal display device according to claim 1, wherein the digital signal processing unit generates corrected video data by alternately repeating the addition and subtraction of the fixed value in the vertical direction for each vertical pixel located at the same horizontal position in the video data, and supplies it to the horizontal scanning circuit.

3. The liquid crystal display device according to claim 1 or 2, wherein the digital signal processing unit generates corrected video data by alternately adding and subtracting the fixed value to the grayscale of each pixel of a plurality of frames located at the same position in the horizontal and vertical directions of the video data, and supplies it to the horizontal scanning circuit.

Images