Indication device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A semiconductor device has a drive circuit part and a display part (also referred to as a pixel part) on the same substrate. The drive circuit part and the display part have a thin-film transistor whose semiconductor layer is configured by an oxide semiconductor, and have first wiring and second wiring. The thin-film transistor has a source electrode layer or a drain electrode layer. The thin-film transistor of the drive circuit part is configured by sandwiching the semiconductor layer between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected with each other via an oxide conductive layer at an opening provided on a gate insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This relates to semiconductor devices using oxide semiconductors.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all things, including electro-optical devices such as liquid crystal displays, semiconductor circuits, and electronic equipment. It is placed there. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates having an insulating surface have been used The technology for constructing thin-film transistors (TFTs) is attracting attention. Thin-film transistors are concentrated Integrated circuits (ICs) and electro-optical devices, etc. It has a wide range of applications in sub-devices, and its development is being accelerated, especially as a switching element in image display devices. Yes. Metal oxides exist in diverse forms and are used in a variety of applications. Indium oxide is one example. It is a well-known material and is used as a transparent electrode material required in liquid crystal displays and other applications. It is being done.

[0004] Some metal oxides exhibit semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and so on. Thin-film transistors using metal oxides exhibiting semiconductor properties as channel formation regions are already known. (Patent Documents 1 and 2) [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] Thin film transistors using an oxide semiconductor film have a high operating speed and a relatively simple manufacturing process and sufficient reliability is required.

[0007] In a thin film transistor using an oxide semiconductor film, improving the operating characteristics and reliability is one of the problems.

[0008] In particular, the operating speed of the thin film transistor used in the drive circuit is preferably high.

[0009] For example, shortening the channel length (L) or widening the channel width (W) of the thin film transistor increases the operating speed. However, shortening the channel length (L) causes a problem that the switching characteristics, such as the on-off ratio, become small. Also, widening the channel width (W) causes a problem of increasing the capacitance load of the thin film transistor itself.

[0010]

[0011] Since the writing time of the display image is shortened, the thin film transistor used in the driving circuit preferably has a fast operation speed.

[0012] Also, reducing the variation in the electrical characteristics of the thin film transistor using the oxide semiconductor film is also one of the problems.

Means for Solving the Problem

[0013] One aspect of the present invention has a driving circuit portion and a display portion (also referred to as a pixel portion) on the same substrate, and the driving circuit portion and the display portion have a thin film transistor, a first wiring (also referred to as a terminal or a connection electrode), and a second wiring (also referred to as a terminal or a connection electrode). The thin film transistor has a gate electrode formed of a metal, a gate insulating film on the gate electrode, an oxide semiconductor layer on the gate insulating film, a source electrode (also referred to as a source electrode layer) and a drain electrode (also referred to as a drain electrode layer) formed of a metal on the oxide semiconductor layer, and a protective insulating layer on the oxide semiconductor layer and the source and drain electrodes. The thin film transistor in the driving circuit portion has a conductive layer at a position overlapping the oxide semiconductor layer on the protective insulating layer, and the thin film transistor in the display portion is electrically connected to a pixel electrode (also referred to as a pixel electrode layer). The first wiring is formed of the same material as the gate electrode, the second wiring is formed of the same material as the source electrode or the drain electrode, and the first wiring and the second wiring in the driving circuit portion are electrically connected through an opening (contact hole) provided in the gate insulating film and the protective insulating layer.

[0014] One aspect of the present invention has a driving circuit portion and a display portion (also referred to as a pixel portion) on the same substrate, and the driving circuit portion and the display portion have a thin film transistor, a first wiring, and a second wiring. ​​​​​​​​​​​​​​ A transistor consists of a gate electrode made of metal and a gate insulating layer on the gate electrode. The structure consists of a film, an oxide semiconductor layer on the gate insulating film, and a metal on the oxide semiconductor layer. The formed source electrode and drain electrode, and the oxide semiconductor layer and the source electrode and drain electrode The thin-film transistor in the drive circuit section has a protective insulating layer on top of it, and the oxide semiconductor on the protective insulating layer The thin-film transistors in the display section have a conductive layer in a position overlapping with the body layer, and are electrically connected to the pixel electrodes. Next, the first wiring is formed of the same material as the gate electrode, and the second wiring is the source electrode or dot Formed from the same material as the rain electrode, the first and second wirings of the drive circuit section are gate This is a semiconductor device that is electrically connected through an opening formed in an insulating film.

[0015] As thin-film transistors for pixels and thin-film transistors for driving circuits, inverse bottom gate structure Staggered thin-film transistors are used. Thin-film transistors for pixels and thin-film transistors for the driving circuit. The zista is an oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer, in contact with the oxide semiconductor layer. This is a channel etch-type thin-film transistor with a material insulating film.

[0016] Thin-film transistors for drive circuits have a configuration in which an oxide semiconductor layer is sandwiched between a gate electrode and a conductive layer. This reduces threshold voltage variation in thin-film transistors, resulting in a more stable operation. A semiconductor device equipped with a thin-film transistor having the specified electrical characteristics can be provided. The electrode layer may be at the same potential as the gate electrode layer, or it may be at a floating potential, or it may be fixed at a fixed potential. The potential can be any potential, such as GND potential or 0V. Also, by applying an arbitrary potential to the conductive layer, the thin film can be The threshold of the transistor can be controlled.

[0017] One aspect of the present invention for realizing the above structure is a first substrate in which the drive circuit section is formed on the same substrate. The area and the second area where the display unit is formed are subjected to a first photolithography process. A first electrode that functions as a terminal electrode and a first wiring made of the same material as the first electrode are formed. A first insulating film, which functions as a gate insulating film, is formed on the first electrode and the first wiring, On the insulating film 1, an oxide semiconductor layer is formed by a second photolithography process, and oxidation A heat treatment is performed to dehydrate or dehydrogenate the material semiconductor layer, and a third layer is applied to the oxide semiconductor layer. The photolithography process involves a second electrode that functions as a source electrode and a drain electrode. A third electrode that functions as a third electrode, and a second electrode made of the same material as the source or drain electrode. A line is formed, and the second electrode, the third electrode, and the oxide semiconductor layer are placed on top of each other, acting as a protective insulating layer. A second insulating film is formed, and the first wiring overlaps with the first wiring by a fourth photolithography process. The insulating film and the second insulating film are selectively removed to form the first opening, which overlaps with the second wiring. The second insulating film is selectively removed to form a second opening, and in the second region, the second electrode Alternatively, the second insulating film can be selectively removed at a position that overlaps with either of the third electrodes. A third opening is formed by a fifth photolithography step, and the first and second openings are formed by a fifth photolithography step. A first conductive layer is formed that electrically connects the first wiring and the second wiring through the opening, and the first region In the region, at a position overlapping with the oxide semiconductor layer via the second insulating film, the same as the first conductive layer A fourth electrode made of the material is formed, and a thin film transient is introduced through the third opening in the second region. A fifth component, made of the same material as the first conductive layer that electrically connects to the st, functions as a pixel electrode. This is a method for manufacturing a semiconductor device, characterized by forming electrodes.

[0018] The first to third apertures are formed simultaneously in the same photolithography process, and the pixel electrode and By simultaneously forming the first conductive layer and the fourth electrode in the same photolithography process, The above configuration can be achieved without increasing the number of photography steps.

[0019] A semiconductor in which the drive circuit and display unit are formed on the same substrate through five photolithography processes. We can provide the device.

[0020] One aspect of the present invention for realizing the above structure is a first substrate in which the drive circuit section is formed on the same substrate. The area and the second area where the display unit is formed are subjected to a first photolithography process. A first electrode that functions as a terminal electrode and a first wiring made of the same material as the first electrode are formed. A first insulating film, which functions as a gate insulating film, is formed on the first electrode and the first wiring, On the insulating film 1, an oxide semiconductor layer is formed by a second photolithography process, and oxidation The semiconductor layer is subjected to heat treatment to dehydrate or dehydrogenate it, and then the third photolithography is performed. The process selectively removes the first insulating film on the first wiring to form a fourth opening, and oxide A second electrode, which functions as a source electrode, is formed on the semiconductor layer by a fourth photolithography process. The electrode, a third electrode that functions as a drain electrode, and the same material as the second or third electrode. A second wiring made of material is formed, and the second electrode and the third electrode are placed on the oxide semiconductor layer, protecting A second insulating film is formed which functions as an insulating layer, and a fifth photolithography step is performed. In region 2, at a position overlapping with either the second electrode or the third electrode, the second A third opening is formed by selectively removing the insulating film, and a sixth photolithography process is performed. Therefore, in the first region, a fourth is formed at a position overlapping with the oxide semiconductor layer via the second insulating film. An electrode is formed and electrically connected to the thin-film transistor through a third aperture in the second region. A fifth electrode is formed, which is made of the same material as the fourth electrode and functions as a pixel electrode. This is a method for fabricating semiconductor devices characterized by the following:

[0021] The formation of the fourth aperture by the third photolithography step can be performed after the formation of the first insulating film. This may be performed before the formation of the oxide semiconductor layer by the second photolithography step.

[0022] Compared to the above-described embodiment, after the oxide semiconductor layer is formed, a for providing an opening on the first wiring is provided. Because a photolithography process is added, a total of 6 photolithography processes are required for the same substrate. The drive circuit and display unit will be formed on the board, and the first wiring and the second wiring will be connected. Because the step in the opening can be made only the thickness of the first insulating film, the first coating can be made with good coverage. This ensures a secure connection between the first and second wiring, improving the reliability of the semiconductor device. It is possible.

[0023] Furthermore, in the aforementioned photolithography process, the transmitted light becomes an exposure mass with multiple intensities. The etching process may be performed using a mask layer formed by a multi-gradation mask. stomach.

[0024] A mask layer formed using a multi-gradation mask has a shape with multiple film thicknesses, and the mask layer By etching, the shape can be further deformed, allowing for different patterns. It can be used in multiple etching processes. Therefore, a single multi-gradation mask can be used. This allows for the formation of mask layers that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced. This allows for a simplification of the process.

[0025] The above configuration solves at least one of the above problems.

[0026] Furthermore, the oxide semiconductor used in this specification is InMO3(ZnO) m (m>0) A thin film is formed, and a thin-film transistor is fabricated using this thin film as an oxide semiconductor layer. M is one or more metallic elements selected from Ga, Fe, Ni, Mn, and Co. This indicates a metallic element. For example, M can be Ga, or Ga and Ni, or Ga and In addition, the above oxide semiconductor may contain metal elements other than Ga, such as Fe. In addition to the metallic elements included as M, Fe, Ni, and other transition metals are included as impurity elements. Some contain elements or oxides of the transition metal. In this specification, In MO3(ZnO) m Among oxide semiconductor layers with a structure represented by (m>0), where M is Ga Oxide semiconductors with a structure containing are called In-Ga-Zn-O based oxide semiconductors, and their thin films are called I It is also called an n-Ga-Zn-O non-single crystal film.

[0027] In addition to the above, other metal oxides that can be applied to oxide semiconductor layers include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be applied. Silicon oxide may be included in the oxide semiconductor layer made of the material.

[0028] Heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in lower resistance, i.e., N-type ( N - (e.g., chemical treatment), and then the formation of an oxide insulating film in contact with the oxide semiconductor layer, or after formation, By heat treatment, the oxide semiconductor layer is subjected to an oxygen-rich state, thereby increasing its resistance, i.e., I It can also be said that they are being molded. Furthermore, solid-phase oxidation is performed to create an oxygen-rich state in the oxide semiconductor layer. It can also be said that this results in thin-film transistors with good electrical characteristics and high reliability. This makes it possible to manufacture and provide semiconductor devices.

[0029] Dehydration or dehydrogenation is performed using nitrogen or an inert gas such as a noble gas (argon, helium, etc.). Under ambient conditions, heating at temperatures above 400°C, below the substrate's strain point, preferably between 420°C and 570°C. Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer. Furthermore, subsequent water treatment ( This can prevent re-impregnation (of H2O).

[0030] Dehydration or dehydrogenation heat treatment is preferably carried out in a nitrogen atmosphere with H2O at a concentration of 20 ppm or less. It seems that way. Alternatively, the process can be carried out in ultra-dry air with an H2O concentration of 20 ppm or less.

[0031] The oxide semiconductor layer that has undergone dehydration or dehydrogenation is the oxide semiconductor layer after dehydration or dehydrogenation. Even when measuring TDS up to 450°C for the body layer, two peaks for water are still visible, at least 300°C. The heat treatment conditions should be such that the single peak appearing around °C is not detectable. Therefore, dehydration Alternatively, for thin-film transistors using an oxide semiconductor layer that has undergone dehydrogenation, the TDS is 45 Even when measurements are taken down to 0°C, the water peak that typically appears around 300°C is not detected.

[0032] Then, the oxide semiconductor layer is dehydrated or dehydrogenated at heating temperature T, and then the temperature When reducing the temperature, by using the same furnace that performed the dehydration or dehydrogenation, and preventing exposure to the atmosphere, It is important not to reintroduce water or hydrogen. Dehydration or dehydrogenation is performed, followed by oxidation. Making the semiconductor layer low resistance, i.e., N-type (N - After (etc.), the acid is made into a type I acid by increasing its resistance. When a thin-film transistor is fabricated using a synthetic semiconductor layer, the threshold voltage of the thin-film transistor... (Vth) can be made positive, realizing a so-called normally-off switching element. It is possible. The gate voltage of the thin-film transistor is channeled at a positive threshold voltage as close as possible to 0V. It is desirable for semiconductor devices (display devices) to have a thin film transistor. If the threshold voltage is negative, even if the gate voltage is 0V, the gap between the source electrode and the drain electrode will be negative. Current flows through it, making it prone to what is known as normally-on. Active matrix display devices In this context, the electrical characteristics of the thin-film transistors that make up the circuit are important, and these electrical characteristics This affects the performance of the display device. In particular, among the electrical characteristics of thin-film transistors, the threshold voltage is This is important. Even if the field effect mobility is high, the threshold voltage value is high, or the threshold voltage value is If it is negative, it is difficult to control as a circuit. The absolute value of the threshold voltage is large. In the case of thin-film transistors, when the driving voltage is low, they function as a switching device like a TFT. It may fail to perform its function and become a burden. In addition, a channel is formed only when a positive voltage is applied to the gate voltage, and drain current flows. A transistor that can produce a channel is desirable. A transistor that does not form a channel unless the drive voltage is high. Distors and transistors that form a channel and allow drain current to flow even under negative voltage conditions are Therefore, it is unsuitable as a thin-film transistor for use in circuits.

[0033] Furthermore, the gas atmosphere used to lower the temperature from heating temperature T is different from the gas atmosphere used to raise the temperature to heating temperature T. The atmosphere may be switched to a gaseous atmosphere. For example, in the same furnace where dehydration or dehydrogenation has been performed, the atmosphere may be switched to air. Without contact, high-purity oxygen gas or N2O gas, or ultra-dry air (with a dew point) is passed through the furnace. Cooling is performed by filling the container with water at -40°C or below, preferably -60°C or below.

[0034] After reducing the moisture content in the membrane by heat treatment that involves dehydration or dehydrogenation, the moisture content is reduced. Slow cooling (or cooling) in an atmosphere where there is no dew (dew point of -40°C or lower, preferably -60°C or lower). Using the oxide semiconductor film, the electrical characteristics of thin-film transistors are improved, and mass production is also possible. To realize thin-film transistors that possess both low performance and high efficiency.

[0035] In this specification, under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) The heat treatment is referred to as a heat treatment for dehydration or dehydrogenation. In this specification, this heat treatment Dehydrogenation is not simply defined as the process of removing H2 through scientific means, but rather as H For convenience, this process, including the removal of OH groups, will be referred to as dehydration or dehydrogenation.

[0036] Heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in lower resistance, i.e., N-type ( N - To cause (such as) transformation.

[0037] In addition, a high-resistance drain region (also referred to as an HRD (High Resistance Drain) region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, a high-resistance source region (also referred to as an HRS (High Resistance Source) region) that is oxygen-deficient and overlaps with the source electrode layer is formed. Specifically, the carrier concentration of the high-resistance drain region is in the range of 1×10 / cm or higher, and is higher than at least the carrier concentration (less than 1×10

[0038] / cm 18 / cm 3 in the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. in the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. 18 / cm 3 in the channel formation region. Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. Furthermore, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into a type-I state to form a channel formation region. The treatment of making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state includes film formation by sputtering of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer, heat treatment after oxide insulating film formation, heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, cooling with ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower), and the like. Furthermore, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, the resistance is further increased, that is, it is made into a type-I state to form a channel formation region. The treatment of making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state includes film formation by sputtering of an oxide insulating film in contact with the dehydrated or dehydrogenated oxide semiconductor layer, heat treatment after oxide insulating film formation, heat treatment in an atmosphere containing oxygen, or treatment of cooling in an oxygen atmosphere after heating in an inert gas atmosphere, cooling with ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower), and the like.

[0039] Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance

[0040] Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance Moreover, in order to use at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer as the channel formation region, by selectively making it in an oxygen-excess state, the high resistance It can also be converted to type I. It is in contact with a dehydrated or dehydrogenated oxide semiconductor layer. Then, a source electrode layer and a drain electrode layer made of metal electrodes such as Ti are formed, and the source electrode layer The exposed region that does not overlap with the drain electrode layer is selectively treated as an oxygen-rich state to form a channel. This can be formed. When selectively creating an oxygen-rich state, the second layer overlaps the source electrode layer. A first high-resistance source region and a second high-resistance drain region overlapping the drain electrode layer are formed. Therefore, the region between the first high-resistance source region and the second high-resistance drain region is a channel-forming region. This becomes a region. That is, the channel-forming region is self-aligned between the source electrode layer and the drain electrode layer. It is formed in this way.

[0041] This allows for the fabrication of semiconductor devices with thin-film transistors that exhibit good electrical characteristics and high reliability. And it becomes possible to provide it.

[0042] Furthermore, a high-resistance drain region is formed in the oxide semiconductor layer superimposed on the drain electrode layer. This improves the reliability of the drive circuit when it is formed. Specifically, By forming a resistive drain region, a high-resistance drain region and a channel are created from the drain electrode layer. It is possible to create a structure in which the conductivity can be changed in stages across the formation region. Therefore, when operating by connecting to wiring that supplies a high power potential VDD to the drain electrode layer, Even when a high electric field is applied between the drain electrode layer and the drain electrode layer, the high-resistance drain region buffs This configuration prevents the application of a localized high electric field, thereby improving the breakdown voltage of the thin-film transistor. It is possible.

[0043] Furthermore, in the oxide semiconductor layer superimposed on the drain electrode layer and the source electrode layer, a high-resistance drain By forming an in region and a high-resistance source region, the channel is formed when a drive circuit is created. This can reduce leakage current in the formed region. Specifically, the high-resistance drain region By forming this, the leakage current of the transistor that flows between the drain electrode layer and the source electrode layer The flow path consists of a drain electrode layer, a high-resistance drain region on the drain electrode layer side, and a channel shape. The order is the formed region, the high-resistance source region on the source electrode layer side, and the source electrode layer. At this time, the channel In the channel formation region, flow from the high-resistance drain region on the drain electrode layer side to the channel formation region. Leakage current is reduced by the gate insulating layer and channel formation region, which have high resistance when the transistor is off. It can be concentrated near the interface, and the back channel (the channel away from the gate electrode layer) This can reduce leakage current in a portion of the surface of the flannel-forming region.

[0044] Furthermore, there is a high-resistance source region that overlaps the source electrode layer and a high-resistance drain region that overlaps the drain electrode layer. The region depends on the width of the gate electrode layer, but it overlaps with a part of the gate electrode layer and the gate insulating layer. This allows for a more effective reduction of the electric field strength near the edge of the drain electrode layer. ru.

[0045] Furthermore, even if an oxide conductive layer is formed between the oxide semiconductor layer and the source and drain electrodes... Good. The oxide conductive layer preferably contains zinc oxide as a component, and preferably contains indium oxide. It is preferable that it does not contain zinc oxide, aluminum zinc oxide, or oxynitride. Lead-aluminum, zinc-gallium oxide, etc., can be used. The oxide conductive layer has low resistance. Drain region (LRN (Low Resistance N-type conduction) Also called the ivity region or LRD (Low Resistance Drain) region. It also functions as a carrier concentration in the low-resistance drain region, Larger than the HRD region, for example, 1 × 10 20 / cm 3 The above 1 x 10 21 / c m 3 Preferably, the oxide conductive layer is within the following range: the oxide semiconductor layer and the source electrode and By placing it between the rain electrodes, the contact resistance between the electrode and the oxide semiconductor layer can be reduced, Because it enables high-speed operation of the zista, the frequency characteristics of the surrounding circuitry (drive circuitry) can be improved. It can be raised.

[0046] The oxide conductive layer and the metal layers for forming the source and drain electrodes can be deposited continuously. That is the case.

[0047] Furthermore, the aforementioned first and second wirings are oxidized to function as LRN or LRD. A laminated wiring harness may be constructed using the same material as the material conductive layer and a metallic material. By laminating conductive layers, coverage against uneven surfaces such as overlapping wiring and openings is improved. This can reduce wiring resistance. Also, localized wiring due to migration etc. Because it can also be expected to have the effect of increasing resistance and preventing wire breakage, it is possible to provide highly reliable semiconductor devices. can.

[0048] Furthermore, when connecting the first and second wirings as described above, an oxide conductive layer is placed in between. By continuing, an insulating oxide is formed on the metal surface of the connection (contact) part. This is expected to prevent an increase in contact resistance and make semiconductor equipment more reliable. We can provide a place for you.

[0049] Furthermore, thin-film transistors are susceptible to damage from static electricity, so the gate wire or source wire may be damaged. For each line, a protection circuit for protecting the thin-film transistors in the pixel area is provided on the same substrate. Preferably, the protection circuit is constructed using a nonlinear element with an oxide semiconductor layer. It's nice.

[0050] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything. [Effects of the Invention]

[0051] A semiconductor device that uses an oxide semiconductor layer and features a thin-film transistor with excellent electrical properties and reliability. This can be achieved. [Brief explanation of the drawing]

[0052] [Figure 1] A diagram illustrating a semiconductor device. [Figure 2] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 3] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 4] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 5] A diagram illustrating a semiconductor device. [Figure 6] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 7] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 8] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 9] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 10] A diagram illustrating a semiconductor device. [Figure 11] A diagram illustrating a semiconductor device. [Figure 12]A diagram illustrating the block diagram of a semiconductor device. [Figure 13] A diagram illustrating the configuration of a signal line drive circuit. [Figure 14] A circuit diagram showing the configuration of a shift register. [Figure 15] A diagram illustrating the configuration of a shift register and a timing chart illustrating its operation. [Figure 16] A diagram illustrating a semiconductor device. [Figure 17] A diagram illustrating a semiconductor device. [Figure 18] An external view showing an example of an e-book. [Figure 19] External view showing examples of television equipment and digital photo frames. [Figure 20] An external view showing an example of a gaming machine. [Figure 21] An external view showing an example of a portable computer and mobile phone. [Figure 22] A diagram illustrating a semiconductor device. [Figure 23] A diagram illustrating a semiconductor device. [Figure 24] A diagram illustrating a semiconductor device. [Figure 25] A diagram illustrating a semiconductor device. [Figure 26] A diagram illustrating a semiconductor device. [Figure 27] A diagram illustrating a semiconductor device. [Figure 28] A diagram illustrating a semiconductor device. [Figure 29] A diagram illustrating a semiconductor device. [Figure 30] A diagram illustrating a semiconductor device. [Figure 31] A diagram illustrating a semiconductor device. [Figure 32] A diagram illustrating a semiconductor device. [Figure 33] A diagram illustrating a semiconductor device. [Figure 34] A diagram illustrating a semiconductor device. [Figure 35] A diagram illustrating a semiconductor device. [Figure 36] A diagram illustrating a semiconductor device. [Figure 37] A diagram illustrating the manufacturing process of semiconductor devices. [Figure 38] A diagram illustrating a semiconductor device. [Figure 39] A diagram illustrating the calculation results of the water generation and desorption mechanisms. [Figure 40] A diagram illustrating the calculation results of the energy diagram. [Modes for carrying out the invention]

[0053] The embodiments will be described in detail with reference to the drawings. However, the following description is not limited to the present invention. The form and details can be changed in various ways without departing from the gist and scope thereof, as is the case for those skilled in the art. Therefore, it is easy to understand. Accordingly, the description of the embodiment shown below should be interpreted as being limited to the following. It is not the case that... The same reference numeral is used consistently across different drawings for parts that are repeated, and explanations of their repetition are omitted.

[0054] (Embodiment 1) The fabrication process for semiconductor devices, including thin-film transistors, will be explained using Figures 1 to 5. .

[0055] A liquid crystal display device is shown in Figure 1 as a semiconductor device according to one embodiment of the present invention. This includes a pixel section containing a thin-film transistor 170 and a capacitor 147, and a thin-film transistor 180 The drive circuit section, pixel electrode layer 110, and insulating layer 191 which functions as an alignment layer are provided. The substrate 100, an insulating layer 193 that functions as an alignment film, a counter electrode layer 194, and a color filter. A colored layer 195 that functions as a counter substrate 190 is provided on the opposing substrate 190, and the liquid crystal layer 192 is sandwiched between them. It is facing in that direction. Also, on the side opposite to the liquid crystal layer 192 of substrate 100 and opposing substrate 190, Polarizing plates (layers containing polarizers, also simply called polarizers) 196a and 196b are provided, The terminal section of the wiring includes a first terminal 121, a connecting electrode 120, and a connecting terminal electrode 128. The source wiring terminal is provided with a second terminal 122 and a connecting terminal electrode 129. ru.

[0056] In the drive circuit section, the thin-film transistor 180 has a conductive layer above the gate electrode layer and the semiconductor layer. A conductive layer 111 is provided, and the drain electrode layer 165b is formed in the same process as the gate electrode layer. It is electrically connected to layer 162. Also, in the pixel area, the thin-film transistor 170 The rain electrode layer is electrically connected to the pixel electrode layer 110.

[0057] The manufacturing method will be explained in detail below using Figures 2 to 5 and Figure 11. Figure 5 shows a liquid crystal display device. These are plan views of the pixel area, and Figures 1 to 4 show the lines A1-A2 and B1-B2 in Figure 5. This corresponds to a cross-sectional view.

[0058] After forming a conductive layer over the entire surface of the substrate 100, which is a substrate having an insulating surface, A photolithography process is performed to form a resist mask, and unwanted parts are removed by etching. Remove the parts and wire and electrodes (gate gate layer 101, gate gate layer 161, conductive layer 162, Capacitive wiring 108 (also called a capacitive wiring layer), and the first terminal 121) are formed. Figure 2(A When etching is performed such that a tapered shape is formed at the ends of the wiring and electrodes, This is preferable because it improves the coverage of the layered film. Note that gate electrode layer 101, gate electrode layer Each of the 161s is included in the gate wiring.

[0059] There are no major restrictions on the substrates that can be used for the substrate 100 having an insulating surface, however In addition, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. A glass substrate can be used for the substrate 100.

[0060] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. Furthermore, by including more barium oxide (BaO) compared to boric acid, it becomes more practical. Heat-resistant glass can be obtained. Therefore, a glass substrate containing more BaO than B2O3 is used. This is preferable.

[0061] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials such as crystallized glass can also be used. Since the liquid crystal display device shown in the embodiment is transmissive, the substrate 100 is a light-transmitting substrate A plate is used, but in the case of a reflective type, a non-transparent metal substrate or the like is used as the substrate 100. That's fine.

[0062] The insulating film that forms the base layer consists of a substrate 100, a gate electrode layer 101, a gate electrode layer 161, and a conductive layer 1 62 may be provided between the capacitive wiring 108 and the first terminal 121. The undercoat is on the substrate 1 It has the function of preventing the diffusion of impurity elements from 00, and silicon nitride film, silicon oxide film, silicon nitride oxide Formed by a laminated structure of one or more films selected from silicon films or silicon oxidnitride films. It is possible.

[0063] Gate gate layer 101, gate gate layer 161, conductive layer 162, capacitive wiring 108, and first The materials for terminal 121 are molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Metal materials such as um, copper, neodymium, scandium, or alloy materials mainly composed of these materials are used. It can be formed as a single layer or by lamination.

[0064] For example, gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring 108, and The two-layer laminated structure of the first terminal 121 is such that a molybdenum layer is laminated on top of an aluminum layer. A two-layer laminated structure, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or on a copper layer A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated, and a titanium nitride layer and molybdenum A two-layer structure with layers stacked is preferable. As for a three-layer stacked structure, tungsten A layer or tungsten nitride layer and an aluminum-silicon alloy layer or aluminum-titanium alloy layer It is preferable to have a laminated structure in which an alloy layer and a titanium nitride layer or a titanium layer are stacked.

[0065] Next, gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring 108, and A gate insulating layer 102 is formed on the first terminal 121 (see Figure 2(A)).

[0066] The gate insulating layer 102 is formed by a silicon oxide layer using plasma CVD or sputtering. , a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer as a single layer or It can be formed by stacking. For example, SiH4, oxygen, and nitrogen can be used as the film-forming gas. Then, a silicon oxide nitride layer can be formed by plasma CVD. The thickness shall be between 100 nm and 500 nm, and in the case of lamination, for example, the film thickness shall be 50 nm or more. A first gate insulating layer with a thickness of 00 nm or less, and a layer with a film thickness of 5 nm or more and 300 nm on the first gate insulating layer. The second gate insulating layer is laminated with a length of m or less.

[0067] In this embodiment, the gate insulating layer 102 is made to a thickness of 200 nm or less by plasma CVD. It forms the silicon nitride layer below.

[0068] Next, an oxide semiconductor film 13 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 102. It forms 0 (see Figure 2(B)).

[0069] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the material is deposited on the surface of the gate insulating layer 102. It is preferable to remove any debris. Reverse sputtering is a process where the substrate side is subjected to an argon atmosphere. This method involves applying a voltage using an RF power supply to form plasma near the substrate and modify the surface. Nitrogen, helium, etc. may be used instead of an argon atmosphere. The procedure can also be carried out in an atmosphere with added oxygen, N2O, etc. Alternatively, in an argon atmosphere with Cl 2. You can also proceed with the addition of CF4, etc.

[0070] Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 130, oxidation does not occur. To make the semiconductor film amorphous, it is preferable to make the film thickness 50 nm or less. By reducing the thickness of the oxide semiconductor film, when the oxide semiconductor layer is heat-treated after formation, It can suppress crystallization.

[0071] The oxide semiconductor film 130 is an In-Ga-Zn-O non-single crystal film, an In-Sn-Zn-O system In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al-Z The present implementation uses oxide semiconductor films based on nO, In-O, Sn-O, and Zn-O. In this state, an In-Ga-Zn-O oxide semiconductor target is used by sputtering. The film is then formed. Furthermore, the oxide semiconductor film 130 is formed under a rare gas (typically argon) atmosphere. Sputtering under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere It can be formed by the sputtering method. Also, when using the sputtering method, SiO2 A target containing 2% to 10% by weight is used to form an oxide semiconductor film 130. The mixture contains SiOx (x>0) which inhibits crystallization, and is subjected to dehydration or dehydrogenation in a later step. It is preferable to suppress crystallization during the heat treatment process.

[0072] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1:0.5[at%]) Using this method, the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and the current is DC. Power supply 0.5kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm, acid The film is deposited in an atmosphere with a raw flow rate ratio of 40%. Note that if a pulsed DC power supply is used, This is preferable because it reduces distortion and results in a uniform film thickness distribution. In-Ga-Zn-O non-single crystal The film thickness shall be between 5 nm and 200 nm. In this embodiment, an oxide semiconductor film is used. Then, a film is formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. A 20 nm thick In-Ga-Zn-O non-single crystal film is deposited.

[0073] The sputtering method includes RF sputtering, which uses a high-frequency power supply for sputtering. Then there is the DC sputtering method, and furthermore, pulsed DC sputtering, which applies a pulsed bias. There is also the sputtering method. RF sputtering is mainly used when depositing insulating films, DC Sputtering is primarily used for depositing metal films.

[0074] There are also multi-target sputtering systems that can set up multiple targets made of different materials. The puttering apparatus can also deposit multiple layers of different material films in the same chamber, or in the same chamber. It is also possible to deposit films by simultaneously discharging multiple types of materials using a burr.

[0075] Furthermore, sputtering using a magnetron sputtering method that incorporates a magnetic mechanism inside the chamber... E There are sputtering machines that use the CR sputtering method.

[0076] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering during film deposition... Reactive sputtering involves chemically reacting gas components to form thin films of those compounds. There are also methods such as the sputtering method and the bias sputtering method, which applies voltage to the substrate during film deposition.

[0077] Next, a second photolithography process is performed on the oxide semiconductor film 130 to create a resin A stock mask 137 is formed, and an oxide semiconductor film 130 and a gate insulating layer 1 are formed by etching. Remove the unnecessary portion of 02 and apply the contacts to the gate insulating layer 102 that reach the first terminal 121. A contact hole 119 and a contact hole 118 that reaches the conductive layer 162 are formed (Figure 2( See C). ).

[0078] In this way, with the oxide semiconductor film 130 laminated over the entire surface of the gate insulating layer 102, the gate When the process of forming contact holes in the insulating layer 102 is performed, the surface of the gate insulating layer 102 Since the dyst mask does not come into direct contact, contamination of the gate insulating layer 102 surface (adhesion of impurities, etc.) is prevented. This prevents the interface between the gate insulating layer 102 and the oxide semiconductor film 130. This allows for improved performance, leading to increased reliability.

[0079] The contact holes may be opened by directly forming a resist pattern on the gate insulating layer. In that case, after removing the resist, heat treatment is performed to dehydrate the surface of the gate insulating film. Hydrogenation and dehydration treatments are preferred. For example, in an inert gas atmosphere (nitrogen, Heat treatment (400°C or higher) under an oxygen atmosphere (or under helium, neon, argon, etc.) The substrate is subjected to a process (below the strain point) to remove impurities such as hydrogen and water contained within the gate insulating layer. That's all you need to do.

[0080] Next, the resist mask 137 is removed, and the oxide semiconductor film 130 is subjected to a third photolithography. Etching is performed using the resist masks 135a and 135b formed by the Fi process, resulting in islands. It forms island-shaped oxide semiconductor layers 131 and 132 (see Figure 3(A)). Resist masks 135a and 135b for forming a material semiconductor layer are shaped by an inkjet method. It may be done. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, manufacturing costs can be reduced.

[0081] Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. Hydrogenated oxide semiconductor layers 133 and 134 are formed (see Figure 3(B)). Dehydration is performed. Alternatively, the temperature of the first heat treatment for dehydrogenation is preferably 400°C or higher and below the strain point of the substrate. The temperature should be 425°C or higher. Note that if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is below 425℃, the heat treatment time should be longer than 1 hour. Here, The substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is subjected to a nitrogen atmosphere. After heat treatment, water and hydrogen are re-transmitted to the oxide semiconductor layer without exposure to the atmosphere. To prevent contamination and obtain an oxide semiconductor layer, in this embodiment, the oxide semiconductor layer is dehydrated or Using the same furnace, from the heating temperature T for dehydrogenation, the temperature is reduced to a sufficient temperature to prevent water from entering again. Specifically, the temperature is slowly cooled under a nitrogen atmosphere until it drops to more than 100°C below the heating temperature T. Dehydration is not limited to plain atmospheres, but also occurs under noble gas atmospheres such as helium, neon, and argon. Alternatively, dehydrogenation can be performed.

[0082] By heat-treating the oxide semiconductor layer at a temperature of 400°C to 700°C, the oxide semiconductor layer is de-oxidized. Hydration and dehydrogenation are achieved, and subsequent re-impregnation with water (H2O) can be prevented.

[0083] As an example of the mechanism of water desorption in oxide semiconductor films, the following reaction pathway was analyzed. (In oxide semiconductor films, the reaction occurs not only as water, but also as OH or H). An In-Ga-Zn-O amorphous film was used as the conductive film.

[0084] Furthermore, the optimal molecular structure in the ground state of the computational model is determined using density functional theory (DFT). I calculated it. The total energy of the DFT is the potential energy, the electrostatic energy between electrons, and the electrons. The sum of the kinetic energy of the electrons and the exchange-correlation energy, which includes all complex electron-electron interactions, is expressed as follows: In DFT, the exchange-correlation interaction is expressed using the one-electron potential expressed in terms of electron density. Because it approximates using a function (meaning a function of a function), the calculation is fast and highly accurate. Here, Using the B3LYP mixture functional, the weights of each parameter related to exchange and correlation energies are calculated. This was defined. Furthermore, as a basis function, La was used for indium, gallium, and zinc atoms. nL2DZ(Ne shell effective shell potential with split valence ground system added) (basis functions), for other atoms 6-311 (each valence orbital has three short functions) The basis functions of the triple split valence basis system used were applied. Depending on the basis set, for example, in the case of a hydrogen atom, the 1s to 3s orbitals are considered, and also, acid For elementary atoms, the 1s-4s and 2p-4p orbitals will be considered. Furthermore, calculations To improve accuracy, a p-function is added to the hydrogen atom and a d-function to the oxygen atom as the polarization base system. Ta.

[0085] The Gaussian03 quantum chemistry calculation program was used. The test was conducted using a high-performance computer (SGI Altix4700).

[0086] Heat treatment that involves dehydration or dehydrogenation causes the -OH groups contained in the oxide semiconductor film to separate. It is thought that H2O is produced in the reaction. Therefore, the water production and desorption mechanism shown in Figure 39 The cannism was analyzed. Note that in Figure 39, since Zn is divalent, both M1 and M2 are present. If either of the atoms is Zn, then one M'-O bond bonded to Zn will be removed. ru.

[0087] In Figure 39, M represents a metal atom, and there are three types: In, Ga, and Zn. Initial state 1 Then, -OH forms a coordinate bond that bridges M1 and M2. In transition state 2, -O The H in H rearranges to another -OH group. In intermediate state 3, the resulting H2O molecule becomes a metal atom. It forms a coordinate bond. In final state 4, the H2O molecule is eliminated and moves away to infinity.

[0088] The total combinations of (M1-M2) are: 1. In-In, 2. Ga-Ga, 3. Zn-Zn, There are 6 possibilities: 4. In-Ga, 5. In-Zn, 6. Ga-Zn, so all combinations are... Calculations were performed for se. Note that in this calculation, M' was replaced with H for simplification. This was performed using cluster computation with a computational model.

[0089] The calculations obtained the energy diagrams corresponding to the reaction pathways in Figure 39. There are a total of 6 possibilities. As a representative example of the M1-M2 combinations, Figure 40 shows the calculation results for the In-In case. vinegar.

[0090] From Figure 40, it was found that the activation energy for water production is 1.16 eV. When a water molecule is removed, the system becomes unstable by about 1.58 eV.

[0091] Conversely, if we consider Figure 40 as a reaction from right to left, the reaction in which water enters the oxide semiconductor film is This can be observed. When this happens, the water coordinated to the metal undergoes hydrolysis, forming two OH groups. The activation energy for this reaction is 0.47 eV.

[0092] Similarly, the reaction pathways for other (M1-M2) combinations were also analyzed. 1-6 Table 1 shows the activation energy (Ea [eV]) of the water formation reaction in the case of .

[0093] [Table 1]

[0094] Table 1 shows that the water formation reaction is more likely to occur with 1.In-In and 4.In-Ga. In contrast, the water formation reaction is unlikely to occur in Zn-Zn. Therefore, the Zn atom It is presumed that the water formation reaction mediated by this medium is less likely to occur.

[0095] Furthermore, the heating apparatus is not limited to electric furnaces; for example, GRTA (Gas Rapid Th) thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) devices such as Anneal devices It is possible to use a LRTA device with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. The TA device utilizes not only lamps but also heat conduction or thermal radiation from heat-generating elements such as resistive heating elements. It may also be equipped with a device to heat the material to be processed. GRTA is a device that uses high-temperature gas to process This is a method of heat treatment. The gas used is a noble gas such as argon, or a gas such as nitrogen, which is heated. An inert gas that does not react with the material being treated is used during the process. Using the RTA method, 600 Heat treatment at 750°C for several minutes may also be performed.

[0096] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. Preferably, it does not contain water, hydrogen, etc. In particular, for the oxide semiconductor layer, 400°C Dehydration and dehydrogenation heat treatments performed at ~700°C are carried out in a nitrogen atmosphere with H2O at 20 ppm or less. It is preferable to use gas. Alternatively, nitrogen, helium, or neonitrile can be introduced into the heat treatment device. The purity of noble gases such as argon is 6N (99.9999%) or higher, preferably 7N (9 9.99999% or more (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do it as shown below.

[0097] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur, and microcrystalline formation may occur. It may be crystalline or polycrystalline. For example, a crystallinity of 90% or more, or 80% or more. It may also form a microcrystalline oxide semiconductor layer. Furthermore, the conditions of the first heat treatment, or the oxide... Depending on the semiconductor layer material, it may be an amorphous oxide semiconductor that does not contain crystalline components. .

[0098] Furthermore, the first heat treatment of the oxide semiconductor layer is used to process the island-shaped oxide semiconductor layers 131 and 132. It can also be performed on the oxide semiconductor film 130 before the first heat treatment. In that case, after the first heat treatment The substrate is then removed from the heating device, and the photolithography process is performed.

[0099] Dehydration and dehydrogenation heat treatments for oxide semiconductor layers are performed after the oxide semiconductor layer is formed. After stacking source electrodes and drain electrodes on a conductive layer, on the source electrodes and drain electrodes This can be done either after forming a passivation film.

[0100] Furthermore, contact holes 118 and 119 are provided in the gate insulating layer 102 as shown in Figure 2(C). The formation process is carried out after the oxide semiconductor film 130 has been subjected to dehydration or dehydrogenation treatment. That's good too.

[0101] Note that the etching of oxide semiconductor films here is not limited to wet etching, but also includes dry etching. Etching may be used.

[0102] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4, etc., are preferred.

[0103] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S)) F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and these gases can be mixed with noble gases such as helium (He) and argon (Ar). Gases with added sulfites, etc., can be used.

[0104] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0105] Etching solutions used in wet etching include a solution of phosphoric acid, acetic acid, and nitric acid. This can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0106] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced. .

[0107] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired processing shape can be etched.

[0108] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layers 133 and 134 by sputtering or vacuum evaporation.

[0109] As the material of the metal conductive film, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W , an alloy containing the above-described elements as components, or an alloy film formed by combining the above-described elements, etc. can be mentioned. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a Ti film, an aluminum film is laminated on top of the Ti film, and a Ti film is formed on top of that, etc. can be mentioned. Also, for Al, titanium (Ti), tantalum (T a), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), an alloy film in which an element selected from scandium (Sc) is combined singly or in plural, or a nitride film may be used.

[0110] When performing a heat treatment after forming the metal conductive film, it is preferable to give the metal conductive film heat resistance that can withstand this heat treatment.

[0111] Next, a fourth photolithography process is performed, and resist masks 136a, 136b, 13 Form 6c, 136d, 136e, and 136f, and remove unnecessary parts by etching the metal conductive film to form the source electrode layer 105a, drain electrode layer 105b, source electrode layer 165a, drain electrode layer 165b, connection electrode 120, and second terminal 122 (see Fig. 3(C )). )).

[0112] Note that when etching the metal conductive film, the oxide semiconductor layers 133 and 134 are not removed. Appropriately adjust the respective materials and etching conditions as needed.

[0113] In this embodiment, a Ti film is used as the metal conductive film, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layers 133 and 134, and aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0114] In this fourth photolithography process, form the connection electrode 120 and the second terminal 122, which are made of the same material as the source electrode layer 105a, 165a, drain electrode layer 105b, 165b, at the terminal portions respectively. Note that the second terminal 122 is electrically connected to the source wiring (the source wiring including the source electrode layers 105a, 165a). Also, the connection electrode 120 is formed in contact with the first terminal 121 at the contact hole 119 and is electrically connected.

[0115] Note that the resist masks 136a, 136b, 136c, 136d, 136e, 136f for forming the source electrode layer and the drain electrode layer may be formed by the inkjet method. When forming the resist mask by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0116] Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are Remove the oxide insulating film 107 which will become a protective insulating film in contact with the oxide semiconductor layers 133 and 134. To form.

[0117] At this stage, regions are formed in which the oxide semiconductor layers 133 and 134 are in contact with the oxide insulating film. Within this region, the gate electrode layer overlaps with the oxide insulating film 107 via the gate insulating layer. The overlapping region becomes the channel-forming region.

[0118] The oxide insulating film 107 has a thickness of at least 1 nm, and is manufactured by an oxidation process such as sputtering. The insulating film 107 can be formed using an appropriate method that prevents the inclusion of impurities such as water and hydrogen. It is possible. When hydrogen is present in the oxide insulating film 107, the hydrogen penetrates into the oxide semiconductor layer, This is due to the abstraction of oxygen from the oxide semiconductor layer by hydrogen, resulting in back channels in the oxide semiconductor layer. The resistance of the film is reduced (becoming N-type), and parasitic channels are formed. Therefore, the oxide insulating film becomes less resistant. To ensure that 107 contains as little hydrogen as possible, the film deposition method should avoid using hydrogen. It is essential.

[0119] In this embodiment, a silicon oxide film with a thickness of 300 nm is sputtered as the oxide insulating film 107. The film is deposited using the densitometry method. The substrate temperature during film deposition should be between room temperature and 300°C. In this embodiment, the temperature is set to room temperature. The silicon oxide film is deposited by sputtering using a rare gas (representative). It can be carried out under an argon atmosphere or an oxygen atmosphere. A silicon dioxide target or a silicon target can be used as the target. For example, By using a silicon target, silicon oxide is formed by sputtering in an oxygen atmosphere. It is possible. An oxide insulating film formed in contact with the oxide semiconductor layer whose resistance has been reduced by the first heat treatment does not contain moisture, hydrogen ions, impurities such as OH, and blocks the intrusion of these from the outside. An inorganic insulating film is used, and typically, a silicon oxide film, a silicon oxynitride film, a gallium oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH, and blocks the intrusion of these from the outside. - It is possible. An oxide insulating film formed in contact with the oxide semiconductor layer whose resistance has been reduced by the first heat treatment does not contain moisture, hydrogen ions, impurities such as OH, and blocks the intrusion of these from the outside. An inorganic insulating film is used, and typically, a silicon oxide film, a silicon oxynitride film, a gallium oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. An inorganic insulating film is used, and typically, a silicon oxide film, a silicon oxynitride film, a gallium oxide film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0120] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 4(A)). Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 4(A)). For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 that overlap with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 that overlap with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 that overlap with the oxide insulating film 107 is heated in a state of being in contact with the oxide insulating film 107.

[0121]

[0122] Region 117b is formed self-aligned with the oxide semiconductor layer 103.

[0123] Note that the drain electrode layers 105b, 165b (and source electrode layers 105a, 165a) overlap. In the folded oxide semiconductor layers 103 and 163, high-resistance drain regions 117b and 167b ( Alternatively, by forming high-resistance source regions 117a, 167a), when the circuit is formed Reliability can be improved. Specifically, the high-resistance drain regions 117b and 167b By forming the drain electrode layers 105b and 165b, the high-resistance drain region 117b ,167b, and channel formation regions 116, 166, the conductivity can be changed in steps. Such a structure can be created. Therefore, a high power supply can be provided to the drain electrode layers 105b and 165b. When operating by connecting to the wiring that supplies the potential VDD, the gate electrode layers 101, 161 and Even when a high electric field is applied between the rain electrode layers 105b and 165b, the high-resistance drain region remains This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage. It is possible.

[0124] Furthermore, the drain electrode layers 105b, 165b (and source electrode layers 105a, 165a) overlap In the folded oxide semiconductor layer, high-resistance drain regions 117b, 167b (or high-resistance drain regions) By forming channel regions 117a and 167a, the channel formation region when the circuit is formed This allows for a reduction in leakage current in regions 116 and 166.

[0125] In this embodiment, a silicon oxide film is formed as the oxide insulating film 107 by sputtering. After formation, heat treatment is performed at 250°C to 350°C to remove the oxide between the source and drain regions. Oxygen is impregnated and diffused into the oxide semiconductor layer from the exposed portion (channel formation region) of the semiconductor layer. The process involves creating a silicon oxide film using the sputtering method, thereby removing excess oxygen from the silicon oxide film. It is possible to incorporate oxygen, and this oxygen can be impregnated and diffused into the oxide semiconductor layer by heat treatment. This is possible. The channel formation region can be made highly resistant by the impregnation and diffusion of oxygen into the oxide semiconductor layer. This allows for conversion to an i-type transistor. As a result, a normally-off thin-film transistor can be created. You can obtain this.

[0126] Through the above process, a thin-film transistor 180 is installed in the drive circuit section and a pixel section is installed on the same substrate. Thin-film transistor 170 can be fabricated. Thin-film transistors 170 and 180 are an oxide semiconductor layer including a high-resistance source region, a high-resistance drain region, and a channel-forming region. This is a bottom-gate thin-film transistor that includes [a specific component]. Therefore, thin-film transistors 170 and 18... 0 means that even when a high electric field is applied, the high-resistance drain region or high-resistance source region acts as a buffer. This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage.

[0127] By forming the drive circuit section and the pixel section on the same substrate, the connection between the drive circuit and external signals is improved. Wiring can be shortened, enabling miniaturization and cost reduction of semiconductor devices.

[0128] A protective insulating layer may be formed on the oxide insulating film 107. For example, RF sputtering A silicon nitride film is formed using the sputtering method. RF sputtering is suitable for mass production, and therefore protects This is a preferred method for forming an insulating layer. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - etc. Using an inorganic insulating film that is free of impurities and blocks their intrusion from the outside, nitridation Silicon films, aluminum nitride films, silicon nitride oxide films, aluminum oxide nitride films, etc., are used.

[0129] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating film 1 Etching of 07 forms a contact hole 125 that reaches the drain electrode layer 105b. Then, remove the resist mask (see Figure 4(B)). Also, etching here The contact hole 127 reaches the second terminal 122, and the contact hole reaches the connecting electrode 120. A contact hole 126 is also formed. Furthermore, a resist mask is used to form the contact hole. The resist mask may be formed by an inkjet method. Because it does not use a photomask, manufacturing costs can be reduced.

[0130] Next, a light-transmitting conductive film is formed. The material for the light-transmitting conductive film is an oxide Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT These are formed using sputtering or vacuum deposition methods (abbreviated as O). As another material for conductive films, there is a nitrogen-containing Al-Zn-O non-single crystal film, i.e., Al- Zn-ON non-single crystal films, nitrogen-containing Zn-O non-single crystal films, and nitrogen-containing Sn-Zn-O non-single crystal films may also be used. Furthermore, Al-Zn-ON non-single crystal films may also be used. The composition ratio (atomic %) of zinc shall be 47 atomic % or less, and the composition ratio of aluminum in the non-single crystal film The composition ratio of aluminum in a non-single crystal film (atomic %) is greater than (atomic %), and the composition ratio of aluminum in a non-single crystal film (atomic %) is greater than (atomic %). The nitrogen content (atomic %) is greater than the composition ratio within it. Etching treatment of such materials is performed using hydrochloric acid-based solutions. This is done using a solution. However, etching ITO in particular tends to generate residue, so etching Even when using indium zinc oxide alloy (In2O3-ZnO) to improve machinability good.

[0131] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and the electron beam microanalyzer... (EPMA:Electron Probe X-ray MicroAnalyzer The evaluation shall be conducted by analysis using ).

[0132] Next, a sixth photolithography step is performed to form a resist mask, and etching is performed. Unnecessary portions of the light-transmitting conductive film are removed to form the pixel electrode layer 110, conductive layer 111, and terminals. Electrodes 128 and 129 are formed, and the resist mask is removed. A cross-sectional view at this stage is shown in Figure 4. This is shown in C). Note that the plan view at this stage corresponds to Figure 5.

[0133] Furthermore, in this sixth photolithography process, the gate insulating layer 102 in the capacitance section And the oxide insulating film 107 is used as a dielectric, and the capacitance wiring 108 and the pixel electrode layer 110 are held together. A quantity is formed.

[0134] The gate insulating layer 102 is used as a dielectric and is formed with capacitive wiring and capacitive electrodes (also called a capacitive electrode layer). The capacitance 147, which is the retaining capacitance, can also be formed on the same substrate. Furthermore, the capacitance wiring Without providing a separate element, the pixel electrodes are connected to the gate wiring of adjacent pixels via a protective insulating film and gate insulating layer. It may be formed by laying down to create a retention capacity.

[0135] The terminal electrodes 128 and 129 formed on the terminal portion are electrodes or connections used for connecting to the FPC. It becomes a line. The terminal electrode 128 formed on the first terminal 121 via the connecting electrode 120 is It serves as a connecting terminal electrode that functions as an input terminal for gate wiring. The formed terminal electrode 129 is a connecting terminal electrode that functions as an input terminal for the source wiring. ru.

[0136] Furthermore, Figures 11(A1) and 11(A2) show the top view of the gate wiring terminal section at this stage and Cross-sectional views are shown for each. Figure 11(A1) is along the line C1-C2 in Figure 11(A2) This corresponds to a cross-sectional view. In Figure 11(A1), the conductive film formed on the oxide insulating film 107 The film 155 is a terminal electrode for connection that functions as an input terminal. Also, see Figure 11(A1) In the terminal section, there is a first terminal 151 formed of the same material as the gate wiring, and a source The connecting electrode 153, which is formed from the same material as the wiring, overlaps with the gate insulating layer 102 and directly They are in contact and electrically connected. Also, the connecting electrode 153 and the conductive film 155 are provided in the oxide insulating film 107. Electrical conductivity is established through direct contact via the cut-out contact holes.

[0137] Furthermore, Figures 11(B1) and 11(B2) show the top view and cross-sectional view of the source wiring terminal section. Each is illustrated. Also, Figure 11(B1) follows the line D1-D2 in Figure 11(B2). This corresponds to a cross-sectional view. In Figure 11(B1), a conductive film is formed on the oxide insulating film 107. The film 155 is a terminal electrode for connection that functions as an input terminal. Also, in Figure 11(B1) In the terminal section, an electrode 156, formed from the same material as the gate wiring, is connected to the source wiring. It overlaps below the second terminal 150, which is gas-connected, via the gate insulating layer 102. Electrode 1 56 is not electrically connected to the second terminal 150, and electrode 156 is not electrically connected to the second terminal 150. Setting to different potentials, such as floating, GND, or 0V, can help with noise reduction. It can form capacitance or capacitance for electrostatic discharge protection. Also, the second terminal 150 It is electrically connected to the conductive film 155 via the oxide insulating film 107.

[0138] Gate wiring, source wiring, and capacitive wiring are arranged in multiples depending on the pixel density. Furthermore, at the terminal section, there is a first terminal at the same potential as the gate wiring, and a second terminal at the same potential as the source wiring. Multiple terminals, such as terminal 2 and a third terminal at the same potential as the capacitance wiring, are arranged in a row. The number of terminals can be any number desired, and the implementer may decide this as appropriate.

[0139] Thus, through six photolithography steps, six photomasks are used to create a thin film. A drive circuit section having a transistor 180, a pixel section having a thin-film transistor 170, and a holding capacity A capacity 147 with a certain amount of volume and an external output terminal can be completed. The pixel section is constructed by arranging the zista and retention capacitance in a matrix corresponding to each individual pixel, and This can be used as one of the substrates for fabricating a dual-matrix type display device. For convenience, this type of substrate is referred to as an active matrix substrate in this book.

[0140] When manufacturing an active-matrix liquid crystal display device, an active-matrix substrate is used. A liquid crystal layer is provided between the opposing substrate on which the opposing electrode is located, and the active matrix substrate and The opposing substrate is fixed in place. Furthermore, a common electrical connection is made between the opposing electrode provided on the opposing substrate and the opposing electrode. The electrodes are provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. It is provided in the section. This fourth terminal sets the common electrode to a fixed potential, for example, GND, 0V, etc. This is a terminal for that purpose.

[0141] An insulating layer functioning as an alignment layer is placed on the oxide insulating film 107, the conductive layer 111, and the pixel electrode layer 110. Forms 191.

[0142] On the opposing substrate 190, there is a colored layer 195, an opposing electrode layer 194, and an insulating layer 19 that functions as an alignment film. Form 3. The substrate 100 and the opposing substrate 190 are used to adjust the cell gap of the liquid crystal display device. The liquid crystal layer 192 is sandwiched between spacers and bonded together with a sealing material (not shown). The above bonding process may be carried out under reduced pressure.

[0143] Typical sealing materials used are visible light-curable, ultraviolet-curable, or thermosetting resins. It is preferable to use acrylic resin, epoxy resin, amine resin, etc. This can be done. Also, light (typically ultraviolet) polymerization initiators, thermosetting agents, fillers, and couplers can be used. It may contain a lubricant.

[0144] The liquid crystal layer 192 is formed by sealing liquid crystal material in the void. The liquid crystal layer 192 is opposite the substrate 100. A dispenser method (dropping method) may be used in which the material is dropped before bonding it to the substrate 190. After bonding the substrate 100 and the opposing substrate 190 together, liquid crystal is injected using capillary action. The injection method can be used. There are no particular limitations on the liquid crystal material; various materials can be used. This can be done. Furthermore, if a material exhibiting a blue phase is used as the liquid crystal material, an alignment film can be eliminated. It is possible.

[0145] A polarizing plate 196a is provided on the outside of substrate 100, and a polarizing plate 196b is provided on the outside of opposing substrate 190. This allows for the fabrication of a transmissive liquid crystal display device according to this embodiment (see Figure 1).

[0146] In addition, although not shown in this embodiment, a black matrix (light-shielding layer), a polarizing member, and a phase Optical components (optical substrates) such as polarizing members and anti-reflective members are provided as appropriate. For example, polarizing substrate Circular polarization using a phase difference substrate may also be used. Furthermore, a backlight and sidelight may be used as light sources. You can also use thread or similar materials.

[0147] In an active-matrix liquid crystal display device, pixel electrodes are arranged in a matrix. By driving the pixels, a display pattern is formed on the screen. For details, see the selected pixels. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode, Optical modulation is performed on the liquid crystal layer placed between the electrode and the counter electrode, and this optical modulation is used to create a display pattern. It is perceived by the observer as such.

[0148] In the display of motion on liquid crystal displays, afterimages occur because the response of the liquid crystal molecules themselves is slow. This has the problem of causing blurring in videos. In order to improve the video characteristics of liquid crystal display devices, the entire surface There is a driving technique called black insertion, which involves displaying a black screen every other frame.

[0149] Furthermore, by increasing the vertical synchronization frequency to 1.5 times, preferably 2 times or more, the video characteristics are improved. There is also a drive technology that improves performance, known as double-speed drive.

[0150] Furthermore, in order to improve the video characteristics of the liquid crystal display device, multiple LEDs (light emission) are used as the backlight. A surface light source is constructed using a diode light source or multiple EL light sources, and the surface light source is constructed There is also a driving technology that drives each light source independently to intermittently light up within a single frame period. You may use three or more types of LEDs, or you may use white-emitting LEDs. Because it can control multiple LEDs, the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. It is also possible to synchronize the timing of the light emission of D. This driving technology partially turns off the LEDs. This is especially useful for video displays where a large proportion of the screen is black. This can lead to a reduction in power consumption.

[0151] By combining these driving technologies, the display characteristics of liquid crystal display devices, such as the motion characteristics, can be improved. This can be improved compared to the previous method.

[0152] By forming it with a thin-film transistor using an oxide semiconductor, manufacturing costs can be reduced. This can be achieved. In particular, by the above method, an oxide insulating film can be formed in contact with the oxide semiconductor layer. By doing so, we can fabricate and provide thin-film transistors with stable electrical characteristics. Therefore, we propose a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability. It can be provided.

[0153] Since the semiconductor layer in the channel formation region is a high-resistivity region, the electrical characteristics of the thin-film transistor are It stabilizes the system and prevents increases in off-current, etc. Therefore, it has good electrical characteristics and is reliable. This makes it possible to create a semiconductor device with high-performance thin-film transistors.

[0154] Furthermore, thin-film transistors are susceptible to damage from static electricity, etc., so the pixel area or driving circuit It is preferable to provide the protection circuit on the same substrate. The protection circuit uses an oxide semiconductor layer. It is preferable to use nonlinear elements in the configuration. For example, the protection circuit consists of a pixel section and a scan line input It is arranged between the terminal and the signal line input terminal. In this embodiment, multiple protection circuits are arranged. When a surge voltage is applied to the scan line, signal line, and capacitive bus line due to static electricity, the pixel It is designed to prevent damage to transistors and other components. Therefore, the protection circuit is designed to protect against surge currents. The circuit is configured to release charge to the common wiring when pressure is applied. Furthermore, the protection circuit is designed to allow the run It is composed of nonlinear elements arranged in parallel between the inspection lines and common wiring. The child is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it is also possible to form it using the same process as the thin-film transistor 170 of the pixel portion. For example, by connecting the gate terminal and drain terminal of a transistor, the same principle as a diode is achieved. It can be given special characteristics.

[0155] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0156] (Embodiment 2) In this embodiment, in Embodiment 1, the oxide semiconductor layer and the source electrode layer or drain Figure 6 shows an example of providing an oxide conductive layer as a source region and a drain region between the electrode layer and the electrode layer. This is shown in Figure 7. Therefore, the rest can be carried out in the same manner as in Embodiment 1, and some parts are the same as in Embodiment 1. The explanation of parts with a similar function or the repetition of the process will be omitted. Also, Figure 6 and Figure 7 is the same as Figures 1 through 5 except for some differences in the process, therefore the same symbols are used in the same locations. We will use a number and omit detailed explanations of the same section.

[0157] First, we will carry out the steps up to Figure 3(B) in Embodiment 1 according to Embodiment 1. Figure 6( A) is identical to Figure 3(B).

[0158] An oxide conductive film 140 is formed on dehydrated or dehydrogenated oxide semiconductor layers 133 and 134. A metal conductive film made of a metal conductive material is then laminated onto the oxide conductive film 140.

[0159] The deposition method for oxide conductive film 140 includes sputtering and vacuum deposition (electron beam deposition). Alternatively, arc discharge ion plating or spray method can be used. Oxide conductive film 14 As for material 0, it is preferable to have one that contains zinc oxide as a component and does not contain indium oxide. It is preferable that the oxide conductive film 140 is zinc oxide, pseudo oxide Lead-aluminum, zinc-aluminum oxynitride, zinc-gallium oxide, etc. can be applied. The film thickness should be appropriately selected within the range of 50 nm to 300 nm. Also, sputtering When using this method, a target containing 2% to 10% by weight of SiO2 is used for film deposition. This process involves incorporating SiOx (X>0) into the oxide conductive film to inhibit crystallization, and then performing the de-icing process in a later step. It is preferable to suppress crystallization during heat treatment for hydration or dehydrogenation. stomach.

[0160] Next, the fourth photolithography process is performed, and resist masks 136a, 136b, 13 Form 6c, 136d, 136e, and 136f, and etch away unwanted parts of the metal conductive film. After removing the material, the source electrode layer 105a, drain electrode layer 105b, and source electrode layer 165a are separated. The drain electrode layer 165b, connecting electrode 120, and second terminal 122 are formed (Figure 6(B) )reference.).

[0161] Furthermore, during etching of the metal conductive film, the oxide conductive film 140 and the oxide semiconductor layer 133, Adjust the materials and etching conditions accordingly to ensure that 134 is not removed.

[0162] Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are Remove the source electrode layer 105a, drain electrode layer 105b, source electrode layer 165a, and drain Using the in electrode layer 165b as a mask, the oxide conductive film 140 is etched, and the oxide conductive layer Form 164a, 164b, and oxide conductive layers 104a, 104b (see Figure 6(C)). The oxide conductive film 140, which has zinc oxide as a component, is an alkaline substance such as a resist stripping solution. It can be easily etched using a recyclable solution. In the same process, oxide can also be applied to the terminal portion. Conductive layers 138 and 139 are formed.

[0163] By utilizing the difference in etching rates between the oxide semiconductor layer and the oxide conductive film, a channel formation region is created. To achieve this, an etching process is performed to divide the oxide conductive film. By taking advantage of the fact that the ching rate is faster compared to the oxide semiconductor layer, the oxide on the oxide semiconductor layer Selectively etches the conductive film.

[0164] Therefore, resist masks 136a, 136b, 136c, 136d, 136e, 136f Removal of the material is preferably done by an ashing process. Etching using a stripping solution In this case, the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are excessively etched. To prevent this, adjust the etching conditions (etchant type, concentration, etching time) as appropriate. To arrange.

[0165] As in this embodiment, after etching the oxide semiconductor layer in an island shape, the oxide conductive film and gold A wiring pattern is created by laminating conductive films and using the same mask to include the source electrode layer and the drain electrode layer. By etching the metal conductive film, the oxide conductive film is left behind beneath the wiring pattern of the metal conductive film. It can be made to happen.

[0166] In the contact between the gate wiring (conductive layer 162) and the source wiring (drain electrode layer 165b) However, because an oxide conductive layer 164b is formed beneath the source wiring, The conductive layer 164b preferably acts as a buffer, and furthermore, it does not form an insulating oxide with the metal. That is preferable.

[0167] An oxide insulating film 107 is formed, which will serve as a protective insulating film in contact with the oxide semiconductor layers 133 and 134. In this embodiment, a silicon oxide film with a thickness of 300 nm is used as the oxide insulating film 107, The film is deposited using the taring method.

[0168] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide insulation A portion of the oxide semiconductor layers 133 and 134 that overlap with film 107 is in contact with the oxide insulating film 107. It is heated in a certain state.

[0169] Through the above process, the oxide semiconductor layer after film formation is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor layer is selectively treated to reduce oxygen content. This is the state.

[0170] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. Region 166 is type I and has a high resistance that overlaps with the source electrode layer 165a and the oxide conductive layer 164a. The anti-source region 167a and the high overlapping the drain electrode layer 165b and the oxide conductive layer 164b The resistive drain region 167b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel formation region 116 becomes type I. A high-resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a, High-resistance drain region 117b overlapping the drain electrode layer 105b and the oxide conductive layer 104b These are formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

[0171] Oxide semiconductor layers 163, 103 and a drain electrode layer 105b made of a metal material, drain The oxide conductive layers 104b and 164b, positioned between the pole layers 165b, are low-resistance drain regions. LRN (Low Resistance N-type conductivity) area It also functions as a region (also called the LRD (Low Resistance Drain) region). Similarly, the oxide semiconductor layers 163 and 103 and the source electrode layer 105a made of a metal material. The oxide conductive layers 104a and 164a, which are placed between the source electrode layers 165a, are low-resistance so LRN (Low Resistance N-type conduction) (Also called the ty) region, or LRS (Low Resistance Source) region) It still functions. The drain electrode consists of an oxide semiconductor layer, a low-resistance drain region, and a metallic material. By using a layered configuration, the transistor's voltage rating can be further improved. In general, the carrier concentration in the low-resistance drain region is higher than in the high-resistance drain region (HRD region). It can also be large, for example, 1 x 10 20 / cm 3 The above 1 x 10 21 / cm 3Within the following range preferable.

[0172] Through the above process, a thin-film transistor 181 is installed in the drive circuit section and a pixel section is installed on the same substrate. Thin-film transistor 171 can be fabricated. Thin-film transistors 171 and 181 are an oxide semiconductor layer including a high-resistance source region, a high-resistance drain region, and a channel-forming region. This is a bottom-gate thin-film transistor that includes [a specific component]. Therefore, thin-film transistors 171 and 18... 1. Even when a high electric field is applied, the high-resistance drain region or high-resistance source region acts as a buffer. This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage.

[0173] Furthermore, in the capacitance section, the capacitance wiring 108, gate insulating layer 102, oxide conductive layer 104b and The oxide conductive layer and drain electrode layer 105b formed in the same process and the metal conductive layer formed in the same process A capacitance 146 is formed by lamination of the electrolayer and the oxide insulating film 107.

[0174] Next, a planar insulating layer 109 is formed on the oxide insulating film 107. The planar insulating layer 109 is formed only in the pixel area. As for the planar insulating layer 109, Heat-resistant materials such as imides, acrylics, benzocyclobutenes, polyamides, and epoxys. The materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. ), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved by stacking multiple insulating films made of these materials. A chemical insulating layer 109 may be formed.

[0175] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0176] The method for forming the planar insulating layer 109 is not particularly limited and may vary depending on the material, such as sputtering. SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, Screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater A tamper, knife coater, etc. can be used. In this embodiment, the planarized insulating layer 109 It is formed using photosensitive acrylic.

[0177] Next, a fifth photolithography step is performed to form a resist mask and a planar insulating layer 1 09, and etching of the oxide insulating film 107 leads to the drain electrode layer 105b. Tact holes 125 are formed to remove the resist mask (see Figure 6(D)). Also, Etching here creates a contact hole 127 that reaches the second terminal 122, and a connecting electrode. It also forms 120 contact holes 126.

[0178] Next, a translucent conductive film is formed, and a sixth photolithography step is performed to create a resist. A mask is formed, and unnecessary parts are removed by etching to form the pixel electrode layer 110 and the conductive layer 11 1. Form terminal electrodes 128 and 129 and remove the resist mask (see Figure 7(A)). .

[0179] Similar to Embodiment 1, the liquid crystal layer 192 is sandwiched and the opposing substrate 190 is bonded together, and in this embodiment... A liquid crystal display device of the specified form is fabricated (see Figure 7(B)).

[0180] The source region and drain region consist of an oxide conductive layer, an oxide semiconductor layer and a source electrode layer and By placing it between the drain electrode layer, the resistance of the source region and the drain region can be reduced. This enables high-speed operation of the transistor. The use of an oxide conductive layer is to improve the frequency characteristics of the peripheral circuit (drive circuit). It is effective for this purpose. Compared to contact between a metal electrode (Ti, etc.) and an oxide semiconductor layer, This is because contact between the ) and the oxide conductive layer can reduce contact resistance.

[0181] Furthermore, molybdenum (Mo), which is used as part of the wiring material in liquid crystal panels, is (for example) The high contact resistance with the oxide semiconductor layer (Mo / Al / Mo) was a problem. Compared to i, Mo is less prone to oxidation, so its effect of extracting oxygen from the oxide semiconductor layer is weaker, and Mo and This is because the contact interface of the oxide semiconductor layer does not become n-type. However, even in such cases, the oxide By interposing an oxide conductive layer between the semiconductor layer and the source electrode layer and drain electrode layer, contact is established. This reduces contact resistance and improves the frequency characteristics of the surrounding circuitry (drive circuitry).

[0182] The channel length of a thin-film transistor is determined during the etching of the oxide conductive layer, therefore It is possible to shorten the channel length. For example, the channel length can be shortened to 0.1 μm or more and 2 μm or less. It can increase the operating speed.

[0183] (Embodiment 3) In this embodiment, in Embodiment 1 or Embodiment 2, the oxide semiconductor layer and the source electric An oxide conductive layer is provided between the polar layer and the drain electrode layer, serving as the source region and the drain region. Other examples are shown in Figures 8 and 9. Therefore, the rest are the same as in Embodiment 1 or Embodiment 2. This can be done, and involves parts that are the same as or have the same function as those in Embodiment 1 or Embodiment 2. The explanation of the repetition of the process will be omitted. Also, Figures 8 and 9 show the process as shown in Figures 1 to 7. Since they are the same except for a few differences, the same symbols are used for the same parts, and the detailed explanation of the same parts is also used. The "Akira" part will be omitted.

[0184] First, according to Embodiment 1, a metal conductive film is formed on the substrate 100, and the metal conductive film is first Etching is performed using a resist mask formed by a photolithography process, and the first edge Child 121, gate electrode layer 161, conductive layer 162, gate electrode layer 101, capacitive wiring 108 To form.

[0185] Next, the first terminal 121, gate electrode layer 161, conductive layer 162, gate electrode layer 101, A gate insulating layer 102 is formed on the wiring 108, and an oxide semiconductor film and an oxide conductive film are laminated. The gate insulating layer, oxide semiconductor film, and oxide conductive film are continuously deposited without exposure to the atmosphere. It is possible.

[0186] A resist mask is formed on the oxide conductive film by a second photolithography process. Using a stoichiometric mask, the gate insulating layer, oxide semiconductor film, and oxide conductive film are etched. Contact hole 119 reaching the first terminal 121, contact hole reaching the conductive layer 162 Forms a ring 118.

[0187] The resist mask is removed by a second photolithography step, and then the oxide conductive film is applied. A resist mask is formed by the photolithography process in step 3. Third photolithograph Island-shaped oxide semiconductor layers and oxide conductive layers are formed using a resist mask produced by the I process.

[0188] In this way, with the oxide semiconductor film and the oxide conductive film laminated across the entire surface of the gate insulating layer, When a process is performed to form contact holes in the gate insulating layer, a resist is formed on the surface of the gate insulating layer. Because the screw does not come into direct contact, contamination of the gate insulating layer surface (adhesion of impurities, etc.) is prevented. Yes, it is possible. Therefore, the interface between the gate insulating layer and the oxide semiconductor film and oxide conductive film is kept good. This allows for improved reliability.

[0189] Next, the oxide semiconductor layer and the oxide conductive layer are subjected to dehydration and dehydrogenation heat treatment while stacked. This process involves heat treatment at temperatures between 400°C and 700°C to dehydrate the oxide semiconductor layer and remove Hydrogenation is achieved, preventing subsequent re-impregnation with water (H2O).

[0190] This heat treatment ensures that the oxide conductive layer does not contain crystallization inhibiting substances such as silicon oxide. The oxide conductive layer then crystallizes. The crystals in the oxide conductive layer grow in a columnar shape relative to the substrate. As a result, in order to form the source electrode layer and the drain electrode layer, the gold on top of the oxide conductive layer When etching a conductive film, it is possible to prevent the formation of undercuts.

[0191] Furthermore, the conductivity of the oxide conductive layer is improved by heat treatment to dehydrate and dehydrogenate the oxide semiconductor layer. This can be achieved. Furthermore, the oxide conductive layer can be heat-treated at a lower temperature than the oxide semiconductor layer. It's okay to do so.

[0192] Furthermore, the first heat treatment of the oxide semiconductor layer and the oxide conductive layer is performed on the island-shaped oxide semiconductor layer and This can also be done on oxide semiconductor films and oxide conductive films before they are processed into oxide conductive layers. In some cases, after the first heat treatment, the substrate is removed from the heating device and proceeds to the photolithography process. To do so.

[0193] Through the above process, oxide semiconductor layers 133, 134 and oxide conductive layers 142, 143 are obtained. (See Figure 8(A).) Oxide semiconductor layer 133 and oxide conductive layer 142, oxide semiconductor layer Layers 134 and 143 are island-like laminates formed using the same mask. ru.

[0194] Next, the fourth photolithography process is performed, and resist masks 136a, 136b, 13 Form 6c, 136d, 136e, and 136f, and etch away unwanted parts of the metal conductive film. After removing the material, the source electrode layer 105a, drain electrode layer 105b, and source electrode layer 165a are separated. The drain electrode layer 165b, the connecting electrode 120, and the second terminal 122 are formed (Figure 8(B) )reference.).

[0195] Furthermore, during etching of the metal conductive film, the oxide conductive layers 142, 143 and the oxide semiconductor layer Adjust the respective materials and etching conditions as needed to ensure that 133 and 134 are not removed. .

[0196] Next, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f are Remove the source electrode layer 105a, drain electrode layer 105b, source electrode layer 165a, and drain Using the in electrode layer 165b as a mask, the oxide conductive layers 142 and 143 are etched, and oxidation The material conductive layers 164a and 164b and the oxide conductive layers 104a and 104b are formed (Figure 8(C)). (See reference.) The oxide conductive layers 142 and 143, which have zinc oxide as a component, are, for example, the peeling of the resist. It can be easily etched using an alkaline solution such as a liquid.

[0197] Therefore, resist masks 136a, 136b, 136c, 136d, 136e, 136f Removal of the material is preferably done by an ashing process. Etching using a stripping solution In this case, the oxide conductive layers 142, 143 and the oxide semiconductor layers 133, 134 are excessively etched. To prevent chipping, the etching conditions (type of etchant, concentration, etching time) Adjust as appropriate.

[0198] An oxide insulating film 107 is formed, which will serve as a protective insulating film in contact with the oxide semiconductor layers 133 and 134. In this embodiment, a silicon oxide film with a thickness of 300 nm is used as the oxide insulating film 107, The film is deposited using the taring method.

[0199] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide insulation A portion of the oxide semiconductor layers 133 and 134 that overlap with film 107 is in contact with the oxide insulating film 107. It is heated in a certain state.

[0200] Through the above process, the oxide semiconductor layer after film formation is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor layer is selectively treated to reduce oxygen content. This is the state.

[0201] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. Region 166 is type I and has a high resistance that overlaps with the source electrode layer 165a and the oxide conductive layer 164a. The anti-source region 167a and the high overlapping the drain electrode layer 165b and the oxide conductive layer 164b The resistive drain region 167b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, a channel is formed that overlaps with the gate electrode layer 101. Region 116 is of type I and overlaps with the source electrode layer 105a and the oxide conductive layer 104a. The resistive source region 117a overlaps with the drain electrode layer 105b and the oxide conductive layer 104b. A high-resistance drain region 117b is formed in a self-aligned manner, and an oxide semiconductor layer 103 is formed. It can be done.

[0202] Oxide semiconductor layers 163, 103 and a drain electrode layer 105b made of a metal material, drain The oxide conductive layers 104b and 164b, positioned between the pole layers 165b, are low-resistance drain regions. It also functions as an LRN region (also called an LRD region). Similarly, oxide semiconductor layer 163, It is placed between the source electrode layer 105a and source electrode layer 165a, which are made of a metal material and 103. The oxide conductive layers 104a and 164a are low-resistance source regions (also called LRN regions and LRS regions). It also functions as a drain. It consists of an oxide semiconductor layer, a low-resistance drain region, and a metal material. By using this electrode layer configuration, the transistor's breakdown voltage can be further improved. Specifically, the carrier concentration in the low-resistance drain region is lower in the high-resistance drain region (HRD region). Larger than ), for example, 1 × 10 20 / cm 3 The above 1 x 10 21 / cm 3 Within the following range It would be desirable to have it.

[0203] Through the above process, a thin-film transistor 182 is formed in the drive circuit section and a pixel section on the same substrate. Thin-film transistor 172 can be fabricated. Thin-film transistors 172 and 182 are an oxide semiconductor layer including a high-resistance source region, a high-resistance drain region, and a channel-forming region. This is a bottom-gate thin-film transistor that includes [a specific component]. Therefore, thin-film transistors 172 and 18... 2. Even when a high electric field is applied, the high-resistance drain region or high-resistance source region acts as a buffer. This configuration prevents the application of a localized high electric field, thereby improving the transistor's breakdown voltage.

[0204] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating film 1 Etching of 07 forms a contact hole 125 that reaches the drain electrode layer 105b. Then, remove the resist mask (see Figure 8(D)). Also, etching at this stage Contact hole 127 reaching the second terminal 122, contact reaching the connecting electrode 120 Hole 126 is also formed.

[0205] Next, a translucent conductive film is formed, and a sixth photolithography step is performed to create a resist. A mask is formed, and unnecessary parts are removed by etching to form the pixel electrode layer 110 and the conductive layer 11 1. Form terminal electrodes 128 and 129 and remove the resist mask (see Figure 9(A)). .

[0206] Similar to Embodiment 1, the liquid crystal layer 192 is sandwiched and the opposing substrate 190 is bonded together, and in this embodiment... A liquid crystal display device of the specified form is fabricated (see Figure 9(B)).

[0207] The source region and drain region consist of an oxide conductive layer, an oxide semiconductor layer and a source electrode layer and By placing it between the drain electrode layer, the resistance of both the source and drain regions is reduced. This enables high-speed operation of the transistor. Source region and drain region Using an oxide conductive layer improves the frequency characteristics of the peripheral circuit (drive circuit). It is effective for this purpose. Compared to contact between a metal electrode (Ti, etc.) and an oxide semiconductor layer, the metal electrode (Ti Contact between the material (etc.) and the oxide conductive layer can reduce contact resistance.

[0208] An oxide conductive layer is interposed between the oxide semiconductor layer and the source electrode layer and drain electrode layer. This reduces contact resistance and improves the frequency characteristics of the surrounding circuitry (drive circuitry). .

[0209] The channel length of a thin-film transistor is determined during the etching of the oxide conductive layer, therefore The channel length can be shortened. For example, a channel length of 0.1 μm to 2 μm. By shortening it, the operating speed can be increased.

[0210] (Embodiment 4) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, the second A common connection portion for electrically connecting to a counter electrode provided on the substrate is formed on the first substrate. An example is shown. Note that a thin-film transistor is formed on the first substrate as a switching element. The manufacturing process for the common connection section is made common with the manufacturing process for the switching elements of the pixel section. This allows for the formation process without complicating it.

[0211] The common connection section is positioned to overlap with the sealing material used to bond the first substrate and the second substrate. Then, an electrical connection is made with the counter electrode via conductive particles contained in the sealing material. A common connection part is provided in the area that does not overlap with the sealing material (except for the pixel area), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap with the opposing electrode, and electrical A connection is established.

[0212] Figure 36(A) shows a cross-section of a semiconductor device in which a thin-film transistor and a common connection part are fabricated on the same substrate. This is a diagram showing the surface structure.

[0213] In Figure 36(A), the thin-film transistor 220 electrically connected to the pixel electrode layer 227 is , a channel etch type thin-film transistor arranged in the pixel area, in this embodiment, The same structure as the thin-film transistor 170 of Embodiment 1 is used.

[0214] Furthermore, Figure 36(B) shows an example of a top view of a common connection section, and the dashed line C3-C4 in the figure... Figure 36(A) shows a cross-sectional view of the common connection section along the line. Note that in Figure 36(B), the line The same symbols are used to explain the parts that are the same as those in 36(A).

[0215] The common potential line 210 is provided on the gate insulating layer 202 and is the saw of the thin-film transistor 220. The same materials and processes are used to manufacture the drain electrode layer and the s electrode layer.

[0216] Furthermore, the common potential line 210 is covered with a protective insulating layer 203, and the protective insulating layer 203 is at the common potential It has multiple openings in a position that overlaps with line 210. These openings are located in thin-film transistor 2 The contact holes connecting the 20 drain electrode layers and the pixel electrode layer 227 are made using the same process. To be manufactured.

[0217] Note that, since the area size is significantly different here, the contact hole in the pixel area and the common We will use the term "opening" to refer to the common connection section. Also, in Figure 36(A), it is common to the pixel section. The connecting parts are not shown at the same scale; for example, the length of the dashed line C3-C4 at the common connecting part is 50 While the width is approximately 0 μm, the width of a thin-film transistor is less than 50 μm, and in reality, 1 Although the area size is more than 0 times larger, for clarity, Figure 36(A) shows the pixel area and common tangent. The continuation is illustrated with different scales.

[0218] Furthermore, the common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made using the same materials and processes.

[0219] In this way, the manufacturing process for the common connection section is made common with the manufacturing process for the switching elements in the pixel section. It is preferable to use metal wiring for the common potential line to reduce wiring resistance.

[0220] Then, a first substrate having a pixel section and a common connection section, and a second substrate having a counter electrode Secure it using a sealant.

[0221] When incorporating conductive particles into the sealing material, a pair of bases should be placed so that the sealing material and the common connection part overlap. The panels are aligned. For example, in a small LCD panel, the diagonal of the pixel area is aligned. Two common connection points are placed overlapping with the sealing material. Furthermore, in large LCD panels, Four or more common connection points are arranged overlapping with the sealing material.

[0222] Furthermore, the common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material, and the second An electrical connection is made with the opposing electrode on the substrate.

[0223] When using the liquid crystal injection method, after fixing the pair of substrates with a sealing material, the liquid crystal is injected between the pair of substrates. Inject. Also, when using the liquid crystal drop method, apply a sealant to the second substrate or the first substrate. After drawing the image and dropping the liquid crystal, the pair of substrates are bonded together under reduced pressure.

[0224] In this embodiment, an example of a common connection part that electrically connects to the counter electrode is shown, but in particular It is not limited to connections to other wiring or to connections to external terminals. It is possible.

[0225] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0226] (Embodiment 5) In this embodiment, Figure 1 shows an example where part of the thin-film transistor fabrication process differs from that of Embodiment 1. Figure 0 is shown. Figure 10 is the same as Figures 1 to 5 except that the process is slightly different, so the same part The same symbols are used for the same locations, and detailed explanations of the same locations are omitted.

[0227] First, according to Embodiment 1, a gate electrode layer, a gate insulating layer, and an oxide semiconductor are placed on a substrate. The film 130 is formed, and the oxide semiconductor film 130 is processed by a second photolithography process to create islands. The material is processed into oxide semiconductor layers 131 and 132.

[0228] Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. The temperature of the first heat treatment for hydrogenation is 400°C or higher and below the strain point of the substrate, preferably 42°C. The temperature should be 5°C or higher. However, if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but 425 If the temperature is below ℃, the heat treatment time should be longer than 1 hour. A substrate is introduced into an electric furnace, one of the scientific devices, and the oxide semiconductor layer is subjected to a nitrogen atmosphere. After heat treatment, the re-imposition of water and hydrogen into the oxide semiconductor layer is prevented without exposure to the atmosphere. This prevents the formation of an oxide semiconductor layer. Then, high-purity oxygen gas and high-purity N2O gas are introduced into the same furnace. Alternatively, cooling is performed by introducing ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower). It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Or, The purity of the oxygen gas or N2O gas introduced into the heating apparatus is set to 6N (99.9999%). Preferably 7N (99.99999%) or more (i.e., in oxygen gas or N2O gas) It is preferable to set the impurity concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0229] Furthermore, the heating apparatus is not limited to electric furnaces; for example, GRTA (Gas Rapid Th) thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) devices such as Anneal devices It is possible to use a LRTA device with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. The TA device utilizes not only lamps but also heat conduction or thermal radiation from heat-generating elements such as resistive heating elements. It may also be equipped with a device to heat the material to be processed. GRTA is a device that uses high-temperature gas to process This is a method of heat treatment. The gas used is a noble gas such as argon, or a gas such as nitrogen, which is heated. An inert gas that does not react with the material being treated is used during the process. Using the RTA method, 600 Heat treatment at 750°C for several minutes may also be performed.

[0230] Furthermore, after the first heat treatment in which dehydration or dehydrogenation is performed, the temperature is preferably between 200°C and 400°C. Alternatively, heating treatment at a temperature between 200°C and 300°C under an oxygen or N2O gas atmosphere. It is permissible to act rationally.

[0231] Furthermore, the first heat treatment of the oxide semiconductor layers 131 and 132 is used to process them into island-shaped oxide semiconductor layers. It can also be performed on the oxide semiconductor film 130 before the first heat treatment. In that case, after the first heat treatment The substrate is then removed from the heating device, and the photolithography process is performed.

[0232] By going through the above process, the entire oxide semiconductor film is made into an oxygen-rich state, The material is converted to type I. Thus, oxide semiconductor layers 168 and 118 that are entirely type I are obtained. ru.

[0233] Next, a resin is applied to the oxide semiconductor layers 168 and 118 by a third photolithography process. A stock mask is formed, and selective etching is performed to shape the source electrode layer and drain electrode layer. Then, an oxide insulating film 107 is formed by sputtering.

[0234] Next, in order to reduce variations in the electrical characteristics of thin-film transistors, under an inert gas atmosphere or perform heat treatment under a nitrogen gas atmosphere (preferably 150°C or higher and less than 350°C). Alternatively, a heat treatment may be performed at 250°C for 1 hour under a nitrogen atmosphere.

[0235] A fourth photolithography step forms a resist mask, followed by selective etching. The gate insulating layer and oxide insulating film are connected to the first terminal 121, conductive layer 162, and drain electrode layer. 105b forms a contact hole reaching the second terminal 122. Translucent conductive After the film is formed, a resist mask is formed by a fifth photolithography step, selectively Etching is performed on the pixel electrode layer 110, conductive layer 111, terminal electrode 128, and terminal electrode 12 9. Form the wiring layer 145.

[0236] In this embodiment, the connection between the first terminal 121 and the terminal electrode 128 is made via the connecting electrode 120. This is an example of performing the procedure directly without using a wire. Also, the connection between the drain electrode layer 165b and the conductive layer 162 is wired This is done via layer 145.

[0237] Furthermore, in the capacitance section, capacitance wiring 108, gate insulating layer 102, source electrode layer and drain The metal conductive layer, oxide insulating film 107, and pixel electrode layer 110 are formed in the same process as the electrode layer. A volume 148 is formed by stacking.

[0238] Through the above process, the drive circuit section has a thin-film transistor 183 and the pixel section has a thin-film transistor 183 and a pixel section on the same substrate. Thin-film transistor 173 can be fabricated using this method.

[0239] Similar to Embodiment 1, the liquid crystal layer 192 is sandwiched and the opposing substrate 190 is bonded together, and in this embodiment... A liquid crystal display device of the specified form is fabricated (see Figure 10).

[0240] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0241] (Embodiment 6) In this embodiment, at least a part of the drive circuit and a thin film to be placed in the pixel area are placed on the same substrate. An example of how to fabricate a lunger is described below.

[0242] The thin-film transistors placed in the pixel area are formed according to Embodiments 1 to 5. Since the thin-film transistors shown in embodiments 1 to 5 are n-channel TFTs, the driving circuit Of these, a portion of the driving circuit that can be constructed with an n-channel TFT is a thin-film transistor in the pixel area. It is formed on the same substrate as the zista.

[0243] An example of a block diagram of an active-matrix display device is shown in Figure 12(A). On the substrate 5300 are a pixel section 5301, a first scan line drive circuit 5302, and a second scan line drive circuit. It has a motion circuit 5303 and a signal line drive circuit 5304. The pixel section 5301 has multiple signal lines The signal line drive circuit 5304 extends and is arranged, and multiple scan lines are connected to the first scan line drive circuit It is arranged as an extension from 5302 and the scan line drive circuit 5303. Note that the scan line and signal In the regions where the lines intersect, pixels, each containing a display element, are arranged in a matrix. Furthermore, the display device substrate 5300 is an FPC (Flexible Printed Circuit). The timing control circuit 5305 (controller, control IC) is connected via a connection part such as it. It is connected to (the term).

[0244] Figure 12(A) shows the first scan line drive circuit 5302, the second scan line drive circuit 5303, and The line drive circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Furthermore, since the number of external components such as drive circuits is reduced, costs can be lowered. Furthermore, when a drive circuit is provided outside the circuit board 5300, extending the wiring at the connection point can cause problems. This can reduce the number of connections, leading to improved reliability or yield.

[0245] The timing control circuit 5305 is, for example, related to the first scan line drive circuit 5302. The first scan line drive circuit start signal (GSP1), the scan line drive circuit clock signal (GCLK1) is supplied. The timing control circuit 5305 also supplies the second scan line drive cycle. For example, for track 5303, the start signal (GSP2) for the second scan line drive circuit (S Also called a tart pulse, it supplies the clock signal (GCLK2) for the scan line drive circuit. The timing control circuit 5305 sends a start signal for the signal line drive circuit 5304 to the signal line drive circuit 5304. (SSP), clock signal for signal line drive circuit (SCLK), data for video signal (DAT) A) The system shall supply a latch signal (LAT) (also simply called a video signal). The clock signal may be multiple clock signals with different periods, or the clock signal may be inverted. It may also be supplied together with the signal (CKB). It is possible to omit either the 5302 or the second scan line drive circuit 5303.

[0246] In Figure 12(B), a circuit with a low drive frequency (for example, the first scan line drive circuit 5302, the second The scan line driving circuit 5303 is formed on the same substrate 5300 as the pixel section 5301, and the signal line driving This shows a configuration in which the dynamic circuit 5304 is formed on a separate substrate from the pixel section 5301. Due to its configuration, it exhibits a lower field-effect mobility compared to transistors using single-crystal semiconductors. A drive circuit can be formed on the substrate 5300 using film transistors. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yield. ru.

[0247] Furthermore, the thin-film transistors shown in Embodiments 1 to 5 are n-channel type TFTs. Figure 1 Figures 3(A) and 13(B) show the configuration and operation of a signal line driving circuit composed of n-channel TFTs. I will explain this by giving an example.

[0248] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. Switching circuit 5602 is a switching circuit 5602_1~5602_N (where N is natural). It has multiple circuits, each of which is called a number. Switching circuits 5602_1 to 5602_N are, , multiple transistors called thin-film transistors 5603_1~5603_k (where k is a natural number) It has a thin-film transistor 5603_1~5603_k, which is an N-channel type TFT. Let me explain an example.

[0249] The connection relationships of the signal line drive circuit will be explained using the switching circuit 5602_1 as an example. The first terminals of thin-film transistors 5603_1 to 5603_k are connected to wiring 5604_1, respectively. Connected to ~5604_k. Second terminal of thin-film transistor 5603_1~5603_k These are connected to signal lines S1~Sk, respectively. Thin-film transistors 5603_1~5603_ The gate of k is connected to wiring 5605_1.

[0250] The shift register 5601 sequentially supplies high levels (high signals) to the wiring 5605_1 to 5605_N. It outputs a signal at a high power supply potential level, also known as the switching circuit 5602_1~56 It has the function of selecting 02_N in order.

[0251] Switching circuit 5602_1 consists of wiring 5604_1~5604_k and signal lines S1~Sk A function to control the conductivity state (conduction between the first terminal and the second terminal), i.e., wiring 5604_ It has a function to control whether or not to supply potentials between 1 and 5604k to signal lines S1 and Sk. Thus, the switching circuit 5602_1 functions as a selector. The film transistors 5603_1 to 5603_k are connected to wiring 5604_1 to 5604_k, respectively. A function to control the continuity state between this and the signal lines S1~Sk, i.e., wiring 5604_1~5604_k It has the function of supplying the potential to the signal lines S1~Sk. Thus, thin-film transistor 56 Each of the 03_1 to 5603_k functions as a switch.

[0252] Note that wiring 5604_1 to 5604_k each contain video signal data (DATA). The input is video signal data (DATA), which is image information or analog corresponding to the image signal. It is often a G signal.

[0253] Next, regarding the operation of the signal line drive circuit in Figure 13(A), see the timing chart in Figure 13(B). Refer to the explanation. Figure 13(B) shows signals Sout_1 to Sout_N, and signals An example of Vdata_1 to Vdata_k is shown. Signals Sout_1 to Sout_N are each The following is an example of the output signals of the shift register 5601, with signals Vdata_1 to Vdata _k represents an example of a signal input to wiring 5604_1~5604_k. One operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The selection period is divided into, for example, periods T1 to TN. Periods T1 to TN are each , a period for writing video signal data (DATA) to pixels belonging to the selected row be.

[0254] Note that the signal waveform distortions, etc., of each configuration shown in the drawings, etc. of this embodiment are for clarity. The figures may be exaggerated for aesthetic reasons. Therefore, they are not necessarily limited to that scale. It should be noted that...

[0255] During periods T1 to TN, the shift register 5601 receives a high-level signal via wiring 560 Outputs are sent sequentially from 5_1 to 5605_N. For example, during period T1, shift register 5 601 outputs a high-level signal to wiring 5605_1. Then the thin-film transistor... Since 5603_1~5603_k will be turned on, the wiring 5604_1~5604_k and signal Lines S1 to Sk become conductive. At this time, wiring 5604_1 to 5604_k are Data(S1) to Data(Sk) are entered. Each of these belongs to the selected row via thin-film transistors 5603_1 to 5603_k. Of the pixels, the data is written to the pixels in columns 1 through k. In this way, during the period T1 to TN... Then, the video signal data (DATA) is sequentially placed in k columns for each pixel belonging to the selected row. It will be written.

[0256] As described above, video signal data (DATA) is written to pixels in multiple columns. This allows for a reduction in the number of video signal data (DATA) or the number of wires. Therefore, the number of connections to external circuits can be reduced. Also, the video signal is displayed in multiple columns. By writing directly, the writing time can be extended, and the video signal can be written. This can prevent overcrowding and under-storage.

[0257] Note that the shift register 5601 and the switching circuit 5602 are as described in Embodiment 1. It is possible to use a circuit composed of thin-film transistors as shown in section 5. In this case, The polarity of all transistors in the 5601 is configured to be N-channel type only. It is possible.

[0258] A form of shift register used in part of a scan line drive circuit and / or signal line drive circuit. This will be explained using Figures 14 and 15.

[0259] The scan line drive circuit has a shift register. In some cases, it also has a level shifter or a bar It may have a ff. In a scan line driving circuit, the clock signal is set to the shift register ( A selection signal is generated when the CLK and start pulse (SP) signals are input. The generated selection signal is buffered and amplified in a buffer and supplied to the corresponding scan line. The scan line is connected to the gate electrode of the transistor for one pixel line. Therefore, all the transistors for the pixels in one line must be turned ON at once, so a buffer A device capable of carrying a large current is used.

[0260] The shift register consists of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N( N is a natural number greater than or equal to 3 (see Figure 14(A)). The shift rate shown in Figure 14(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the ZISTA are: The first clock signal CK1 is transmitted from wiring 11, and the second clock signal CK2 is transmitted from the second wiring 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. CK4 is supplied. Also, in the first pulse output circuit 10_1, from the fifth wiring 15 The start pulse SP1 (the first start pulse) is input. Also, the nth pulse from the second stage onward In the pulse output circuit 10_n (where n is a natural number between 2 and N), the pulse output cycle of the preceding stage A signal from the road (called the preceding signal OUT(n-1)) (where n is a natural number between 2 and N) is received. It is powered. Also, in the first pulse output circuit 10_1, the third pulse output circuit 1 is two stages later. A signal from 0_3 is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward... This is the signal from the (n+2)th pulse output circuit 10_(n+2) of the second stage downstream (the downstream signal O A signal called UT(n+2) is input. Therefore, the pulse output circuit of each stage outputs to the subsequent stage and / or the first output signal OUT(1)(SR) to be input to the pulse output circuit two stages prior. )~OUT(N)(SR), a second output signal (OUT( 1) OUT(N)) is output. Note that, as shown in Figure 14(A), the shift register The last two stages of the signal do not receive the subsequent signal OUT(n+2), so for example, In addition, a second start pulse SP2 and a third start pulse SP3 are input separately. You can just write "completion".

[0261] The clock signal (CK) alternates between high and low levels (L signal, low power supply potential) at regular intervals. This is a signal that repeats the same values ​​(also called the level). Here, the first clock signal (CK1) to the second... The 4th clock signal (CK4) is delayed by 1 / 4 period in sequence. In this embodiment, Using the first clock signal (CK1) to the fourth clock signal (CK4), pulse output cycles It controls the drive of the road, etc. The clock signal is GCL according to the input drive circuit. Although it is sometimes referred to as K or SCLK, we will use CK in this explanation.

[0262] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11~ It is electrically connected to one of the fourth wires 14. For example, in Figure 14(A), The first pulse output circuit 10_1 has a first input terminal 21 that is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is It is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is Input terminal 21 is electrically connected to the second wiring 12, and input terminal 22 is connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14, and the third input terminal 23 is electrically connected to the fourth wiring 14. Yes, they are.

[0263] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal Assume that it has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 14(B)). (See). In the first pulse output circuit 10_1, the first clock signal is connected to the first input terminal 21. When signal CK1 is input, the second clock signal CK2 is input to the second input terminal 22, and the third The third clock signal CK3 is input to input terminal 23, and the start signal is input to the fourth input terminal 24. A pulse is input, and the subsequent signal OUT(3) is input to the 5th input terminal 25, and the 1st output The first output signal OUT(1)(SR) is output from terminal 26, and the second output terminal 27 This indicates that the second output signal, OUT(1), is being output.

[0264] The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are 3-terminal thin film In addition to transistors (also known as TFT: Thin Film Transistors), The four-terminal thin-film transistor described in the above embodiment can be used. Figure 14(C) The equivalent circuit of the 4-terminal thin-film transistor 28 described in the above embodiment is shown below. In this specification, a thin-film transistor has two gate electrodes separated by a semiconductor layer. In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the lower gate electrode. The upper electrode is also called the gate electrode.

[0265] When oxide semiconductors are used in the semiconductor layer including the channel formation region of a thin-film transistor, manufacturing Depending on the process, the threshold voltage may shift to the negative or positive side. Therefore, in thin-film transistors that use oxide semiconductors in the semiconductor layer including the channel formation region, A configuration that allows control of the threshold voltage is preferred. A 4-terminal thin-film transistor 2 The threshold voltage of 8 is controlled by controlling the potential of the upper and / or lower gate electrodes. It can be controlled to the desired value.

[0266] Next, let's look at an example of a specific circuit configuration of the pulse output circuit shown in Figure 14(B). (D) will explain this.

[0267] The pulse output circuit shown in Figure 14(D) consists of the first transistor 31 to the thirteenth transistor It has a 43. Also, the first input terminal 21 to the fifth input terminal 25 described above, and In addition to the first output terminal 26 and the second output terminal 27, the first high power supply potential VDD is supplied to the power supply terminal 26. Power line 51, power line 52 to which a second high power potential VCC is supplied, and power line 52 to which a low power potential VSS is supplied. Signals are sent from the power line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied. Here, the relative magnitudes of the power supply potentials of each power line are shown in Figure 14(D). The first power supply potential VDD is set to be at a potential equal to or greater than the second power supply potential VCC, and the second power supply potential VC C shall be at a potential greater than the third power supply potential VSS. Note that the first clock signal (CK1) The fourth clock signal (CK4) is a signal that alternates between high and low levels at regular intervals. However, it is assumed that VDD is at the H level and VSS is at the L level. Note that power line 51 By making the potential VDD higher than the potential VCC of the power line 52, the operation will be affected. In other words, the potential applied to the gate electrode of the transistor can be kept low, The shift in the threshold of the sta is reduced, and degradation can be suppressed. Of transistors 31 to 43, the first transistor 31 and the sixth transistor For transistors 36 through 9, it is preferable to use 4-terminal thin-film transistors. It seems. The first transistor 31, the sixth transistor 36 to the ninth transistor 39 The operation involves the potential of the node to which one of the electrodes, which will be the source or drain, is connected, and the gate This is a transistor that is required to be switched by an electrode control signal, and the gate electrode is Faster response to input control signals (steep rise of on-current) results in a more pulsed response. This transistor can reduce malfunctions in output circuits. Therefore, it has a thin 4-terminal design. By using film transistors, the threshold voltage can be controlled, resulting in a lower rate of malfunction. This allows for a pulse output circuit that can reduce the frequency.

[0268] In Figure 14(D), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode The (lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has its first terminal electrically connected to the power line 53, and its second terminal The first terminal of the ninth transistor 39 is electrically connected, and the gate electrode is connected to the fourth transistor It is electrically connected to the gate electrode of transistor 34. The third transistor 33 is connected to the first terminal The first input terminal 21 is electrically connected, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode and the gate electrode of the fourth transistor 34 are electrically connected, and the gate electrode is the fourth It is electrically connected to input terminal 24. The sixth transistor 36 has its first terminal connected to the power line. Electrically connected to 52, the second terminal is the gate electrode of the second transistor 32 and the fourth terminal It is electrically connected to the gate electrode of the transistor 34, and the gate electrode (the lower gate electrode and the upper The gate electrode of the transistor is electrically connected to the fifth input terminal 25. 37 has its first terminal electrically connected to the power line 52, and its second terminal connected to the eighth transistor 38. It is electrically connected to the second terminal, and the gate electrodes (lower gate electrode and upper gate electrode) The third input terminal 23 is electrically connected to the eighth transistor 38, the first terminal The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 are electrically charged. They are connected to the second input terminal, with the gate electrodes (lower gate electrode and upper gate electrode) connected to the second input terminal. It is electrically connected to 22. The ninth transistor 39 has its first terminal connected to the first transistor It is electrically connected to the second terminal of the sta 31 and the second terminal of the second transistor 32, and the second terminal The child is connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40. Electrically connected, the gate electrodes (lower gate electrode and upper gate electrode) are connected to power line 52 It is electrically connected to the first input terminal 2. The tenth transistor 40 has its first terminal connected to the first input terminal 2. It is electrically connected to terminal 1, and the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to terminal 1. This is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power line 53, and its second terminal electrically connected to the second output terminal 27. Connected electrically, the gate electrode of the second transistor 32 and the fourth transistor It is electrically connected to the gate electrode of transistor 34. Transistor 42 is the 12th terminal The child is electrically connected to the power line 53, and the second terminal is electrically connected to the second output terminal 27. , the gate electrode is the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper gate electrode It is electrically connected to the electrode. The 13th transistor 43 has its first terminal connected to the power line 5 It is electrically connected to 3, and the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to 3. The electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) is charged. They are connected by energy.

[0269] In Figure 14(D), the gate electrode of the third transistor 33, the tenth transistor Node A is defined as the connection point between the gate electrode of transistor 40 and the second terminal of transistor 9, transistor 39. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, and the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is a node. Let's call it B.

[0270] Figure 15(A) shows the pulse output circuit described in Figure 14(D) as the first pulse output circuit 10_ When applied to 1, the first input terminals 21 to the fifth input terminals 25 and the first output terminal 26 The signals input to or output to the second output terminal 27 are shown.

[0271] Specifically, the first clock signal CK1 is input to the first input terminal 21, and the second input terminal The second clock signal CK2 is input to child 22, and the third clock signal is input to the third input terminal 23. When signal CK3 is input, a start pulse is input to the fourth input terminal 24, and the fifth input terminal The subsequent signal OUT(3) is input to terminal 25, and the first output signal OUT is output from the first output terminal 26. (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. It will be done.

[0272] A thin-film transistor is defined as a transistor with at least three components, including a gate, a drain, and a source. It is an element having terminals. Furthermore, a channel formation region is formed in the region superimposed on the gate. It has a semiconductor, and by controlling the gate potential, it can drain through the channel formation region. The current flowing between the source and the drain can be controlled. Here, the source and drain are: This varies depending on the structure and operating conditions of the thin-film transistor, so which is the source or the slave? It is difficult to determine whether it is a source or a drain. Sometimes the regions are not called source or drain. In such cases, for example, each These are sometimes referred to as the first terminal and the second terminal.

[0273] Note that in Figures 14(D) and 15(A), the boot process is performed by setting node A to a floating state. A capacitive element may be provided separately to perform the strapping action. Also, the potential of node B may be maintained. Therefore, a capacitive element with one electrode electrically connected to node B may be provided separately.

[0274] Here, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 15(A) The chart is shown in Figure 15(B). Note that if the shift register is a scan line drive circuit... In total, period 61 in Figure 15(B) is the vertical retrace period, and period 62 corresponds to the gate selection period. do.

[0275] Furthermore, as shown in Figure 15(A), the ninth gate to which the second power supply potential VCC is applied By installing the Rangista 39, the following occurs before and after the bootstrap operation: It has advantages like these.

[0276] If there is no 9th transistor 39 to which the second power supply potential VCC is applied to the gate electrode, then When the potential of node A rises due to the trapping action, the second of the first transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, to the power line 51 side. Therefore, in the first transistor 31, between the gate and source, and between the gate and drain Both are subjected to significant stress due to the application of a large bias voltage, and the transistor This can be a factor in degradation. Therefore, the 9th gate electrode is subjected to a second power supply potential VCC. By providing transistor 39, the power of node A is supplied by the bootstrap operation. Although the position rises, the potential of the second terminal of the first transistor 31 does not rise. This can be done. In other words, by providing the ninth transistor 39, the first transistor The value of the negative bias voltage applied between the gate and source of the zistor 31 can be reduced. Yes, it is possible. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, thus reducing stress. This makes it possible to suppress the degradation of the first transistor 31.

[0277] Furthermore, the location where the ninth transistor 39 is installed is the second of the first transistor 31. The terminal is connected to the gate of the third transistor 33 via the first and second terminals. Any configuration that is set up in this manner is acceptable. Note that the pulse output circuit in this embodiment may be equipped with multiple pulse output circuits. In the case of a soft register, in a signal line drive circuit with more stages than a scan line drive circuit, the 9th transistor The ZISTA39 can be omitted, which has the advantage of reducing the number of transistors.

[0278] Furthermore, the semiconductor layers of the first transistor 31 to the thirteenth transistor 43 are made of oxide semiconductor material. By using a conductor, the off-current of the thin-film transistor is reduced, as well as the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. This can reduce malfunctions within the circuit. Also, transistors using oxide semiconductors are Compared to transistors using morphous silicon, a high potential is applied to the gate electrode. The degree of transistor degradation caused by this is small. Therefore, the second power supply potential VCC is supplied. The same operation can be obtained by supplying the first power potential VDD to the power line, and the connections between circuits are also This allows for a reduction in the number of power lines, thus enabling the miniaturization of the circuit.

[0279] Note that the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The clock signal supplied by the third input terminal 23, and the gateway of the eighth transistor 38. The electrodes (lower gate electrode and upper gate electrode) are supplied by the second input terminal 22. The clock signal is transmitted to the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper The clock signal supplied by the second input terminal 22 to the gate electrode of the eighth transistor The gate electrodes of terminal 38 (lower gate electrode and upper gate electrode) are connected to the third input terminal 23. Therefore, the same effect can be achieved by reversing the wiring so that it becomes the supplied clock signal. In addition, in the shift register shown in Figure 15(A), the seventh transistor 37 and From a state where both transistors 38 are ON, the 7th transistor 37 turns OFF, and the 8th transistor turns OFF. Transistor 38 is ON, then transistor 37 (number 7) is OFF, and the eighth transistor By turning off the 38, the second input terminal 22 and the third input terminal 23 The decrease in potential at node B, which occurs as a result of the potential drop, affects the gate of the seventh transistor 37. Due to the decrease in electrode potential and the decrease in the potential of the gate electrode of transistor 8 38, 2 This will occur multiple times. On the other hand, in the shift register shown in Figure 15(A), the seventh transistor With both transistor 37 and the 8th transistor 38 turned ON, the 7th transistor 37 When the first transistor is on, the eighth transistor 38 is off, and then the seventh transistor 37 is off. By turning off the eighth transistor 38, the second input terminal 22 and The decrease in potential at node B caused by a decrease in potential at input terminal 23 of 3 is handled by the 8th transistor. This can be reduced to one instance by lowering the potential of the gate electrode of Zistor 38. Therefore, the The gate electrodes (lower gate electrode and upper gate electrode) of transistor 37 of 7 are connected to the third A clock signal is supplied from input terminal 23, and the gate electrode of the 8th transistor 38 (downward) A clock signal is supplied from the second input terminal 22 to the gate electrode and the upper gate electrode. It is preferable to have this connection relationship. This is because the number of fluctuations in the potential of node B is reduced, This is because it can reduce noise.

[0280] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at an L level. During the period, a high-level signal is periodically supplied to node B, thus creating a pulse This can suppress malfunctions in the output circuit.

[0281] (Embodiment 7) Thin-film transistors are fabricated, and these thin-film transistors are used in the pixel section and further in the driving circuit. It is possible to fabricate semiconductor devices (also called display devices) that have display functions. The transistor is integrated into the drive circuit, either partially or entirely, on the same substrate as the pixel section, and the system On-panel formation is possible.

[0282] A display device includes a display element. A liquid crystal element (also called a liquid crystal display element) is used as the display element. It is possible to do so. Also, displays where the contrast changes due to electrical action, such as electronic ink. The medium can also be used.

[0283] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. It includes a module on which ICs and the like are mounted. Furthermore, it is a device for manufacturing the display device. With respect to an element substrate that corresponds to one form before the display element is completed in the process, the element substrate is The element substrate is specifically provided with means for supplying current to the display element in each of the multiple pixels. This may be a state where only the pixel electrodes of the display element are formed, or a conductive film that will serve as the pixel electrode may be formed. This may be the state after the film has been formed but before etching to form the pixel electrodes. All forms apply.

[0284] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of a TAB tape or TCP cable. The display element uses the COG (Chip On Glass) method to create an IC (integrated circuit board). Modules in which the road is directly implemented are also included in the display device.

[0285] Figure 16 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let me explain. Figures 16(A1)(A2) show thin-film transistors 4010 and 4011, and liquid crystal. Element 4013 is placed between the first substrate 4001 and the second substrate 4006 in the sealing material 4005. Therefore, Figure 16(B) is a plan view of the sealed panel, and Figure 16(A1)(A2) is M - This corresponds to a cross-sectional view in N.

[0286] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0287] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 16(A1) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 16(A2) shows, This is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0288] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple thin-film transistors, and in Figure 16(B), the thin film included in the pixel section 4002 Transistor 4010 and thin-film transistor 4011 included in scan line drive circuit 4004 This illustrates the following: A protective insulating layer 4020, 4 is placed on thin-film transistors 4010, 4011. 021 is provided.

[0289] Thin-film transistors 4010 and 4011 have an oxide semiconductor layer as shown in Embodiments 1 to 5. Highly reliable thin-film transistors can be applied. Thin-film transistors for drive circuits As for st4011, thin-film transistors 180, 181 as shown in Embodiments 1 to 5, 182, 183, and thin-film transistor 4010 for pixels, thin-film transistor 170 , 171, 172, and 173 can be used. In this embodiment, thin film transient The 4010 and 4011 are n-channel thin-film transistors.

[0290] On the insulating layer 4021, the oxide semiconductor layer of the thin-film transistor 4011 for the drive circuit A conductive layer 4040 is provided in a position that overlaps with the channel formation region. The conductive layer 4040 is acid By placing it in a position that overlaps with the channel formation region of the synthetic semiconductor layer, before and after BT testing... This can reduce the change in the threshold voltage of the thin-film transistor 4011. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin-film transistor 4011. They can be different, and can also function as a second gate electrode layer. Also, the conductive layer The potential of 4040 may be GND, 0V, or floating.

[0291] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin-film transistor 4010. They are electrically connected. And the counter electrode layer 4031 of the liquid crystal element 4013 is on the second substrate 40 Formed on 06. Pixel electrode layer 4030, counter electrode layer 4031, and liquid crystal layer 4008 The overlapping portion corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the opposite The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033.

[0292] Furthermore, translucent substrates can be used as the first substrate 4001 and the second substrate 4006. Glass, ceramics, and plastics can be used. As for plastics... , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0293] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 It is provided in [location]. A spherical spacer may also be used. Also, the counter electrode layer 4031 It is electrically connected to a common potential line located on the same substrate as the thin-film transistor 4010. Using a common connection part, the opposing electrode layer 40 is connected via conductive particles placed between the pair of substrates. 31 and the common potential line can be electrically connected. Note that the conductive particles are the sealing material 40 It will be included in 05.

[0294] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. It is short, optically isotropic, and therefore requires no orientation processing, and has low dependence on viewing angle.

[0295] In addition to transmissive liquid crystal displays, this method can also be applied to semi-transmissive liquid crystal displays.

[0296] In addition, in liquid crystal displays, a polarizing plate is provided on the outside (viewing side) of the substrate, and a colored layer (color) is provided on the inside. The example shows the order of arrangement of the filter, electrode layer used for the display element, but the polarizing plate is inside the substrate. It may also be provided on the side. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and polarizing The settings should be adjusted as appropriate depending on the materials and manufacturing process conditions of the plate and colored layer. In addition, other than the display area... A light-shielding film that functions as a black matrix may be provided.

[0297] Furthermore, an insulating layer 4020 is formed on the thin-film transistors 4010 and 4011. The insulating layer 4020 is formed using the same materials and methods as the oxide insulating film 107 shown in Embodiment 1. It is possible to do so, but here, as the insulating layer 4020, silicon oxide is produced by sputtering. It forms a film.

[0298] Furthermore, a protective insulating layer may be formed on the insulating layer 4020. Here, the protective insulating layer is A silicon nitride film is formed by RF sputtering (not shown).

[0299] Furthermore, an insulating layer 4021 is formed as a planarizing insulating film. It can be formed using the same materials and methods as the planar insulating layer 109 shown in Embodiment 2, such as acrylic. Heat-resistant organic materials such as polyimide, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low dielectric constant materials (low-k materials) can be used. Use roxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved. Furthermore, by stacking multiple insulating films formed from these materials, an insulating layer 40 21 may be formed.

[0300] The method for forming the insulating layer 4021 is not particularly limited and may be sputtering, S OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, spray Lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used. The firing process of the insulating layer 4021 and the semiconductor layer By combining this function with that of a wire, it becomes possible to efficiently manufacture semiconductor devices.

[0301] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon oxide Electrical materials can be used.

[0302] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or more. Also, the resistance of the conductive polymer contained in the conductive composition The ratio is preferably 0.1 Ω·cm or less.

[0303] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0304] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0305] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? The terminal electrode 4016 is formed from the source electrode layer and drain of the thin-film transistor 4011. It is formed from the same conductive film as the electrode layer.

[0306] Furthermore, in Figure 16, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. The example shown illustrates this configuration, but it is not limited to this setup. A separate scan line drive circuit can be formed to implement it. Alternatively, you may install it, or separately form only a part of the signal line drive circuit or a part of the scan line drive circuit. It's okay to implement it.

[0307] Figure 17 shows a semi-finished TFT substrate 2600 fabricated by the fabrication method disclosed herein. This shows an example of how a liquid crystal display module can be configured as a conductive device.

[0308] Figure 17 shows an example of a liquid crystal display module, in which the TFT substrate 2600 and the opposing substrate 2601 are The pixel portion 2603, which includes a TFT and the like, is fixed in place by a material 2602, and the liquid crystal layer is also included between them. Display elements 2604 and colored layers 2605 are arranged to form a display area. Colored layer 2605 This is necessary for color display, and in the case of the RGB method, it corresponds to red, green, and blue. A colored layer is arranged corresponding to each pixel. The TFT substrate 2600 and the opposing substrate 2601 Polarizing plates 2606, 2607, and 2613 are arranged on the outside. The light source is cold It consists of a cathode tube 2610 and a reflector 2611, and the circuit board 2612 is flexible The wiring circuit section 2608 of the TFT board 2600 is connected by the wire board 2609, and the control External circuits such as polarizing circuits and power supply circuits are incorporated. Also, between the polarizing plate and the liquid crystal layer The layers may be stacked with a phase difference plate in place.

[0309] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0310] Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. ru.

[0311] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. (Embodiment 8)

[0312] The semiconductor device disclosed herein provides flexibility to enable the creation of e-books (electronic (Children's books), posters, in-vehicle advertisements such as trains, and various cards such as credit cards. This can be applied to display units and the like in electronic devices. An example of an electronic device is shown in Figure 18.

[0313] Figure 18 shows an example of an e-book. For example, the e-book 2700 is housed in the casing 2701. It consists of two enclosures, enclosure 2701 and enclosure 2703. Enclosure 2701 and enclosure 2703 are It is integrated with the shaft portion 2711, and the opening and closing operation is performed with the shaft portion 2711 as the axis. Yes, it's possible. This configuration allows it to function like a physical book.

[0314] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 18), and the left-hand display unit An image can be displayed on the display unit 2707 in Figure 18.

[0315] Furthermore, Figure 18 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB A configuration that includes terminals that can connect to various cables such as cables, a recording medium insertion section, and so on. It may also be done this way. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's fine.

[0316] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0317] (Embodiment 9) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0318] Figure 19(A) shows an example of a television system. The television system 9600 is, The display unit 9603 is integrated into the housing 9601. The display unit 9603 displays video. It is possible to do so. In addition, here the stand 9605 supports the housing 9601. This shows the configuration.

[0319] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0320] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0321] Figure 19(B) shows an example of a digital photo frame. For example, a digital photo Frame 9700 has a display unit 9703 integrated into the housing 9701. Display unit 970 3 is capable of displaying various images, such as images taken with a digital camera. By displaying data, it can function just like a regular picture frame.

[0322] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0323] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0324] Figure 20(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least in this specification. Any configuration that includes the semiconductor device disclosed herein, and other auxiliary equipment as appropriate, is acceptable. This can be done. The portable gaming machine shown in Figure 20(A) has the data recorded on the recording medium. Functions for reading programs or data and displaying them on the display unit, and wireless communication with other portable gaming machines. It has the function of sharing information by doing so. Furthermore, the portable gaming machine shown in Figure 20(A) has the following features. The functions are not limited to these, and it can have a variety of functions.

[0325] Figure 20(B) shows an example of a slot machine, which is a large-scale gaming machine. Slot machine 9 The 900 has a display unit 9903 integrated into the casing 9901. Also, slot machine 9 The 900 also includes other features such as a start lever, stop switch, coin slot, It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is not limited to those mentioned above. Not specified, and any configuration comprising at least the semiconductor device disclosed herein is sufficient, and other The configuration can include ancillary equipment as appropriate.

[0326] Figure 21(A) is a perspective view showing an example of a portable computer.

[0327] The portable computer in Figure 21(A) is constructed by connecting the upper casing 9301 and the lower casing 9302. The hinge unit is in the closed position, and the upper housing 9301 has a display unit 9303, and the keyboard The lower housing 9302, which has code 9304, can be stacked on top of each other, making it easy to carry. This is convenient, and when the user is typing on the keyboard, the hinge unit can be opened. Therefore, input operations can be performed by looking at the display unit 9303.

[0328] In addition, the lower casing 9302 houses the keyboard 9304 and a pointing device for input operations. It has a chair 9306. Also, if the display unit 9303 is a touch input panel, one of the display units Input operations can also be performed by touching the part. In addition, the lower chassis 9302 contains the CPU and hardware. It has a processing unit such as a disk. Furthermore, the lower enclosure 9302 can be used with other devices, for example, U It has an external connection port 9305 into which a communication cable compliant with SB's communication standards is plugged in. Yes, they are.

[0329] The upper housing 9301 also contains a display unit 93 which can be slid and stored inside the upper housing 9301. It has 07, which enables a large display screen. It also has a retractable display unit 93 The user can adjust the orientation of the 07 screen. Additionally, the retractable display unit 9307 can be used for touch input. If it's a panel, input operations can also be performed by touching a part of the retractable display.

[0330] The display unit 9303 or the retractable display unit 9307 is a video display device such as a liquid crystal display panel. Use this.

[0331] Furthermore, the portable computer shown in Figure 21(A) is configured to include a receiver, etc., and can also function as a television. The broadcast can be received and the image displayed on the display unit 9303 or the display unit 9307. Furthermore, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is left in the closed position. Well, you slide the display unit 9307 to expose the entire screen, and then adjust the screen angle so that the user can Television broadcasts can also be viewed. In this case, the hinge unit is in the open position and the display unit 9 To avoid displaying 303 and to activate only the circuit that displays the television broadcast, It can consume minimal power, making it suitable for portable computers with limited battery capacity. It is useful in that context.

[0332] Furthermore, Figure 21(B) shows a portable device that can be worn on the user's wrist like a wristwatch. This is a perspective illustrating one example of the story.

[0333] This mobile phone has a communication device with at least telephone functionality and a battery, and this Band portion 9204 for attaching to the body on the arm, adjustment for fixing the band portion to the arm It consists of a node 9205, a display unit 9201, a speaker 9207, and a microphone 9208. Yes, they are.

[0334] The main unit also has an operation switch 9203, a power input switch, and a display switching switch. In addition to the start-up switch for imaging, for example, pressing a button will launch an internet-enabled program. Each function can be associated with a specific event, such as when it is activated.

[0335] Input operations on this mobile phone are performed by touching the display unit 9201 with a finger or input pen, or by operating it. This is done by operating switch 9203 or by voice input to microphone 9208. In 21(B), the display button 9202 displayed on the display unit 9201 is shown, and a finger Input can be performed by touching the screen.

[0336] Furthermore, the main unit is an imaging device that converts the image of the subject formed through the imaging lens into an electronic image signal. It has a camera section 9206 with a step. However, the camera section is not required.

[0337] Furthermore, the mobile phone shown in Figure 21(B) is configured to include a television broadcast receiver, etc. It can receive TV broadcasts and display the images on the display unit 9201, and also record memory and other data. With a configuration that includes a memory device, television broadcasts can be recorded into memory. Also, Figure 21(B) The mobile phones shown may have the ability to collect location information such as GPS.

[0338] The display unit 9201 uses an image display device such as a liquid crystal display panel. (See Figure 21(B) for details.) Because the band phone is small and lightweight, its battery capacity is limited, and the display unit 920 It is preferable to use a panel that can be driven with low power consumption for the display device used in 1.

[0339] Note that Figure 21(B) illustrates an electronic device that is worn on the "arm," but it is not particularly limited to this. In short, it just needs to be something that can be carried around.

[0340] (Embodiment 10) In this embodiment, as one form of a semiconductor device, the thin film transient shown in Embodiments 1 to 5 Examples of display devices having a sta will be described with reference to Figures 22 to 35. This embodiment is a display An example of a liquid crystal display device using liquid crystal elements as components will be explained with reference to Figures 22 to 35. The TFTs 628 and 629 used in the liquid crystal display devices shown in Figures 22 to 35 are from Embodiment 1 to A thin-film transistor as shown in 5 can be applied, and the process is similar as shown in Embodiments 1 to 5. This is a thin-film transistor with excellent electrical characteristics and high reliability that can be manufactured quickly.

[0341] First, we will explain VA (Vertical Alignment) type liquid crystal display devices. VA type is a type of method that controls the arrangement of liquid crystal molecules in a liquid crystal display panel, and voltage is applied. This method aligns the liquid crystal molecules perpendicular to the panel surface when no action is taken. In terms of morphology, in particular, pixels are divided into several regions (subpixels), and each is separate The design is such that the molecule is tilted in that direction. This is called multi-domainization or multi-domainization. This is called multi-domain design. The following explanation describes liquid crystal display devices that take multi-domain design into consideration. explain.

[0342] Figures 23 and 24 show the pixel electrode and counter electrode, respectively. Note that Figure 23 shows the pixel This is a plan view of the substrate side on which the electrodes are formed, and the cross-sectional structure corresponding to the cutting line EF shown in the figure is This is shown in Figure 22. Figure 24 is a plan view of the substrate side where the counter electrodes are formed. The explanation will be explained using these diagrams.

[0343] Figure 22 shows the TFT 628, the pixel electrode layer 624 connected to it, and the holding capacitance section 630. The formed substrate 600 and the opposing substrate 601 on which the opposing electrode layer 640 etc. are formed are superimposed. This indicates that the liquid crystal has been injected.

[0344] Although not shown in the diagram, a first colored film is applied to the position where the spacer is formed on the opposing substrate 601. A second colored film, a third colored film, and a counter electrode layer 640 are formed. This structure allows the liquid The height of the protrusions 644 and the spacer are different to control the orientation of the crystals. Pixel electrode layer 6 An alignment film 648 is formed on 24, and similarly, an alignment film 646 is formed on the counter electrode layer 640. During this time, the liquid crystal layer 650 is formed.

[0345] The spacers may be formed as columnar spacers or scattered as bead spacers. In the case of optical properties, the photoelectrode may be formed on a pixel electrode layer 624 formed on the substrate 600.

[0346] On the substrate 600 are a TFT 628, a pixel electrode layer 624 connected to it, and a holding capacitance section 6 30 is formed. The pixel electrode layer 624 consists of a TFT 628, wiring 616, and a holding capacitance portion 6 The insulating film 620 covering 30 and the third insulating film 622 covering insulating film 620 are each penetrated by The tact hole 623 is connected to the wiring 618. The TFT 628 is shown in Embodiments 1 to 5. Thin-film transistors can be used as appropriate.

[0347] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the shape of the liquid crystal element. It has been done.

[0348] Figure 23 shows the structure on the substrate 600. The pixel electrode layer 624 uses the material shown in Embodiment 1. It is formed by shaping. A slit 625 is provided in the pixel electrode layer 624. The slit 625 is formed by the liquid crystal It is for controlling orientation.

[0349] The TFT 629 shown in Figure 23, the pixel electrode layer 626 connected thereto, and the retaining capacitance unit 631 are, Each of these can be formed in the same manner as the TFT628, the pixel electrode layer 624, and the holding capacitance section 630. Yes, it is. Both the TFT628 and TFT629 are connected to wiring 616. This LCD display A pixel in Nell is composed of a pixel electrode layer 624 and a pixel electrode layer 626. Pixel electrode layers 624 and 626 are subpixels.

[0350] Figure 24 shows the structure on the opposing substrate side. The opposing electrode layer 640 is made of the same material as the pixel electrode layer 624. It is preferable to form it using [a specific method]. On the counter electrode layer 640, there are protrusions 6 that control the orientation of the liquid crystal. 44 is formed.

[0351] The equivalent circuit of this pixel structure is shown in Figure 25. Both TFT628 and TFT629 have gate configurations. It is connected to wire 602 and wiring 616. In this case, the power of capacitive wiring 604 and capacitive wiring 605 By changing their positions, the operation of liquid crystal elements 651 and 652 can be made different. In other words, by individually controlling the potential of capacitive wiring 604 and capacitive wiring 605, liquid crystals can be formed. The field of view is widened by precisely controlling the orientation of the elements.

[0352] When a voltage is applied to the pixel electrode layer 624 with the slit 625, near the slit 625... This generates distortion of the electric field (oblique electric field). This slit 625 and the protrusion on the opposing substrate 601 side By arranging 644 and other elements in an alternating interlocking manner, a diagonal electric field is effectively generated, resulting in a liquid crystal. By controlling the orientation, the direction in which the liquid crystals align varies depending on the location. That is, The multi-domain architecture widens the viewing angle of the LCD display panel.

[0353] Next, a VA-type liquid crystal display device, different from the one described above, will be explained using Figures 26 to 29. ru.

[0354] Figures 26 and 27 show the pixel structure of a VA-type liquid crystal display panel. Figure 27 shows the substrate 600 This is a plan view, and Figure 26 shows the cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0355] This pixel structure has multiple pixel electrodes for each pixel, and a TFT is in contact with each pixel electrode. It continues. Each TFT is configured to be driven by a different gate signal. In a multi-domain designed pixel, the signals applied to each pixel electrode are independently It has a configuration that controls it.

[0356] The pixel electrode layer 624 is connected to the TFT 628 by wiring 618 in the contact hole 623. Furthermore, the pixel electrode layer 626 is connected to the contact hole 627 by wiring 619. It is connected to the FT629. The gate wiring 602 of the TFT628 and the gate of the TFT629 Wiring 603 is isolated so that it can be given a different gate signal. On the other hand, The wiring 616, which functions as a data line, is used in common by TFT628 and TFT629. TFT628 and TFT629 are thin-film transistors as shown in Embodiments 1, 2, 5, and 6. It can be used as appropriate.

[0357] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different, and they are separated by the slit 625. They are separated. The pixel electrode layer 626 surrounds the outside of the V-shaped pixel electrode layer 624. It is formed. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is set to TFT628 The orientation of the liquid crystal is controlled by varying the TFT629. The equivalent circuit is shown in Figure 29. TFT628 is connected to gate wiring 602, and TFT629 is connected to gate It is connected to wiring 603. Also, both TFT628 and TFT629 are connected to wiring 616. It is connected to the gate wiring 602 and gate wiring 603, which provide different gate signals. Therefore, the operation of liquid crystal elements 651 and 652 can be made different. That is, TF By individually controlling the operation of T628 and TFT629, the liquid crystal element 651 and the liquid crystal element The viewing angle can be widened by precisely controlling the alignment of the 652 liquid crystals.

[0358] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601. A planarization film 637 is formed between 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal. Figure 28 shows the structure on the opposing substrate side. The opposing electrode layer 640 is common across different pixels. The electrode has a slit 641 formed on it. This slit 641 and the pixel electrode The polar layer 624 and the slit 625 on the pixel electrode layer 626 side are arranged to interlock alternately. This allows for the effective generation of oblique electric fields, thereby controlling the orientation of the liquid crystal. Furthermore, the orientation of the liquid crystal can be varied depending on the location, thereby widening the viewing angle. In Figure 28, the pixel electrode layer 624 and pixel electrode are formed on the substrate 600 shown in Figure 26. The polar layer 626 is shown by a dashed line, and the opposing electrode layer 640, the pixel electrode layer 624 and the pixel electrode layer 626 This shows how they are arranged in an overlapping manner.

[0359] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and similarly the counter electrode An alignment film 646 is also formed on layer 640. A liquid crystal is formed between substrate 600 and opposing substrate 601. Layer 650 is formed. Also, the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 The overlapping of these elements forms the first liquid crystal element. Furthermore, the pixel electrode layer 626 and the liquid crystal... The second liquid crystal element is formed by the overlapping of layer 650 and the counter electrode layer 640. (Figure) The pixel structure of the display panel described in Figures 26 to 29 is such that each pixel contains a first liquid crystal element and a second liquid crystal element. It has a multi-domain structure with crystal elements.

[0360] Next, we will describe a transverse electric field type liquid crystal display device. In the transverse electric field type, the liquid crystal molecules within the cell This method drives the liquid crystal by applying an electric field in the horizontal direction to express gradation. This allows the field of view to be expanded to approximately 180 degrees. The following explanation uses a transverse electric field method. The liquid crystal display device used will be described below.

[0361] Figure 30 shows the shape of the electrode layer 607, TFT 628, and the pixel electrode layer 624 connected to the TFT 628. This shows the completed substrate 600 and the opposing substrate 601 superimposed, with liquid crystal injected. A colored film 636, a planarization film 637, etc., are formed on the opposing substrate 601. No opposing electrodes are placed on the substrate 601 side. Also, between substrate 600 and the opposing substrate 601 A liquid crystal layer 650 is formed via alignment films 646 and 648.

[0362] On the substrate 600 are an electrode layer 607 and capacitive wiring 604 connected to the electrode layer 607, and T The FT628 is formed. The capacitive wiring 604 is formed simultaneously with the gate wiring 602 of the TFT628. This can be achieved. As for TFT628, the thin film transients shown in Embodiments 1 to 5 A st can be applied. The electrode layer 607 is the pixel electrode layer shown in Embodiments 1 to 5 Similar materials can be used. Furthermore, the electrode layer 607 is divided into sections roughly the shape of a pixel. It is formed as follows. Furthermore, a gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. It can be done.

[0363] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0364] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, an insulating film is formed on the insulating film 620. Pixel electrical signals connected to wiring 618 via contact holes 623 formed in the edge film 620 A polar layer 624 is formed. The pixel electrode layer 624 is the same as the pixel electrode layer shown in Embodiments 1 to 5. It is formed using similar materials.

[0365] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacity is determined by the gate insulating film 606 between the electrode layer 607 and the pixel electrode layer 624. It is established and formed as a result.

[0366] Figure 31 is a plan view showing the configuration of the pixel electrode. The section corresponding to the cutting line OP shown in Figure 31 The surface structure is shown in Figure 30. A slit 625 is placed in the pixel electrode layer 624. The 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is between the electrode layer 607 and It occurs between the pixel electrode layer 624. Gate insulation is present between electrode layer 607 and pixel electrode layer 624. A film 606 is arranged, and the thickness of the gate insulating film 606 is between 50 nm and 200 nm. Since it is sufficiently thin compared to the thickness of the liquid crystal layer, which is between 2 μm and 10 μm, it is effectively the substrate 60 An electric field is generated in a direction parallel to zero (horizontal direction). This electric field controls the orientation of the liquid crystal. This uses an electric field approximately parallel to the substrate to rotate the liquid crystal molecules horizontally. Because crystal molecules are horizontal in all states, the influence of contrast and other factors depending on the viewing angle is minimal. This results in a wider field of view. In addition, both the electrode layer 607 and the pixel electrode layer 624 are made of light-transmitting material. Because it is a pole, the aperture ratio can be improved.

[0367] Next, we will show another example of a transverse electric field type liquid crystal display device.

[0368] Figures 32 and 33 show the pixel structure of an IPS-type liquid crystal display device. Figure 33 is a plan view. Yes, and Figure 32 shows the cross-sectional structure corresponding to the cutting line VW shown in the diagram.

[0369] Figure 32 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, This shows the state after the opposing substrate 601 has been placed on top and liquid crystal has been injected. A colored film 636, a planarization film 637, etc., are formed. The pixel electrodes are on the substrate 600 side. Therefore, no counter electrodes are installed on the opposing substrate 601 side. Substrate 600 and opposing substrate 60 A liquid crystal layer 650 is formed between 1 via alignment films 646 and 648.

[0370] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT628. Therefore, the thin-film transistors shown in Embodiments 1 to 5 can be applied.

[0371] The wiring 616 and wiring 618 of the TFT628 are formed on the gate insulating film 606. 6 is a data line in an LCD display panel that carries video signals and is a unidirectional wiring. At the same time, it connects to the source or drain area of ​​the TFT628, and the source and drain It becomes one electrode. Wiring 618 becomes the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0372] An insulating film 620 is formed on wiring 616 and wiring 618. In addition, insulating film 620 has an insulating layer. Pixel electrodes connected to wiring 618 via contact holes 623 formed in film 620 A layer 624 is formed. The pixel electrode layer 624 is the same as the pixel electrode layer shown in Embodiments 1 to 5 It is formed using the same material. Note that, as shown in Figure 33, the pixel electrode layer 624 is a common electric The comb-shaped electrode formed simultaneously with the position line 609 is formed so that a transverse electric field is generated. The comb-shaped portions of the base electrode layer 624 alternately bite with the comb-shaped electrodes formed simultaneously with the common potential line 609. They are formed to fit together.

[0373] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, This electric field controls the orientation of the liquid crystal. The liquid crystal is formed using an electric field approximately parallel to the substrate. Rotate the molecules horizontally. In this case, since the liquid crystal molecules are horizontal in any state, the viewing angle... The impact on contrast and other factors is minimal, resulting in a wider viewing angle.

[0374] In this way, the TFT 628 and the pixel electrode layer 624 connected to it are formed on the substrate 600. The retention capacitance is achieved by providing a gate insulating film 606 between the common potential line 609 and the capacitive electrode 615. , thereby forming the capacitive electrode 615 and the pixel electrode layer 624 in contact hole 63 It is connected via 3.

[0375] Next, we will describe the configuration of TN-type liquid crystal display devices.

[0376] Figures 34 and 35 show the pixel structure of a TN-type liquid crystal display device. Figure 35 is a plan view. Figure 34 shows the cross-sectional structure corresponding to the cutting line KL shown in the diagram. I will explain this by referring to these two figures.

[0377] The pixel electrode layer 624 has contact holes 623 and wiring 618 formed in the insulating film 620. It is connected to the TFT628 via [this]. Wiring 616, which functions as a data line, is connected to the TFT628. It is connected to 28. TFT628 applies one of the TFTs shown in Embodiments 1 to 5. It is possible.

[0378] The pixel electrode layer 624 is formed using the pixel electrode layer shown in Embodiments 1 to 5. The quantized wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the wiring 602 and the capacitance wiring 604. The retained capacitance is A gate insulating film 606 is formed between the capacitance wiring 604 and the capacitance electrode 615. The pole 615 and the pixel electrode layer 624 are connected via the contact hole 623.

[0379] A colored film 636 and a counter electrode layer 640 are formed on the opposing substrate 601. A planarization film 637 is formed between 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal. The liquid crystal layer 650 has an alignment film 648 and an alignment film between the pixel electrode layer 624 and the counter electrode layer 640. It is formed via film 646.

[0380] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the shape of the liquid crystal element. It has been done.

[0381] Furthermore, the colored film 636 may also be formed on the substrate 600 side. A polarizing plate is attached to the side opposite to the side where the transistor is formed, and the opposing substrate 601 A polarizing plate is attached to the side opposite to the side where the opposing electrode layer 640 is formed.

[0382] Through the above process, a liquid crystal display device can be manufactured as a display device.

[0383] (Embodiment 11) In this embodiment, another example of a semiconductor device manufacturing method, which is one embodiment of the present invention, is shown in Figure 37. I will explain.

[0384] A gate electrode layer is formed on a substrate having an insulating surface (S101 in Figure 37). Gate electrode layer The materials are molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, Using metallic materials such as neodymium and scandium, or alloy materials mainly composed of these, It can be formed by or by lamination.

[0385] A gate insulating layer is formed on the gate electrode layer (S102 in Figure 37). The gate insulating layer is made of plastic. Using the Zuma CVD method or sputtering method, a silicon oxide layer, a silicon nitride layer, and silicon oxide nitride are produced. A layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or in a laminated manner. In this embodiment, the gate insulating layer is made by plasma CVD with a film thickness of 200 nm or less. It forms a silicon nitride layer.

[0386] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is formed on the gate insulating layer. (S103 in Figure 37). In this embodiment, the In-Ga-Zn-O oxide semiconductor target Using a tweezers, an In-Ga-Zn-O oxide semiconductor film is deposited by sputtering. .

[0387] Next, using a resist mask formed by a photolithography process on an oxide semiconductor film, The material is then etched to form island-shaped oxide semiconductor layers (S104 in Figure 37).

[0388] Next, the oxide semiconductor layer is subjected to a heat treatment to dehydrate or dehydrogenate it. The temperature of the heat treatment for the transformation shall be 400°C or higher and less than 700°C for the substrate (S105 in Figure 37). In this embodiment, a heat treatment is performed at 450°C under a nitrogen atmosphere. Here, the heat treatment equipment The substrate is introduced into an electric furnace, one of the furnaces, and the oxide semiconductor layer is subjected to a nitrogen atmosphere. After heat treatment, prevent the re-incorporation of water and hydrogen into the oxide semiconductor layer without exposure to the atmosphere. , an oxide semiconductor layer is obtained. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. Using the same furnace, from the heating temperature T to a temperature sufficient to prevent water from entering again, specifically, Slowly cool under a nitrogen atmosphere until the temperature drops by more than 100°C below the heating temperature T. Without limitation, dehydration or dehydration under a noble gas atmosphere such as helium, neon, or argon. Perform elementary processing.

[0389] By heat-treating the oxide semiconductor layer at a temperature of 400°C to 700°C, the oxide semiconductor layer is de-oxidized. Hydration and dehydrogenation are achieved, and subsequent re-impregnation with water (H2O) can be prevented.

[0390] Furthermore, the heating apparatus is not limited to electric furnaces; for example, GRTA (Gas Rapid Th) thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) devices such as Anneal devices It is possible to use a LRTA device with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. The TA device utilizes not only lamps but also heat conduction or thermal radiation from heat-generating elements such as resistive heating elements. It may also be equipped with a device to heat the material to be processed. GRTA is a device that uses high-temperature gas to process This is a method of heat treatment. The gas used is a noble gas such as argon, or a gas such as nitrogen, which is heated. An inert gas that does not react with the material being treated is used during the process. Using the RTA method, 600 Heat treatment at 750°C for several minutes may also be performed.

[0391] Furthermore, in the heat treatment of dehydration or dehydrogenation, nitrogen, or helium, neon, or It is preferable that the noble gas such as argone does not contain water, hydrogen, etc. In particular, in the oxide semiconductor layer In contrast, dehydration and dehydrogenation heat treatments performed at 400°C to 700°C result in H2O at a concentration of 20 pp. It is preferable to carry out the procedure in a nitrogen atmosphere of m or less. Alternatively, nitrogen introduced into the heat treatment device, The purity of noble gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0392] Next, the resist mask formed by the photolithography process is used to determine the gate insulating layer. Remove the unnecessary parts and form an opening (contact hole) in the gate insulating layer (S in Figure 37). 106).

[0393] Next, a metallic conductive film made of a metallic material is deposited onto the oxide semiconductor layer using sputtering or vacuum deposition. It is formed by [this method].

[0394] The material for the metal conductive film is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Examples include alloys containing the aforementioned elements, or alloy films combining the aforementioned elements. Furthermore, the metal conductive film may be a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure of an aluminum film containing silicon, and a titanium film laminated on top of the aluminum film. Layered structure, Ti film, and an aluminum film stacked on top of the Ti film, and then Ti on top of that. Examples include a three-layer structure for forming a film. Also, aluminum can be combined with titanium (Ti) and tantalum (T). a) Tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), A film, alloy film, or combination of one or more elements selected from scandium (Sc). Alternatively, a nitride film may be used.

[0395] If heat treatment is performed after the metal conductive film is applied, the metal conductive film must have sufficient heat resistance to withstand this heat treatment. It is preferable to do so.

[0396] Next, a photolithography process is performed to form a resist mask, and the metal conductive film is etched. Unnecessary parts are removed by the process to form the source electrode layer and drain electrode layer (S in Figure 37). 107).

[0397] Furthermore, during the etching of the metal conductive film, the oxide semiconductor layer is not removed. Adjust the materials and etching conditions as appropriate.

[0398] In this embodiment, a Ti film, an Al film, and a Ti film are used as the metal conductive film, In-Ga-Zn-O oxide is used for the semiconductor layer, and ammonia peroxide is used as the etchant. A. Use a mixture of ammonia, water, and hydrogen peroxide.

[0399] Next, the target and substrate are heat-treated in a chamber where an oxide insulating film is formed (Figure 3). (7, S108). After the heat treatment, the target and substrate are cooled (Figure 37, S109), to room temperature. This forms an oxide insulating film (S110 in Figure 37). The heating temperature is between 100°C and 250°C. That's all you need to do.

[0400] The oxide insulating film shall have a thickness of at least 1 nm, (preferably 100 nm to 500 nm) Methods that do not introduce impurities such as water and hydrogen into the oxide insulating film, such as sputtering (less than nm). It can be formed using the appropriate method. In this embodiment, the oxide insulating film is made with a film thickness of 30 A 0 nm silicon oxide film is deposited using the sputtering method. The substrate temperature during film deposition is below room temperature. The temperature should be 300°C or lower, and in this embodiment, it is set to room temperature. Sputtering of silicon oxide film Thin film deposition by the galvanic gas method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas It can be carried out in an atmosphere of oxygen (typically argon) and oxygen. A silicon dioxide target or a silicon target can be used as the target. For example, silicon Using a target, silicon oxide can be formed by sputtering in an oxygen atmosphere. Yes, it is possible. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen. On, or OH - It does not contain impurities such as these, and blocks them from entering from the outside. An insulating film is used, typically a silicon oxide film, silicon nitride film, aluminum oxide film, or Aluminum oxide nitride film is used.

[0401] Furthermore, a protective insulating layer may be formed on the oxide insulating film. For example, RF sputtering A silicon nitride film is formed using the sputtering method. RF sputtering is suitable for mass production, and therefore protects This is a preferred method for forming an insulating layer. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - etc. Using an inorganic insulating film that is free of impurities and blocks their intrusion from the outside, nitridation Silicon films, aluminum nitride films, silicon nitride oxide films, aluminum oxide nitride films, etc., are used. In this embodiment, a silicon nitride film is used as the protective insulating layer.

[0402] A silicon oxide insulating film with a thickness of 100 nm was formed by sputtering (under an oxygen atmosphere, at room temperature). The base film is used, and the protective insulating layer to be laminated is produced by sputtering (under a nitrogen and argon atmosphere, at room temperature). A configuration that forms a film thickness of 100 nm is also possible.

[0403] Furthermore, after the formation of the oxide insulating film, heat treatment is performed under an inert gas atmosphere or a nitrogen gas atmosphere. Even if you perform the procedure (preferably between 200°C and 400°C, for example between 250°C and 350°C), Good. For example, heat treatment at 250°C for 1 hour under a nitrogen atmosphere.

[0404] Next, the oxide insulating film and the protective insulating layer are selectively etched to form openings (S1 in Figure 37). 11) A planar insulating layer may be formed on the protective insulating layer. Material and method of forming the planar insulating layer. Depending on the method, heat treatment at around 250°C may be performed during formation, in which case the aforementioned oxide After the formation of the insulating film, the heat treatment under an inert gas atmosphere or nitrogen gas atmosphere can be omitted. good.

[0405] Next, a light-transmitting conductive film is formed. The material for the light-transmitting conductive film is an oxide Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT These are formed using sputtering or vacuum deposition methods (abbreviated as O). As another material for conductive films, there is a nitrogen-containing Al-Zn-O non-single crystal film, i.e., Al- Zn-ON non-single crystal films, nitrogen-containing Zn-O non-single crystal films, and nitrogen-containing Sn-Zn-O non-single crystal films may also be used. Furthermore, Al-Zn-ON non-single crystal films may also be used. The composition ratio (atomic %) of zinc shall be 47 atomic % or less, and the composition ratio of aluminum in the non-single crystal film The composition ratio of aluminum in a non-single crystal film (atomic %) is greater than (atomic %), and the composition ratio of aluminum in a non-single crystal film (atomic %) is greater than (atomic %). The nitrogen content (atomic %) is greater than the composition ratio within it. Etching treatment of such materials is performed using hydrochloric acid-based solutions. This is done using a solution. However, etching ITO in particular tends to generate residue, so etching Even when using indium zinc oxide alloy (In2O3-ZnO) to improve machinability good.

[0406] Next, a photolithography process is performed to form a resist mask, and then light is transmitted by etching. Unnecessary portions of the conductive film having properties are removed to form a pixel electrode layer and a conductive layer, and a resist mask is formed. Remove (S112 in Figure 37).

[0407] Next, heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. (Figure 37, S113). In this embodiment, the heat treatment is performed at 150°C for 10 hours. The process may involve heating while maintaining a constant heating temperature, or heating from room temperature to 100°C or above 200°C. The process of raising the temperature to the heating temperature and then lowering it back to room temperature may be repeated multiple times. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By performing this procedure, the heating time can be shortened. This heat treatment allows the oxide semiconductor layer to be shortened. By incorporating hydrogen into the oxide insulating layer, a thin-film transistor that is normally off can be obtained. This allows for improved reliability of semiconductor devices.

[0408] Through the above process, thin-film transistors are fabricated on the same substrate for both the drive circuit and the pixel. It can be manufactured.

[0409] Similar to Embodiment 1, the liquid crystal layer is sandwiched and the opposing substrate is bonded together, and the liquid crystal surface of this embodiment A display device can be manufactured.

[0410] (Embodiment 12) In this embodiment, Figure 38 shows an example where the oxide semiconductor layer is surrounded by a nitride insulating film when viewed in cross-section. Figure 38 shows the differences between the top surface shape and edge position of the oxide insulating layer and the gate insulating layer in Figure 1. Since they are the same except for the differences in structure, the same symbols are used for the same parts, and the details of the same parts I will omit the explanation.

[0411] The thin-film transistor 180 placed in the drive circuit is a channel-etch type thin-film transistor. There is a gate electrode layer 161 and a nitride insulating film layer on a substrate 100 having an insulating surface. A first gate insulating layer 188, a second gate insulating layer 187a made of an oxide insulating film, and an oxide insulating film It includes a conductive layer 163, a source electrode layer 165a, and a drain electrode layer 165b. The oxide semiconductor layer covering the transistor 180 is in contact with the channel formation region of the oxide semiconductor layer 163. An edge layer 177a is provided. A protective insulating layer 178 is further provided on the oxide insulating layer 177a. Formed, and further on the oxide insulating layer 177a, the gate electrode layer 161 and the oxide semiconductor A conductive layer 111 is provided in a position that overlaps with layer 163.

[0412] The thin-film transistor 170 placed in the pixel area is a channel-etch type thin-film transistor. Furthermore, on a substrate 100 having an insulating surface, a gate electrode layer 101 and a first nitride insulating film are placed. The gate insulating layer 188, the second gate insulating layer 187b made of an oxide insulating film, and the oxide semiconductor It includes a body layer 103, a source electrode layer 105a, and a drain electrode layer 105b. An oxide insulating layer that covers the transistor 170 and is in contact with the channel formation region of the oxide semiconductor layer 103. A layer 177b is provided. A protective insulating layer 178 is further formed on the oxide insulating layer 177b. Furthermore, the pixel electrode layer is in contact with the drain electrode layer 105b on the protective insulating layer 178. 110 is provided.

[0413] In this embodiment, the gate insulating layer in thin-film transistors 170 and 180 is the gate electrode. The layered structure consists of a nitride insulating film and an oxide insulating film from the layer side. In addition, the openings in the oxide insulating layer are During formation, the oxide insulating film of the second gate insulating layer is also selectively removed, and the nitride insulating film is exposed. Process it so that it comes out.

[0414] At least the oxide insulating layers 177a, 177b and the second gate insulating layers 187a, 187b The top surface shape is wider than the top surface shape of the oxide semiconductor layers 163 and 103, and thin-film transistor 1 It is preferable to have an upper surface shape that covers 80 and 170.

[0415] Furthermore, the top and side surfaces of the oxide insulating layers 177a and 177b are covered, and the first gate insulating layer A protective insulating layer 178 made of a nitride insulating film is formed in contact with the nitride insulating film.

[0416] The protective insulating layer 178 and the first gate insulating layer 188, which are made of a nitride insulating film, are sputtering Silicon nitride films, silicon oxide nitride films, aluminum nitride films, obtained by the CVD method or plasma CVD method. Moisture, hydrogen ions, and OH in aluminum oxide and nitride films, etc. - It does not contain impurities such as An inorganic insulating film is used to block these from entering from the outside.

[0417] In this embodiment, the protective insulating layer 178, which is made of a nitride insulating film, is an oxide semiconductor layer 16 3. RF sputtering was used to surround the top and side surfaces of 103, resulting in a film thickness of 100 nm. A silicon nitride film is provided. In addition, a protective insulating layer 178 is provided as a first gate insulating film made of nitride insulating film. The configuration will be in contact with the marginal layer 188.

[0418] By adopting the structure shown in Figure 38, the manufacturing process after the formation of the protective insulating layer 178 made of a nitride insulating film is performed. In the process, it is possible to prevent the intrusion of moisture from the outside. Also, semiconductor devices, for example Even after the device is completed as a liquid crystal display, it will not be able to prevent moisture from entering from the outside over the long term. This can improve the long-term reliability of the device.

[0419] Furthermore, this embodiment shows a configuration in which one thin-film transistor is surrounded by a nitride insulating film, but The configuration is not limited to this, and multiple thin-film transistors may be surrounded by a nitride insulating film, or pixels A configuration in which multiple thin-film transistors are grouped together and surrounded by a nitride insulating film is also possible. A protective insulating layer 178 and a first gate surround the periphery of the pixel area of ​​the active matrix substrate. The configuration should include a region in contact with the insulating layer 188.

[0420] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Explanation of Symbols]

[0421] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminals 22 Input terminals 23 Input terminals 24 input terminals 25 Input terminals 26 output terminals 27 Output terminals 28 Thin-film transistors 31 transistors 32 transistors 33 transistors 34 transistors 35 transistors 36 transistors 37 transistors 38 transistors 39 Transistors 40 transistors 41 Transistors 42 transistors 43 transistors 51 Power line 52 Power line 53 Power line 100 circuit boards 101 Electrode 102 Gate Insulation Layer 103 Oxide semiconductor layer 107 Oxide insulating film 108 Capacitance wiring 109 Planarized insulating layer 110 Pixel electrode layer 111 Conductive layer 116 Channel formation region 118 Contact Holes 119 Contact Holes 120 connecting electrodes 121 terminals 122 terminals 125 Contact Holes 126 Contact Holes 127 Contact Holes 128 Terminal electrode 129 Terminal electrode 130 Oxide semiconductor film 131 Oxide semiconductor layer 133 Oxide semiconductor layer 134 Oxide semiconductor layer 137 Resist Mask 138 Oxide conductive layer 140 Oxide conductive film 142 Oxide conductive layer 143 Oxide conductive layer 145 Wiring layer 146 capacity 147 capacity 148 capacity 150 terminals 151 terminals 153 Connecting electrodes 155 Conductive film 156 Electrode 161 Grid control platform 162 Conductive layer 163 Oxide semiconductor layer 166 Channel formation region 168 Oxide semiconductor layer 170 Thin-Film Transistors 171 Thin-film transistors 172 Thin-film transistors 173 Thin-film transistors 178 Protective insulating layer 180 Thin-Film Transistors 181 Thin-film transistors 182 Thin-film transistors 183 Thin-film transistors 188 Gate Insulation Layer 190 Opposing substrate 191 Insulating layer 192 Liquid crystal layer 193 Insulating layer 194 Counter electrode layer 195 Colored layer 202 Gate Insulation Layer 203 Protective insulating layer 206 Common electrode layer 210 Common potential line 220 Thin-Film Transistors 227 Pixel electrode layer 402 Gate Insulation Layer 600 circuit boards 601 Opposing substrate 602 Gate Wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate Insulator 607 Electrode layer 609 Common potential line 615 Capacitive electrode 616 Wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact Hole 624 Pixel Electrode Layer 625 Slit 626 Pixel Electrode Layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 alignment film 648 Alignment film 650 liquid crystal layers 651 Liquid crystal elements 652 liquid crystal elements 104a Oxide conductive layer 104b Oxide conductive layer 105a Source electrode layer 105b Drain electrode layer 117a High-resistance source region 117b High-resistance drain region 135a Resist Mask 136a Resist Mask 164a Oxide conductive layer 164b Oxide conductive layer 165a Source electrode layer 165b Drain electrode layer 167a High-resistance source region 167b High-resistance drain region 177a Oxide insulating layer 177b Oxide insulating layer 187a Gate insulating layer 187b Gate insulating layer 196a Polarizing plate 2600 TFT substrate 2601 Opposing substrate 2602 Sealant 2603 pixel section 2604 display elements 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible Wiring Board 2610 cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Thin-Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4020 Protective Insulation Layer 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4035 Spacer 4040 conductive layer 5300 circuit boards 5301 pixel section 5302 Scan line drive circuit 5303 Scan line drive circuit 5304 Signal Line Drive Circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper enclosure 9302 Lower enclosure 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display section 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section

Claims

1. A device comprising a first transistor, a second transistor, and a capacitor, The first transistor described above includes a first gate electrode layer, a first oxide semiconductor layer, a first source electrode layer, a first drain electrode layer, and a second gate electrode layer. The second transistor comprises a third gate electrode layer, a second oxide semiconductor layer, a second source electrode layer, and a second drain electrode layer. The first transistor has a dual-gate structure in which the first gate electrode layer and the second gate electrode layer overlap via the first oxide semiconductor layer. The second transistor has a single-gate structure having a region where the third gate electrode layer and the second oxide semiconductor layer overlap. The channel formation region of the first transistor is provided in the first oxide semiconductor layer, The channel formation region of the second transistor is provided in the second oxide semiconductor layer, The first oxide semiconductor layer comprises indium, gallium, and zinc. The second oxide semiconductor layer comprises indium, gallium, and zinc. The aforementioned capacitor comprises a first conductive layer, a first insulating layer, a second insulating layer, and a second conductive layer. The first conductive layer has a region that overlaps with the second conductive layer via the first insulating layer and the second insulating layer. The first conductive layer is provided on the same layer as the first gate electrode layer and is made of the same material. The second conductive layer has a region that functions as a pixel electrode electrically connected to either the second source electrode or the second drain electrode, The first insulating layer has a region in contact with the lower surface of the first oxide semiconductor layer, a region in contact with the upper surface of the first gate electrode layer, a region in contact with the lower surface of the second oxide semiconductor layer, and a region in contact with the upper surface of the third gate electrode layer. The second insulating layer has a region in contact with the upper surface of the first oxide semiconductor layer, a region in contact with the lower surface of the pixel electrode, and a region in contact with the upper surface of the second oxide semiconductor layer. Either the first source electrode layer or the first drain electrode layer is electrically connected to the third conductive layer. The third conductive layer is provided on the same layer as the first gate electrode layer and is made of the same material. In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a region at its edge that is in contact with the other of the first source electrode layer or the first drain electrode layer. In a cross-sectional view of the first transistor in the channel length direction, the edge of the first oxide semiconductor layer having a region in contact with the other of the first source electrode layer or the first drain electrode layer does not have a region overlapping with the first gate electrode layer and does not have a region overlapping with the second gate electrode layer. In a cross-sectional view of the second transistor in the channel length direction, the second oxide semiconductor layer has a region at its edge that is in contact with either the second source electrode layer or the second drain electrode layer. A display device wherein, in a cross-sectional view of the second transistor in the channel length direction, the end of the second oxide semiconductor layer having a region in contact with either the second source electrode layer or the second drain electrode layer does not have a region overlapping with the third gate electrode layer.

2. In Claim 1, An organic resin layer is provided, The organic resin layer is a display device having a region located between the second insulating layer and the second conductive layer.

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