Synchronous rectifier for use in wireless power transmission systems, and method for synchronous rectification in wireless power transmission.

Abstract

A rectifier for use in a receiver of a wireless power transfer system for receiving wireless power transmitted from a transmitter of the wireless power transfer system is provided. The rectifier includes a field effect transistor (FET) having a source terminal electrically connected to ground and a drain terminal electrically connected to a receiving element of the receiver. The receiving element is for extracting power from the transmitter of the wireless power transfer system. The FET further includes a gate terminal electrically connected to the receiving element. The gate terminal is driven by a gate signal that is in phase with an input signal received at the receiving element.

Description

[Technical Field]

[0001] This disclosure relates in general to wireless power transmission, and more particularly to synchronous rectifiers used in wireless power transmission systems, and to methods for synchronous rectification in wireless power transmission. [Background technology]

[0002] Wireless charging and wireless power transmission systems are becoming increasingly important technologies for enabling next-generation devices. The potential benefits and advantages offered by these technologies are evident in the increasing number of manufacturers and companies investing in them.

[0003] A variety of wireless power transmission systems are known. A typical wireless power transmission system includes a wireless power transmitter, which has a power supply electrically connected to the transmitting element, and a wireless power receiver, which has a receiving element electrically connected to the load.

[0004] For example, in a magnetic induction system, a transmitting element has an induction coil, which transmits electrical energy from a power source to an induction coil in a receiving element. The transmitted electrical energy is then applied to a load. Power transmission occurs through the coupling of magnetic fields between the transmitting and receiving elements. However, the range of these magnetic induction systems is limited, and the transmitting and receiving elements must be in an optimal position-matched state for power transmission. There are also resonant magnetic systems that transmit power through the coupling of magnetic fields between the transmitting and receiving elements. In these resonant magnetic systems, the transmitting and receiving elements resonate using high-Q capacitors. The range of power transmission in resonant magnetic systems is increased compared to that of magnetic induction systems, and the position-matching problem is resolved. While electromagnetic energy is generated in both magnetic induction and resonant magnetic systems, the majority of power transmission occurs via magnetic fields. Only a small amount of power, if any, is transmitted via electrical induction or resonant electric induction.

[0005] Another example of a wireless power system is the field-coupled system, in which the transmitting and receiving elements have capacitive electrodes, and power transmission occurs through the coupling of the electric field between the capacitive electrodes of the transmitting and receiving elements. Resonant electric field systems also exist, in which the capacitive electrodes of the transmitting and receiving elements resonate using a high-Q inductor. Similar to resonant magnetic systems, resonant electric field systems also have an increased power transmission range compared to non-resonant electric field systems, and positional matching problems are corrected. While electromagnetic energy is generated in electric induction and resonant electric systems, the majority of power transmission occurs via electric fields. Power transmitted via magnetic induction or resonant magnetic induction is minimal, if any.

[0006] Other exemplary wireless power systems can transmit power using radio frequency (RF) waves. Controlled constructive interference of RF waves creates energy in the receiver, resulting in the wireless transmission of power. [Overview of the project] [Problems that the invention aims to solve]

[0007] While systems, transmitters, receivers, and methods for wireless power transmission are known, improvements are desired. [Means for solving the problem]

[0008] This background is merely there to provide context so that those skilled in the art may better understand the following description. Therefore, none of the above discussions should necessarily be considered an admission that the discussions are part of the current art or common knowledge. One or more aspects / embodiments of this disclosure may or may not address one or more of the background issues.

[0009] According to one aspect of the present disclosure, a rectifier for use in a receiver of a wireless power transmission system is provided for receiving wireless power transmitted from a transmitter of a wireless power transmission system, the rectifier comprising a field-effect transistor (FET), the field-effect transistor (FET) comprising a source terminal electrically connected to ground, a drain terminal electrically connected to a receiving element of the receiver, the receiving element being for extracting power from the transmitter of the wireless power transmission system, and a gate terminal electrically connected to the receiving element, the gate terminal being driven by a gate signal in phase with an input signal received in the receiving element.

[0010] The rectifier is a trigger circuit electrically connected to a receiving element and a gate driver, and may further include a trigger circuit that outputs a trigger signal for operating the gate driver.

[0011] The trigger signal may include a pulse signal.

[0012] The trigger circuit may include a sampling circuit for sampling the input signal.

[0013] The sampling circuit can be a voltage divider.

[0014] The trigger circuit may further include a delay line to delay the output of the sampling circuit so that the input signal received at the drain element and the gate signal are synchronized.

[0015] The trigger circuit may further include a comparator for generating a clock signal by comparing the delayed signal output by the delay line with a DC voltage level.

[0016] The trigger circuit may include a resistor-capacitor (RC) delay circuit to delay the output of the sampling circuit so that the input signal received at the receiving element and the gate signal are synchronized.

[0017] An RC delay circuit may comprise at least one resistor electrically connected to at least one capacitor.

[0018] The trigger circuit may include a comparator for generating a clock signal by comparing the delayed signal output by the RC delay circuit with a DC voltage level.

[0019] The rectifier may further comprise a gate driver that receives a trigger signal and generates a gate signal, the gate signal being input to a gate terminal to control the operation of the rectifier.

[0020] The rectifier may further include an input stage for at least one of the following: optimizing the load impedance, ensuring that the current input to the drain terminal is approximately sinusoidal, and reducing harmonics.

[0021] The input stage may be equipped with a double impedance inverter circuit.

[0022] The rectifier may further include a converter for transforming the signal to supply power to the trigger circuit.

[0023] The rectifier can be a load-independent Class E synchronous rectifier.

[0024] According to another aspect of the present disclosure, a receiver is provided for extracting power from a transmitter of a wireless power transmission system, the receiver comprising a receiving element for receiving wireless power transmitted from the transmitter and a rectifier, one of the described rectifiers, electrically connected to the receiving element.

[0025] The receiving element may be designed to extract power via electric field coupling or magnetic field coupling.

[0026] The receiving element may be designed to extract power via resonant and / or non-resonant electric field coupling or magnetic field coupling.

[0027] The input signal received by the receiving element can be an alternating current (AC) signal.

[0028] The receiver may further include a load electrically connected to the rectifier.

[0029] Another aspect of the present disclosure provides a wireless power transmission system for transmitting power via magnetic field coupling or electric field coupling, the wireless power transmission system comprising a transmitter having a transmitting element for generating a magnetic field or an electric field, and a receiver having a receiving element for extracting power from a magnetic field via magnetic field coupling or from an electric field via electric field coupling, and a rectifier, one of the described rectifiers, electrically connected to the receiving element.

[0030] The wireless power transmission system may also be equipped with a power supply electrically connected to the transmitter.

[0031] The wireless power transmission system may further include a load electrically connected to the rectifier.

[0032] Another aspect of the present disclosure provides a method for rectifying an input signal received in a receiving element of a receiver of a wireless power transmission system, the receiver comprising a rectifier comprising a field-effect transistor (FET), the field-effect transistor (FET) comprising a source terminal electrically connected to ground, a drain terminal electrically connected to the receiving element, and a gate terminal electrically connected to the receiving element, the method comprising driving the gate terminal with a gate signal in phase with the input signal received in the receiving element.

[0033] The method may further include driving a gate driver to generate a gate signal.

[0034] The method may further include receiving an input signal in a trigger circuit and operating a gate driver via the trigger signal output by the trigger circuit.

[0035] The trigger signal may include a pulse signal.

[0036] The method may further include sampling the input signal through a sampling circuit.

[0037] The method may further include delaying the output of the sampling circuit so that the input signal and the gate signal received at the receiving element are synchronized.

[0038] Delaying the output can include delaying the output via a delay line or an RC delay circuit.

[0039] The method may further include at least one of the following: optimizing the load impedance, ensuring that the current input to the drain terminal is approximately sinusoidal, and reducing harmonics.

[0040] Another aspect of the present disclosure provides a method for receiving wireless power, the method comprising: extracting power by a receiving element of a receiver of a wireless power transmission system from a magnetic or electric field generated by a transmitting element of a transmitter of a wireless power transmission system; and rectifying the extracted power using a field-effect transistor (FET), the FET being controlled via a gate signal in phase with the signal of the extracted power.

[0041] It should be understood that any feature described in relation to one aspect, example, or embodiment of this disclosure may also be applicable to any other aspect or embodiment of this disclosure.

[0042] Those skilled in the art will see from the detailed description, along with the accompanying drawings, that other advantages of this disclosure will become apparent.

[0043] Next, I will explain using the attached diagram as just one example. [Brief explanation of the drawing]

[0044] [Figure 1] This is a block diagram of a wireless power transmission system. [Figure 2] This is a block diagram of a receiver for a wireless power transmission system. [Figure 3] This is a block diagram of a rectifier according to one aspect of the present disclosure, used in a wireless power transmission system. [Figure 4] This is a block diagram of a receiver including a rectifier according to one aspect of the present disclosure. [Figure 5] This is a schematic diagram of a model of the receiving element of a receiver in a wireless power transmission system. [Figure 6] This is a schematic diagram of a portion of a rectifier according to one aspect of the present disclosure. [Figure 7] This is a block diagram of a portion of a rectifier according to one aspect of the present disclosure. [Figure 8] This is a schematic diagram of a portion of a rectifier according to one aspect of the present disclosure. [Figure 9] This is a schematic diagram of a portion of a rectifier according to one aspect of the present disclosure. [Figure 10] This is a graph showing the relationship between input power, output power, and load current for an experimental design of a wireless power transmission system equipped with a rectifier according to one aspect of this disclosure. [Figure 11] This is a graph showing the relationship between the power transmission efficiency and load current of this experimental design. [Figure 12] This graph shows the relationship between the input voltage, output voltage, and rectified voltage of this experimental design, and the load current. [Figure 13] This is a graph showing the response of the rectified voltage to the load step in this experimental design. [Figure 14] This graph shows the rectifier switch node voltages of this experimental design before and after load application. [Figure 15] This is a graph showing the relationship between input power, output power, and load current for another experimental design of a wireless power transmission system equipped with a rectifier according to one aspect of the present disclosure. [Figure 16] This is a graph showing the relationship between the power transmission efficiency and load current of another experimental design. [Figure 17] This is a graph showing the relationship between the input voltage, output voltage, and rectified voltage of this other experimental design, and the load current. [Figure 18]This is a graph showing the response of the rectified voltage to the load step in this experimental design. [Figure 19] This graph shows the rectifier switch node voltages of this experimental design before and after load application. [Figure 20] This is a schematic diagram of a receiver including a portion of another rectifier according to one aspect of the present disclosure. [Figure 21] This is a graph showing the received voltage and current, as well as the trigger signal generated by this rectifier. [Figure 22] This is a block diagram of a portion of a rectifier according to one aspect of the present disclosure. [Figure 23] This is a schematic diagram of a part of this rectifier. [Figure 24] This is a schematic diagram of a part of this rectifier. [Figure 25] This is a schematic diagram of a part of this rectifier. [Figure 26] This graph shows the received voltage and current, trigger signal, and delay signal for various resistance values ​​in this rectifier. [Modes for carrying out the invention]

[0045] The above overview, as well as the following detailed descriptions of some embodiments, will be better understood when read in conjunction with the accompanying drawings. To ensure understanding, similar reference letters are used throughout the description and drawings to refer to similar elements. In this specification, an element or feature described in the singular and preceded by the words “a” or “an” should not be understood as necessarily excluding multiple such elements or features. Furthermore, the reference to “an example” or “an embodiment” is not intended to be construed as excluding the existence of additional examples or embodiments that also incorporate the elements or features described in that example or embodiment. Furthermore, unless otherwise explicitly stated, an example or embodiment that “comprises,” “having,” or “includes” one or more elements or features having a particular nature may further include additional elements or features that do not possess that particular nature. Furthermore, it will be understood that the terms "comprises," "has," and "includes" mean "to include but not limited to," and that the terms "comprising," "having," and "including" have equivalent meanings.

[0046] In this specification, the term "and / or" may include any combination of one or more of the related enumerated elements or features.

[0047] When an element or feature is described as being "on top of," "attached to," "connected to," "combined with," or "in contact with" another element or feature, it is understood that the element or feature may directly be on top of, attached to, connected to, combined with, or in contact with another element or feature, or that an intervening element may exist. In contrast, when an element or feature is described as being, for example, "directly on top of," "directly attached to," "directly connected to," "directly combined with," or "in direct contact with" another element or feature, there is no intervening element or feature.

[0048] It will be understood that spatial relative terms such as "under," "below," "lower," "over," "above," "upper," "front," and "back" may be used herein to facilitate the explanation of the relationship between one element or feature and another as depicted in a diagram. However, spatial relative terms can encompass various orientations in use or action, in addition to the orientation depicted in the diagram.

[0049] In this specification, the term “Example” means that one or more features, structures, elements, components, characteristics, and / or operational steps described in relation to that example are included in at least one embodiment and / or implementation of the subject matter of this disclosure. Thus, throughout this disclosure, the phrases “One Example,” “Another Example,” and similar wording may, but not necessarily, refer to the same example. Furthermore, the subject matter characterizing any one example may, but not necessarily, include the subject matter characterizing any other example.

[0050] In this specification, the term “configured” refers to an actual state of configuration that essentially links an element or feature to the physical properties of that element or feature preceding the phrase “configured to be configured to be.”

[0051] Unless otherwise indicated, terms such as “first,” “second,” etc., are used solely as labels in this specification and are not intended to impose any sequential, positional, or hierarchical requirements on the items they refer to. Furthermore, a reference to a “second” item neither requires nor excludes the existence of smaller numbered items (e.g., a “first” item) and / or larger numbered items (e.g., a “third” item).

[0052] In this specification, the terms “approximately” and “about” refer to an amount close to the stated amount that still performs the desired function or achieves the desired result. For example, the terms “approximately” and “about” may refer to amounts less than 10%, less than 5%, less than 1%, less than 0.1%, or less than 0.01% of the stated amount.

[0053] The use of the word "exemplary" means "as an example" or "an example of," unless otherwise specified, and does not imply a preferred or optimal design, configuration, or implementation.

[0054] Now, moving to Figure 1, we see the wireless power transmission system 2. The wireless power transmission system 2 comprises a transmitter 10 with a power supply 12 electrically connected to a transmitting element 14, and a receiver 16 with a receiving element 18 electrically connected to a load 20. Power is transmitted from the power supply 12 to the transmitting element 14. Power is then transmitted from the transmitting element 14 to the receiving element 18 via resonant or non-resonant electric field coupling or magnetic field coupling. Power is then transmitted from the receiving element 18 to the load 20.

[0055] Moving on to Figure 2, an exemplary receiver 22 is shown in more detail. The receiver 22 comprises a receiving element 24, a rectifier 26, a converter 28, and a load 30. The receiving element 24 is electrically connected to the rectifier 26. The receiving element 24 is configured to receive power from a transmitter, for example, transmitter 10, using resonant or non-resonant field coupling or magnetic field coupling. The receiving element 24 can extract power from the transmitter via non-resonant or resonant magnetic field coupling or field coupling. Thus, the receiving element 24 comprises one or more receiving coils (i.e., inductors) or one or more capacitive electrodes. The corresponding transmitters each comprise a corresponding transmitting coil (i.e., inductor) or capacitive electrodes.

[0056] The rectifier 26 is electrically connected to the receiving element 24. The rectifier 26 is electrically connected to the converter 28. The rectifier 26 is an AC / DC rectifier. In general, the rectifier 26 is used to rectify the AC received by the receiving element 24 to DC. Specifically, the rectifier 26 is used to convert the sinusoidal radio frequency (RF) power signal from the receiving element 24 into a DC power signal. The rectifier 26 is configured to output the DC power signal to the converter 28.

[0057] Converter 28 is electrically connected to rectifier 26. Converter 28 is electrically connected to load 30. Converter 28 is a DC / DC converter. A DC power signal is output from rectifier 26 and reaches converter 28. Converter 28 interfaces rectifier 26 with load 30. Converter 28 is for converting the received DC voltage signal to a desired voltage level. The converted DC power signal is output from converter 28 and reaches load 30.

[0058] Load 30 is electrically connected to converter 28. Load 30 may be a fixed load or a variable load.

[0059] The receiver 22 has been described as having a converter 28, but those skilled in the art will understand that other configurations are possible. In another embodiment, the receiver 22 does not have a converter 28. In this embodiment, a rectifier 26 is electrically connected to the load 30. The rectifier 26 is configured to generate a DC power signal that is acceptable to the load 30.

[0060] As mentioned earlier, the rectifier 26 is used to convert the sinusoidal RF power signal from the receiving element 24 into a DC power signal. The operation of the rectifier 26 may not be synchronized with the sinusoidal RF power signal. Therefore, it may be necessary to synchronize the switching point within the rectifier 26 with the waveform of the received sinusoidal RF power signal. If the switching point is asynchronous, it may lead to a loss of received power, which can reduce power transmission efficiency and result in insufficient power being supplied to the load 30.

[0061] The rectifier 26 may include at least one diode for rectifying AC to DC. Generally, the diode is placed between the AC source and the load configured to operate using DC. The diode acts like a valve for current by allowing current to flow in one direction and blocking current to flow in the other direction. Thus, while AC is flowing in the first direction, the diode acts like a closed switch (i.e., forward biased), allowing current to reach the load 30. While AC is flowing in the second direction opposite to the first direction, the diode acts like an open switch (i.e., reverse biased), preventing current from reaching the load 30. Thus, a unidirectional current flows to the load 30 without a change of polarity.

[0062] Diodes are generally lossy electrical components in that they consume a considerable amount of power that they rectify. For example, a diode consumes approximately 0.7V of forward bias if it has a forward threshold of 0.7V. Therefore, when current flows through a diode, there is a voltage drop of 0.7V across the diode.

[0063] To reduce, at least partially, the effects of the diode losses in the rectifier 26, the rectifier 26 may instead be equipped with a transistor, such as a field-effect transistor (FET). The gate of the FET is biased by a separate power supply. The current between the source and drain of the FET is controlled by the gate voltage.

[0064] As mentioned earlier, it may be necessary to synchronize the switching point within the rectifier 26 with the waveform of the received sinusoidal RF power signal. For example, if the switching point is synchronized, it is possible to increase the power transmission efficiency and ensure that sufficient power is supplied to the load 30 and / or converter 28.

[0065] Broadly speaking, the rectifier of this disclosure comprises a source terminal electrically connected to ground and a drain terminal electrically connected to a receiving element of a receiver of a wireless power transmission system. The receiving element is for extracting power from a transmitter of the wireless power transmission system. The rectifier further comprises a gate terminal electrically connected to the receiving element. The gate terminal is driven by a gate signal that is in phase with the input signal received in the receiving element.

[0066] The gate signal controls the current behavior between the source and drain, and therefore controls the rectification of the input signal received in the receiving element. Since the gate signal is in phase with the input signal, the FET operates as a Class E inverter. Class E inverters generally operate with high efficiency, resulting in a highly efficient rectifier. Details of the rectifier of this disclosure are described below.

[0067] Next, moving to Figure 3, a block diagram of a rectifier 100 according to one aspect of the present disclosure is shown. The rectifier 100 is for use in a wireless power transmission system. Specifically, the rectifier 100 is suitable for use in a receiver of a wireless power transmission system. As will be described later, the rectifier 100 is a synchronous rectifier.

[0068] The rectifier 100 comprises a rectifier element 114, an auxiliary DC / DC converter 118, a trigger circuit 122, and a gate driver 120. The rectifier element 114 is for rectifying the input RF power to DC. The rectifier element 114 is electrically connected to the trigger circuit 122 and the auxiliary DC / DC converter 118. The rectifier element 114 comprises at least one FET. The FET of the rectifier element 114 is electrically connected to the gate driver 120 at its gate terminal, thereby controlling the rectifier element 114 by the gate driver 120, as will be described later.

[0069] In this embodiment, the rectifier element 114 comprises a load-independent Class E rectifier. Generally, in Class E rectifiers, the performance of the rectifier is optimized to a specified output load, i.e., a desired load. During operation, when the output load deviates from the desired load, the DC voltage of the rectifier fluctuates significantly. Furthermore, when the output load deviates from the desired load, the zero-voltage switching (ZVS) operation of the rectifier switch is impaired, which can result in a decrease in the efficiency of the rectifier. In contrast, a load-independent Class E rectifier maintains the ZVS operation of the rectifier switch from the no-load state, i.e., zero-load state, to the full-load state. In addition, the rectified voltage is relatively constant between the no-load and full-load states. Switching losses from the no-load to the full-load state are approximately constant, and efficiency is generally unaffected.

[0070] The design of this class E rectifier is adapted to convert the input RF power into DC. The operating frequency or switching frequency of the rectifier element 114 can be, for example, 13.56 MHz and 27.12 MHz. The rectified voltage or signal output by the rectifier element 114 is V rect . The RF power input to the rectifier element 114 is V in . In this embodiment, the rectified DC voltage, that is, V rect is not regulated. Since the rectifier element 114 includes a load-independent rectifier, the waveform of the switching node does not vary significantly with the load as described above. Therefore, the rectified voltage is relatively stable.

[0071] The auxiliary DC / DC converter 118 is electrically connected to the gate driver 120, the trigger circuit 122, and the rectifier element 114. The converter 118 is for converting the V rect output by the rectifier element 114 into an auxiliary voltage range, for example, within the range of 5V, that is, V aux , for powering the trigger circuit 122 and the gate driver 120. The auxiliary power supply voltage or signal V aux powers the trigger circuit 122 and the gate driver 120. Until the auxiliary DC / DC converter 118 can regulate, the FET of the rectifier element 114 is off, and the rectifier element 114 acts as a passive (diode) rectifier. In this embodiment, the auxiliary DC / DC converter 118 includes a low-power buck converter.

[0072] The trigger circuit 122 is electrically connected to the gate driver 120, the auxiliary DC / DC converter 118, and the rectifier element 114. The trigger circuit is powered by a signal from the auxiliary DC / DC converter 118, for example, V aux . The trigger circuit 122 samples the RF power input V in received by the rectifier element 114 to generate a properly timed trigger voltage V trig . The trigger voltage or signal V trigThis is the gate drive voltage or gate signal V output by the gate driver. gate is input V in The timing is synchronized so that it is in phase with the gate. The trigger circuit 122 is triggered by the gate drive voltage or gate signal V output by the gate driver 120. gate This is to ensure the correct timing. As will be explained later, the trigger circuit 122 receives the input signal V in Use the trigger signal V to restore timing. trig It is configured to provide the trigger signal V. trig This includes pulse signals.

[0073] Ideally, the rectifier element 114 is open when the input current is positive and closed when the input current is negative, resulting in proper rectification. Assuming perfect tuning, V gate is V in It should be in phase with [the other object].

[0074] The gate driver 120 is electrically connected to the rectifier element 114, the auxiliary DC / DC converter 118, and the trigger circuit 122. The gate driver 120 receives a signal (e.g., V) from the auxiliary DC / DC converter 118. aux It is powered by ). The gate driver 120 outputs a signal to switch the FET of the rectifier element 114. Specifically, the gate driver 120 controls the operation of the rectifier element 114, for example, controls the switching of the FET of the rectifier element 114, i.e., a gate drive voltage or gate signal, i.e., V gate Outputs.

[0075] In this embodiment, the gate drive voltage V gate This is the trigger voltage V input to the gate driver 120. trig It is a delayed, more powerful replica.

[0076] The gate driver 120 and trigger circuit 122 exhibit a non-negligible propagation delay. To address the issue of non-negligible propagation delay from the gate driver 120 and trigger circuit 122, the trigger circuit 122 has a V gate ga V in To ensure synchronization, the trigger circuit 122 outputs the V trig It is designed to further delay the process.

[0077] The rectifier 100 has been described in isolation. However, the rectifier 100 is used in a receiver of a wireless power transmission system. An exemplary receiver 102 including the rectifier 100 is shown in Figure 4.

[0078] The receiver 102 comprises a receiving element 110, a rectifier 100, a main DC / DC converter 116, and a load 124. The rectifier 100 comprises a rectifier element 114, an auxiliary DC / DC converter 118, a trigger circuit 122, and a gate driver 120. In the illustrated configuration, the rectifier also comprises an input stage 112.

[0079] The receiving element 110 is electrically connected to the input stage 112 and the trigger circuit 122. The receiving element 110 may be similar to the receiving element 24. The receiving element 110 is configured to receive power from a transmitter, for example, transmitter 10, using resonant or non-resonant field coupling or magnetic field coupling. The receiving element 110 can extract power from the transmitter via non-resonant or resonant magnetic field coupling or field coupling. Thus, the receiving element 110 comprises one or more receiving coils (i.e., inductors) or one or more capacitive electrodes. The corresponding transmitters each comprise a corresponding transmitting coil (i.e., inductor) or capacitive electrodes.

[0080] The receiving element 110 extracts power from the transmitter and therefore inputs an input voltage or signal V corresponding to the extracted power or signal. in Outputs.

[0081] The input stage 112 is electrically connected to the rectifier element 114, the receiving element 110, and the trigger circuit 122. The input stage 112 is adapted to perform any combination of three functions. Specifically, the input stage 112 converts the impedance exhibited by the rectifier element 114 under a nominal load to the optimal load impedance for the receiving element 110. The input stage 112 reduces harmonic components generated by the nonlinear action of the rectifier element 114 so that the receiver 102, and by extension the wireless power system in which the receiver 102 is a part, can meet international product requirements related to electromagnetic compatibility (EMC). The input stage 112 ensures that the current input to the rectifier element 114 is approximately sinusoidal.

[0082] In this embodiment, the input stage 112 comprises a low-pass implementation of a double-impedance inverter circuit. The input stage 112 further includes additional filtering added in series with the rectifier element 114. The double-impedance inverter topology is beneficial in that it ensures the rectifier element 114 is driven by a quasi-constant voltage source. Further details of the input stage 112 are described below.

[0083] The rectifier element 114 is electrically connected to the input stage 112, the gate driver 120, the main DC / DC converter 116, and the auxiliary DC / DC converter 118. The rectifier element 114 has been described previously.

[0084] The main DC / DC converter 116 is electrically connected to the rectifier element, the auxiliary DC / DC converter 118, and the load 124. The main DC / DC converter 116 receives the DC power signal output from the rectifier element 114, i.e., V rectThis is for receiving the DC power signal. The main DC / DC converter 116 interfaces the rectifier element 114 with the load 124. The main DC / DC converter 116 is for converting the received DC power signal. The converted DC power signal is output from the main DC / DC converter 116 and reaches the load 124.

[0085] The auxiliary DC / DC converter 118 is further electrically connected to the main DC / DC converter 116. The auxiliary DC / DC converter 118 has been described earlier.

[0086] The gate driver 120 has already been explained.

[0087] Load 124 is electrically connected to the main DC / DC converter 116. Load 124 receives the signal output by the main DC / DC converter 116, i.e., V out It receives. Load 124 can be variable. As those skilled in the art will understand, when DC conversion is not required, load 124 is connected directly to rectifier element 114, V rect You may accept it.

[0088] While the receiver 102 has been described as comprising an input stage 112 and a main DC / DC converter 116, those skilled in the art will understand that other configurations are possible. Specifically, the receiver 102 may not include one or both of the input stage 112 and the main DC / DC converter 116.

[0089] The trigger circuit 122 is electrically connected to the receiving element 110 and the input stage 112. As previously described, in order to address the challenge of non-negligible propagation delay from the gate driver 120 and the trigger circuit 122, the trigger circuit 122 is V gate ga V in To ensure synchronization, the trigger circuit 122 outputs the V trig It is designed to further delay the process.

[0090] To determine the requirements for the trigger circuit 122 to address at least some of these significant propagation delays, we schematically modeled at least some of the components described here.

[0091] Specifically, the receiving element 110 was modeled using Thevenin equivalent circuit 200. As shown in Figure 5, the circuit 200 has a voltage source 202 and a small resistive impedance Z at the operating frequency. ref Series impedance 204, capacitance C r A capacitor 206 having a capacitor L r The model includes an inductor 208 having the following characteristics: This model is based on the fact that both the transmitting element and the receiving element 110 are well tuned, exhibit a high no-load Q value, and are well coupled. In other words, the power transmission efficiency across the wireless gap (the space between the transmitting element and the receiving element 110, through which power is transmitted from the transmitting element to the receiving element 110) is high (>90%). As a result, the input voltage V in The signal is a clean sine wave that remains relatively constant as the load 124 changes. Therefore, the input voltage is relatively load-independent.

[0092] The series impedance 204, capacitor 206, and inductor 208 can form a tuning element that ensures resonance at the switching frequency between the receiving element 110 and the corresponding transmitting element of the transmitter of the wireless power transmission system. As those skilled in the art will understand, only the impedance 204, capacitor 206, and inductor 208 may be present.

[0093] For convenience, only the single-ended half-circuit is shown. The other half-circuit is identical but has a 180° phase shift over the open-circuit voltage and is assumed to exhibit perfect balance.

[0094] The induced single-ended open-circuit voltage, i.e., V oc This is based on the signal return. The reflection impedance, i.e., Zref This represents the load imposed by the transmitting element. Assuming perfect synchronization on the transmitting side, this can be expressed in equation (1) as follows:

[0095]

number

[0096] Here, X 21 This embodies the mutual coupling between the transmitting and receiving elements, R s R represents the Norton equivalent source resistance exhibited by the transmitting element. t This represents the loss resistance of the transmitting element. The equivalent capacitance of circuit 200 is C r This is expressed as follows: When power is extracted by the receiving element 110 primarily through electric field induction or resonant electric field induction, the attached inductance L r It resonates together with the capacitor at the switching frequency. As a result, the circuit 200 of the receiving element 110 is reduced to a series resistor with a sinusoidal voltage source at the switching frequency. When power is extracted by the receiving element 110 mainly via magnetic field induction or resonant magnetic field induction, the inductor resonates together with the attached capacitor at the switching frequency.

[0097] The example circuit parameters at 27.12MHz are: V oc =36V rms , Z ref =2.5Ω, Cr=16.4pF, and L r This can be calculated as 2.1 μH, and the equivalent series resistance can be approximately 1.2 Ω.

[0098] Next, moving to Figure 6, a schematic diagram of a portion of the rectifier 100 is shown. This schematic diagram illustrates an exemplary design of the power path of the rectifier 100. As with circuit 200, only the single-ended half-circuit 210 is shown.

[0099] The input stage 112 is electrically connected to the receiving element 110 and the rectifier element 114. The input stage 112 receives an input voltage (Vin) from the receiving element 110. As previously mentioned, the input stage 112 includes a double impedance inverter circuit. The double impedance inverter circuit is configured to match impedances, reduce harmonics, and ensure that the current is sinusoidal. Input voltage (V in The phase of the input voltage (V) is fixed, and the rectifier element 114 can utilize this phase. Without the double impedance inverter circuit of the input stage 112, the phase will fluctuate with load fluctuations. Therefore, the efficiency of the rectifier 100 may decrease. In the illustrated configuration, the input voltage (V) in The phase of the rectifier element 114 is fixed, and this phase can be utilized by the rectifier element 114. Without the double impedance inverter circuit of the input stage 112, the phase would fluctuate with load fluctuations, which could reduce the efficiency of the rectifier 100. In the illustrated configuration, the double impedance inverter circuit comprises inductors 212, 214, 216, and capacitors 218, 220, 222. The inductance of inductor 212 is given by L2, the inductance of inductor 214 is given by inductance L1 + L2, and the inductance of inductor 216 is given by L1 + L f +L a The capacitance of capacitor 218 is given by capacitance C2, the capacitance of capacitor 220 is given by capacitance C1, and the capacitance of capacitor 222 is given by capacitance C f It is given by.

[0100] Circuit 210 further comprises a rectifier element 114 consisting of an FET (Q1) 230, a diode (D1) 232, a capacitor 234, and a shunt capacitor 238, all connected in parallel to the input stage 112. An inductor 236 is connected in series between the capacitor 234 and the shunt capacitor 238. The capacitance of capacitor 234 is capacitance C. ZVS Given by, the capacitance of the shunt capacitor 238 is capacitance C. rectThe inductance of inductor 236 is given by L. ZVS It is given by.

[0101] The circuit parameters L1, C1, L2, and C2 are related to double impedance inversion. The inductor / capacitor pairs (L1,C1) and (L2,C2) resonate at the switching frequency. The input impedance of the rectifier element 114 is Z rect It is given by Z. Therefore, at the switching frequency, rect This is given by equation (2).

[0102]

number

[0103] Here, Z in This is the input impedance of the receiving element 110. Assuming that the rectifier element 114 is perfectly tuned, Z at the nominal load. rect and Z in This results in resistance. In that case, the optimal load for the receiving element 110 can be obtained by adjusting the capacitance ratio.

[0104] Additional filtering of the current input to the rectifier element 114 is achieved via (Lf, Cf), which also resonates at the switching frequency. Assuming the current is approximately sinusoidal, equations (3) and (4) can be applied to achieve load independence and ZVS.

[0105]

number

[0106] Here, ω0 is the switching frequency expressed in radians, Cj is the junction capacitance of diode 232 (D1), Coss is the output capacitance of FET 230 (Q1) of rectifier element 114, and La is the additional series inductance required for a proper ZVS.

[0107] Assuming an output voltage of approximately 25V, (Coss+Cj) ≈ 250pF, which tends to limit ZVS tuning options. Therefore, at an operating frequency of 13.56MHz, the following parameters were determined based on the above equation: Lzvs = 140nH, resulting in Czvs ≈ 340pF and La = 37.3nH. At an operating frequency of 27.12MHz, the following parameters were determined based on the above equation: Lzvs = 66nH, resulting in Czvs ≈ 63pF and La = 17.6nH. Ideally, Czvs should always be greater than (Coss+Cj) to better stabilize the rectifier 200 circuit, but achieving this can become more difficult as the switching frequency increases.

[0108] Filtering of the rectified output voltage is achieved using shunt capacitor 238 with capacitance Crect. Additional filtering may be required to meet EMC requirements.

[0109] In another embodiment, the rectifier element 114 and the main DC / DC converter 116 can occupy the same printed circuit board (PCB). This makes it possible to combine the output filtering of the rectifier element 114 with the input filtering of the main DC / DC converter 116.

[0110] Next, moving to Figure 7, we see a block diagram of a portion of the rectifier 100. Specifically, the block diagrams of the trigger circuit 122 and the gate driver 120 are shown. As shown in Figure 7, the input voltage or signal V in However, the signal is sampled via the sampling circuit 250 and supplied to the delay line 252. In this embodiment, the sampling circuit 250 is a voltage divider, and the delay line 252 is a lumped element delay line circuit. The output of the delay line 252 is supplied to the comparator circuit 254. The comparator circuit 254 processes the delayed signal (V) output by the delay line 252. d This is for generating a clock signal by comparing it with a DC level.

[0111] The resulting trigger voltage (V trig The trigger voltage is supplied to the gate driver 120. The gate driver 120 sets the trigger voltage to a waveform (V) suitable for driving the FET of the rectifier element 114. gate ). Both the comparator circuit 254 and the gate driver 120 have propagation delays of several nanoseconds, and this propagation delay can become significant when dealing with switching periods of approximately 73.7 ns (for an operating frequency of 13.56 MHz) or 36.9 ns (for an operating frequency of 27.12 MHz). The sampling circuit 250, delay line 252, and comparator 254 form the trigger circuit 122. These elements are V gate ga V in It is designed to ensure synchronization.

[0112] Next, moving to Figure 8, a schematic diagram of a portion of the rectifier 100 is shown. This schematic diagram shows an exemplary configuration of the sampling circuit 250 and the delay line 252. As mentioned earlier, in this embodiment, the sampling circuit 250 is a voltage divider, and the delay line 252 is a lumped element delay line circuit.

[0113] Specifically, the sampling circuit 250 includes a capacitor 260 having capacitance Cs1 and a capacitance C s2 A capacitive voltage divider comprising a capacitor 262 having, and an inductor (L) for canceling out the associated capacitive reactance. s The circuit includes an inductor 264 having ). Capacitor 260 is connected in series with inductor 264, while capacitor 262 is connected in parallel between capacitor 260 and inductor 264.

[0114] In the illustrated configuration, the delay line 252 comprises a four-stage lumped element transmission line circuit that implements the delay. The total inductance and capacitance associated with this transmission line, represented by Ld and Cd respectively, are evenly divided among the inductors (266, 268, 270, 272) and capacitors (274, 276, 278, 280) to form four sections of the delay line 252. Capacitors 274, 276, 278, and 280 are connected in parallel with the inductors 266, 268, 270, and 272 between adjacent capacitors 274, 276, 278, and 280. Inductor 264 of the sampling circuit 250 is electrically connected to inductor 266 of the delay line 252. Assuming that the delay line 252 is matched-terminated, the associated time delay is given by equation (5).

[0115]

number

[0116] Assuming that the transmission line is lossless, the characteristic impedance (Z o ) is given by equation (6).

[0117]

number

[0118] As a result, characteristic impedance (Z o ) and total delay (τ d If you select ), then L for 4-stage delay line 252 dn and C dn The value of can be determined by equation (7).

[0119]

number

[0120] While a specific delay line 252 has been described, those skilled in the art will understand that other configurations are possible. In another embodiment, the delay line comprises more stages than a four-stage lumped element transmission line circuit to implement the delay. Specifically, more than four stages can be used when the switching frequency is lower. In another embodiment, the delay line comprises fewer stages, for example, a three-stage lumped element transmission line. Fewer stages can be used when the switching frequency is higher. Accordingly, each section of the delay with more than four stages may occupy less than one-tenth of the wavelength, or each section of the delay with fewer than four stages may occupy more than one-tenth of the wavelength.

[0121] While we have illustrated the separator inductors 264 and 266 as described in the sampling circuit 250 and delay line 252, those skilled in the art will understand that other configurations are possible. In another embodiment, inductors 264 and 266 are shared or combined into one L s +L dn This can be a single inductor having a certain inductance. In this embodiment, a portion of the single inductor is used by the sampling circuit 250, and a portion is used by the delay line 252.

[0122] Next, moving to Figure 9, a schematic diagram of another part of the rectifier 100 is shown. This schematic diagram shows an exemplary configuration of the comparator circuit 254 and the gate driver 120. As mentioned earlier, the comparator circuit 254 receives the delayed signal (V) output by the delay line 252. d This is for generating a clock signal by comparing it with a DC level.

[0123] As shown in Figure 9, the comparator circuit 254 uses an auxiliary supply voltage (V aux The comparator 280 (A1) is powered by an auxiliary power supply having ). The input to the comparator 280 is V aux It is biased to approximately half. Positive comparator input (V +) In this case, this is achieved by using two resistors 282 and 284 each having the same value of resistor R2. Negative comparator input (V - ) In this case, this is achieved by using two resistors 286 and 288 each having the same value of resistor R1.

[0124] The delayed voltage signal (V d ) output by the delay line 252 is coupled to the negative comparator input section (V - ) via a DC blocking capacitor 290 having a capacitance (C b ). Thus, the trigger voltage (V trig ) will be inverted (180° phase shifted) with respect to the delayed voltage signal (V d ). In terms of the total delay required to ensure that V gate is in the same phase as V in , this effectively occupies half of the switching period, and thus the burden on the delay line 252 is reduced. As a result, the total delay (τ d ) is given as follows by Equation (8).

[0125]

Equation

[0126] Here, T s [[ID=3�]] is the switching period, τ c is the propagation delay of the comparator 254, and τ g is the propagation delay of the gate driver 120.

[0127] To supply the gate signal V gate to the rectifier element 114, the output section of the gate driver 120 is connected to a resistor 294 having a resistor R g .

[0128] At startup, when the FET 230 of the rectifier element 114 is off and the diode 232 is performing rectification, the output voltage Vout is less than the turn-on voltage of the auxiliary DC / DC converter 118. When the output voltage Vout exceeds this turn-on voltage, Vaux begins to rise to its nominal value. The presence of the capacitor 290 has the effect of slowing down the rise time of the negative input V- to the comparator 280. Unless a similar capacitive load is applied to the positive input section V+ of the comparator 280, there may be a large time interval during which the positive input V+ exceeds the negative input V-, and thus the trigger voltage Vtrig becomes high. This can cause the rectifier 200 to become unstable and damage the FET 230. Therefore, in order to ensure that the negative input voltage V- is greater than the positive input voltage V+ at startup, a shunt capacitor 292 having a capacitance C st is added to the positive input section V+. This capacitance C st of the shunt capacitor 292 is selected to be at least twice the capacitance C b of the blocking capacitor 290. In an exemplary configuration, when C b is 200 nF, C st can be made to be470 nF.

[0129] An experimental design of the receiver 102 including the rectifier 100 was constructed and tested as part of a complete wireless power transmission system including the receiver 102.

[0130] For the rectifier 100, operating frequencies or switching frequencies of 13.56 MHz and 27.12 MHz were considered. Using the circuit diagrams of the trigger circuit 122 discussed herein, a set of printed circuit boards (PCBs) was developed for each frequency. After tuning the rectifier element 110, the rectifier element 114 was tested as part of a complete wireless power transmission system. A wireless link between the transmitting and receiving elements 110 of this wireless power transmission system was implemented using a set of 100 Ω resonant circuit pairs with custom electrode PCBs and solenoid air-core inductors.

[0131] Furthermore, in the experimental design for an operating frequency of 13.56 MHz, the Q values ​​of each inductor (212, 214, 216, and 236) were approximately 300. This allows for high RF efficiency.

[0132] In the experimental design for an operating frequency of 27.12 MHz, the inductors 214, 216, and 236 used were air-core inductors. These are generally less expensive and can exhibit better tolerances than custom-wound inductors. However, their associated Q-factor (Q) is generally around 150, and therefore lower than that of custom-wound inductors.

[0133] Therefore, in these experimental designs, designs operating at 27.12 MHz may be less efficient than designs operating at 13.56 MHz due to increased RF and switching losses, but designs operating at 27.12 MHz can be lower in cost and have shorter manufacturing times.

[0134] On the transmitter side of the experimental wireless power transmission system, the transmitter PCB was tuned for each frequency. Similar to the case of receiver element 110, RF loss and switching loss are expected to be lower at 13.56 MHz, but at 27.12 MHz, the transmitting element can be made less expensive and easier to manufacture.

[0135] The transmitter PCB used for testing was pre-modified so that the main onboard DC / DC could handle a higher output voltage. To achieve the desired power level, the transmitter PCB was powered from 28V, and the nominal DC / DC output voltage, or inverter input voltage, was 25V. The transmitter PCB was powered from 28V, and the nominal inverter input voltage of the transmitter PCB was 25V.

[0136] In these experimental designs, the main DC / DC converter 116 of the receiver 102 was configured to produce an output of approximately 12.6V. The load for this wireless power transmission system was obtained by using an electronic load in constant current mode. In these experimental designs, the rectifier element 114 was designed to produce an 80W output signal, allowing it to easily handle load power up to 70W.

[0137] In these experimental designs, the comparator 280 exhibited a propagation delay of approximately 4.5 ns. The gate driver 120 exhibited a propagation delay of approximately 2.5 ns. At an operating frequency of 13.56 MHz, this translates to a nominal time delay (τd) of approximately 29.87 ns according to the formula given above, while at an operating frequency of 27.12 MHz, the nominal time delay (τd) is 11.44 ns. At both frequencies, each section of the delay line 252 occupies less than one-tenth of the wavelength, as desired.

[0138] Next, we present experimental results for the wireless power transmission system described here, which includes a receiver 102 equipped with a rectifier 100. In this experimental wireless power transmission system design, the operating frequency was 13.56 MHz.

[0139] During the test, the transmitter's inverter input voltage was first increased to 25V, and then the load current was increased from 0A to 6A in 0.2A steps. Next, moving to Figure 10, a graph of the relationship between input power, output power and load current for an experimental design of a wireless power transmission system equipped with a rectifier 100 having the values ​​described above.

[0140] As shown in Figure 10, approximately 19W is required to excite this wireless power transmission system under no-load conditions. A nominal output power of 70W is achieved when the load current is 5.6A, but this wireless power transmission system operates without any problems at a current of 6A.

[0141] Next, moving to Figure 11, the relationship between power transmission efficiency and load current for this experimental wireless power transmission system is depicted. In this experimental design, the operating frequency was 13.56 MHz. Power transmission efficiency is calculated between the transmitter and receiver, i.e., end-to-end. Power transmission efficiency is given by dividing the output DC power result by the input DC power result. As shown in Figure 11, the efficiency rises from zero at 0A (as expected), reaches above 50% at 1.6A, reaches approximately 60% at 2.4A, and settles at approximately 70% between a load current of 5A and a load current of 6A. The efficiency of the transmitting and receiving elements 110 was previously measured to be approximately 92%. Therefore, the peak efficiency of the end-to-end electronic circuit including the rectifier 100 is approximately 76%.

[0142] Next, moving to Figure 12, the relationship between the input voltage, output voltage, rectified voltage, and load current for this experimental wireless power transmission system is shown. As shown in Figure 12, the input voltage (V in ) and output voltage (V out These values ​​are generally stable at approximately 28V and 12.6V, respectively, with the load.

[0143] Rectified voltage (V) due to load rect The voltage is generally stable, which is beneficial for system stability. Furthermore, since the rectified voltage is not regulated, this wireless transmission system has been shown to be particularly stable and robust. The rectified voltage is approximately 32.8V under no load (0A load current) and decreases linearly to approximately 27.2V under a 6A load current. This drop of only 5.6V (approximately 18%) is significantly more stable than the drop (approximately 30%) that can be expected with conventional passive rectification.

[0144] The rectifier 100 can also be operated at a much lower rectified output voltage compared to a passive rectifier, and a higher voltage is often required to reduce the current stress on the diodes, which can place an additional burden on the main DC / DC converter 116.

[0145] Next, moving to Figure 13, we see the rectified voltage (V) in this experimental wireless power transmission system. rect Figure 13 shows a graph of the response of the rectifier to the load step. This is particularly relevant in the context of evaluating the stability of timing recovery under dynamic conditions. To simulate the load step change, the electronic load was configured to step from 0A to 6A over approximately 20μs (0.3A / μs). The dynamic response to this load step is shown in Figure 13.

[0146] The load current is initially 0A. At time 0ms, the load current increases relatively instantaneously to approximately 6A. This corresponds to a load step. Subsequently, the load current remains constant at 6A from time 0ms to time 1ms. Before the load current steps or increases to 6A, the rectified voltage (V) rect The rectified voltage (V) is approximately 32.8V at time -0.2ms. If the load current increases or steps upward at time 0ms, the rectified voltage (V) rect The rectified voltage (V) gradually decreases or attenuates to 27.2V over 800μs. rect The voltage settles to 27.2V in 1ms and remains at that value.

[0147] As shown in Figure 13, the load current rises very rapidly, but the rectified voltage (V rect The voltage gradually decays from 32.8V to 27.2V over approximately 800μs. As shown in Figure 13, the rectified voltage response is relatively smooth and controlled.

[0148] Next, moving to Figure 14, graphs of the rectifier switch node voltage before and after load application in this experimental wireless power transmission system are shown. As shown in Figure 14, the waveform of the switch node voltage is broader, and the peak is reduced by approximately 10% after load application. However, although the shape of the switch node voltage changes slightly before and after load application, the rectifier 100 is shown to be stable, and load independence is observed over large step changes. Similar switch node voltage behavior was observed in the transmitter of this experimental wireless power transmission system.

[0149] In contrast, in passive rectification, the inverter switch node often changes significantly with the load, and this effect is attributed to the non-linear junction capacitance of the diode. This essentially translates to a significant phase shift in the receiver input impedance with respect to the load. The fact that this does not occur in rectifier 100 means that rectifier 100 exhibits a much more practical impedance from no load to full load. As a result, the inverter's ZVS tuning can be more effectively optimized in terms of efficiency.

[0150] Next, we present experimental results for the wireless power transmission system described here, which includes a receiver 102 equipped with a rectifier 100. In this experimental wireless power transmission system design, the operating frequency was 27.12 MHz.

[0151] Due to increased switching losses and the resulting thermal stress on the FET 230 and gate driver 120, this rectifier 100 was designed to handle half the power compared to the rectifier 100 of the wireless power transmission system operating at 13.56 MHz. Therefore, the wireless power transmission system operating at 27.12 MHz is optimized for 40 W output power, easily accommodating a nominal load power of 35 W. A separate transmitter optimized for a 27.12 MHz switching or operating frequency was used. The transmitter was powered from 24 V, and the transmitter's nominal inverter input voltage was 18 V.

[0152] During the test, the transmitter's inverter input voltage was first increased to 18V, and then the load current was increased from 0A to 3.2A in 0.2A steps. Next, moving to Figure 15, a graph of the relationship between input power, output power and load current for an experimental design of a wireless power transmission system equipped with a rectifier 100 having the values ​​described above.

[0153] As shown in Figure 15, approximately 16W is required to excite this wireless power transmission system under no-load conditions. A nominal output power of 35W is achieved when the load current is 2.8A, but this wireless power transmission system operates without any problems at a current of 3.2A.

[0154] Next, moving to Figure 16, the relationship between power transmission efficiency and load current for this experimental wireless power transmission system is depicted. As mentioned earlier, the operating frequency for this experimental design was 27.12 MHz. Power transmission efficiency is calculated end-to-end, from transmitter to receiver. Power transmission efficiency is given by dividing the output DC power result by the input DC power result. As shown in Figure 16, the efficiency increases (as expected) from zero at 0 A, reaching approximately 50% at 1.2 A, approximately 60% at 2 A, and peaks at approximately 64% at a load current of 3.2 A. The efficiency of the transmitting and receiving elements 110 was previously measured to be approximately 95%. Therefore, the peak efficiency of the end-to-end electronic circuit including the rectifier 100 is approximately 68%.

[0155] Several factors explain the 8% difference between this system and the 13.56MHz system: all switching losses are roughly doubled, the reduction in power levels increases the effect of quiescent draw, and perhaps most importantly, the RF inductor losses are 2-3 times higher because a commercially available air-core coil is used instead of a custom-wound toroid.

[0156] Next, moving to Figure 17, the relationship between the input voltage, output voltage, and rectified voltage and the load current for this experimental wireless power transmission system is shown. As shown in Figure 17, the input voltage (V in ) and output voltage (V out These values ​​are generally stable at approximately 24V and 12.6V, respectively, depending on the load.

[0157] Rectified voltage (V) due to load rectThe voltage is generally stable, which is beneficial for the system's stability. Furthermore, since the rectified voltage is not regulated, this wireless power transmission system has been shown to be particularly stable and robust. The rectified voltage is approximately 23V under no load (0A load current) and decreases linearly to approximately 19V under a 3.2A load current. This drop of only 4V (approximately 17%) is significantly more stable than the drop (approximately 30%) that can be expected with conventional passive rectification.

[0158] Next, moving to Figure 18, we see the rectified voltage (V) in this experimental wireless power transmission system. rect Figure 18 shows a graph of the response of the rectifier to the load step. Figure 18 shows the performance of the rectifier 100 under changes in the load step. This may be particularly relevant in the context of evaluating the stability of timing recovery under dynamic conditions. To simulate changes in the load step, the electronic load was configured to step from 0A to 2.8A over approximately 10μs (0.3A / μs). The dynamic response to this load step is shown in Figure 18.

[0159] The load current is initially 0A. At time 0ms, the load current increases relatively instantaneously to approximately 2.8A. This corresponds to a load step. Subsequently, the load current remains constant at 2.8A from time 0ms to time 1.5ms. Before the load current steps or increases to 2.8A, the rectified voltage (V) rect The rectified voltage (V) is approximately 23V at time -0.5ms. If the load current increases or steps upward at time 0ms, the rectified voltage (V) rect The rectified voltage (V) gradually decreases or attenuates to 20V over 1000μs. rect The voltage settles to 20V at a time of 1.5ms and remains at that value.

[0160] As shown in Figure 18, the load current rises very rapidly, but the rectified voltage (V rectThe voltage gradually attenuates from 23V to 20V over approximately 1ms. As shown in Figure 18, the rectified voltage response is relatively smooth and controlled.

[0161] Next, moving to Figure 19, graphs of the rectifier switch node voltages of this experimental wireless power transmission system before and after load application are shown. As shown in Figure 19, the waveforms of these switch node voltages remain generally unchanged, and it is safe that the peaks decrease slightly after load application. Thus, the rectifier 100 is shown to be stable, and load independence is observed over large step changes. Similar switch node voltage behavior was observed in the transmitter of this experimental wireless power transmission system.

[0162] In contrast, in passive rectification, the inverter switch node often changes significantly with the load, and this effect is attributed to the non-linear junction capacitance of the diode. This essentially translates to a significant phase shift in the receiver input impedance with respect to the load. The fact that this does not occur in rectifier 100 means that rectifier 100 exhibits a much more practical impedance from no load to full load. As a result, the inverter's ZVS tuning can be more effectively optimized in terms of efficiency.

[0163] As these experimental results show, the rectifier described here is shown to be stable from no load to full load at operating frequencies of 13.56 MHz and 27.12 MHz.

[0164] Furthermore, at an operating frequency of 13.56 MHz, the end-to-end efficiency was found to be 76% at output powers exceeding 70 W. This is achieved for rectifier voltages well below 60 V, providing significant design flexibility for the main DC / DC converter 116.

[0165] At an operating frequency of 27.12 MHz, the end-to-end efficiency was found to be 68% at output powers exceeding 35 W. Wireless power transmission systems operating at 27.12 MHz can offer lower-cost options and / or faster and simpler manufacturing options.

[0166] We have described a specific rectifier 100, but those skilled in the art will understand that other configurations are possible. Moving on to Figure 20, a receiver 300 equipped with a rectifier is shown. In addition, like the receiver 102 shown in Figure 4, the receiver 300 also includes a receiving element 310, a rectifier element 314, and a load (R L It is equipped with 324.

[0167] The receiving element 310 is configured to receive power from a transmitter, for example, transmitter 10, using resonant or non-resonant field coupling or magnetic field coupling. The receiving element 310 can extract power from the transmitter via non-resonant or resonant magnetic field coupling or field coupling. Thus, the receiving element 310 comprises one or more receiving coils (i.e., inductors) or one or more capacitive electrodes. The corresponding transmitters each comprise a corresponding transmitting coil (i.e., inductor) or capacitive electrodes. In Figure 20, the receiving element 310 is connected to a voltage source (V s )330, inductance L 11 An inductor 332 having a capacitance C 11 It is modeled as a capacitor 334 having the voltage V. s This represents the signal received by the receiving element 310. The load 324 may be variable or fixed.

[0168] The inductor 332 and capacitor 334 can form a tuning element that ensures resonance at the switching frequency between the receiving element 310 and the corresponding transmitting element of the transmitter of the wireless power transmission system. As those skilled in the art will understand, only the inductor 332 and capacitor 334 may be present.

[0169] Similar to the rectifier 100 shown in Figure 3, the rectifier 300 comprises a rectifier element 314, a gate driver 320, a trigger circuit 360, and an auxiliary DC / DC converter 318 connected to the gate driver 320. The rectifier element 314 is a switch (Q) which is an FET 340 in the illustrated configuration. 11 ), and diode (D 11 The rectifier element 314 further comprises a capacitor 350 and a shunt capacitor 354. An inductor 352 is connected in series between the capacitor 350 and the shunt capacitor 354. The capacitance of the capacitor 350 is capacitance C 22 Given by, the capacitance of the shunt capacitor 354 is capacitance C. 33 The inductance of inductor 352 is given by L. 22 It is given by.

[0170] In contrast to rectifier 100, the double impedance inverter circuit of input stage 112 does not exist within rectifier 300. The feedback for trigger circuit 360 is V s In other words, when the voltage is taken from the voltage received by the receiving element 310, a double impedance inverter circuit is unnecessary.

[0171] Roughly speaking, the rectifier 300 is configured to supply a signal in phase with the input signal received by the receiving element 310 to the gate terminal of the FET 340 of the rectifier element 314. Specifically, the trigger circuit 360 receives the current (I) from the rectifier element 314. s ) supplies a signal in the same phase as ).

[0172] The voltage and current received by the receiving element 310 can be given by equations (9) and (10) as follows:

[0173]

number

[0174] Here, V s ω is the voltage received at the receiving element 310, ω is the operating frequency, and I s φ is the current induced in the receiving element 310, and φ is the phase difference between the voltage and the current induced in the receiving element 310.

[0175] Figure 21 shows the received voltage V s and current I s , and trigger signal V trig This is a plot of the voltage waveform V received at the receiving element 310. Specifically, Figure 21 shows the voltage waveform V s , current waveform I in the receiving element 310 s , and the trigger signal V output by comparator circuit 366 trig This is a plot of the current I. Figure 21 shows the ideal pulse that should be generated by the trigger circuit 360 and the gate driver 320. As shown in Figure 21, the current I S The trigger signal V trig It is synchronized with that.

[0176] The receiving element 310 is electrically connected to the rectifier element 314. The rectifier element 314 is electrically connected to the load 324. Specifically, the receiving element 310 is electrically connected to the rectifier element 314 and, as will be described later, to the trigger circuit 360. The rectifier element 314 is electrically connected to the receiving element 310 and the gate driver 320. The gate driver 320 is electrically connected to the rectifier element 314, the trigger circuit 360, and the auxiliary DC / DC converter 318. The trigger circuit 360 is electrically connected to the receiving element 310, the gate driver 320, and the auxiliary DC / DC converter 318. The load 324 is electrically connected to the rectifier element 314.

[0177] Next, moving to Figure 22, a block diagram of the trigger circuit 360 and gate driver 320 is shown. As shown in Figure 22, the input voltage or signal V s However, the signal is sampled via the sampling circuit 362 and supplied to the RC delay circuit 364. In the illustrated configuration, the sampling circuit 362 is a voltage divider consisting of capacitors 370 and 372, each having capacitances C1 and C2, as shown in Figure 22. The RC delay circuit 364 is a resistor R, as shown in Figure 23. s The RC delay circuit 364 has a resistor 378 and capacitors 374 and 376, each having capacitances C3 and C4. C4 The delay signal V generated by the RC delay circuit 364 is supplied to the comparator circuit 366. C4 This is used to generate a clock signal by comparing it with a DC level.

[0178] Next, moving to Figure 23, a schematic diagram of a portion of the trigger circuit 360, namely the sampling circuit 362 and the RC delay circuit 364, is shown in more detail. As previously mentioned, the sampling circuit 362 is for sampling the voltage waveform received by the receiving element 310. As previously mentioned, the sampling circuit 362 is electrically connected to the receiving element 310. Therefore, the sampling circuit 362 receives the voltage waveform Vs from the voltage source 330 of the receiving element 310. The sampling circuit 362 includes a first capacitive drive circuit comprising capacitors 370 and 372. The first capacitive drive circuit receives the voltage V s This is scaled down. By selecting sufficiently low values ​​for the capacitance value C1 of capacitor 370 and the capacitance value C2 of capacitor 372, the effect of the load on the sampling circuit 362 can be minimized and ignored.

[0179] The RC delay circuit 364 further comprises a second capacitive drive circuit comprising a series resistor 378, as well as capacitors 374 and 376. The second capacitive drive circuit already comprises a scaled voltage V s Further scale it down.

[0180] R s By selecting an appropriate value for , the phase difference φ in equation (10) can be compensated.

[0181] Next, moving to Figure 24, a schematic diagram of another part of the rectifier is shown in more detail. This schematic diagram shows an exemplary configuration of the comparator circuit 366 and the gate driver 320. As shown in Figure 24, the comparator circuit 366 consists of one or more comparators (A1, A2, ..., A n ) equipped with an auxiliary power supply V aux Power is supplied from. Comparator (A1, A2, ..., A n The input is V aux It is biased to approximately half. The positive input of the first comparator A1, i.e., V+, is this resistor R d This is achieved using two resistors 702 and 704, each with equal values. To maintain the voltage at the positive input, capacitance C st A capacitor 706 having the following properties is added.

[0182] The negative input of the first comparator A1 is the voltage across capacitor 708 with capacitance C4, i.e., voltage V c4 And, V aux It is the product of a DC bias voltage equal to half of it. The DC bias voltage is the product of the resistor R d This is achieved using two resistors 710 and 712, each having equal values. Integration can be achieved by using capacitor 708. The positive input of the first comparator A1 is a DC bias voltage equal to the DC bias voltage at the negative input. Since the DC bias voltages at both the positive and negative inputs must be equal, the voltage divider circuits on each pin can be identical to each other. The auxiliary voltage V used to power the first comparator A1 aux Using this, the DC bias voltages at the negative and positive inputs of the first comparator A1 can also be generated. To add more delay due to the intrinsic propagation delay of the first comparator A1, multiple comparators (A2, ..., A) can be used. n) can be added. Any additional comparator A i The upper positive input section corresponds to the previous comparator A. i-1 Connected to the output of (for example, the positive input of A2 is connected to the output of A1). Any additional comparators (A2, ..., A n The negative input of ) is V aux It is biased to approximately half. This is done by using two resistors of equal value (e.g., resistor R d This is achieved using resistors 720, 722 / 724, 726, each having their own characteristics. Final comparator A n The output section receives the trigger signal V. trig The resistor R g This supplies power to a gate driver 320, which includes a resistor 730 having the following properties.

[0183] Next, moving to Figure 25, a schematic diagram of the sampling circuit 362, RC delay circuit 364, and comparator 366 is shown in more detail. This schematic diagram shows an exemplary configuration of the sampling circuit 362, RC delay circuit 364, comparator circuit 366, and gate driver 320. As previously mentioned, the comparator circuit 366 is for generating a clock signal by comparing the signal generated by the RC delay circuit 364 with a DC level. As previously mentioned, the gate driver 320 is for matching the trigger signal output by the trigger circuit 360 to generate a gate signal for operating the FET 340 of the rectifier element 314. The gate driver 320 controls the voltage across capacitor 376, for example, voltage V C4 The gate driver 320 is configured to generate a gate signal based on the auxiliary power supply V aux It is powered by [source].

[0184] As previously mentioned, the RC delay circuit 364 includes a series resistor 378, as well as a second capacitive drive circuit comprising capacitors 374 and 376. The second capacitive drive circuit already has a scaled voltage V s We further scale it down. The scaled voltage can be expressed according to equation (11).

[0185]

number

[0186] Here, each X i Each corresponds to a capacitor C. i It is the reactance of V C4 This is the voltage across capacitor 376.

[0187] each element i This can be expressed in equation (12) as follows:

[0188]

number

[0189] Therefore, the phase of capacitor 376 can be expressed in equation (13) as follows:

[0190]

number

[0191] Here, R s This is the resistance of resistor 378.

[0192] R s By selecting an appropriate value for , the phase difference φ in equation (10) can be compensated.

[0193] Figure 26 shows the received voltage V s and current I s , trigger signal V trig , as well as the voltage V for various values ​​of resistor 378 C4 This is a plot of the resistor R of resistor 378. Specifically, the resistor R s R s1 , R s2 , R s3 , and R s4 Equivalent to, where R s1 >R s2 >Rs3 >R s4 Figure 26 shows the voltage V C4 R of the phase s This shows the effect of resistor R. s A specific value of (in this case R) s3 Regarding the voltage V C4 The phase of the current I s This is identical to the previous signal, and it can be seen that this signal can be used to trigger the gate of the FET340.

[0194] While specific trigger circuits 122 and 360, as well as gate drivers 120 and 320, have been described, those skilled in the art will understand that other configurations are possible.

[0195] While specific rectifier elements have been described above, those skilled in the art will understand that other configurations are possible. In another embodiment, the current between the source and drain of the switch is controlled by the current leading to the gate of the switch, rather than by the gate voltage.

[0196] Each individual feature described herein may be disclosed individually, and any combination of two or more features may be disclosed. To what extent such features or combinations may be implemented in light of the ordinary knowledge of a person skilled in the art, based on the entire specification, without limiting the scope of the claims, regardless of whether such features or combinations of features solve any problem disclosed herein. The aspects of this disclosure may consist of any such individual features or combinations of features. In view of the foregoing, it will be apparent to a person skilled in the art that various modifications can be made within the scope of this disclosure. [Explanation of Symbols]

[0197] 2 Wireless Power Transmission System 10 Transmitters 12 Power supply 14 Sending elements 16 Receivers 18 Receiving elements 20 load 22 Receiver 24 Receiving element 26 Rectifier 28 Converter 30 Load 100 Rectifier 102 Receiver 110 Receiving element 112 Input stage 114 Rectifier element 116 Main DC / DC converter 118 Auxiliary DC / DC converter 120 Gate driver 122 Trigger circuit 124 Load 250 Sampling circuit 252 Delay line 254 Comparator circuit 320 Gate driver 360 Trigger circuit 362 Sampling circuit 364 RC delay circuit 366 Comparator circuit

Claims

1. A rectifier for use in a receiver of a wireless power transmission system, for receiving wireless power transmitted from a transmitter of the wireless power transmission system, Field-effect transistor (FET) The field-effect transistor (FET) is equipped with Source terminal electrically connected to ground, A drain terminal electrically connected to the receiving element of the receiver, wherein the receiving element is for extracting power from the transmitter of the wireless power transmission system, A gate terminal electrically connected to the receiving element, which is driven by a gate signal that is in phase with the input signal received by the receiving element, A trigger circuit electrically connected to the receiving element and the gate driver, which outputs a trigger signal for operating the gate driver, A sampling circuit for sampling the aforementioned input signal, A delay line that delays the output of the sampling circuit so that the input signal received at the drain terminal and the gate signal are synchronized, the delay line including a lumped element delay line, A trigger circuit comprising, A rectifier equipped with the following features.

2. The rectifier according to claim 1, wherein the trigger signal includes a pulse signal.

3. The rectifier according to claim 1, wherein the sampling circuit is a voltage divider.

4. The trigger circuit, A comparator for generating a clock signal by comparing the delayed signal output by the aforementioned delay line with a DC voltage level. The rectifier according to claim 1, comprising:

5. The trigger circuit, A resistor-capacitor (RC) delay circuit for delaying the output of the sampling circuit so that the input signal received in the receiving element and the gate signal are synchronized. The rectifier according to claim 3, comprising:

6. The rectifier according to claim 5, wherein the RC delay circuit comprises at least one resistor electrically connected to at least one capacitor.

7. The trigger circuit, A comparator for generating a clock signal by comparing the delayed signal output by the RC delay circuit with a DC voltage level. A rectifier according to claim 5 or 6, comprising:

8. A gate driver for receiving the trigger signal and generating the gate signal, wherein the gate signal is input to the gate terminal to control the operation of the rectifier. A rectifier according to any one of claims 1 to 6, further comprising the following:

9. An input stage for optimizing the load impedance, ensuring that the current input to the drain terminal is approximately sinusoidal, and reducing harmonics. A rectifier according to any one of claims 1 to 6, further comprising the following:

10. The rectifier according to claim 9, wherein the input stage comprises a double impedance inverter circuit, and the double impedance inverter circuit comprises a circuit configuration of a capacitor and an inductor configured to match the impedance.

11. Converter for converting the signal to supply power to the trigger circuit. A rectifier according to any one of claims 1 to 6, further comprising the following:

12. A load-independent Class E synchronous rectifier, as described in any one of claims 1 to 6.

13. A receiver for extracting power from a transmitter of a wireless power transmission system, A receiving element for receiving wireless power transmitted from the transmitter, A rectifier according to any one of claims 1 to 6, wherein the rectifier is electrically connected to the receiving element and A receiver equipped with the following features.

14. The receiver according to claim 13, wherein the receiving element is for extracting power via electric field coupling or magnetic field coupling.

15. The receiver according to claim 13, wherein the receiving element is for extracting power via resonant and / or non-resonant electric field coupling or magnetic field coupling.

16. The receiver according to claim 13, wherein the input signal received by the receiving element is an alternating current (AC) signal.

17. A wireless power transmission system for transmitting power via magnetic field coupling or electric field coupling, A transmitter equipped with a transmitting element for generating a magnetic field or electric field, It is a receiver, A receiving element for extracting power from the magnetic field via magnetic field coupling, or from the electric field via electric field coupling, and A rectifier according to any one of claims 1 to 6, wherein the rectifier is electrically connected to the receiving element. A receiver equipped with A wireless power transmission system equipped with the following features.

18. Power supply electrically connected to the transmitter The wireless power transmission system according to claim 17, further comprising:

19. A method for rectifying an input signal received in a receiving element of a receiver of a wireless power transmission system, wherein the receiver comprises a rectifier, the rectifier comprises a field-effect transistor (FET), and the field-effect transistor (FET) Source terminal electrically connected to ground, A drain terminal electrically connected to the receiving element, A gate terminal electrically connected to the receiving element and The method comprises, The steps include driving the gate terminal with a gate signal that is in phase with the input signal received by the receiving element, The steps include driving a gate driver that generates the gate signal, The steps include receiving the input signal with a trigger circuit, The steps include operating the gate driver via the trigger signal output from the trigger circuit, The steps include sampling the input signal via a sampling circuit, The steps include delaying the output of the sampling circuit so that the gate signal is synchronized with the input signal received by the receiving element, Methods that include...

20. The method according to claim 19, wherein the trigger signal includes a pulse signal.

21. The method according to claim 19 or 20, wherein the step of delaying the output includes delaying the output via a delay line or an RC delay circuit.

22. Steps to optimize load impedance, The steps of ensuring that the current input to the drain terminal is approximately sinusoidal, and Steps to reduce harmonics The method according to claim 19 or 20, further comprising at least one of the following.

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