Surface mount device chip fuse

Abstract

To provide a surface mount device chip fuse including a fusible element formed from solder disposed on a de-wetting substrate.SOLUTION: A surface mount device chip fuse includes: a dielectric substrate 12; electrically conductive first and second upper terminals 14a, 14b disposed on a top surface of the dielectric substrate and defining a gap 22 therebetween; a fusible element 18 formed from solder disposed in the gap on the top surface of the dielectric substrate, as a bridge between the first and second upper terminals; and electrically conductive first and second lower terminals 16a, 16b disposed on a bottom surface of the dielectric substrate and electrically connected to the first and second upper terminals, respectively; where a material of the dielectric substrate exhibits a de-wetting characteristic relative to the solder from which the fusible element is formed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure generally relates to the field of circuit protection devices. More particularly, this disclosure relates to surface mount device chip fuses that include a fusible element formed from solder disposed on a printed circuit board.

Background Art

[0002] [Description of Related Art] Fuses are commonly used as circuit protection devices and are typically installed between a power source and components of an electrical circuit to be protected. Conventional surface mount device (SMD) chip fuses include a fusible element disposed on an electrically insulating substrate. The fusible element may extend between conductive terminals located at opposite ends of the substrate. In an abnormal condition such as an overcurrent condition, the fusible element melts or otherwise separates to interrupt the flow of current through the fuse. <00上に配置されているハンダから形成された可溶エレメントを含む表面実装デバイスチップヒューズに関する。

背景技術

[0002] [関連技術の記載] ヒューズは、回路保護デバイスとして一般に使用されており、通常は電力源と保護すべき電気回路の部品との間に設置される。従来の表面実装デバイス(SMD)チップヒューズは、電気絶縁性の基板上に配置されている可溶エレメントを含む。可溶エレメントは、基板の両端部に位置する導電性端子の間に延在し得る。過電流状態などの異常状態が発生すると、可溶エレメントが溶融するか、または別様に分離して、ヒューズを通る電流の流れを遮断する。

[0003] 過電流状態の結果としてヒューズの可溶エレメントが分離すると、場合によっては、可溶エレメントの分離した部分の間に空気を介して(例えば、溶融した可溶エレメントの蒸発粒子を介して)電気アークが伝搬する可能性がある。この電気アークを消滅させないと、電力源から回路内の保護対象部品に著しい続流が流れることが可能になり、可溶エレメントが物理的に開放していても保護対象部品の損傷につながり得る。

[0004] 本改善が有用になり得るのは、これらおよび他の考慮事項に対してである。

発明の概要

[0005] この概要は、以下の発明を実施するための形態においてさらに説明される特定の概念を簡略化した形態で紹介するために提供される。この概要は、特許請求される主題の重要な特徴または不可欠な特徴を特定することを意図するものではなく、特許請求される主題の範囲を決定するにあたっての助けとなることを意図するものでもない。 It seems there are some repetitions and odd formatting in the original text you provided. I've done my best to translate it as per the instructions. If you have any further questions or need clarification, please let me know.

[0006] A surface-mount device chip fuse according to an exemplary embodiment of the present disclosure may include a dielectric substrate, conductive first and second upper terminals disposed on the upper surface of the dielectric substrate with a gap defined between them, a fusible element formed of solder disposed within the gap on the upper surface of the dielectric substrate and spanning the first and second upper terminals, and conductive first and second lower terminals disposed on the lower surface of the dielectric substrate and electrically connected to the first and second upper terminals, respectively, wherein the material of the dielectric substrate exhibits dewetting properties with respect to the solder forming the fusible element. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing a surface mount device chip fuse according to an exemplary embodiment of the present disclosure.

[0008] [Figure 2] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0009] [Figure 3] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0010] [Figure 4] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0011] [Figure 5] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0012] [Figure 6] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0013] [Figure 7] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure.

[0014] [Figure 8] This is a perspective view showing a surface mount device chip fuse according to another exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0015] Hereafter, exemplary embodiments of the surface-mount device (SMD) chip fuse according to this disclosure will be described in more detail with reference to the accompanying drawings. However, the SMD chip fuse may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that specific exemplary forms of the SMD chip fuse may be conveyed by this disclosure to those skilled in the art.

[0016] Referring to Figure 1, a perspective view is shown illustrating an SMD chip fuse 10 according to an exemplary embodiment of the present disclosure. The SMD chip fuse 10 may generally include a dielectric substrate 12, conductive first and second upper terminals 14a, 14b, conductive first and second lower terminals 16a, 16b, and a fusible element 18. The dielectric substrate 12 may be a substantially planar rectangular chip formed from a heat-resistant material with low surface energy and electrical insulation properties. Examples of such materials include, but are not limited to, glass, ceramic, FR-4, perfluoroalkoxy (PFA), ethylene tetrafluoroethylene (ETFE), or polyvinylidene fluoride (PVDF). The longitudinal edges of the dielectric substrate 12 may have semicircular castellations 20a, 20b formed therein. The present disclosure is not limited thereto.

[0017] The upper terminals 14a, 14b and the lower terminals 16a, 16b may be located on the upper and lower surfaces of the dielectric substrate 12, respectively, and may be formed from any suitable conductive material, including but not limited to copper, gold, silver, nickel, and tin. The upper terminals 14a, 14b may extend toward each other from their respective longitudinal edges of the dielectric substrate 12, and a gap 22 may be defined between them, with their terminations just before the longitudinal center of the upper surface. The castellations 20a, 20b may be plated with a conductive material (e.g., the same conductive material forming terminals 14a, 14b and lower terminals 16a, 16b) or otherwise coated to provide electrical connections between the upper terminal 14a and the lower terminal 16a and between the upper terminal 14b and the lower terminal 16b. In an alternative embodiment of the SMD chip fuse 10 shown in Figure 2, the castellations 20a, 20b may be omitted, and the substantially planar longitudinal edges 21a, 21b of the dielectric substrate 12 may be plated with or otherwise coated with a conductive material to provide electrical connections between the upper terminal 14a and the lower terminal 16a and between the upper terminal 14b and the lower terminal 16b, respectively. In another alternative embodiment of the SMD chip fuse 10 shown in Figure 3, conductive vias 25a, 25b may extend through the dielectric substrate 12 between the upper terminal 14a and the lower terminal 16a and between the upper terminal 14b and the lower terminal 16b, respectively, to provide electrical connections between them. The disclosure is not limited thereto.

[0018] Referring again to Figure 1, the fusible element 18 is positioned in the gap 22 on the upper surface of the dielectric substrate 12 and may be formed of a certain amount of solder to provide an electrical connection between the upper terminals 14a and 14b. The solder forming the fusible element 18 may be selected such that, when the solder is in a molten or semi-molten state, the solder may have avoidance of, or a tendency to move away from, the surface of the dielectric substrate 12. In other words, the material of the dielectric substrate 12 may exhibit significant "dewetting" characteristics with respect to the solder forming the fusible element 18. In one example, the dielectric substrate 12 may be formed from PFA and the solder may be SAC305 solder. In another example, the dielectric substrate 12 may be formed from ETFE and the solder may be eutectic solder. In yet another example, the dielectric substrate 12 may be formed from FR-4, PI (polyimide) and the solder may be high-temperature molten solder (i.e., solder having a melting point above 260 degrees Celsius). The disclosure is not limited thereto.

[0019] Under normal operation, the SMD chip fuse 10 may be connected within the circuit (for example, the lower terminals 16a and 16b may be soldered to their respective contacts on a printed circuit board), and current may flow through the lower terminals 16a and 16b, the upper terminals 14a and 14b, and the fusible element 18. If an overcurrent occurs in which the current flowing through the SMD chip fuse 10 exceeds its rated current, the fusible element 18 may melt or otherwise separate. The current flowing through the SMD chip fuse 10 is thus blocked, preventing or suppressing damage to surrounding circuit components to which it is connected.

[0020] Furthermore, due to the low surface energy of the dielectric substrate 12 and the avoidance “de-wetting” characteristic with respect to the molten or semi-molten solder of the soluble element 18 (described above), the separated portions of the soluble element 18 can move away from each other and away from the surface of the dielectric substrate 12, and can accumulate on the opposing edges / portions of the upper terminals 14a, 14b, thereby ensuring a galvanic opening within the SMD chip fuse 10 in response to an overcurrent condition. Thereby, an electric arc between the separated portions of the soluble element 18 is prevented or suppressed.

[0021] Referring to FIG. 4, an alternative embodiment of the SMD chip fuse 10 is contemplated, where the soluble element 18 and the adjacent portions of the upper terminals 14a, 14b may be covered with a dielectric passivation layer 26 to protect the soluble element 18 from external contaminants and to prevent a short circuit with external circuit components. The passivation layer 26 may be formed from epoxy, polyimide, glass, ceramic, or other materials that may exhibit an avoidance “de-wetting” characteristic with respect to the solder forming the soluble element 18. Thus, when the soluble element 18 melts in the SMD chip fuse 10 in an overcurrent condition, the avoidance “de-wetting” characteristic of the passivation layer 26 with respect to the molten or semi-molten solder of the soluble element 18 can bounce the separated portions of the soluble element 18, further assisting in a galvanic separation therebetween.

[0022] Referring to FIG. 5, another alternative embodiment of the SMD chip fuse 10 is provided, where the upper surfaces of the opposing portions of the upper terminals 14a, 14b are coated or plated with collecting pads 31a, 31b formed from a flux or wetting agent that exhibits a significant affinity or "wetting" property for the solder forming the soluble element 18. Examples of such materials include, but are not limited to, flux compounds made from rosin and / or polyglycol ethers. Thus, when the soluble element 18 melts in the SMD chip fuse 10 in an overcurrent state, the melted and separated portions of the soluble element 18 can be attracted to and accumulate on the collecting pads 31a, 31b so as to further assist in the galvanic electrical separation between the upper terminals 14a, 14b.

[0023] Referring to FIG. 6, another alternative embodiment of the SMD chip fuse 10 is provided that includes a "non-contact" cover 30 disposed over the soluble element 18 and adjacent portions of the upper terminals 14a, 14b to protect the soluble element 18 from external contaminants and prevent short circuits with external circuit components. The cover 30 may be substantially the same as the dielectric substrate 12 (e.g., formed from the same material as the dielectric substrate 12 and having the same size and shape), or may include a cavity 32 formed in its lower surface. When the cover 30 is placed over the dielectric substrate 12 as shown, the soluble element 18 and adjacent portions of the upper terminals 14a, 14b can be disposed within the cavity 32.

[0024] Referring to FIG. 7, another alternative embodiment of the SMD chip fuse 10 is provided that includes electrically insulated metal pads 34a, 34b disposed on the dielectric substrate 12, entering the gap 22 and extending under the soluble element 18. When the soluble element 18 melts in the SMD chip fuse 10 in an overcurrent state, the metal pads 34a, 34b are in the gap 22 Clear and go upThe fusible element 18 can be provided with additional surface area for collecting molten solder, resulting in galvanic electrical isolation between the side terminals 14a and 14b. Thus, the metal pads 34a and 34b can also provide high insulation resistance after galvanic electrical opening, while facilitating high fuse ratings and low electrical resistance in small fuse packages.

[0025] Referring to Figure 8, another alternative embodiment of the SMD chip fuse 10 is provided, which includes a pocket or trench 36 formed beneath the fusible element 18 in the dielectric substrate 12. When the fusible element 18 melts in the SMD chip fuse 10 under an overcurrent condition, the trench 36 is formed in the gap 22 Clear and go up The trench 36 may provide a space for collecting the molten solder of the fusible element 18, resulting in galvanic electrical isolation between the side terminals 14a and 14b. Thus, the trench 36 may facilitate high fuse ratings and low electrical resistance in small fuse packages.

[0026] Where used herein, an element or stage described in the singular and following the word "a" or "an" should be understood not to exclude multiple elements or stages, unless such exclusion is expressly stated. Furthermore, any reference in this disclosure to "one embodiment" is not intended to be construed as excluding the existence of further embodiments that similarly incorporate the described features.

[0027] While this disclosure refers to specific embodiments, numerous modifications, alterations, and changes can be made to the embodiments described without departing from the scope and realm of this disclosure as defined in the appended claims. Therefore, this disclosure is not limited to the embodiments described and is intended to encompass the entire scope defined by the following claims and their equivalents. 。 [Item 1] Dielectric substrate and The dielectric substrate is disposed on the upper surface, with a gap defined between it, and comprises conductive first and second upper terminals, A fusible element formed from solder is disposed within the gap on the upper surface of the dielectric substrate and is attached to the first and second upper terminals, The conductive first and second lower terminals are located on the lower surface of the dielectric substrate and are electrically connected to the first and second upper terminals, respectively. Equipped with, The material of the dielectric substrate exhibits dewetting characteristics with respect to the solder forming the soluble element. Surface mount device chip fuse. [Item 2] The surface mount device chip fuse according to item 1, wherein the edge of the dielectric substrate includes a conductive material disposed thereon to provide electrical connections between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal. [Item 3] The edges of the dielectric substrate are castellated, as described in item 2, for the surface-mount device chip fuse. [Item 4] The surface mount device chip fuse according to item 1, further comprising conductive vias extending through the dielectric substrate and providing electrical connections between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal. [Item 5] The surface mount device chip fuse according to item 1, further comprising the fusible element and a passivation layer disposed on adjacent portions of the first and second upper terminals. [Item 6] The surface mount device chip fuse according to item 1, further comprising collection pads disposed on opposing portions of the first and second upper terminals, wherein the collection pads are formed of a wetting agent that exhibits significant wetting characteristics with respect to the solder forming the fusible element. [Item 7] The surface mount device chip fuse according to item 1, further comprising a non-contact cover disposed on the upper surface of the dielectric substrate, wherein the non-contact cover is formed of a dielectric material and has a cavity formed on its lower surface, and the fusible element is disposed within the cavity. [Item 8] The surface mount device chip fuse according to item 1, further comprising an electrically insulated metal pad disposed on the upper surface of the dielectric substrate, extending into the gap and beneath the fusible element. [Item 9] The surface mount device chip fuse according to any one of items 1 to 8, further comprising a trench formed beneath the fusible element on the upper surface of the dielectric substrate.

Claims

1. Dielectric substrate and The dielectric substrate is disposed on the upper surface, with a gap defined between it, and comprises conductive first and second upper terminals, A fusible element formed from solder is disposed within the gap on the upper surface of the dielectric substrate and is attached to the first and second upper terminals, Conductive first and second lower terminals are arranged on the lower surface of the dielectric substrate and are electrically connected to the first and second upper terminals, respectively. Displaced on the upper surface of the dielectric substrate, the first and second metal pads enter the gap from both sides of the gap and extend beneath the soluble element. Equipped with, When the fusible element melts during an overcurrent condition, the first and second metal pads are electrically insulated from the first and second upper terminals and the first and second lower terminals, collect the solder and clear the gap, and provide galvanic electrical isolation between the first and second upper terminals. The material of the dielectric substrate exhibits dewetting characteristics with respect to the solder forming the soluble element. Surface mount device chip fuse.

2. The surface mount device chip fuse according to claim 1, wherein the edge of the dielectric substrate includes a conductive material disposed thereon to provide an electrical connection between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal.

3. The surface mount device chip fuse according to claim 2, wherein the edge of the dielectric substrate is castellated.

4. The surface mount device chip fuse according to claim 1, further comprising conductive vias extending through the dielectric substrate and providing electrical connections between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal.

5. The surface mount device chip fuse according to claim 1, further comprising the fusible element and a passivation layer disposed on adjacent portions of the first and second upper terminals.

6. The surface mount device chip fuse according to claim 1, further comprising collection pads disposed on opposing portions of the first and second upper terminals, wherein the collection pads are formed of a wetting agent that exhibits wetting properties with respect to the solder forming the fusible element.

7. The surface mount device chip fuse according to claim 1, further comprising a non-contact cover disposed on the upper surface of the dielectric substrate, wherein the non-contact cover is formed of a dielectric material and has a cavity formed on its lower surface, and the fusible element is disposed within the cavity.

8. The surface mount device chip fuse according to any one of claims 1 to 7, further comprising a trench formed beneath the fusible element on the upper surface of the dielectric substrate.

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