Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing inductance.SOLUTION: A first wiring 50 comprises a heat sink 51 and a positive electrode terminal 52. A second wiring 60 comprises a heat sink 61 arranged side by side with the heat sink 51 in a Y direction, and an output terminal 62. A third wiring 80 comprises a clip 81 and a negative electrode terminal 82. A semiconductor element 40H is arranged in the heat sink 51, and a drain electrode 40D is connected to the heat sink 51. A semiconductor element 40L is arranged in the heat sink 61, and the drain electrode 40D is connected to the heat sink 61. A clip 70 connects a source electrode 40S of the semiconductor element 40H and the heat sink 61. The clip 81 of the third wiring 80 is connected to the source electrode 40S of the semiconductor element 40L. The third wiring 80 runs parallel to the first wiring 50 and the clip 70.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The disclosure in this specification relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device that constitutes an upper and lower arm circuit. The description of the prior art document is incorporated by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the inductance of the upper and lower arm circuits is large, the surge voltage generated during switching increases. Although it is possible to reduce the surge voltage by limiting the switching speed, the switching loss increases.

[0005] In Patent Document 1, the inductance is reduced by the parallel arrangement of the positive and negative terminals which are power supply terminals, and the parallel arrangement of the connecting portions that connect the power supply terminals to the corresponding heat sinks. However, a further reduction in inductance is desired. From the above viewpoints, or from other viewpoints not mentioned, further improvements are required for the semiconductor device.

[0006] One disclosed object is to provide a semiconductor device capable of reducing inductance.

Means for Solving the Problems

[0007] The semiconductor device disclosed herein is A semiconductor device comprising at least one phase of an upper and lower arm circuit (9), A plurality of semiconductor elements (40) include a first element (40H) that constitutes one of the arms of the upper and lower arm circuit, and a second element (40L) that constitutes the other arm of the upper and lower arm circuit, each having a first main electrode on one surface and a second main electrode on the back surface opposite to the surface in the thickness direction, A first wiring (50) having a first mounting section (51) on which a first element is arranged and to which the first main electrode of the first element is connected, and a first power terminal section (52) connected to the first mounting section, A second wiring (60) having a second mounting section (61) arranged alongside the first mounting section in one direction perpendicular to the plate thickness direction, on which the second element is placed and the first main electrode of the second element is connected, and an output terminal section (62) connected to the second mounting section, A clip (70) electrically connects the second main electrode of the first element to the second mounting portion, A third wiring (80) having a connection portion (81) to which the second main electrode of the second element is connected, and a second power terminal portion (82) connected to the connection portion, Equipped with, The first wiring, clip, and third wiring extend in one direction, which is the direction in which the first mounting portion and the second mounting portion are aligned in a plan view in the thickness direction of the plate. A portion of the third wiring and a portion of the first wiring are arranged side by side in a direction perpendicular to both the thickness direction and the unidirectional direction, and another portion of the third wiring and a portion of the clip are arranged side by side in a direction perpendicular to both the thickness direction and the unidirectional direction. 3rd wiring teeth , By facing each of the first wiring and clips in a lateral direction over a predetermined length in one direction, It runs parallel to the first wire and clip.

[0008] According to the disclosed semiconductor device, a clip is used to connect the second main electrode of the first element to the second wiring including the output terminal. Furthermore, the third wiring including the second power supply terminal runs parallel not only to the first wiring including the first power supply terminal, but also to the clip. In other words, the third wiring also runs parallel to the wiring portion connecting the second main electrode of the first element to the connection point (midpoint) of the upper and lower arm circuit. This parallel arrangement effectively reduces inductance in the upper and lower arm circuit.

[0009] The disclosed embodiments in this specification employ different technical means to achieve their respective purposes. The claims and the reference numerals in parentheses described in this section exemplarily show the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The purposes, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the attached drawings.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram showing the circuit configuration of a power conversion device to which a semiconductor device according to the first embodiment is applied. [Figure 2] It is a plan view showing a semiconductor device. [Figure 3] It is a cross-sectional view taken along line III-III of FIG. 2. [Figure 4] It is a diagram showing a state in which the sealing body is omitted with respect to FIG. 2. [Figure 5] It is a cross-sectional view showing a semiconductor module. [Figure 6] It is a diagram showing a state in which the sealing body is omitted with respect to FIG. 3. [Figure 7] It is a diagram showing a modification example. [Figure 8] It is a diagram showing a modification example. [Figure 9] It is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 10] It is a plan view showing a state in which the sealing body is omitted. [Figure 11] It is a diagram showing a state in which the sealing body is omitted with respect to FIG. 9. [Figure 12] It is a diagram showing the circuit configuration of a power conversion device according to the third embodiment. [Figure 13] It is a plan view showing a semiconductor device. [Figure 14] It is a diagram showing a modification example. [Figure 15] It is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 16] It is a diagram showing a modification example. [Figure 17] It is a diagram showing other modification examples. [Figure 18] It is a diagram showing other modification examples. [Figure 19] It is a diagram showing other modification examples. [Figure 20] It is a diagram showing other modification examples. [Figure 21] It is a diagram showing other modification examples. [Figure 22] It is a diagram showing other modification examples. [Figure 23] It is a diagram showing other modification examples. [Figure 24] It is a diagram showing other modification examples. [Figure 25] It is a diagram showing other modification examples.

Mode for Carrying Out the Invention

[0011] Hereinafter, a plurality of embodiments will be described based on the drawings. In each embodiment, corresponding components may be denoted by the same reference numerals, and redundant descriptions may be omitted. When only a part of the configuration is described in each embodiment, the configuration of other embodiments described previously can be applied to other parts of the said configuration. Also, not only the combinations of configurations explicitly shown in the description of each embodiment, but also the configurations of a plurality of embodiments can be partially combined with each other as long as there is no problem with the combination, even if not explicitly stated.

[0012] The semiconductor device of the present embodiment is applied, for example, to a power conversion device of a moving body having a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), a flying body such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. Hereinafter, an example applied to a vehicle will be described.

[0013] (First Embodiment) First, based on FIG. 1, the schematic configuration of the drive system of the vehicle will be described.

[0014] <Vehicle drive system> As shown in Figure 1, the vehicle's drive system 1 includes a DC power supply 2, a motor generator 3, and a power converter 4.

[0015] The DC power supply 2 is a DC voltage source composed of rechargeable secondary batteries. These secondary batteries are, for example, lithium-ion batteries or nickel-metal hydride batteries. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as the vehicle's driving source, i.e., an electric motor. During regeneration, the motor generator 3 functions as a generator. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0016] <Power converter> Next, the circuit configuration of the power converter 4 will be described based on Figure 1. The power converter 4 is equipped with a power conversion circuit. The power converter 4 in this embodiment is equipped with a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0017] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power line, and the N line 8, which is the low-potential power line. The P line 7 is connected to the positive terminal of the DC power supply 2, and the N line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage to a three-phase AC voltage according to switching control by a control circuit (not shown) and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels to a DC voltage according to switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with three phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via the output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, N line 8, and output line 10 is made of conductive material such as a busbar.

[0020] In this embodiment, an n-channel type MOSFET 11 is used as the switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited; there may be one or multiple. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0021] As an example, in this embodiment, each arm has one MOSFET 11. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are interconnected.

[0022] Each MOSFET 11 has a freewheeling diode 12 connected in antiparallel. Diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or it may be a separate diode. The anode of diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0023] The power converter 4 may further include a converter as a power conversion circuit. The converter is a DC-DC converter circuit that converts a DC voltage to, for example, a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described up-and-down arm circuit 9. With this configuration, step-up and step-down voltage conversion is possible. The power converter 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0024] The power converter 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm's MOSFET 11 based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on or off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0025] The power converter 4 may include a control circuit for the switching element. The control circuit generates a drive command to operate the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0026] Various sensors include, for example, current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the windings 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured, for example, with a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

[0027] <Semiconductor device> Next, the schematic configuration of the semiconductor device will be described based on Figures 2 to 4. Figure 2 is a plan view showing the semiconductor device. Figure 2 is a top view plan view of the semiconductor device. Figure 3 is a cross-sectional view along line III-III in Figure 2. Figure 4 shows the same configuration as in Figure 2, but with the encapsulant and signal terminals omitted.

[0028] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction, and the alignment direction of the semiconductor elements on the upper arm and the lower arm is defined as the Y direction. The direction perpendicular to both the Z and Y directions is defined as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the view from the Z direction is sometimes simply referred to as the planar view.

[0029] As shown in Figures 2, 3, and 4, the semiconductor device 20 comprises a encapsulant 30, a plurality of semiconductor elements 40, a first wiring 50, a second wiring 60, a clip 70, a third wiring 80, and a signal terminal 90. The semiconductor device 20 constitutes an upper and lower arm circuit 9 for at least one phase. As an example, the semiconductor device 20 of this embodiment constitutes an upper and lower arm circuit 9 for one phase.

[0030] The encapsulant 30 encapsulates a portion of the other elements that constitute the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, resin or gel. As an example, the encapsulant 30 in this embodiment comprises a case 31, which is a primary molded body made of resin, and a gel 32. The case 31 is cylindrical with openings at both ends in the Z direction. The case 31 has side walls 311 that form a substantially rectangular annular shape in plan view. The gel 32 fills the housing space of the case 31. The gel 32 fills the empty areas of the housing space. Note that the filler is not limited to gel 32. For example, the housing space may be filled by potting with resin.

[0031] As shown in Figure 2, the sealing body 30 has a substantially rectangular shape in plan. The sealing body 30 has one surface 30a and a back surface 30b which is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. As an example, in this embodiment, the one surface 30a is the surface from which the signal terminal 90 protrudes. The outer periphery of the one surface 30a and the back surface 30b is made up of a case 31, and the central part is made up of gel 32.

[0032] The encapsulant 30 has sides 30c, 30d, 30e, and 30f, which are surfaces connecting one surface 30a and the back surface 30b. Side 30c is the surface from which the main terminals, the positive terminal 52 and the negative terminal 82, protrude. Side 30d is the surface opposite to side 30c in the Y direction. Side 30d is the surface from which the main terminal, the output terminal 62, protrudes. Side 30e is the surface opposite to side 30f in the X direction.

[0033] The semiconductor element 40 is formed by creating a vertical element on a semiconductor substrate made of materials such as silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes referred to as a power element or semiconductor chip.

[0034] The vertical element is configured to pass the main current in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes on both sides in the Z direction, which is its thickness direction. In this embodiment, the semiconductor element 40 is formed as an n-channel type MOSFET 11 as a vertical element on a semiconductor substrate made of SiC. The semiconductor element 40 has a drain electrode 40D on one side as a main electrode, and a source electrode 40S on the back side, which is the opposite side in the Z direction from the first side. In this embodiment, the drain electrode 40D corresponds to the first main electrode, and the source electrode 40S corresponds to the second main electrode.

[0035] When MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode 40D and the source electrode 40S. If diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. Diode 12 may be configured on a separate chip from MOSFET 11. The drain electrode 40D is the main electrode on the high-potential side, and the source electrode 40S is the main electrode on the low-potential side. The drain electrode 40D is formed over almost the entire back surface. The source electrode 40S is formed on a portion of one surface.

[0036] The semiconductor element 40 has a substantially rectangular planar shape. Although not shown in the figure, the semiconductor element 40 has pads on its back surface, which are signal electrodes. The pads are formed on the back surface at a different position from the source electrode 40S. The pads include at least a gate pad.

[0037] The multiple semiconductor elements 40 include semiconductor elements 40H that constitute the upper arm 9H and semiconductor elements 40L that constitute the lower arm 9L. Semiconductor element 40H is sometimes referred to as the upper arm element. Semiconductor element 40L is sometimes referred to as the lower arm element. For example, the configurations of semiconductor elements 40H and 40L are common to each other. In this embodiment, semiconductor element 40H corresponds to the first element, and semiconductor element 40L corresponds to the second element.

[0038] As an example, the semiconductor element 40 of this embodiment includes one semiconductor element 40H and one semiconductor element 40L, as shown in Figures 3 and 4. The semiconductor elements 40H and 40L are aligned in the Y direction. The semiconductor elements 40H and 40L are positioned at approximately the same location in the Z direction. The semiconductor elements 40H and 40L are positioned in the same orientation such that the source electrode 40S faces one side 30a and the drain electrode 40D faces the back side 30b.

[0039] The first wiring 50 is electrically connected to the first main electrode of the first element. As an example, in this embodiment, the first wiring 50 is electrically connected to the drain electrode 40D of the semiconductor element 40H. In other words, the first wiring 50 is electrically connected to the positive electrode of the smoothing capacitor 5. The first wiring 50 is sometimes referred to as P wiring, positive electrode wiring, P conductor, positive electrode conductor, etc.

[0040] The first wiring 50 is a metal plate made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plate may be provided, for example, as part of a lead frame. Instead of the metal plate, a metal body (metal pattern) placed on an insulating substrate made of ceramic or resin may be used. In other words, it may be provided as part of a substrate. The substrate may be a single-sided substrate with a metal body placed on one side of the insulating substrate, or a double-sided substrate with metal bodies placed on both sides of the insulating substrate. The first wiring 50 may have a plating film of Ni or Au on its surface.

[0041] As an example, the first wiring 50 of this embodiment has a heat sink 51 and a positive terminal 52. The heat sink 51 has a substantially rectangular shape in plan view. In plan view, the heat sink 51 encloses the semiconductor element 40H. One side of the heat sink 51 is the side on which the semiconductor element 40H is placed, i.e., the mounting surface. The drain electrode 40D of the semiconductor element 40H is connected to one side of the heat sink 51 via a bonding material (not shown), such as solder. The back surface of the heat sink 51 is exposed from the back surface 30b of the sealant 30. The back surface of the heat sink 51 is the heat dissipation surface. The heat sink 51 provides a wiring function that electrically connects the positive terminal 52 and the semiconductor element 40H. The heat sink 51 provides a heat dissipation function that dissipates the heat generated by the semiconductor element 40H. The heat sink 51 corresponds to the first mounting section.

[0042] The positive terminal 52 is connected to the heat sink 51. The positive terminal 52 may be provided integrally with the heat sink 51, or it may be provided as a separate component and connected by joining. As an example, in this embodiment, the positive terminal 52 is connected to the heat sink 51 by joining. The positive terminal 52 is joined to one end in the Y direction of one surface of the heat sink 51. The positive terminal 52 is joined to the end away from the heat sink 61, not the end closer to the heat sink 61.

[0043] The positive terminal 52 extends in the Y direction. The positive terminal 52 is held in the case 31. The positive terminal 52 is integrally molded with the case 31. A portion of the positive terminal 52 is located in the housing space of the case 31 and is joined to the heat sink 51. Another portion of the positive terminal 52 protrudes outside the case 31. Conductive members, such as busbars that constitute the P line 7 (not shown), are connected to the portion of the positive terminal 52 outside the case. The positive terminal 52 is sometimes referred to as a high-potential power supply terminal, P terminal, etc. The positive terminal 52 corresponds to the first power supply terminal.

[0044] The second wiring 60 is electrically connected to the first main electrode of the second element. As an example, in this embodiment, the second wiring 60 is electrically connected to the drain electrode 40D of the semiconductor element 40L.

[0045] The second wiring 60 is a metal plate made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plate may be provided, for example, as part of a lead frame. Instead of the metal plate, a metal body (metal pattern) placed on an insulating substrate may be used. In other words, it may be provided as part of a substrate. The substrate may be a single-sided substrate or a double-sided substrate. The second wiring 60 may have a plating film of Ni or Au on its surface.

[0046] As an example, the second wiring 60 of this embodiment has a heat sink 61 and an output terminal 62. The heat sink 61 has a substantially rectangular shape in plan view. The heat sink 61 encloses the semiconductor element 40L in plan view. One side of the heat sink 61 is the side on which the semiconductor element 40L is placed, i.e., the mounting side. The drain electrode 40D of the semiconductor element 40L is connected to one side of the heat sink 61 via a bonding material (not shown), such as solder. The back side of the heat sink 61 is exposed from the back side 30b of the sealant 30. The back side of the heat sink 61 is the heat dissipation surface. The heat sink 61 provides a wiring function that electrically connects the output terminal 62 to the connection point (midpoint) of the upper and lower arm circuit 9. The heat sink 61 provides a wiring function that electrically connects the source electrode 40S of the semiconductor element 40H to the connection point of the upper and lower arm circuit 9. The heat sink 61 provides a heat dissipation function that dissipates the heat generated by the semiconductor element 40L.

[0047] The heatsink 61 is positioned alongside the heatsink 51 in the Y direction. The heatsink 61 has a planar shape that is substantially the same as that of the heatsink 51. The heatsink 61 corresponds to the second mounting section.

[0048] The output terminal 62 is connected to the heat sink 61. The output terminal 62 may be provided integrally with the heat sink 61, or it may be provided as a separate component and connected by joining. As an example, in this embodiment, the output terminal 62 is connected to the heat sink 61 by joining. The output terminal 62 is joined to one end in the Y direction of one surface of the heat sink 61. The output terminal 62 is joined to the end away from the heat sink 51, not the end closer to the heat sink 51. With the above arrangement, the joint between the heat sink 61 and the semiconductor element 40L provides the connection point for the upper and lower arm circuit 9.

[0049] The output terminal 62 extends in the Y direction. The output terminal 62 extends in the Y direction opposite to the positive terminal 52. The output terminal 62 is held in the case 31. The output terminal 62 is integrally molded with the case 31. A portion of the output terminal 62 is located in the housing space of the case 31 and is joined to the heat sink 61. Another portion of the output terminal 62 protrudes outside the case 31. The winding 3a of the corresponding phase of the motor generator 3 is electrically connected to the portion of the output terminal 62 outside the case. The output terminal 62 is sometimes referred to as the O terminal, AC terminal, etc. The output terminal 62 corresponds to the output terminal section.

[0050] The clip 70 electrically connects the second main electrode of the first element to the second mounting portion. As an example, the clip 70 in this embodiment electrically connects the source electrode 40S of the semiconductor element 40H to the heat sink 61 of the second wiring 60. The clip 70 provides at least a portion of the wiring that electrically connects the source electrode 40S of the semiconductor element 40H to the connection point of the upper and lower arm circuit 9. The clip 70 may be referred to as a bridging member, relay member, metal bridge, etc. The clip 70 is a metal plate material made of a metal with good conductivity, such as Cu or a Cu alloy. The clip 70 may have a plating film of Ni or Au on its surface.

[0051] The clip 70 extends in the Y direction in a plan view. The clip 70 has ends 71 ​​and 72 and a connecting portion 73. End 71 is one of the ends of the clip 70. End 71 is joined to the source electrode 40S of the semiconductor element 40H via a bonding material (not shown). End 72 is the other end of the clip 70. End 72 is joined to one end in the Y direction of one surface of the heat sink 61. End 72 is joined to the end of the heat sink 61 that is closer to the heat sink 51. The connecting portion 73 electrically connects ends 71 ​​and 72 above, spaced apart from the heat sinks 51 and 61. The clip 70 is located in the housing space of the case 31.

[0052] The third wiring 80 is electrically connected to the second main electrode of the second element. As an example, in this embodiment, the third wiring 80 is electrically connected to the source electrode 40S of the semiconductor element 40L. In other words, the third wiring 80 is electrically connected to the negative electrode of the smoothing capacitor 5. The third wiring 80 is sometimes referred to as N wiring, negative electrode wiring, N conductor, or negative electrode conductor. The third wiring 80 is a metal plate material made of a metal with good conductivity, such as Cu or a Cu alloy. The third wiring 80 may have a plating film of Ni or Au on its surface.

[0053] As an example, the third wiring 80 of this embodiment has a clip 81 and a negative terminal 82. The clip 81 electrically connects the source electrode 40S of the semiconductor element 40L to the negative terminal 82. The clip 81 corresponds to the connection part. The clip 81 may be referred to as a bridging member, relay member, metal bridge, etc. The clip 81 extends in the Y direction in a plan view. The clip 81 has end portions 811, 812 and a connecting portion 813.

[0054] End 811 is one of the ends of the clip 81. End 811 is joined to the source electrode 40S of the semiconductor element 40L via a bonding material (not shown). End 812 is the other end of the clip 81. End 812 is joined to the negative electrode terminal 82. The connecting portion 813 electrically connects ends 71 ​​and 72 above, spaced apart from the heat sinks 51 and 61. The clip 81 is located in the housing space of the case 31.

[0055] The negative terminal 82 is connected to the clip 81. The negative terminal 82 may be provided integrally with the clip 81, or it may be provided as a separate component and connected by joining. As an example, in this embodiment, the negative terminal 82 is connected to the clip 81 by joining. The negative terminal 82 is joined to the end portion 812 of the clip 81.

[0056] The negative terminal 82 extends in the Y direction. The negative terminal 82 is held in the case 31. The negative terminal 82 is integrally molded with the case 31. A portion of the negative terminal 82 is located in the housing space of the case 31 and is joined to the clip 81. Another portion of the negative terminal 82 protrudes outside the case 31. Conductive members, such as busbars that constitute the N line 8 (not shown), are connected to the portion of the negative terminal 82 outside the case. The negative terminal 82 is sometimes referred to as a low-potential power supply terminal or N terminal. The negative terminal 82 corresponds to the second power supply terminal.

[0057] The signal terminal 90 is electrically connected to the pad of the corresponding semiconductor element 40. In one example, the signal terminal 90 in this embodiment is held in the case 31. The signal terminal 90 is integrally molded with the case 31. The signal terminal 90 extends in the Z direction. One end of the signal terminal 90 protrudes upward from the upper end of the case 31, i.e., from one surface 30a. Of the other end of the signal terminal 90, the portion that connects to the pad is exposed in the housing space of the case 31. The exposed portion of the signal terminal 90 is electrically connected to the pad of the corresponding semiconductor element 40 via a connecting member (not shown), such as a bonding wire.

[0058] As described above, in the semiconductor device 20 of this embodiment, a encapsulant 30 encapsulates a plurality of semiconductor elements 40 that constitute one phase of the upper and lower arm circuit 9. The encapsulant 30 integrally encapsulates the plurality of semiconductor elements 40, a portion of the first wiring 50, a portion of the second wiring 60, the clip 70, a portion of the third wiring 80, and a portion of each of the signal terminals 90.

[0059] The semiconductor element 40H is placed on the heat sink 51 of the first wiring 50. The semiconductor element 40L is placed on the heat sink 61 of the second wiring 60. This allows heat from the semiconductor elements 40H and 40L to be dissipated through the corresponding heat sinks 51 and 61. For example, the heat dissipation surfaces of the heat sinks 51 and 61 are substantially flush with the back surface 30b of the encapsulant 30. Since the heat dissipation surface is an exposed surface, heat dissipation can be improved.

[0060] <Semiconductor Module> Figure 5 is a cross-sectional view showing a semiconductor module. Figure 5 corresponds to Figure 3. As shown in Figure 5, the semiconductor module 100 comprises the semiconductor device 20 described above and a cooler 101.

[0061] The semiconductor device 20 is positioned on one surface of the cooler 101 in the Z direction. The cooler 101 has a flow channel 101F inside. The cooler 101 cools the semiconductor device 20 from the back surface 30b side. The flow channel 101F is provided so as to overlap at least a portion of the semiconductor device 20 in a plan view in order to effectively cool the semiconductor device 20. In this embodiment, the flow channel 101F is provided so as to enclose most of the semiconductor device 20 in a plan view.

[0062] Refrigerant 101R is supplied to the flow path 101F via an inlet pipe (not shown). The refrigerant 101R that has flowed through the flow path 101F is discharged outside the cooler 101 via an outlet pipe (not shown). As the refrigerant 101R, a phase-changing refrigerant such as water or ammonia, or a non-phase-changing refrigerant such as ethylene glycol, can be used.

[0063] An electrically insulating material is placed between the semiconductor device 20 and the cooler 101 as needed. As an example, the semiconductor module 100 of this embodiment includes an insulating material 102. As the insulating material 102, for example, a ceramic plate or a resin sheet can be used. A thermal interface material (TIM) such as silicone gel may be used to improve thermal conductivity.

[0064] <Manufacturing method> Next, an example of a manufacturing method for the semiconductor device 20 described above will be explained.

[0065] First, a case 31 is prepared in which the positive terminal 52, output terminal 62, negative terminal 82, and signal terminal 90 are integrally molded. Next, other components constituting the semiconductor device 20 are prepared, specifically the semiconductor element 40, heat sinks 51 and 61, and clips 70 and 81.

[0066] Next, heatsinks 51 and 61 are placed inside the case 31, at the end on the back side 30b. Then, the heatsink 51 is joined to the positive terminal 52 inside the case 31. Similarly, the heatsink 61 is joined to the output terminal 62.

[0067] Next, the semiconductor element 40H is placed on one surface of the heat sink 51, and the drain electrode 40D is joined to the heat sink 51. Similarly, the semiconductor element 40L is placed on one surface of the heat sink 61, and the drain electrode 40D is joined to the heat sink 61.

[0068] Next, the clip 70 is placed in the housing space of the case 31. Then, the end 71 is joined to the source electrode 40S of the semiconductor element 40H. The end 72 is also joined to the heat sink 61.

[0069] Next, the clip 81 is placed in the housing space of the case 31. Then, the end 811 is joined to the source electrode 40S of the semiconductor element 40L. The end 812 is also joined to the negative electrode terminal 82.

[0070] Next, the signal terminal 90 is electrically connected to the corresponding pad of the semiconductor element 40. Then, the gel 32 is filled into the housing space of the case 31 to obtain the semiconductor device 20 with the above configuration. When filling with gel 32, it is preferable to fill it with the back surface 30b side closed. For example, the gel 32 may be filled with the case 31 placed on the cooler 101. The gel 32 may also be filled with the case 31 closed with the insulating member 102.

[0071] The connection between the signal terminal 90 and the pad is not limited to the timing described above. It is possible after the drain electrode 40D of the semiconductor element 40 has been joined to the corresponding heat sinks 51 and 61.

[0072] <Parallel arrangement> Next, the parallel arrangement of wiring will be described based on Figures 4 and 6. Figure 6 shows the state in which the encapsulant and signal terminals are omitted compared to Figure 3. In Figures 4 and 6, the current flowing from the positive terminal 52 toward the connection point of the upper and lower arm circuits 9 is indicated by a dashed-dotted arrow, and the current flowing from the connection point toward the negative terminal 82 is indicated by a double-dotted-dotted arrow. In the following, "parallel arrangement" refers to a state in which opposing arrangements with a predetermined interval continue along the extension direction over a predetermined range.

[0073] As described above, the semiconductor elements 40H and 40L are arranged side by side in the Y direction. The semiconductor elements 40H and 40L are arranged in a line along the Y direction. The heat sink 51 of the first wiring 50 and the heat sink 61 of the second wiring 60 are arranged side by side in the Y direction with a predetermined gap between them. The positive terminal 52 extends from the heat sink 51 in the Y direction, opposite to the heat sink 61. The output terminal 62 extends from the heat sink 61 in the Y direction, opposite to the positive terminal 52.

[0074] Clip 70 electrically connects the source electrode 40S of the semiconductor element 40H, which is located on the heat sink 51, to the heat sink 61. Clip 70 extends in the Y direction in a plan view. The third wiring 80 is electrically connected to the source electrode 40S of the semiconductor element 40L, which is located on the heat sink 61. The negative electrode terminal 82 extends in the Y direction. Clip 81 extends in the Y direction in a plan view and electrically connects the semiconductor element 40L to the negative electrode terminal 82.

[0075] As shown in Figure 4, clip 81 is positioned to overlap with clip 70 in a plan view. As an example, clip 81 in this embodiment has approximately the same width as clip 70. Width is the length in the direction perpendicular to the extension direction. Clip 81 is longer than clip 70 in the Y direction. Clip 81 is positioned to approximately coincide with clip 70 in the width direction (X direction). Clip 81 is positioned to overlap the entire area of ​​clip 70 in a plan view.

[0076] Most of clip 81 runs parallel to clip 70. The remaining portion of clip 81 runs parallel to heat sinks 51 and 61. For example, clip 81 runs parallel to the portion of heat sink 61 from the junction with clip 70 to the junction of semiconductor element 40L. Clip 81 runs parallel to the wiring connecting the source electrode 40S of semiconductor element 40H to the connection point of the upper and lower arm circuit 9. The distance between clip 81 and clip 70 is shorter than the distance between clip 81 and heat sinks 51 and 61. In the Z direction, clip 81 faces clip 70 at a closer position than heat sinks 51 and 61. Note that some parts of clips 70 and 81 face each other in the Y direction. For example, the end 811 of clip 81 faces the end 72 of clip 70 in the Y direction.

[0077] The negative terminal 82 is positioned so as to overlap with the positive terminal 52 in a plan view. As an example, the negative terminal 82 in this embodiment has approximately the same width as the positive terminal 52. The negative terminal 82 is wider than the clip 81. The negative terminal 82 is narrower than the heatsink 51. The negative terminal 82 is positioned so as to approximately coincide with the positive terminal 52 in the width direction.

[0078] As shown in Figures 4 and 6, the negative terminal 82 runs parallel to the first wiring 50 along its entire length. Most of the negative terminal 82 runs parallel to the positive terminal 52. The remaining portion of the negative terminal 82 runs parallel to the heat sink 51. The distance between the negative terminal 82 and the positive terminal 52 is shorter than the distance between the negative terminal 82 and the heat sink 51. In the Z direction, the negative terminal 82 faces the positive terminal 52 at a closer position than the heat sink 51.

[0079] <Summary of the First Embodiment> As described above, in the semiconductor device 20 of this embodiment, a clip 70 is used to connect the source electrode 40S (second main electrode) of the semiconductor element 40H (first element) to the second wiring 60 including the output terminal 62 (output terminal section). Furthermore, the third wiring 80 including the negative electrode terminal 82 (second power supply terminal section) runs parallel not only to the first wiring 50 including the positive electrode terminal 52 (first power supply terminal section) but also to the clip 70.

[0080] In other words, the third wiring 80 runs parallel to the wiring that connects the positive terminal 52 to the junction of the semiconductor element 40L in the heat sink 61 that provides the connection point for the upper and lower arm circuits 9. The third wiring 80 also runs parallel to the wiring that connects the source electrode 40S of the semiconductor element 40H to the connection point for the upper and lower arm circuits 9. Due to this parallel arrangement, the current flowing from the positive terminal 52 to the connection point for the upper and lower arm circuits 9 when the MOSFET 11 configured in the semiconductor element 40H is turned on, and the current flowing from the connection point to the negative terminal 82 when the MOSFET 11 configured in the semiconductor element 40L is turned on, are opposite to each other and flow in opposite directions. Therefore, the inductance in the upper and lower arm circuits 9 (main circuit) can be reduced by the canceling effect of the magnetic flux generated by the current. This makes it possible to reduce the surge voltage generated during switching.

[0081] Furthermore, by using clip 70, the wiring from the positive terminal 52 to the connection point of the upper and lower arm circuits 9 is brought closer to the wiring from the connection point to the negative terminal 82, thereby reducing the PN current loop of the main circuit wiring. The PN current loop refers to the loop shape of the current path from the positive terminal 52 (P terminal) through the connection point of the upper and lower arm circuits 9 to the negative terminal 82 (N terminal). When the PN current loop is small, the wirings carrying current in opposite directions are brought closer to each other, increasing the magnetic flux cancellation effect, and thus reducing the inductance.

[0082] Furthermore, the heat generated by the semiconductor element 40H can be dissipated to the outside of the semiconductor device 20 via the first wiring 50 (heat sink 51). The heat generated by the semiconductor element 40L can be dissipated to the outside of the semiconductor device 20 via the second wiring 60 (heat sink 61). The single-sided heat dissipation structure allows the semiconductor device 20 to be miniaturized, i.e., reduced in height, in the Z direction.

[0083] The distance over which the third wiring 80 and the clip 70 run parallel is not particularly limited. By providing the third wiring 80 to run parallel to at least a portion of the clip 70, the inductance can be reduced to some extent. As an example, in this embodiment, the third wiring 80 runs parallel to the entire length of the clip 70 in a plan view. Because the parallel distance is long, the inductance can be reduced even further.

[0084] The parallel arrangement is not particularly limited. For example, in this embodiment, the third wiring 80 runs parallel to the first wiring 50 and the clip 70, facing each other in the Z direction. In other words, the board surfaces face each other. This increases the facing area and effectively reduces inductance.

[0085] As an example, in this embodiment, the third wiring 80 includes a clip 81 and a negative terminal 82. This makes it easier to adopt a sealed structure using the case 31. Clip 70 corresponds to the first clip, and clip 81 corresponds to the second clip. The negative terminal 82 corresponds to the terminal connected to the second clip.

[0086] <Variation> The case 31 constituting the sealing body 30 is not limited to the structure described above. For example, as shown in Figure 7, the case 31 may have a bottom wall 312 that closes one of the openings in the side wall 311. The heat sinks 51 and 61 are held in place by the bottom wall 312 (case 31) such that, for example, one side and the back side are exposed.

[0087] The encapsulant 30 is not limited to a configuration that includes a case 31. For example, as shown in Figure 8, the encapsulant 30 may be integrally molded as a whole. The encapsulant 30 shown in Figure 8 is molded from resin, for example, by a transfer molding method. An example of a resin is an epoxy resin. Such an encapsulant 30 may be called an encapsulating resin body, molded resin, or resin molded body. For convenience, the signal terminal 90 is not shown in Figure 8.

[0088] As shown in Figure 8, the third wiring 80 may be configured such that the connection part and the second power terminal part are provided continuously and integrally. As described above, the same applies to the first wiring 50 and the second wiring 60.

[0089] (Second Embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the elements were running parallel to each other while facing each other in the Z direction. Alternatively, they may be arranged in a parallel configuration that satisfies a facing relationship in the width direction.

[0090] Figure 9 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Figure 9 corresponds to Figure 3. Figure 10 is a plan view showing the state with the encapsulant 30 omitted. Figure 10 corresponds to Figure 4. Figure 11 shows the state with the encapsulant 30 and signal terminals 90 omitted compared to Figure 9. Figure 11 corresponds to Figure 6. In Figures 10 and 11, as in the prior embodiment, the current flowing from the positive terminal 52 toward the connection point of the upper and lower arm circuits 9 is indicated by a dashed-dotted arrow, and the current flowing from the connection point toward the negative terminal 82 is indicated by a double-dotted arrow.

[0091] The semiconductor device 20 constitutes a single-phase upper and lower arm circuit 9, similar to the configuration described in the prior embodiment. The semiconductor device 20 includes a encapsulant 30, a plurality of semiconductor elements 40, a first wiring 50, a second wiring 60, a clip 70, a third wiring 80, and a signal terminal 90.

[0092] The third wiring 80 is positioned to face the first wiring 50 and clip 70 in the width direction (X direction), rather than facing them in the thickness direction. As an example, the clip 81 of this embodiment has one end 811, two ends 812, and two connecting parts 813. The end 811 is joined to the source electrode 40S of the semiconductor element 40L. The two connecting parts 813 are connected to a common end 811. Each of the connecting parts 813 includes an X-direction extension extending from the end 811 in the X direction and a Y-direction extension extending in the Y direction. The two Y-direction extensions are positioned to sandwich the clip 70 (connecting part 73) in the X direction. The end 812 is provided at the end of the Y-direction extension.

[0093] For example, the thickness of clip 81 is approximately equal to that of clip 70. The Y-direction extension of connecting portion 813 is positioned so as to approximately coincide with the connecting portion 73 of clip 70 in the Z-direction. Each of the connecting portions 813 faces the connecting portion 73 in the X-direction. The connecting portions 813 and 73 face each other not on their plate surfaces, but on their end faces (side surfaces). The connecting portion 813 is positioned so as to enclose the connecting portion 73 in a plan view in the X-direction. The connecting portion 813 runs parallel to the entire length of the connecting portion 73.

[0094] The third wiring 80 has two negative terminals 82. Each of the negative terminals 82 extends in the Y direction. The negative terminals 82 are joined, for example, to a corresponding end 812. The two negative terminals 82 are positioned so as to sandwich the positive terminal 52 in the X direction.

[0095] As an example, the thickness of the negative terminal 82 is approximately equal to that of the positive terminal 52. The negative terminals 82 are positioned so as to coincide with the positive terminals 52 in the Z direction. Each of the negative terminals 82 faces the positive terminal 52 in the X direction. The negative terminals 82 and the positive terminals 52 face each other not at their plate faces, but at their end faces (side faces). The negative terminals 82 face the positive terminals 52 for most of their entire length. The other configurations are the same as those described in the prior embodiment.

[0096] <Summary of the second embodiment> In this embodiment, as in the prior embodiment, a clip 70 is used to connect the source electrode 40S (second main electrode) of the semiconductor element 40H (first element) to the second wiring 60 including the output terminal 62 (output terminal section). Furthermore, the third wiring 80 including the negative electrode terminal 82 (second power supply terminal section) runs parallel not only to the first wiring 50 including the positive electrode terminal 52 (first power supply terminal section) but also to the clip 70. As a result, the inductance in the upper and lower arm circuit 9 (main circuit) can be reduced.

[0097] In this embodiment in particular, the clip 81 of the third wiring 80 runs parallel to the clip 70 while facing it in the width direction (X direction). Also, the negative terminal 82 of the third wiring 80 runs parallel to the positive terminal 52 of the first wiring 50 while facing it in the width direction (X direction). The end faces (sides) of the third wiring 80, the first wiring 50, and the clip 70 face each other. Therefore, the inductance can be reduced while further reducing the profile. The PN current loop becomes smaller due to the facing in the width direction, thus reducing the inductance.

[0098] The clip 81 may have one end portion 812 and a connecting portion 813. In other words, the clip 81 may be positioned so as to face only one of the positive terminal 52 or one of the sides of the clip 70 in the X direction. As an example, the clip 81 in this embodiment is branched into two. The clip 81 then faces the positive terminal 52 and the clip 70 on both sides in the X direction. This increases the facing area and further reduces the inductance.

[0099] The arrangement described in this embodiment, in which the elements run parallel to each other while facing each other in the X direction, can be combined with various configurations shown in the prior embodiments.

[0100] (Third embodiment) This embodiment is a modification based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the parallel arrangement was applied to a configuration in which one semiconductor element forms one arm. Alternatively, the parallel arrangement may be applied to a configuration in which multiple semiconductor elements form one arm.

[0101] <Power converter> Figure 12 shows the circuit configuration of the power converter 4 according to this embodiment. As shown in Figure 12, the inverter 6 is configured with upper and lower arm circuits 9 for three phases. As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two parallel-connected MOSFETs 11 are connected to the P line 7. In the lower arm 9L, the sources of the two parallel-connected MOSFETs 11 are connected to the N line 8. The sources of the two parallel-connected MOSFETs 11 in the upper arm 9H and the drains of the two parallel-connected MOSFETs 11 in the lower arm 9L are interconnected.

[0102] Two parallel-connected MOSFETs 11 are driven on and off at the same time by a common gate drive signal (drive voltage). A freewheeling diode 12 is connected in antiparallel to each of the MOSFETs 11. The upper and lower arm circuit 9 for one phase is provided by a single semiconductor device 20.

[0103] <Semiconductor device> Figure 13 is a plan view showing the semiconductor device 20 according to this embodiment. For convenience, the encapsulant 30 and signal terminals 90 are omitted in Figure 13. Figure 13 corresponds to Figure 4.

[0104] The semiconductor device 20 shown in Figure 13 employs the configuration described in the prior embodiment in which the semiconductor elements are arranged in parallel while facing each other in the Z direction. Two semiconductor elements 40H are arranged on one surface of the heat sink 51. The drain electrodes 40D of each semiconductor element 40H are connected to a common heat sink 51. The two semiconductor elements 40H are arranged side by side in the X direction.

[0105] Two semiconductor elements 40L are arranged on one side of the heat sink 61, the same number as the semiconductor elements 40H. The drain electrode 40D of each semiconductor element 40L is connected to a common heat sink 61. The two semiconductor elements 40L are arranged side by side in the X direction. One of the semiconductor elements 40L is aligned with one of the semiconductor elements 40H in the Y direction. The other semiconductor element 40L is aligned with the other semiconductor element 40H in the Y direction.

[0106] The first wiring 50 includes a heat sink 51 and two positive terminals 52. Each of the positive terminals 52 extends in the Y direction. One of the positive terminals 52 is aligned in the Y direction with one pair of semiconductor elements 40H, 40L. The other positive terminal 52 is aligned in the Y direction with another pair of semiconductor elements 40H, 40L. The two positive terminals 52 are aligned in the X direction.

[0107] The semiconductor device 20 comprises two clips 70 and two third wirings 80. Each clip 70 extends in the Y direction. One clip 70 is aligned in the Y direction with one pair of semiconductor elements 40H, 40L. The other clip 70 is aligned in the Y direction with another pair of semiconductor elements 40H, 40L. One clip 70 electrically connects one source electrode 40S of semiconductor element 40H to the heat sink 61. The other clip 70 electrically connects another source electrode 40S of semiconductor element 40H to the heat sink 61. The two clips 70 are aligned in the X direction.

[0108] Each of the third wirings 80 extends in the Y direction. One of the negative terminals 82 faces one of the positive terminals 52 in the Z direction, and the other negative terminal 82 faces the other positive terminal 52 in the Z direction. One of the clips 81 electrically connects one of the source electrodes 40S of one of the semiconductor elements 40L to one of the negative terminals 82. The other clip 81 electrically connects one of the source electrodes 40S of the other semiconductor element 40L to the other negative terminal 82. One of the clips 81 faces one of the clips 70 in the Z direction, and the other clip 81 faces the other clip 70 in the Z direction. The two third wirings 80 are aligned in the X direction.

[0109] The semiconductor device 20 is arranged symmetrically with respect to a virtual line substantially parallel to the Y direction, i.e., a line-symmetric arrangement. The two semiconductor elements 40H, two semiconductor elements 40L, two positive terminals 52, two clips 70, and two third wirings 80 are arranged symmetrically with respect to the virtual line. The output terminal 62 is also arranged symmetrically with respect to the virtual line. The other configurations are the same as those described in the prior embodiment (see Figures 2 to 6).

[0110] <Summary of the third embodiment> This embodiment provides the same effects as the prior embodiment. Specifically, as in the prior embodiment, a clip 70 is used to connect the source electrode 40S of the semiconductor element 40H to the second wiring 60 including the output terminal 62. Furthermore, the third wiring 80 including the negative terminal 82 runs parallel not only to the first wiring 50 including the positive terminal 52, but also to the clip 70. Therefore, in a configuration in which the semiconductor elements 40H and 40L are connected in parallel, the inductance of the upper and lower arm circuits 9 can be reduced. By using the clip 70, the PN current loop of the main circuit wiring can be reduced, thereby reducing the inductance. In addition, the single-sided heat dissipation structure allows for a lower profile semiconductor device 20.

[0111] As an example, in this embodiment, the third wiring 80 runs parallel to the corresponding clip 70 over its entire length in a plan view. Because the parallel distance is long, the inductance can be further reduced.

[0112] As an example, in this embodiment, the third wiring 80 runs parallel to the first wiring 50 and the clip 70, facing each other in the Z direction. In other words, the board surfaces face each other. This increases the facing area and effectively reduces inductance.

[0113] <Variation> In a configuration comprising two semiconductor elements 40H and 40L, an example has been shown in which the semiconductor device 20 has two positive terminals 52, two clips 70, and two third wirings 80, but it is not limited to this. At least one of the positive terminals 52, clips 70, and third wirings 80 may be provided as a single unit. For example, as shown in Figure 14, the semiconductor device 20 may have one positive terminal 52, one clip 70, and one third wiring 80.

[0114] In Figure 14, the positive terminal 52 is provided so as to encompass the two positive terminals 52 shown in Figure 13. The clip 70 is provided so as to overlap the source electrodes 40S of the two semiconductor elements 40H in a plan view. The clip 70 is provided so as to encompass the two clips 70 shown in Figure 13. The clip 81 of the third wiring 80 is provided so as to overlap the source electrodes 40S of the two semiconductor elements 40L in a plan view. The clip 81 is provided so as to encompass the two clips 81 shown in Figure 13. The negative terminal 82 is also provided so as to encompass the two negative terminals 82 shown in Figure 13. With the above configuration, the opposing area can be increased and the inductance can be further reduced.

[0115] The parallel connection structure of the semiconductor elements 40 described in this embodiment can be combined with various configurations shown in the first and second embodiments. For example, it may be combined with an arrangement in which the elements run parallel to each other while facing each other in the X direction.

[0116] (Fourth Embodiment) This embodiment is a modification based on the prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the parallel arrangement was applied to a semiconductor device that constitutes a single-phase upper and lower arm circuit. Alternatively, it may be applied to a semiconductor device that constitutes a multi-phase upper and lower arm circuit.

[0117] Figure 15 is a plan view showing the semiconductor device 20 according to this embodiment. For convenience, the encapsulant 30 and signal terminals 90 are omitted in Figure 15. Figure 15 corresponds to Figure 4.

[0118] The semiconductor device 20 constitutes a three-phase upper and lower arm circuit 9, that is, it constitutes an inverter 6. For example, each arm is composed of one semiconductor element 40. The semiconductor device 20 has six semiconductor elements 40, specifically three semiconductor elements 40H and three semiconductor elements 40L. The three semiconductor elements 40H are arranged in a line in the X direction. The three semiconductor elements 40L are also arranged in the X direction. The semiconductor elements 40H and 40L are arranged in the Y direction for each phase.

[0119] The semiconductor device 20 has three second wirings 60. The second wirings 60 are arranged according to phase. One of the second wirings 60 has a U-phase output terminal 62U, another has a V-phase output terminal 62V, and another has a W-phase output terminal 62W. The three second wirings 60 are arranged side by side in the X direction.

[0120] The heatsink 61 of the second wiring 60 having output terminal 62U has semiconductor elements 40L that constitute the lower arm 9L of the U phase. The heatsink 61 of the second wiring 60 having output terminal 62V has semiconductor elements 40L that constitute the lower arm 9L of the V phase. The heatsink 61 of the second wiring 60 having output terminal 62W has semiconductor elements 40L that constitute the lower arm 9L of the W phase.

[0121] As an example, the first wiring 50 has one heat sink 51 and three positive terminals 52. The semiconductor device 20 has three clips 70 and three third wirings 80. Three semiconductor elements 40H are arranged on the heat sink 51. Each of the clips 70 extends in the Y direction. One of the clips 70 electrically connects the source electrode 40S of the semiconductor element 40H constituting the U-phase upper arm 9H to the heat sink 61. Another of the clips 70 electrically connects the source electrode 40S of the semiconductor element 40H constituting the V-phase upper arm 9H to the heat sink 61. Another of the clips 70 electrically connects the source electrode 40S of the semiconductor element 40H constituting the W-phase upper arm 9H to the heat sink 61. The three clips 70 are aligned in the X direction.

[0122] Each of the third wirings 80 extends in the Y direction. One clip 81 electrically connects the source electrode 40S of the semiconductor element 40L constituting the U-phase lower arm 9L to the corresponding negative terminal 82. Another clip 81 electrically connects the source electrode 40S of the semiconductor element 40L constituting the V-phase lower arm 9L to the corresponding negative terminal 82. Another clip 81 electrically connects the source electrode 40S of the semiconductor element 40L constituting the W-phase lower arm 9L to the corresponding negative terminal 82. Each of the negative terminals 82 faces the corresponding positive terminal 52 in the Z direction. Each of the clips 81 faces the corresponding clip 70 in the Z direction. The three third wirings 80 are aligned in the X direction.

[0123] The semiconductor device 20 is arranged symmetrically with respect to a virtual line substantially parallel to the Y direction, i.e., a line-symmetric arrangement. The three semiconductor elements 40H, three semiconductor elements 40L, three positive terminals 52, three output terminals 62U, 62V, 62W, three clips 70, and three third wirings 80 are arranged symmetrically with respect to the virtual line. The other configurations are the same as those described in the prior embodiment (see Figures 2 to 6).

[0124] <Summary of the fourth embodiment> This embodiment provides the same effects as the prior embodiment. Specifically, as in the prior embodiment, a clip 70 is used to connect the source electrode 40S of the semiconductor element 40H to the second wiring 60 including the output terminal 62. Furthermore, the third wiring 80 including the negative terminal 82 runs parallel not only to the first wiring 50 including the positive terminal 52, but also to the clip 70. Therefore, in the semiconductor device 20 that constitutes a multi-phase upper and lower arm circuit 9, the inductance of the upper and lower arm circuit 9 can be reduced. By using the clip 70, the PN current loop of the main circuit wiring can be reduced, thereby reducing the inductance. In addition, the single-sided heat dissipation structure allows for a lower profile semiconductor device 20.

[0125] As an example, in this embodiment, the third wiring 80 runs parallel to the corresponding clip 70 over its entire length in a plan view. Because the parallel distance is long, the inductance can be further reduced.

[0126] As an example, in this embodiment, the third wiring 80 runs parallel to the first wiring 50 and the clip 70, facing each other in the Z direction. In other words, the board surfaces face each other. This increases the facing area and effectively reduces inductance.

[0127] <Variation> Multiple phases are not limited to three phases. For example, two phases are also acceptable.

[0128] The example shown illustrates a semiconductor device 20 comprising a three-phase upper and lower arm circuit 9, which includes three positive terminals 52, three clips 70, and three third wirings 80, but is not limited to this. At least one of the positive terminals 52, clips 70, and third wirings 80 may be provided as a single unit. For example, as shown in Figure 16, the semiconductor device 20 may have one positive terminal 52, one clip 70, and one third wiring 80.

[0129] In Figure 16, the positive terminal 52 is provided so as to encompass the three positive terminals 52 shown in Figure 15. The clip 70 is provided so as to overlap with the source electrodes 40S of the three semiconductor elements 40H in a plan view. The clip 70 is provided so as to encompass the three clips 70 shown in Figure 15. The clip 81 of the third wiring 80 is provided so as to overlap with the source electrodes 40S of the three semiconductor elements 40L in a plan view. The clip 81 is provided so as to encompass the three clips 81 shown in Figure 15. The negative terminal 82 is also provided so as to encompass the three negative terminals 82 shown in Figure 15. With the above configuration, the opposing area can be increased and the inductance can be further reduced.

[0130] The configuration providing the multi-phase upper and lower arm circuit 9 described in this embodiment can be combined with various configurations shown in the first, second, and third embodiments. For example, it may be combined with an arrangement in which the arms run parallel to each other while facing each other in the X direction. For example, it may be combined with a parallel connection structure of each arm.

[0131] (Other embodiments) The disclosures in this specification and drawings are not limited to the exemplary embodiments. The disclosures include the exemplary embodiments and variations thereof by those skilled in the art. For example, the disclosures are not limited to combinations of parts and / or elements shown in the embodiments. The disclosures are implementable in a variety of combinations. The disclosures may have additional parts that can be added to the embodiments. The disclosures include those in which parts and / or elements of the embodiments have been omitted. The disclosures include substitutions or combinations of parts and / or elements between one embodiment and another. The scope of the disclosed technical areas is not limited to the descriptions of the embodiments. Some of the scope of the disclosed technical areas are indicated by the claims and should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0132] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims and extend to a wider and more diverse range of technical ideas than those described in the claims. Therefore, a variety of technical ideas can be extracted from the disclosures in the specification and drawings without being bound by the claims.

[0133] When an element or layer is referred to as “on top of,” “connected to,” “connected to,” or “joined,” it may be directly on top of, connected to, connected to, or joined to another element or layer, and there may also be an intervening element or layer. In contrast, when an element is referred to as “directly on top of,” “directly connected to,” “directly connected to,” or “directly joined to” another element or layer, there is no intervening element or layer. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used in this specification, the term “and / or” includes any combination with respect to one or more of the enumerated items relating to the relationship, and all combinations thereof.

[0134] Spatially relative terms such as "inside," "outside," "back," "below," "low," "above," and "high" are used here to facilitate descriptions of the relationship between one element or feature and other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned upside down, an element described as "below" or "directly below" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can encompass both up and down orientations. The device may also be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0135] The vehicle's drive system 1 is not limited to the configuration described above. For example, although an example with one motor generator 3 has been shown, it is not limited to this. It may have multiple motor generators. The power conversion device 4 is shown as having an inverter 6 as a power conversion unit, but it is not limited to this. For example, it may have a configuration with multiple inverters. It may have a configuration with at least one inverter and a converter. It may have only a converter.

[0136] The example shown illustrates a semiconductor element 40 having a MOSFET 11 as a switching element, but it is not limited to this. For example, an IGBT can also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. An IGBT with diodes connected in antiparallel, i.e., an RC-IGBT, may also be used. RC is an abbreviation for Reverse Conducting.

[0137] Although an example has been shown in which the semiconductor device 20 includes a encapsulant 30, the semiconductor device is not limited to this. A configuration without the encapsulant 30 is also possible.

[0138] In the semiconductor module 100, a cooler separate from the cooler 101 may be placed on one side 30a of the encapsulant 30.

[0139] The extraction of the signal terminal 90 is not limited to the configuration described above. Relay wiring (not shown) may be provided inside the semiconductor device 20. The relay wiring electrically connects the signal terminal 90 to the pad. Relay wiring can improve the flexibility of the placement of the signal terminal 90. For example, the signal terminal 90 may be placed in the housing space of the case 31 and electrically connected to the pad of the semiconductor element 40.

[0140] In a configuration in which the signal terminal 90 is held in the case 31, the arrangement of the signal terminal 90 is not particularly limited. For example, in a semiconductor device 20 that constitutes a two-phase upper and lower arm circuit 9, as shown in Figure 17, the signal terminal 90 may be arranged outside the positive terminal 52, output terminal 62, and negative terminal 82 in the X direction. In the X direction, the above-mentioned terminals 52, 62, and 82 are arranged between the signal terminal 90 connected to the pad of a semiconductor element 40 that constitutes one of the upper and lower arm circuits 9 and the signal terminal 90 connected to the pad of a semiconductor element 40 that constitutes the other upper and lower arm circuit 9.

[0141] Alternatively, as shown in Figure 18, the signal terminal 90 may be positioned in the X direction at a location that overlaps with the terminals 52, 62, and 82 described above, instead of as shown in Figure 17. Alternatively, as shown in Figure 19, the signal terminal 90 may be positioned between the terminals 52, 62, and 82 described above. Alternatively, as shown in Figure 20, the signal terminal 90 may be positioned on one of the four substantially rectangular annular side walls 311 (side wall portion), other than the side wall 311 from which the terminals 52, 62, and 82 are drawn.

[0142] In a configuration in which the encapsulant 30 is integrally molded, for example by a transfer molding method, the arrangement of the signal terminals 90 is not particularly limited. For example, in a semiconductor device 20 that constitutes a three-phase upper and lower arm circuit 9, as shown in Figures 21 and 22, the signal terminals 90 may be brought out from a position between the positive terminals 52 (negative terminals 82) that are aligned in the X direction on the side surface 30c. Similarly, the signal terminals 90 may be brought out from a position between the output terminals 62U, 62V, and 62W of each phase on the side surface 30d. As shown in Figure 23, the signal terminals 90 may be brought out from sides 30e and 30f, which are different from the sides 30c and 30d from which the terminals 52, 62, and 82 are brought out.

[0143] For example, in a semiconductor device 20 that constitutes a two-phase upper and lower arm circuit 9, as shown in Figure 24, the signal terminal 90 may be brought out from a position outside the positive terminal 52, output terminal 62, and negative terminal 82 in the X direction. As shown in Figure 25, the signal terminal 90 may also be brought out from a position between the aforementioned terminals 52, 62, and 82. Although not shown, the signal terminal 90 may also be brought out from the sides 30e and 30f.

[0144] (Disclosure of technical ideas) This specification discloses several technical concepts, as listed in the following paragraphs. Some paragraphs are written in a multiple dependent form, where subsequent paragraphs optionally refer to preceding paragraphs. Furthermore, some paragraphs are written in a multiple dependent form, referring to other multiple dependent forms. These paragraphs written in multiple dependent forms define several technical concepts.

[0145] <Technical philosophy 1> A semiconductor device comprising at least one phase of an upper and lower arm circuit (9), A plurality of semiconductor elements (40) include a first element (40H) that constitutes one of the arms of the upper and lower arm circuit, and a second element (40L) that constitutes the other arm of the upper and lower arm circuit, each having a first main electrode provided on one surface and a second main electrode provided on the back surface opposite to the surface in the thickness direction, A first wiring (50) having a first mounting portion (51) on which the first element is arranged and to which the first main electrode of the first element is connected, and a first power terminal portion (52) connected to the first mounting portion, A second wiring (60) having a second mounting portion (61) arranged alongside the first mounting portion in one direction perpendicular to the plate thickness direction, on which the second element is mounted and the first main electrode of the second element is connected, and an output terminal portion (62) connected to the second mounting portion, A clip (70) electrically connects the second main electrode of the first element and the second mounting portion, A third wiring (80) having a connection portion (81) to which the second main electrode of the second element is connected, and a second power terminal portion (82) connected to the connection portion, Equipped with, The third wiring runs parallel to the first wiring and the clip. <Technical philosophy 2> The semiconductor device according to technical concept 1, wherein the third wiring runs parallel to the entire length of the clip in a plan view in the thickness direction of the plate.

[0146] <Technical philosophy 3> The semiconductor device according to Technical Concept 1 or Technical Concept 2, wherein the third wiring runs parallel to the first wiring and the clip, facing each other in the thickness direction of the plate.

[0147] <Technical philosophy 4> The semiconductor device according to Technical Concept 1 or Technical Concept 2, wherein the third wiring runs parallel to the first wiring and the clip, facing each other in a direction perpendicular to both the alignment direction of the first mounting portion and the second mounting portion and the thickness direction.

[0148] <Technical philosophy 5> The aforementioned clip is the first clip, The semiconductor device according to any one of technical concepts 1 to 4, wherein the third wiring includes a second clip including the connection portion and a second power terminal portion, and includes a terminal connected to the second clip. [Explanation of symbols]

[0149] 1…Drive system, 2…DC power supply, 3…Motor generator, 4…Power converter, 5…Smoothing capacitor, 6…Inverter, 7…P line, 8…N line, 9…Upper and lower arm circuit, 9H…Upper arm, 9L…Lower arm, 10…Output line, 11…MOSFET, 12…Diode, 20…Semiconductor device, 30…Encapsulation, 30a…One side, 30b…Back side, 30c, 30d, 30e, 30f…Side, 31…Case, 311…Side wall, 312…Bottom wall, 32…Gel, 40, 40H, 40L… Semiconductor element, 40D...drain electrode, 40S...source electrode, 50...first wiring, 51...heat sink, 52...positive terminal, 60...second wiring, 61...heat sink, 2, 62U, 62V, 62W...output terminals, 70...clip, 71, 72...end, 73...connecting part, 80...third wiring, 81...clip, 811, 812...end, 813...connecting part, 82...negative terminal, 90...signal terminal, 100...semiconductor module, 101...cooler, 101F...flow channel, 101R...refrigerant, 102...insulating material

Claims

1. A semiconductor device comprising at least one phase of an upper and lower arm circuit (9), A plurality of semiconductor elements (40) include a first element (40H) that constitutes one of the arms of the upper and lower arm circuit, and a second element (40L) that constitutes the other arm of the upper and lower arm circuit, each having a first main electrode provided on one surface and a second main electrode provided on the back surface opposite to the surface in the thickness direction from the first surface, A first wiring (50) having a first mounting portion (51) on which the first element is arranged and to which the first main electrode of the first element is connected, and a first power terminal portion (52) connected to the first mounting portion, A second wiring (60) having a second mounting portion (61) arranged alongside the first mounting portion in one direction perpendicular to the plate thickness direction, on which the second element is mounted and the first main electrode of the second element is connected, and an output terminal portion (62) connected to the second mounting portion, A clip (70) electrically connects the second main electrode of the first element and the second mounting portion, A third wiring (80) having a connection portion (81) to which the second main electrode of the second element is connected, and a second power terminal portion (82) connected to the connection portion, Equipped with, The first wiring, the clip, and the third wiring extend in the direction of alignment of the first mounting portion and the second mounting portion in a plan view in the thickness direction of the plate. A portion of the third wiring and a portion of the first wiring are arranged side by side in a direction perpendicular to both the thickness direction and the one direction, and another portion of the third wiring and a portion of the clip are arranged side by side in a direction perpendicular to both the thickness direction and the one direction, A semiconductor device wherein the third wiring runs parallel to the first wiring and the clip, facing each of them in a lateral direction over a predetermined length in one direction.

2. The third wiring has two extensions that extend in one direction, The two extensions are arranged so as to sandwich the first wiring and the clip in the side-by-side direction. The semiconductor device according to claim 1, wherein the portion sandwiched between the two extensions in the first wiring and the portion sandwiched between the two extensions in the clip are aligned in one direction in a plan view in the thickness direction of the plate.

3. The aforementioned clip is the first clip, The semiconductor device according to claim 1 or 2, wherein the third wiring includes a second clip including the connection portion and a second power terminal portion, and includes a terminal connected to the second clip.

Images