Memory access popularity statistics method and memory

Abstract

A method for statistically analyzing memory access popularity, a controller, a chip, a memory, a motherboard, and a computer device are disclosed, which relate to the field of computers. The method includes: collecting statistics on the access frequency of a processor accessing data blocks in a memory based on the operations performed on the memory by an application program executed by the processor; and determining the access popularity of the data blocks based on the access frequency. The access frequency represents the frequency at which the application program accesses the data blocks. The fact that the number of accesses by the application program to a data block is greater indicates that the access frequency of the application program to the data block is higher and the access popularity of the data block is higher. The fact that the number of accesses by the application program to a data block is less indicates that the access frequency of the application program to the data block is lower and the access popularity of the data block is lower. In this way, hot data is transferred to near-memory, and cold data is transferred to far-memory. As a result, the processor can obtain the frequently accessed data from near-memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay in data processing is reduced, and the access performance of the system is significantly improved.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202210575022.5, titled "DATA MIGRATION METHOD," filed with the China National Intellectual Property Administration on 24 May 2022, and Chinese Patent Application No. 202211016161.0, titled "MEMORY ACCESS POPULARITY STATISTICS METHOD AND RELATED APPARATUS AND DEVICE," filed with the China National Intellectual Property Administration on 24 August 2022, both of which are incorporated herein by reference.

[0002] This application relates to the computer field, and more particularly to memory access popularity statistics methods, controllers, chips, memory, mainboards, and computer devices. [Background technology]

[0003] Currently, high-speed memory devices are expected to store frequently accessed data, while slow-access memory devices are expected to store infrequently accessed data. However, due to the low accuracy of existing memory access popularity statistics, high-speed memory devices may store infrequently accessed data, or slow-access memory devices may store frequently accessed data. This affects the data processing speed and latency of the system. [Overview of the Initiative]

[0004] This application provides a memory access popularity statistics method, controller, chip, memory, mainboard, and computer device for improving the data processing speed of a system and reducing data processing delays.

[0005] According to a first aspect, a memory access popularity statistics method is provided, which is performed by a controller. The method comprises: collecting statistics on the frequency of access by a processor to a data block in memory based on operations performed on the memory of the computer device by an application program executed by the processor in the computer device, and determining the access popularity of the data block based on the access frequency.

[0006] In this way, access frequency intuitively represents how often an application program accesses a data block. A higher number of accesses by an application program to a data block indicates that the application program accesses that data block frequently and that the data block is more popular for access. A lower number of accesses by an application program indicates that the application program accesses that data block less frequently and that the data block is less popular for access. Therefore, when data migration is triggered based on the access popularity of a data block, hot data may be migrated to near memory and cold data may be migrated to far memory, and as a result, the processor can retrieve frequently accessed data from near memory as quickly as possible. This improves the system's data processing speed, reduces data processing delays, and significantly improves the system's access performance.

[0007] In a possible implementation, the step of collecting statistics on the frequency of access to the data block where the first address is located includes: the step of collecting statistics on the frequency of access to the data block where the unit storage space to which the first address belongs is located.

[0008] The size of a data block is a multiple of the unit memory space accessible to the processor. Computer devices manage memory space by performing read or write operations using cache lines as a granularity and by using pages as a granularity. A page may contain multiple cache lines. The size of a data block is the size of a page in memory accessible to the processor in the computer device. The size of a unit memory space may be the size of a cache line when the processor in the computer device accesses memory. Operations performed on cache lines in memory by application programs executed by the processor in the computer device can be considered operations on pages. In this way, the processor performs operations on memory using cache lines as a granularity, and the cache line belongs to a managed page. Therefore, once an operation is performed on a cache line in memory, the page to which that cache line belongs is read and written once. The controller collects statistics on the frequency of access to the page to which the cache line on which the operation was performed belongs. This effectively improves the accuracy of identifying the access popularity of pages. In addition, the controller collects statistics on the frequency of page access by using pages as the granularity, which is compatible with the memory page management methods performed by computer devices. The memory access popularity statistics method is easy to use.

[0009] In addition, interleaving means that the processor within a computer device distributes data across multiple memory locations for operation. Application programs executed by the processor within the computer device perform operations in an interleaved manner against the computer device's memory and perform data processing based on multiple memory channels, thereby improving the memory bandwidth utilization and processing performance of the computer device. Alternatively, the size of a data block may be the size of the interleaved data blocks in the memory accessible in an interleaved manner by the processor within the computer device.

[0010] In another possible implementation, the method further comprises: identifying a second address based on the address of the data block where the first address is located and an address mapping relationship. The second address indicates a location within the controller where the access frequency for accessing the data block is stored. The address mapping relationship indicates a mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored. Thus, the controller obtains the access frequency for accessing the data block stored in the first storage medium based on the second address and updates the access frequency for accessing the data block.

[0011] In another possible implementation, the memory comprises a first storage medium configured to store the access frequencies for accessing data blocks in the memory, and the second address indicates a storage space within the first storage medium where the access frequencies for accessing data blocks are stored.

[0012] In another possible implementation, the computer device pre-allocates the capacity of the memory device in memory. When the processor accesses the first storage medium, the computer device allocates a physical address space corresponding to the capacity of the first storage medium from the capacity of the memory device in memory, and the controller maps the physical address for accessing the first storage medium to the first storage medium. In this way, the corresponding capacity in the memory device cannot be used, resulting in wasted storage space in the memory device. For example, the total capacity of the memory device in memory is 64 GB, the page size is 4 KB, and the bit width of the access frequency for storing each data block is 4 B. This results in 64 MB of memory storage space being wasted. This method further comprises: identifying a second address and obtaining the access frequency for accessing a data block based on a third address and address mapping relationship indicated by the processor, where the third address is determined based on the second address. Thus, the storage space of the memory device is saved, and the utilization rate of the memory device's storage space is improved.

[0013] In another possible implementation, the method further includes: a controller determining the access popularity of data blocks based on access frequency and triggering data migration based on access popularity. For example, the controller feeds the access popularity of data blocks back to the processor, and the processor controls data blocks with different access popularity to perform data migration. For example, the processor stores cold data in far memory and hot data in near memory. In this way, when the controller triggers data migration based on the access popularity of data blocks, hot data may be migrated to near memory and cold data may be migrated to far memory, and as a result the processor can retrieve data from near memory as quickly as possible. This improves the system's data processing speed, reduces data processing delays, and improves the overall system performance.

[0014] According to a second aspect, a memory access popularity statistics method is provided. This method is executed by a processor: receiving the access frequencies of interleaved data blocks transmitted by a plurality of memories, and obtaining the access frequency of accessing a page by combining the access frequencies of accessing the interleaved data blocks. The access frequency of accessing an interleaved data block indicates the access frequency at which the processor accesses the data blocks in one of the plurality of memories in an interleaved manner.

[0015] In this way, in order to improve the memory bandwidth utilization rate and processing performance of a computer device, when an application program executed by a processor in the computer device operates on the memory of the computer device in an interleaved manner and executes data processing based on a plurality of memory channels, the controller combines the access frequencies of accessing the interleaved data blocks transmitted by the plurality of memories to obtain the access frequency of accessing a page. As a result, the access popularity of the page is determined based on the access frequency of accessing the page. When data migration is triggered based on the access popularity of the page, hot data can be migrated to near-memory, and cold data can be migrated to far-memory. In this way, the processor can obtain the frequently accessed data from near-memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay of data processing is reduced, and the access performance of the system is greatly improved.

[0016] According to a third aspect, a memory access popularity statistics apparatus is provided. This apparatus includes a module configured to execute the memory access popularity statistics method in any one of the first aspect or possible designs of the first aspect, or a module configured to execute the memory access popularity statistics method in any one of the second aspect or possible designs of the second aspect.

[0017] According to a fourth aspect, a controller is provided. The controller includes a processing unit and a memory unit. The memory unit is configured to store a group of computer instructions. When the processing unit is used as the controller in any one of the first aspect or a possible implementation form of the first aspect to execute a group of computer instructions, the processing unit executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect. The controller is a register clock driver (RCD) or an extended controller in the memory of a computer device.

[0018] According to a fifth aspect, a chip including a processor and a power supply circuit is provided. The power supply circuit is configured to supply power to the processor, and the processor is configured to execute the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0019] According to a sixth aspect, a memory is provided. The memory includes a storage device and a controller according to the fourth aspect. The storage device is configured to store a group of computer instructions. When executing a group of computer instructions, the controller executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0020] According to a seventh aspect, a motherboard is provided. The motherboard includes a controller according to the fourth aspect, and the controller executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0021] According to an eighth aspect, a computer device is provided. The computer device includes a motherboard according to the seventh aspect.

[0022] According to the ninth aspect, a computer-readable storage medium is provided that includes computer software instructions. When the computer software instructions are executed on a computing device, the computing device is able to perform the operational steps of the method according to the first aspect or any one of the possible implementations of the first aspect.

[0023] According to the tenth aspect, a computer program product is provided. When the computer program product is executed on a computer, the computing device is able to perform the operational steps of the method according to the first aspect or any one of the possible implementations of the first aspect.

[0024] In this application, the implementation configurations can be combined based on the above-described configurations to provide a wider range of implementation configurations. [Brief explanation of the drawing]

[0025] [Figure 1] This is a schematic diagram of the structure of the computer device according to the present invention.

[0026] [Figure 2] This is a schematic flowchart of the memory access popularity statistics method according to this application.

[0027] [Figure 3] This is a schematic diagram illustrating the relationship between cash lines and pages according to the present application.

[0028] [Figure 4] This is a schematic diagram of the memory structure for access frequency according to the present invention.

[0029] [Figure 5] This is a schematic diagram of the interleaving method according to the present invention.

[0030] [Figure 6] This is a schematic diagram of the structure of another computer device according to the present invention.

[0031] [Figure 7] This is a schematic diagram of the memory access popularity statistics device according to the present invention.

[0032] [Figure 8] This is a schematic diagram of the structure of the controller according to the present invention. [Modes for carrying out the invention]

[0033] To facilitate the explanation, the terminology used in this application will be briefly explained first.

[0034] Memory Devices: Memory devices are memory components used to store programs and various types of data. Access speed refers to the data transmission speed at which data is written to or read from a memory device. Access speed can also be called read / write speed. Based on the access speed of memory devices, main memory devices connected to the processor within a computer device can be classified into far memory and near memory. Main memory devices can be abbreviated as main memory or memory. The access speed of near memory is greater than that of far memory. For example, near memory may be Dynamic Random Access Memory (DRAM) or Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Far memory may be storage class memory (SCM).

[0035] Hot Data: Hot data is data that is frequently accessed by the processor. When hot data is stored in near memory, the processor can retrieve the data as quickly as possible. This improves the system's data processing speed, reduces data processing delays, and significantly improves the system's access performance.

[0036] Cold data: Cold data is data that is not frequently accessed by the processor. When cold data is stored in far memory, data reliability can be improved, and more hot data can be stored in near memory. This improves the resource utilization of near memory and reduces system costs.

[0037] Cache line: A cache line is a unit used by computer devices to perform read or write operations on memory storage space. The size of a cache line can be 64 bytes (B).

[0038] Page: A page is a unit used by computer devices to manage memory space. For example, page size can be 4 kilobytes (KB), 2 megabytes (MB), or another byte size. A 4KB page may be called a small page. A 2MB page may be called a huge page. A smaller page indicates that more resources are required by the computer device to manage the memory, and a larger page indicates that fewer resources are required by the computer device to manage the memory. A page can contain multiple cache lines. Specifically, the page size is a multiple of the cache line size.

[0039] Interleaving: Interleaving refers to the distribution of data accessed in memory evenly across multiple memory channels based on a unit of memory space (e.g., a cache line). The interleaving method can be configured by the system administrator, and interleaving can be performed across multiple memory channels connected to a single processor, or across multiple memory channels of multiple processors.

[0040] Memory Channels: Memory channels refer to multiple memory locations connected to the processor within a computer device. The processor can perform operations on memory using interleaving techniques. For example, the processor distributes data to be written to memory evenly across multiple memory channels based on the size of the cache lines. Furthermore, the processor reads data from multiple memory channels based on the size of the cache lines. Data processing is performed across multiple memory channels, resulting in improved memory bandwidth utilization and processing performance of the computer device.

[0041] To improve the accuracy of memory access popularity statistics, this application provides a memory access popularity statistics method. Specifically, statistics on the frequency of access by the processor to data blocks in memory are collected based on the actions performed on the memory of the computer device by an application program executed by the processor in the computer device. The access popularity of the data block is determined based on the access frequency, and data migration is triggered based on the access popularity. Access frequency intuitively represents how often the application program accesses the data block. A higher number of accesses by the application program to a data block indicates that the application program accesses the data block more frequently and that the data block is more popular. A lower number of accesses by the application program indicates that the application program accesses the data block less frequently and that the data block is less popular. Therefore, when data migration is triggered based on the access popularity of a data block, hot data can be migrated to near memory and cold data can be migrated to far memory. As a result, the processor can retrieve frequently accessed data from near memory as quickly as possible. This improves the system's data processing speed, reduces data processing delays, and significantly improves the system's access performance.

[0042] The size of a data block is a multiple of the unit storage space in memory accessible to the processor. For example, the size of a data block is the page size used by a computer device to manage memory. Another example is the size of an interleaved data block in memory accessible in an interleaved manner to the processor within a computer device.

[0043] The memory access popularity statistics method provided in this application will be described in detail below with reference to the attached drawings.

[0044] Figure 1 is a schematic diagram of the structure of a computer device according to the present invention. In this specification, an example in which the computer device includes near memory is used for illustrative purposes. As shown in Figure 1, the computer device 100 includes a processor 110 and memory 120. The processor 110 is connected to the memory 120 by using a bus 130.

[0045] The processor 110 may be a central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), neural processing unit (NPU), or embedded neural network processing unit (NPU), or an XPU used for data processing. The processor 110 may also be another general-purpose processor, digital signal processing (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or system on chip (SoC) or another programmable logic device, discrete gate or transistor logic device, discrete hardware component, or similar. The general-purpose processor may be a microprocessor or any conventional processor, or similar. For ease of explanation, in the following embodiments, an example in which the processor 110 is a CPU is used for explanation.

[0046] The computer device 100 in Figure 1 may include one or more processors. The processors may be multi-core processors. The processors as used herein may be one or more devices, circuits, and / or processing units configured to process data (e.g., computer program instructions).

[0047] The processor 110 is configured to execute an application program to perform read or write operations to the memory 120 and to trigger data migrations based on the frequency of access to the memory 120.

[0048] Bus 130 may include channels configured to transmit data between the aforementioned components (e.g., processor 110 and memory 120). For example, processor 110 sends access requests to memory 120, and memory 120 feeds back to processor 110 the frequency of accessing data blocks. In addition to the data bus, bus 130 may further include a power bus, control bus, status signal bus, and similar. For example, bus 130 is a DDR bus. However, for the sake of clarity, various types of buses are shown as bus 130 in the diagram.

[0049] Memory 120 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. As an illustrative rather than restrictive description, many forms of RAM may be used, such as static random access memory (static RAM, SRAM), DRAM, synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus random access memory (direct rambus RAM, DR RAM).

[0050] Memory 120 includes a memory device 121, a data buffer (DB) 122, and a register clock driver (RCD) 123. DB 122 is connected to memory device 121 and RCD 123.

[0051] The memory device 121 is configured to store application data for an application program executed by the processor 110. For example, the memory device 121 may be a DRAM.

[0052] DB122 is configured to drive data signals generated by the memory controller in the processor 110 to write data transmitted by the processor 110 to the memory device 121, and to transmit application data stored in the memory device 121 to the processor 110, or to transmit the access frequency for accessing data blocks stored in RCD123 to the processor 110.

[0053] The RCD123 is configured to drive clock, address, and command signals generated by the memory controller in the processor 110 to implement operations on multiple memory devices 121. Based on access requests from the processor 110, the RCD123 is configured to perform read or write operations on the memory devices 121 in the memory 120, count the access frequency of accessing data blocks in the memory devices 121 in the memory 120, and store the access frequency of accessing data blocks. The RCD123 is further configured to obtain the access frequency of accessing data blocks from the storage medium 124. Optionally, the RCD123 may determine the access popularity of a data block based on its access frequency and trigger a data migration.

[0054] The RCD123 includes a storage medium 124, which is configured to store the access frequency of accessing data blocks. In this way, the storage space of the memory device 121 is not occupied to store the access frequency of accessing data blocks, and the resource utilization of the memory device 121 is improved. The storage medium 124 may be a volatile memory pool or a non-volatile memory pool, or it may include both volatile and non-volatile memory. For example, the storage medium 124 may be RAM or ROM. The storage capacity of the storage medium 124 is related to the size of the data blocks used to collect statistics on access frequency. The storage capacity of the storage medium 124 can be determined in the following two ways.

[0055] Method 1: The capacity of the storage medium that stores the access frequency of page access is determined based on the memory capacity, page size, and the bit width of the counter that counts the access frequency.

[0056] If statistics on the frequency of accessing a page are collected, the capacity of the storage medium used to store the access frequency of the page can be determined based on the memory capacity, page size, and the bit width of the counter that counts the access frequency. The capacity of the storage medium is given by the following equation (1). n1 capacity =(n capacity / X page size )*W count Formula (1)

[0057] n1 capacity n represents the capacity of the storage medium used to store the frequency of accessing a page. capacity This represents the memory capacity, X page size This represents the page size, W count This represents the bit width of the counter that counts access frequency. The bit width of the counter can be determined based on empirical values. A larger bit width indicates that the counter records larger values; and a smaller bit width indicates that the counter records smaller values.

[0058] Example 1: Assume the memory capacity is 64GB, the page size is 4KB, the counter bit width is 4B, and the storage medium capacity is (64GB / 4KB)*4B=64MB.

[0059] Example 2: Assume the memory capacity is 64GB, the page size is 2MB, the counter bit width is 4B, and the storage medium capacity is (64GB / 2MB)*4B=128KB.

[0060] It can be seen that a larger page size indicates a smaller storage capacity and that less data needs to be stored for each page access. Conversely, a smaller page size indicates a larger storage capacity and that more data needs to be stored for each page access.

[0061] In addition, if the computer device manages memory by using 4KB pages, the storage medium 124 requires a large storage space. In some embodiments, the RCD 123 may be further connected to an external storage medium to expand the capacity of the RCD 123 for storing the access frequency of accessing pages. For example, as shown in Figure 1, the RCD 123 is further connected to a storage medium 125. The storage medium 124 may be configured to cache the access frequency of frequently accessed pages. The storage medium 125 is configured to store the access frequency of accessing pages. Optionally, when the RCD 123 updates the access frequency of accessing pages stored in the storage medium 125, two operations performed by the storage medium 125 are involved. The RCD 123 may satisfy the requirement for storing access frequency by expanding the bandwidth of the storage medium or by increasing the access frequency to the storage medium. For example, the RCD 123 may be connected to at least two storage media to expand the bandwidth of the storage media and increase the access frequency to the storage media.

[0062] Method 2: Based on the memory capacity, page size, bit width of the counter that counts access frequency, and the number of interleaved internal channels, the capacity of the storage medium that stores the access frequency to the interleaved data block is determined.

[0063] When statistics regarding the access frequency for accessing interleaved data blocks are collected, the capacity of the storage medium used to store the access frequency for accessing interleaved data blocks can be determined based on the capacity of the memory, the page size, the bit width of the counter for counting the access frequency, and the number of interleaved internal channels.

[0064] There are N channel memory channels in the computer device, the page size is X page size bytes, and the data is interleaved among N channel memory channels based on the cache line granularity, and assume that the size of the interleaved data block (sub-page) dispersed within each memory channel is X page size / N channel bytes. Specifically, the controller of each memory channel manages the memory unit based on X page size / N channel bytes, and the controller of each memory channel records the access frequency for accessing the data block based on X page size / N channel bytes. The capacity of the storage medium is shown in the following formula (2). n1 capacity =(n capacity / (X page size / N channel )*W count ) Formula (2)

[0065] n1 capacity represents the capacity of the storage medium for storing the access frequency for accessing the interleaved data block, n capacity represents the capacity of the memory, X page size represents the page size, and W count represents the bit width of the counter for counting the access frequency. N <​​​​page size (=2MB), the data is interleaved into 8 memory channels based on the granularity of the cache lines (N channel =8), the size of the interleaved data blocks in each memory channel is 256KB, and the memory capacity is 64GB (n capacity =64GB), and the bit width of the counter that counts access frequency is 4B (W count Assume the storage medium has a capacity of 1 MB (=4B). The physical address space of the storage medium that needs to be reserved by the computer device for the 8 memory channels is 8 MB. The processor can obtain access frequencies based on 256 KB units to access the 8 memory channels, combine these access frequencies to obtain access frequencies to access a full 2 ​​MB page, and perform data migration. For example, the processor may add 8 data items.

[0067] Example 2: The page size is 4KB (X page size (=4KB), the data is interleaved into 8 memory channels based on the granularity of the cache lines (N channel (=8) The size of the interleaved data blocks in each memory channel is 512B, and the memory capacity is 64GB (n capacity =64GB), and the bit width of the counter that counts access frequency is 4B (W count Assume the storage medium has a capacity of 0.5GB (=4B). The RCD of each memory channel needs to record access frequency based on 512B units. The physical address space of the storage medium that the computer device needs to reserve for 8 memory channels is 4GB.

[0068] Please understand that the components included in the computer device 100 shown in Figure 1 are merely illustrative examples. In certain embodiments, the quantity of components may be determined based on service requirements.

[0069] The following describes the memory access popularity statistics method according to this application, with reference to Figure 2.

[0070] Step 210: RCD123 determines the memory space that will be accessed by the access request sent by processor 110.

[0071] The RCD123 receives access requests sent by the processor 110 using a memory bus (e.g., a DDR bus), decodes the access requests, and obtains the physical address and operation instructions. Based on the physical address, the RCD123 determines whether the processor 110 accesses the memory device 121 or the storage medium 124 in the memory 120.

[0072] If the physical address points to the memory space of memory device 121, it indicates that RCD123 has determined that an application program executed by processor 110 will access memory device 121 and, based on the operation instruction, will perform a read or write operation on memory device 121. Steps 220 and 230 are then performed.

[0073] If the physical address points to the storage space of the storage medium 124, it indicates that the RCD 123 has determined to obtain the access frequency by which the processor 110 accesses the storage medium 124 to access data blocks, and has also determined to perform a read operation on the storage medium 124 based on the operation instruction. Steps 240 and 250 are then performed.

[0074] Step 220: RCD123 performs an operation on memory device 121 in memory 120.

[0075] If the operation instruction tells RCD123 to perform a write operation to the storage space indicated by the physical address in memory device 121, RCD123 writes the data obtained using DB122 to the storage space indicated by the physical address.

[0076] When an operation instruction tells the RCD123 to perform a read operation on the memory space indicated by the physical address in the memory device 121, the RCD123 reads the data stored in the memory space indicated by the physical address and transmits the data to the processor 110 using the DB122.

[0077] Step 230: RCD123 collects statistics on the frequency of access to the data block where the first address is located.

[0078] Because cache lines are used as the smallest granularity for operations performed on memory 120 by application programs executed by processor 110, access requests sent by processor 110 indicate that the application program executed by processor 110 is performing a read or write operation on a cache line. RCD 123 performs the read or write operation based on the cache line indicated by the physical address. Once a cache line has been read or written to, the access frequency to the page to which that cache line belongs increases by 1. RCD 123 can set a counter for each page and collect statistics on the access frequency to that page. Each time an application program executed by processor 110 accesses a page, the counter corresponding to that page is incremented by 1. Therefore, to improve the accuracy of collecting statistics on memory access popularity, memory access popularity statistics are collected using pages of the memory storage space managed by the computer device as the granularity.

[0079] For example, as shown in Figure 3(a), the size of the physical address space of memory is 2 N+1 The cache line size is 64 bytes. The page size can be 4KB or 2MB.

[0080] As shown in Figure 3(b), we assume that the size of a cache line is 64 bytes and the page size is 4KB. A 4KB page contains 64 consecutive cache lines. Physical address 0x000 represents the starting address of the first page. Physical address 0x1000 represents the starting address of the second page. The first page contains 64 consecutive cache lines between physical addresses 0x000 and 0x1000. The second page contains 64 consecutive cache lines between physical addresses 0x1000 and 0x2000.

[0081] When RCD123 collects statistics on page access frequency, the address segment for statistics is determined based on the page size. For example, if the page size is 4KB, RCD123 collects statistics on access frequency to pages contained in address segment [N:12]. N represents the capacity of memory 120. For example, if the capacity of memory 120 is 64GB, then N=35. Assume the capacity of memory 120 is 64GB. Address segment [N:12] contains pages of 64GB / 4KB=16MB, and RCD123 collects statistics on access frequency to 16MB pages contained in address segment [N:12].

[0082] As another example, the page size is 2MB, and RCD123 collects statistics on the frequency of accessing pages contained in address segment [N:21]. Assume the capacity of memory 120 is 64GB. Address segment [N:21] contains pages of 64GB / 2MB=32KB, and RCD123 collects statistics on the frequency of accessing 32KB pages contained in address segment [N:21].

[0083] The physical address included in the access request points to a first address, and it is assumed that the application program executed by the processor 110 accesses the cache line indicated by the first address in the memory device 121. The first address may be the address of the cache line, or an address segment within an address segment where statistics related to it are collected. The RCD 123 identifies a second address based on the address of the page where the first address is located and the address mapping relationship, and based on the second address, reads the access frequency of the accessed page from the storage medium 124 and updates the access frequency for accessing the page. In other words, it increments the access frequency for accessing the page by 1 and writes the updated access frequency for accessing the page back to the storage medium 124. The second address indicates the location in the memory space where the access frequency for accessing the page is stored. The second address may be the page number or the address of the page. The address mapping relationship indicates the mapping relationship between the address of the page and the address in the memory space where the access frequency is stored. For example, if the first address indicates an address, the RCD123 determines the page number of the page where the cache line indicated by the first address is located, and reads the access frequency of the accessed page from the storage medium 124 based on the page number of that page. If the first address indicates an address segment, the RCD123 determines the page numbers of all pages where the cache line indicated by that address segment is located, and then reads the access frequency of the accessed page from the storage medium 124 based on the page numbers of those pages.

[0084] Step 240: RCD123 performs an operation on the storage medium 124 in memory 120.

[0085] The computer device pre-allocates the capacity of memory device 121 within memory 120. Therefore, when the processor 110 accesses storage medium 124, the computer device allocates a physical address space corresponding to the capacity of storage medium 124 from the capacity of memory device 121 within memory 120, and the RCD 123 maps the physical address for accessing storage medium 124 to storage medium 124. In this way, the corresponding capacity within memory device 121 cannot be used, resulting in wasted storage space in memory device 121. For example, if the page size is 4KB, 64MB of memory storage space is wasted.

[0086] The RCD123 determines the physical address of the storage medium 124 based on the page number (page address) of the page, and can store a field formed by some bits of the page number and the access frequency in the corresponding address space within the storage medium 124. As shown in Figure 4, the bit width of each page counter is 4B (32 bits) and is divided into two parts. One part is used to record the access frequency of accessing the page, and the other part is used to record any 8 bits of the page number of the page. The location for recording the access frequency of accessing the page and the location for recording any 8 bits of the page number of the page are not limited. Bits 23 to 0 are used to record the access frequency of accessing the page, and bits 32 to 24 are used to record any 8 bits of the page number of the page. For example, bits 32 to 24 represent the least significant 8 bits of the page number of the page. Furthermore, the page number of a page is accessed by the processor 110, and the access frequency of accessing that page is stored in the storage medium 124. This is used to generate a corresponding address space, and a mapping relationship is obtained between the address of the data block and the address of the storage space used to store the access frequency. As a result, the address space reserved for memory 120 can be saved, and the objective of mapping the address space of the storage medium for storing the access frequency is achieved by using a small amount of address space. This helps the RCD 123 determine the physical address for the processor 110 to access the storage medium 124 based on the address mapping relationship, thereby improving the storage space utilization rate of the memory device 121.

[0087] In some embodiments, some bits of the page number of a page are used by the processor 110 to generate a corresponding address space, in which the frequency of accessing the page is stored in the storage medium 124. For example, the remaining bits obtained by deleting any bits in the page number of a page are used as a corresponding address space, in which the frequency of accessing the page is stored in the storage medium 124. If a larger number of arbitrary bits are deleted from the page number of a page, it indicates that the corresponding address space, in which the frequency of accessing the page is stored in the storage medium 124, is smaller. Conversely, if a smaller number of arbitrary bits are deleted from the page number of a page, it indicates that the corresponding address space, in which the frequency of accessing the page is stored in the storage medium 124, is larger. For example, after the RCD 123 performs an operation on a page in the memory device 121, it stores the least significant 8 bits of the page number of the page in bits 32 to 24 of the counter and increments the access frequency recorded in bits 23 to 0 by one.

[0088] The physical address obtained by RCD123 indicates the storage space of storage medium 124, which indicates that RCD123 has decided to obtain the access frequency of the processor 110 accessing storage medium 124 to access data blocks, and has decided to perform a read operation on storage medium 124 based on the operation instruction. The physical address may be the remaining bits obtained by deleting any bit in the page number of the page. For example, RCD123 obtains a third address, determines the storage space of storage medium 124 indicated by the third address, extracts the most significant 8 bits after reading 32 bits of data, then adds the third address to obtain the page number, where the corresponding 24 bits of data are the access frequency of accessing the page corresponding to the page number.

[0089] Step 250: RCD123 determines the access popularity of a data block based on its access frequency.

[0090] If the access frequency is greater than or equal to a threshold, the data block is determined to be hot data; or if the access frequency is less than the threshold, the data block is determined to be cold data. The RCD123 may feed back the page number and the access popularity of the page indicated by that page number to the processor 110 to trigger a data migration.

[0091] In this way, the processor performs operations on memory using cache lines as the granularity, and each cache line belongs to a managed page. Therefore, once an operation is performed on a cache line in memory, the page to which that cache line belongs is read and written once. The controller collects statistics on the frequency of access to the page to which the cache line on which the operation was performed belongs. This effectively improves the accuracy of identifying the access popularity of pages. In addition, the controller collects statistics on the frequency of access to pages using pages as the granularity, which is compatible with the memory page management methods performed by computer devices. The memory access popularity statistics method is easy to use. Furthermore, if data migration is triggered based on the access popularity of data blocks, hot data may be migrated to near memory and cold data may be migrated to far memory, so that the processor can retrieve frequently accessed data from near memory as quickly as possible. This improves the system's data processing speed, reduces data processing delays, and significantly improves the system's access performance.

[0092] In the embodiments described above, 4KB pages (small pages) and 2MB pages (huge pages) are used to illustrate the memory access popularity statistics method.

[0093] In some other embodiments, when an application program executed by a processor performs interleaved operations on the memory of a computer device, the data accessed in memory is evenly distributed across multiple memory channels based on a unit of storage space (e.g., a cache line). When the controller of each memory channel collects statistics on memory access popularity, the controller also collects statistics on the frequency of access to interleaved data blocks. For how the controller of each memory channel collects statistics on the frequency of access to interleaved data blocks, see the above description of the frequency of access to pages.

[0094] The difference in collecting statistics on the access frequency of accessing interleaved data blocks compared to non-interleaved scenarios is that the size of the interleaved data block is less than the page size, and the corresponding address space, which is accessed by the processor 110 and whose access frequency to the page is stored in the storage medium 124, is generated based on some bits within the address of the interleaved data block.

[0095] For example, as shown in Figure 5, a 2MB page contains 512 4KB pages, with a cache line size of 64B, and a 4KB page contains 64 cache lines. A 2MB page contains 512*64 cache lines evenly distributed across 8 memory channels, with each memory channel allocated 512*512B of cache lines. Each memory channel contains 256KB of interleaved data blocks.

[0096] For example, if the page size is 4KB (X page size (=4KB) and if the data is interleaved into 8 memory channels based on the granularity of the cache lines (N channel(8) The size of the interleaved data blocks in each memory channel is 512B. The controller in each memory records the access frequency to the interleaved data blocks, which is 64GB / 512B=128MB. The capacity of the storage medium located within the controller in each memory and used to store the access frequency to the interleaved data blocks is 0.5GB. The physical address space of the storage medium that needs to be allocated by the computer device for the 8 memory channels is 4GB.

[0097] As another example, the page size is 2MB (X page size The memory capacity is 64GB (2MB), and the counter bit width is 4B. The address space allocated within each memory is 1MB, and 8MB of memory address space is allocated for the 8 memory channels.

[0098] In some embodiments, the controller may determine, based on a mapping relationship between the address of the interleaved data block and the address of the storage space for storing access frequencies, the address of the storage space accessed by the processor and used to store the access frequencies of the interleaved data block within the controller. Specifically, the controller stores any 8 bits of the address of the interleaved data block in bits 32-24 of the interleaved data block counter and increments the access frequency recorded in bits 23-0 by 1, which is the access frequency for accessing the interleaved data block. The remaining bits of the address of the interleaved data block are used as physical addresses accessed by the processor and used to store the access frequencies for accessing the interleaved data block in the storage medium.

[0099] For example, if a controller in memory records the frequency of accessing an interleaved data block of 64GB / 512B=128MB, the physical address space for the processor to access the storage medium is reduced to 0.5GB / 256=2MB, and the bit width of the counter that counts the access frequency is 4B. The minimum data granularity of the counter that counts the access frequency of accesses performed by the processor is 4B, and the 2MB physical address space can be further reduced to 2MB / 4B=512KB. A total of 4MB of physical address space needs to be reserved for the 8 memory channels, and therefore only 4MB of memory capacity is wasted.

[0100] The controller determines the physical address within the storage medium that stores the access frequency for accessing a page, based on the physical address indicated by the processor to access the storage medium. For example, for each memory, the processor periodically and continuously reads the access frequency stored in the controller within the memory for accessing interleaved data blocks. The controller detects the access to the corresponding 512KB address, where the physical address is designated as PA[18:0]. The controller implements an 8-bit address counter AddrCnt[7:0]. If the 512KB address is accessed continuously once, the counter AddrCnt[7:0] is incremented by 1, and the controller generates the physical address MAT_Addr={AddrCnt[7:0],PA[18:0]}. Based on the physical address MAT_Addr, the controller accesses the access frequency stored in the controller for accessing interleaved data blocks.

[0101] After reading 32 bits of data, the controller extracts the most significant 8 bits and then adds PA[18:0]. The total of 27 bits is the address (subpage) of the interleaved data block, and the least significant 24 bits of the corresponding data bits represent the access frequency to the corresponding interleaved data block. The processor obtains the 512B-based access frequencies for accessing the 8 memory channels and can combine these 512B-based access frequencies to obtain the access frequency for accessing a full 4KB page. For example, the access frequencies for accessing the 8 memory channels are added together, or the average, variance, maximum, and similar values ​​of the access frequencies for accessing the 8 memory channels are obtained.

[0102] In the embodiments described above, the processor 110 uses access requests as an example to illustrate a memory access popularity statistics method. When an application program executed by the processor 110 sends multiple access requests for operations on the memory of a computer device, statistics are collected regarding the data block where the physical address corresponding to each access request is located. For specific methods, please refer to the description in the embodiments described above.

[0103] In the embodiments described above, scenarios of connection relationships between a controller and near memory included in a computer device, and methods for stating the memory access popularity of the near memory, are explained with reference to the accompanying drawings. In the embodiments described above, memory 120 may represent near memory (which may also be referred to as near memory), and RCD 123 may refer to a controller that controls the near memory to collect statistics on memory access popularity.

[0104] In some other embodiments, the computer device may include far memory (which may also be referred to as fur memory), and the controller collects statistics on the frequency of access to the far memory. The difference from the connection relationship between near memory and the controller is that, compared to a memory controller within the processor, the controller that controls the far memory to collect statistics on memory access popularity may be an extension controller.

[0105] Optionally, the computer device includes far memory and near memory. The RCD in near memory collects statistics on the frequency of access to the near memory, and the extension controller connected to far memory collects statistics on the frequency of access to the far memory.

[0106] Access frequency thresholds are determined based on the application. Data accessed more frequently than the threshold is identified as hot data and stored in near memory, while data accessed less frequently is identified as cold data and stored in far memory. Assuming that the threshold setting does not affect application performance, it is found that a very small amount of memory access data is hot data, and most memory access data is cold data. Computer devices may be configured with a higher proportion of far memory to reduce system costs. Reducing the proportion of hot data reduces data migration between near and far memory, which can reduce system memory bandwidth usage and CPU overhead.

[0107] In possible implementations, the present invention further provides schematic diagrams of the structure of another computer device. Based on the fact that computer device 100 includes a processor 110 and memory 120, as shown in Figure 6, computer device 100 further includes memory 610. Memory 120 may be used as near memory, and memory 610 may be used as far memory. The processor 110 is connected to memory 610 by using bus 620.

[0108] The memory 610 includes an expansion controller 611, a memory device 612, and a storage medium 613. The memory device 612 includes DRAM and SCM. The storage medium 613 may be DRAM.

[0109] The expansion controller 611 is configured to perform read or write operations in the memory device 612 based on access requests from the processor 110, count the frequency of access to data blocks in the memory device 612, and store the frequency of access to data blocks in the storage medium 613. The expansion controller 611 may also be connected to an external storage medium 614 to expand the storage capacity of the storage medium 613 and store the frequency of access to data blocks.

[0110] The expansion controller 611 is further configured to obtain the access frequency for accessing data blocks from the storage medium 613.

[0111] For information on the functions of the expansion controller 611, how to count the access frequency of accessing data blocks in the memory device 612 within memory 610, and how to obtain the access frequency of accessing data blocks obtained from the storage medium 613, please refer to the relevant description of collecting statistics on the access frequency of the controller accessing near memory.

[0112] Memory 610 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Non-volatile memory may be ROM, PROM, EPROM, EEPROM, or flash memory. Volatile memory may be RAM. Many forms of RAM, e.g., SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, and DR RAM, may be used as illustrative rather than limiting descriptions.

[0113] Bus 620 may include channels configured to transmit data between the aforementioned components (e.g., processor 110 and memory 610). For example, processor 110 sends access requests to memory 610, and memory 610 feeds back to processor 110 the frequency of accessing data blocks. In addition to the data bus, bus 620 may further include power buses, control buses, status signal buses, and the like. For example, bus 620 is a DDR bus. However, for the sake of clarity, various types of buses are shown as bus 620 in the diagram. Bus 620 may be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or the like. Bus 620 can be classified as an address bus, data bus, control bus, and similar.

[0114] In this embodiment of the present application, the structures of near memory and far memory included in a computer device are described. For a method of collecting memory access popularity statistics for near memory and far memory, please refer to the above description of collecting statistics on memory access popularity for near memory. The RCD in near memory collects statistics on the frequency of access to near memory, and the extension controller connected to far memory collects statistics on the frequency of access to far memory, which consumes little CPU performance. In addition, the processor performs operations on memory using cache lines as the granularity, and such cache lines belong to managed pages. Therefore, once an operation is performed on a cache line in memory, the page to which that cache line belongs is read and written once. The controller collects statistics on the frequency of access to the page to which the cache line on which the operation was performed belongs. This effectively improves the accuracy of identifying the access popularity of pages. In addition, the controller collects statistics on the frequency of access to pages using pages as the granularity, which is compatible with the memory page management method performed by the computer device. The memory access popularity statistics method is easy to use. In addition, the access frequency threshold is determined based on the application. Data accessed more frequently than the threshold is identified as hot data and stored in near memory, while data accessed less frequently is identified as cold data and stored in far memory. Assuming that the threshold setting does not affect application performance, it is found that a very small amount of memory access data is hot data, and most memory access data is cold data. Computer devices may be configured with a higher proportion of far memory to reduce system costs. Reducing the proportion of hot data reduces data migration between near and far memory, which can reduce system memory bandwidth usage and CPU overhead.

[0115] To implement the functions in the embodiments described above, the controller includes corresponding hardware structures and / or software modules for performing the functions. Those skilled in the art will readily recognize, in combination with the units and method steps described in the examples of embodiments disclosed herein, that the present application can be implemented using hardware, or a combination of hardware and computer software. Whether a particular function is performed using hardware, or hardware driven by computer software, depends on the specific application scenario and the design constraints of the technical solution.

[0116] Referring to Figures 1 to 6, the memory access popularity statistics method according to the present invention has been described in detail above. Referring to Figure 7, the memory access popularity statistics device according to the present invention will be described below.

[0117] Figure 7 is a schematic diagram of the structure of a possible memory access popularity statistical device according to the present invention. These memory access popularity statistical devices may be configured to implement the functions of the controller in the embodiments of the method described above, and therefore may also implement the beneficial effects of the embodiments of the method described above. In this embodiment, the memory access popularity statistical device may be the controller shown in Figure 2, or it may be a module (such as a chip) applied to a computer device.

[0118] As shown in Figure 7, the memory access popularity statistical device 700 includes a communication module 710, a statistics module 720, and a storage module 730. The memory access popularity statistical device 700 is configured to implement the functions of the controller in the embodiment of the method shown in Figure 2.

[0119] The communication module 710 is configured to determine a first address based on an acquired access request, where the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in memory.

[0120] The statistics module 720 is configured to collect statistics on the access frequency of accessing the data block located at the first address, where the size of the data block is a multiple of the unit storage space in memory accessible to the processor. For example, the statistics module 720 is configured to perform steps 210 to 250 in Figure 2.

[0121] The statistics module 720 is specifically configured to collect statistics on the frequency of access to the data block located in the unit memory space to which the first address belongs.

[0122] The memory module 730 is configured to store access frequency, and as a result, the statistics module 720 determines the access popularity of a data block based on that access frequency and triggers data migration.

[0123] The memory access popularity statistic device 700 in this embodiment of the present application may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a DPU, a SoC, or any combination thereof. If the memory access popularity statistic method shown in Figure 2 can also be implemented using software, then the module of the method may also be a software module, and the memory access popularity statistic device 700 and the module of the device 700 may also be software modules.

[0124] The memory access popularity statistic device 700 according to this embodiment of the present application can accordingly perform the method described in the embodiments of the present application, and the above-described operations and other operations and / or functions of the units within the memory access popularity statistic device 700 are used, respectively, to implement the corresponding steps of the method in Figure 2. For the sake of brevity, further details are not described herein.

[0125] Figure 8 is a schematic diagram of the structure of the controller 800 according to the present invention. As shown in the figure, the controller 800 includes a processing unit 810, a bus 820, a storage unit 830, and a communication interface 840. The processing unit 810, the storage unit 830, and the communication interface 840 are connected by using the bus 820.

[0126] In this embodiment, the processing unit 810 may be a CPU, or it may be another general-purpose processor, digital signal processing (DSP), ASIC, FPGA, or another programmable logic device, discrete gate, or transistor logic device, discrete hardware component, or the like. The general-purpose processor may be a microprocessor, or any conventional processor, or the like.

[0127] The communication interface 840 is configured to implement communication between the controller 800 and an external device or component. In this embodiment, if the controller 800 is configured to implement the controller functions shown in Figure 2, the communication interface 840 is configured to receive access requests.

[0128] Bus 820 may include channels configured to transmit information between the aforementioned components (e.g., processing unit 810 and storage unit 830). In addition to the data bus, bus 820 may further include a power bus, control bus, status signal bus, and similar. However, for clarity, various types of buses are shown as bus 820 in the diagram. Bus 820 may be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or similar. Bus 820 may be classified as an address bus, data bus, control bus, and similar.

[0129] In one example, the controller 800 may include multiple processors. The processors may be multi-core (multi-CPU) processors. The processors as used herein may be one or more devices, circuits, and / or processing units configured to process data (e.g., computer program instructions). In this embodiment, if the controller 800 is configured to implement the controller functions shown in Figure 2, the processing unit 810 collects statistics on the access frequency to the data block where the first address is located.

[0130] A method for optionally collecting statistics on the frequency of access to data blocks may also be incorporated into the processing unit 810, and as a result, the processing unit 810 collects statistics on the frequency of access to data blocks.

[0131] In Figure 8, only one example is used in which the controller 800 includes one processing unit 810 and one storage unit 830. In this specification, the processing unit 810 and the storage unit 830 are configured separately to indicate the type of component or device. In a particular embodiment, the quantity of each type of component or device may be determined based on service requirements.

[0132] The storage unit 830 may correspond to embodiments of the method described above and is configured to store information such as access frequency. The storage unit 830 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM) used as an external cache. As an illustrative rather than restrictive description, many forms of RAM may be used, such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus random access memory (direct rambus RAM, DR RAM).

[0133] The storage unit 830 may further correspond to a storage medium configured to store information such as computer instructions in the embodiments of the above-described method, for example, a mechanical hard disk drive or a magnetic disk such as a solid-state disk.

[0134] The controller 800 may be a general-purpose device or a dedicated device. For example, the controller 800 may be a server with computing power or another device.

[0135] The controller 800 in this embodiment may correspond to the memory access popularity statistic device 700 in this embodiment, and may correspond to a corresponding entity that performs any of the methods shown in Figure 2. In addition, the above-described operations and other operations and / or functions of the modules within the memory access popularity statistic device 700 are used, respectively, to implement the corresponding steps of the method in Figure 2. For the sake of brevity, further details are not described herein.

[0136] In this embodiment of the present application, the controller 800 may be an RCD controller in the memory of a computer device. Alternatively, the controller 800 may be an extension controller connected to the memory of a computer device.

[0137] One embodiment of the present invention further provides a chip comprising a processor and a power supply circuit, wherein the power supply circuit is configured to supply power to the processor, and the processor is configured to perform the memory access popularity statistics method of the above-described embodiment.

[0138] One embodiment of the present invention further provides a memory comprising a storage device and a controller. The storage device is configured to store a set of computer instructions. When the controller executes the set of computer instructions, the memory access popularity statistics method of the above-described embodiment is performed.

[0139] One embodiment of the present invention further provides a mainboard, the mainboard comprising a controller which performs the memory access popularity statistics method of the above-described embodiment.

[0140] The method steps in this embodiment may be implemented in hardware, or by a processor executing software instructions. Software instructions may include corresponding software modules. Software modules may be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk drives, removable hard disk drives, CD-ROMs, or any other form of storage medium known in the art. For example, the storage medium may be coupled to a processor, thereby enabling the processor to read information from and write information to the storage medium. It is clear that the storage medium may be a component of the processor. The processor and storage medium may be located in an ASIC. In addition, the ASIC may be located within a computing device. It is also clear that the processor and storage medium may alternatively exist within a computing device as discrete components.

[0141] All or some of the embodiments described above may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or some of the embodiments may be implemented in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When a computer program or instruction is loaded onto a computer and executed, all or part of the procedures or functions in the embodiments of the Application are executed. The computer may be a general-purpose computer, a dedicated computer, a computer network, a network device, user equipment, or another programmable device. The computer program or instruction may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program or instruction may be transmitted by wire or wirelessly from one website, computer, server, or data center to another website, computer, server, or data center. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The usable media may be magnetic media, such as floppy disks, hard disk drives, or magnetic tapes; optical media, such as digital video discs (DVDs); or semiconductor media, such as solid-state drives (SSDs).

[0142] The above description represents only specific embodiments of the Application and is not intended to limit the scope of protection. Any modifications or substitutions that a person skilled in the art can easily conceive within the scope of the technical scope disclosed herein shall fall within the scope of protection. Accordingly, the scope of protection of this Application shall be subject to the scope of protection of the claims. 。 [Item 1] A memory access popularity statistics method, executed by the controller: The step of determining a first address based on an acquired access request, where the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; A step of collecting statistics on the frequency of access to the data block where the first address is located, wherein the size of the data block is a multiple of the unit storage space in the memory accessible to the processor; and A step in determining the access popularity of the data block based on the aforementioned access frequency. A method for statistically determining the popularity of memory accesses. [Item 2] The step of collecting statistics on the frequency of access to the data block where the first address is located is: Steps to collect statistics on the frequency of access to the data block in which the unit storage space to which the first address belongs is located. The method described in item 1, having the characteristics of item 1. [Item 3] The aforementioned method is: A step of identifying a second address based on the address of the data block where the first address is located and the address mapping relationship, where the second address indicates the location in the controller where the access frequency for accessing the data block is stored, and the address mapping relationship indicates the mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored. The method described in item 2, further comprising the above. [Item 4] The aforementioned method is: A step of identifying the second address and obtaining the access frequency for accessing the data block based on the third address and the address mapping relationship indicated by the processor, wherein the third address is determined based on the second address. The method described in item 3, further comprising the above. [Item 5] The method according to any one of items 1 to 4, wherein the size of the data block is the size of one page in the memory accessible to the processor. [Item 6] The method according to any one of items 1 to 4, wherein the size of the data block is the size of an interleaved data block in the memory that is interleavedly accessible to the processor, and the interleaving method means that the processor in the computer device distributes the data of the operation performed by the running application program to the memory of the computer device across multiple memories for the operation. [Item 7] The method according to any one of items 1 to 6, wherein the size of the unit memory space is the size of the cache line when the processor accesses the memory. [Item 8] A communication module configured to determine a first address based on an acquired access request, wherein the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; and A statistics module configured to collect statistics on the frequency of access to the data block where the first address is located, wherein the size of the data block is a multiple of the unit storage space in the memory accessible to the processor. Equipped with, The statistics module is further configured to determine the access popularity of the data block based on the access frequency. Memory access popularity statistics device. [Item 9] When collecting statistics on the frequency of access to the data block where the first address is located, the statistics module: The apparatus according to item 8, which is particularly configured to collect statistics on the frequency of access to the data block in which the unit storage space to which the first address belongs is located. [Item 10] The aforementioned statistics module is: Based on the address of the data block where the first address is located and the address mapping relationship, a second address is identified, where the second address indicates the location within the controller where the access frequency for accessing the data block is stored, and the address mapping relationship indicates the mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored. The apparatus described in item 9, further configured as follows. [Item 11] The aforementioned statistics module is: Based on the third address and the address mapping relationship indicated by the processor, the second address is identified and the access frequency for accessing the data block is obtained, where the third address is determined based on the second address. The apparatus described in item 10, further configured as follows. [Item 12] The apparatus according to any one of items 8 to 11, wherein the size of the data block is the size of one page in the memory accessible to the processor. [Item 13] The apparatus according to any one of items 8 to 11, wherein the size of the data block is the size of an interleaved data block in the memory accessible to the processor in an interleaved manner, and the interleaved manner means that the processor in the computer device distributes the data of an operation performed by the running application program to the memory of the computer device into multiple memories for the operation. [Item 14] The apparatus according to any one of items 8 to 13, wherein the size of the unit memory space is the size of the cache line when the processor accesses the memory. [Item 15] A controller comprising a storage unit and a processing unit, wherein the storage unit is configured to store a group of computer instructions, and when executing the group of computer instructions, the processing unit performs the operational steps described in any one of items 1 to 7 and identifies the access frequency to which an application program accesses a data block in memory. [Item 16] The controller is the controller described in item 15, which is a register clock driver RCD in the memory of the computer device. [Item 17] The controller is an extension controller in the memory of the computer device, as described in item 15. [Item 18] A chip comprising a processor and a power supply circuit, wherein the power supply circuit is configured to supply power to the processor, and the processor is configured to perform the operational steps described in any one of items 1 to 7. [Item 19] A memory comprising a storage device and a controller as described in any one of items 15 to 17, wherein the storage device is configured to store a set of computer instructions, and when the set of computer instructions is executed, the controller performs the operational steps as described in any one of items 1 to 7, and identifies the frequency of access by an application program to access a data block in the memory. [Item 20] A mainboard comprising a controller as described in any one of items 15 to 17, wherein the controller performs the operational steps of the method described in any one of items 1 to 7 and identifies the access frequency of an application program accessing a data block in memory. [Item 21] A computer device equipped with the mainboard described in item 20.

Claims

1. A memory access popularity statistics method, executed by the controller: The step of determining a first address based on the acquired access request, where the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; A step in which a second address is identified based on the address of the data block where the first address is located and the address mapping relationship, wherein the second address indicates the location in the controller where the access frequency for accessing the data block is stored, and the address mapping relationship indicates the mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored: A step of collecting statistics on the frequency of access to the data block in which the first address is located, wherein the size of the data block is a multiple of the unit storage space in the memory accessible to the processor; and A step in determining the access popularity of the data block based on the aforementioned access frequency. A method for statistically determining the popularity of memory accesses.

2. The step of collecting statistics on the frequency of access to the data block where the first address is located is: Steps to collect statistics on the frequency of access to the data block in which the unit storage space to which the first address belongs is located. A method for statistically determining the popularity of memory accesses according to claim 1, comprising:

3. The aforementioned memory access popularity statistics method is: A step of identifying the second address and obtaining the access frequency for accessing the data block based on the third address and the address mapping relationship indicated by the processor, wherein the third address is determined based on the second address. The memory access popularity statistics method according to claim 1, further comprising the following:

4. The memory access popularity statistics method according to any one of claims 1 to 3, wherein the size of the data block is the size of one page in the memory accessible to the processor.

5. The memory access popularity statistics method according to any one of claims 1 to 3, wherein the size of the data block is the size of an interleaved data block in the memory that is interleavedly accessible to the processor, and the interleaving method means that the processor in the computer device distributes the data of the operation performed by the running application program to the memory of the computer device across multiple memories for the operation.

6. The memory access popularity statistics method according to any one of claims 1 to 3, wherein the size of the unit memory space is the size of the cache line when the processor accesses the memory.

7. A memory comprising a storage device and a controller, wherein the storage device is configured to store a group of computer instructions, and when executing the group of computer instructions, the controller puts the following into the memory: Based on the acquired access request, a first address is determined, where the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; Based on the address of the data block where the first address is located and the address mapping relationship, a second address is identified, where the second address indicates the location within the controller where the access frequency for accessing the data block is stored, and the address mapping relationship indicates the mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored; Statistics relating to the frequency of access to the data block where the first address is located are collected, where the size of the data block is a multiple of the unit storage space in the memory accessible to the processor; and Based on the aforementioned access frequency, the access popularity of the aforementioned data block is determined. Memory configured in such a way.

8. The procedure for collecting statistics on the frequency of access to the data block where the first address is located is: A procedure for collecting statistics on the frequency of access to the data block in which the unit storage space to which the first address belongs is located. The memory according to claim 7, having the following features.

9. When executing the aforementioned group of computer instructions, the controller puts the following into memory: Based on the third address and the address mapping relationship indicated by the processor, the second address is identified and the access frequency for accessing the data block is obtained, where the third address is determined based on the second address. The memory according to claim 7, further configured as follows.

10. The memory according to claim 7, wherein the size of the data block is the size of one page in the memory accessible to the processor.

11. The memory according to any one of claims 7 to 10, wherein the size of the data block is the size of an interleaved data block in the memory that is interleavedly accessible to the processor, and the interleaving method means that the processor in the computer device distributes the data of the operation performed by the running application program to the memory of the computer device across multiple memories for the operation.

12. The memory according to any one of claims 7 to 10, wherein the size of the unit storage space is the size of the cache line when the processor accesses the memory.

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