Methods and systems and memory devices for low-power dual data transfer rate (LPDDR) compatible high-bandwidth NAND (HBN).

Abstract

The present invention provides a method and system for LPDDR-compatible high-bandwidth NAND, as well as a memory device. [Solution] The present invention provides a method for a memory device, comprising the steps of: receiving a request from an application relating to the memory device, wherein the request has a request type, and issuing a first command to the memory device via a memory controller, wherein the first command is based on the request type, and polling the memory device for the state of the memory device, wherein the state is related to whether the memory device is ready for the request, and determining, based on the state, that the memory device is ready; and issuing a second command to the memory device via a memory controller to execute the request.

Description

Technical Field

[0001] The present invention relates to a computing system, and more particularly, to a method and system for high-bandwidth flash with low-power double data rate (LPDDR) compatibility, and a memory device.

Background Art

[0002] Some computing devices, such as mobile devices, can utilize low-power double data rate (LPDDR) SDRAM and are equipped with an LPDDR memory controller.

[0003] High-bandwidth flash (HBF) NAND memory devices can provide a higher throughput, but may not be compatible with an LPDDR memory controller.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above conventional memory devices, and an object of the present invention is to provide a method and system for high-bandwidth NAND with LPDDR compatibility, and a memory device.

Means for Solving the Problems

[0005] A method according to the present invention made to achieve the above objective is a method for a memory device, comprising the steps of: receiving a request from an application relating to the memory device, wherein the request has a request type, and issuing a first command to the memory device via a memory controller, wherein the first command is based on the request type, and polling the memory device for the state of the memory device, wherein the state is related to the readiness of the memory device for the request, and determining, based on the state, that the memory device is ready; and issuing a second command to the memory device via the memory controller to execute the request.

[0006] The memory controller preferably includes a low-power double data rate (LPDDR) memory controller. Preferably, the memory device includes a high-bandwidth flash NAND memory and a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from the LPDDR memory controller. The aforementioned request type is preferably a write request. The state of the Mori device is preferably based on the availability of space within the buffer of the memory device. Preferably, the process further includes a step of reserving a predetermined space within the buffer for the application. The request type is preferably a read request. The state of the memory device is preferably based on the availability of data related to the request in the buffer of the memory device.

[0007] To achieve the above objective, the present invention provides a host comprising a memory controller, a processing circuit including a processor, and a memory connected to the processing circuit, wherein the memory stores executable instruction words by the processing circuit, and when the instruction words are executed by the processing circuit, the processing circuit receives a request from an application relating to the memory, wherein the request has a request type, issues a first command to the memory via the memory controller, wherein the first command is based on the request type, polls the memory for its state, wherein the state is related to the readiness of the memory for the request, determines that the memory is ready based on the state, and issues a second command to the memory via the memory controller to execute the request.

[0008] The memory controller preferably includes a low-power double data rate (LPDDR) memory controller. Preferably, the memory includes a high-bandwidth flash NAND memory and a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from the LPDDR memory controller. The aforementioned request type is preferably related to a write request. The state of the memory is preferably based on the availability of space within the buffer of the memory device. The processing circuit may further preferably reserve a predetermined space within the buffer for the application. The request type is preferably a read request. The state of the memory is preferably based on the availability of data related to the request in the memory's buffer.

[0009] To achieve the above objective, the present invention provides a memory device comprising: high-bandwidth NAND (HBN); and a front-end controller configured to control access to the HBN, wherein the front-end controller includes a buffer; a processing circuit including a processor; and a memory connected to the processing circuit, wherein the memory stores an instruction word executable by the processing circuit, and when the instruction word is executed by the processing circuit, the processing circuit receives a first command from the memory controller of the host device, determines that the state of the buffer satisfies the conditions related to the first command, transfers the state of the buffer to the memory controller, receives a second command from the memory controller, and performs an operation on the buffer based on the second command.

[0010] The second command is preferably a read request for data stored in the HBN, and the condition preferably includes that the data is in the buffer. The second command is a write request for data stored in the HBN, and the condition preferably includes that the buffer has sufficient available space for the data. The processing circuit preferably further reserves a predetermined space within the buffer for the data. [Effects of the Invention]

[0011] The present invention provides a method, system, and memory device that includes a front-end controller for facilitating interaction between an LPDDR memory controller and an HBN, wherein the front-end controller preloads data from the HBN into a buffer for read operations and allocates space on the buffer for write operations, thereby providing a method, system, and memory device with improved compatibility between the LPDDR memory controller and the HBN. [Brief explanation of the drawing]

[0012] [Figure 1] This block diagram shows a schematic configuration of a system according to an embodiment of the present invention. [Figure 2] This is a block diagram illustrating the schematic configuration of a system having an LPDDR-compatible HBN according to an embodiment of the present invention. [Figure 3] This figure illustrates the timing of a read operation performed by a system having an LPDDR-compatible HBF according to an embodiment of the present invention. [Figure 4] This figure illustrates the timing of a write operation performed by a system having an LPDDR-compatible HBF according to an embodiment of the present invention. [Figure 5] This is a flowchart illustrating a process of interacting with a memory device via a host memory controller according to an embodiment of the present invention. [Figure 6] This is a flowchart illustrating the process of executing a read request on a memory device via a host memory controller according to an embodiment of the present invention. [Figure 7] This is a flowchart illustrating the process of executing a write request on a memory device via a host memory controller according to an embodiment of the present invention. [Figure 8A] This is a flowchart illustrating the process by which a memory device executes a request received from a host memory controller according to an embodiment of the present invention. [Figure 8B] A flowchart for explaining a process of executing a request received from a host memory controller by a memory device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0013] Next, specific examples of embodiments for implementing the method, system, and memory device according to the present invention will be described with reference to the drawings.

[0014] The detailed description disclosed below in relation to the accompanying drawings is intended as an explanation of embodiments as examples of systems and methods for high-bandwidth NAND with LPDDR-compatibility provided in accordance with this description, and is not intended to show the only form in which this description can be configured or utilized. The description discloses the features of this description in relation to the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures can be achieved by different embodiments as intended to be included within the scope of this description. As shown elsewhere in this specification, the same reference numbers are intended to indicate the same elements or features.

[0015] As used in this specification, "a portion of" something means "at least some of" it, and thus can mean less than all of it, or all of it. Thus, "a portion of" something includes all of it as a special case, i.e., all of it is an example of a portion of it. As used in this specification, when a second quantity is "within Y" of a first quantity X, this means that the second quantity is at least (X - Y) and at most (X + Y). As used herein, when a second quantity is "within Y%" of a first quantity, this means that the second quantity is (1-Y / 100) times the smallest first quantity and (1+Y / 100) times the largest first quantity. As used herein, the term "or" should be interpreted as "and / or," and therefore, for example, "A or B" means any one of "A," "B," or "A and B."

[0016] The background art provided in the technical section that forms the background of the invention described herein is included solely to establish context, and the context of this section is not considered prior art. Any component or any combination of components described (for example, in any system drawing included herein) may be used to perform one or more operations of any flowchart included herein. moreover, (i) The actions described are illustrative and may include a variety of additional steps not explicitly covered. (ii) The temporal order of the actions can vary.

[0017] The terms “processing circuit” and “processing means” are used herein to mean any combination of hardware, firmware, and software used to process data or digital signals. Processing circuit hardware may include, for example, programmable logic devices such as application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and field-programmable gate arrays (FPGAs). Within the processing circuit, as used herein, each function is executed by one of the more general-purpose hardware components, such as a CPU, configured to perform that function, i.e., by hard-wired hardware, or by executing instructions stored in a non-temporary storage medium. The processing circuit may be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. The processing circuit may include other processing circuits; for example, the processing circuit may include two processing circuits, an FPGA and a CPU, interconnected on the PCB.

[0018] As used herein, when a method (e.g., adjustment) or a first quantity (e.g., first variable) is referred to as “based” on a second quantity (e.g., second variable), this means that the second quantity is an input to the method or influences the first quantity. Therefore, for example, the second quantity may be an input to the function that computes the first quantity (e.g., a single input or one of several inputs), the first quantity may be identical to the second quantity, or the first quantity may be together with the second quantity (e.g., stored at the same location in memory, or at the same location).

[0019] Although terms such as the first, second, third, etc., may be used to describe a variety of elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited to these terms. These terms may simply be used to distinguish one element, component, region, layer, or section from other elements, components, regions, layers, or sections. Therefore, the first elements, components, regions, layers, or sections described herein may be referred to as second elements, components, regions, layers, or sections, provided that they do not deviate from the technical idea and scope of the inventive concept.

[0020] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit any progressive viewpoint. As used herein, the terms “substantially,” “about,” and similar terms may be used as terms of approximation, not as terms of degree, and may be intended to take into account inherent deviations within estimated or calculated values ​​recognized by a person of the ordinary skill in the art of the present invention.

[0021] As used herein, the singular forms "a" and "an" include the plural form unless the context clearly indicates a different meaning. When used in the detailed description of the present invention, the terms “comprises” and / or “comprising” may identify the presence of the features, integers, steps, operations, elements, and / or components mentioned, but they do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Expressions like "at least one of" modify the entire list of elements, but not the individual elements of the list, when they precede a list of elements. Furthermore, the use of "may" refers to "one or more embodiments described herein" when describing embodiments from an inventive perspective. The term "example" is intended to refer to an illustration or diagram. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0022] When an element or layer is said to be "on," "connected to," "coupled to," or "adjacent to" another element or layer, this may mean that it is directly on, connected to, coupled to, or adjacent to the other element or layer, or that one or more intervening elements or layers exist. That's good too. Conversely, if an element or layer is described as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, then there is no intermediate element or layer.

[0023] High-bandwidth NAND (HBN) is a type of NAND flash memory with a wide input / output (I / O: iNPUt / output) interface, providing more data channels (e.g., I / O lines) for faster communication with the memory controller and higher throughput. This high bandwidth and throughput improve the performance of mobile devices for high-throughput applications such as large language model (LLM) applications and other artificial intelligence (AI) or machine learning (ML) applications. However, some mobile platforms utilize low-power double data rate (LPDDR) SDRAM interfaces for high-throughput applications, which are generally incompatible with HBN. For example, an LPDDR memory controller operates based on read and write latency that is shorter than the read and write latency of HBN. Therefore, there is a problem in that when the LPDDR memory controller reads data directly from the HBN or writes data directly to the HBN, there is a timing issue that can cause system problems.

[0024] This invention provides a technology for making memory devices utilizing HBFNAND (high bandwidth flash NAND) memory compatible with existing LPDDR memory controllers. The memory device includes a front-end controller that facilitates interactions between the LPDDR memory controller and the HBN. In one embodiment, with respect to read operations, the front-end controller preloads data from the HBN into a buffer, thereby enabling the LPDDR memory controller to load data from the buffer instead of the HBN. This reduces the read latency experienced by the LPDDR memory controller to an acceptable predetermined time. Similarly, with respect to write operations, the front-end controller allocates space on the buffer, allowing the front-end controller to write data to the buffer instead of the HBN. Therefore, the write latency experienced by LPDDR is the time it takes to write the data to the buffer, which may be shorter than the latency of writing the data to the HBN. The present invention allows for the use of HBN in a mobile device having an LPDDR controller without modifying the device's application processor memory controller.

[0025] Figure 1 is a block diagram showing a schematic configuration of system 100 according to an embodiment of the present invention. System 100 includes a host computing device (or host) 102 and a memory device 104. In one embodiment, the host 102 and the memory device 104 communicate via a data communication link or general-purpose interface, such as an LPDDR interface, Ethernet (registered trademark), Universal Serial Bus (USB), and / or any wired or wireless data communication link.

[0026] The host 102 includes a processor 108, an application 106, and a memory controller 110. The processor 108 includes one or more central processing unit (CPU) cores configured to execute one or more applications 106 based on computer program instructions stored in system memory, other locations in the host 102, in memory device 104, other locations in the system 100, or obtained via one or more communication links.

[0027] The processor 108 is a processing circuit or is included in a processing circuit and includes a digital circuit (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or such)) that can execute data access instructions (e.g., via firmware and / or software) to provide access to or access from data stored in memory according to data access instructions.

[0028] Application 106 is any application configured to send requests (e.g., write requests, read requests) to the memory controller 110 to access the memory device 104. For example, application 106 could be a big data analytics application, a large-scale language modeling application, an e-commerce application, a database application, an artificial intelligence application, a machine learning application, and / or such.

[0029] The memory controller 110 is configured to facilitate interaction between the processor 108 and memory such as the memory device 104. For example, the memory controller 110 executes a read or write (or load and store) command to the memory device 104. In one embodiment, the memory controller 110 is an LPDDR memory controller configured to interface with an LPDDR SDRAM. In one embodiment, the memory controller 110 includes a plurality of memory devices 104 and accesses a plurality of memory devices. Multiple memory devices may each have their own rank. For example, memory device 104 is a rank 1 memory device and is activated by chip select for rank 1.

[0030] The memory device 104 includes a memory 116 and a front-end controller 114. The front-end controller 114 is connected to the memory 116 via one or more storage interfaces such as Serial Advanced Technology Attachment (SATA), Non-Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Serial Attached SCSI (SAS), M.2 form factor, and Direct Memory Access (DMA). The front-end controller 114 receives requests from the memory controller 110 and facilitates interaction between the memory controller 110 and the memory 116. In one embodiment, such as when the memory controller 110 is an LPDDR memory controller, the memory 116 exhibits a higher latency than that of an LPDDR memory controller. In such cases, the front-end interface controls the sides of the memory device 104 to ensure that the LPDDR memory controller experiences the expected latency for read and write operations.

[0031] In one embodiment, the host 102 includes one or more kernels. In one embodiment, the device driver is installed within the kernel. The device driver enables the memory controller 110 to interact with the front-end controller 114 of the memory device 104 (for example, to execute read / write requests). In one embodiment, application 106 includes or utilizes libraries and / or application programming interfaces (APIs) that facilitate requests made for the device driver and memory device 104.

[0032] In one or more embodiments, some connections between the various components shown in Figure 1 transmit and receive data using a protocol such as Compute Express Link (CXL), but the embodiments are not limited to this. In addition to CXL, or instead of CXL, a variety of interfaces can be used for accelerators, including Cache Coherent Interconnect (CCIX), Dual Inline Memory Module (DIMM) interface, Small Computer System Interface (SCSI), Non-Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Remote Direct Memory Access (RDMA) over Ethernet (Ethernet®), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), NVMe Overfabric (NVMe-oF), iWARP protocol, InfiniBand protocol, 5G wireless protocol, Wi-Fi protocol, Bluetooth® protocol, and / or other such protocols.

[0033] Figure 2 is a block diagram showing a schematic configuration of a system 200 having an LPDDR-compatible HBN according to an embodiment of the present invention. System 200 is one embodiment of System 100. System 200 includes a host 202 and a memory device 204. The host 202 includes one or more processors 206 such as a central processing unit (CPU), a graphics processing unit (GPU), and / or a neural processing unit (NPU). The host 202 also includes a memory allocator 208, a device driver 210, a kernel 212, an application processor 214, and an LPDDR memory controller 216. The memory device 204 includes a high-bandwidth NAND (HBN) 228 and a front-end controller 218 configured to facilitate interaction between the LPDDR memory controller and the HBN 228.

[0034] In one embodiment, application 230 forwards a read request or write request to application processor 214, triggering kernel 212 to issue various commands to execute the request from application 230. In one embodiment, the device driver 210 causes the kernel 212 to forward a command to the LPDDR memory controller 216, and then to the memory device 204 via the LPDDR memory controller 216, in order to execute a request from the application 230. In one embodiment, the device driver 210 includes mapping addresses in the HBN228 to virtual addresses utilized by the kernel 212 and / or application 230. In one embodiment, the device driver 210 includes a mapping of reserved addresses in the HBN228 to the corresponding handshake commands.

[0035] The LPDDR memory controller 216 receives commands from the kernel 212 to issue various commands to the memory device 204 using LPDDR commands. In one embodiment, the LPDDR memory controller 216 issues access commands (e.g., read and write) or handshake commands (e.g., fetch, allocate, poll data, poll buffer).

[0036] In one embodiment, a fetch command is a handshake operation performed between the memory device 204 and the host 202 prior to a read command issued by the host 202, so that the memory device 204 preloads the requested data from the HBN228 into the buffer 222, allowing the LPDDR memory controller 216 to load the data from the buffer 222 instead of directly loading the data from the HBN228. Loading data directly from the HBN228 results in longer latency than it would with the LPDDR memory controller 216. Loading data from buffer 222 results in shorter latency than is possible with the LPDDR memory controller 216. In one embodiment, buffer 222 is a stagger buffer, in which data is configured or can be accessed in a non-sequential way. For example, different parts of a staggered buffer may be accessed at different times, or data may be written to and read from the buffer at staggered intervals.

[0037] In one embodiment, the allocate command is a handshake operation performed between the memory device 204 and the host 202 prior to a write command issued by the host 202, which allows the memory device 204 to allocate space on the buffer 222 and enables the LPDDR memory controller 216 to write data to the buffer 222 instead of writing it directly to the HBN 228. Writing data directly to the HBN228 results in longer latency than would be possible with the LPDDR memory controller 216. Writing data to buffer 222 generates a shorter latency than is compatible with the LPDDR memory controller 216.

[0038] In one embodiment, a pole data command is a handshake operation performed between the memory device 204 and the host 202 prior to a read command issued by the host 202, so that the host 202 can know whether the requested data is in the buffer 222 and therefore ready for reading by the LPDDR memory controller 216. In one embodiment, the pole buffer command is a handshake operation performed between the memory device 204 and the host 202 before a write command is issued by the host 202, so that the host 202 can know whether there is available space on the buffer 222 and whether the LPDDR memory controller 216 can write data directly to the buffer 222.

[0039] The LPDDR command converter 220 receives commands from the LPDDR memory controller 216 and triggers processes within the front-end controller 218 based on the received commands. In one embodiment, the received command includes data parameters that include the address of the HBN228. In one embodiment, the address is a reserved address representing the type of handshake command to be executed.

[0040] Buffer 222 provides an intermediate storage device that is directly accessed by the LPDDR memory controller 216 for read or write commands, allowing the LPDDR memory controller 216 to experience lower latency and thus function as expected. The buffer manager 224 accesses buffer 222 or manages the metadata of buffer 222 in order to check whether the requested data is available in buffer 222 in response to a pole data command, or in order to check whether space is available in buffer 222 in response to a pole buffer command. The HBN manager 226 writes data from buffer 222 to HBN228, or loads data from HBN228 to buffer 222.

[0041] In one embodiment, the LPDDR memory controller 216 includes a memory device 204 and accesses multiple memory devices. Multiple memory devices have their own ranks, and the LPDDR memory controller 216 selects from among them through chip selection. For example, the memory device 204 may be a rank 1 memory device.

[0042] Figure 3 is a diagram illustrating a timing graph 300 of a read operation performed by a system 200 having an LPDDR-compatible HBN according to an embodiment of the present invention. System 200 has components of a host 202, including an application 230, a kernel 212 on which a device driver 210 is installed, and an LPDDR memory controller 216. The system 200 has components of a memory device 204, including a front-end controller 218 and an HBN 228.

[0043] Application 230 sends a read request 302 to kernel 212, triggering kernel 212 to issue a fetch command 304 to the front-end controller 218 of memory device 204. In one embodiment, a fetch command is generated to the front-end controller 218 via the LPDDR memory controller 216. In one embodiment, a fetch command is issued to the front-end controller 218 as a command associated with a reserved address of the HBN228 specific to the fetch command. In one embodiment, the fetch command includes data indicating the address of the data to be fetched. In one embodiment, a fetch command is a handshake operation performed between the memory device 204 and the host 202 prior to a read command issued by the host 202, so that the memory device 204 preloads the requested data from the HBN228 into a buffer, allowing the LPDDR memory controller 216 to load the data from the buffer instead of directly from the HBN2208. Loading data directly from the HBN228 results in longer latency than if it were compatible with the LPDDR memory controller 216. Loading data from a buffer results in shorter latency than is possible with the LPDDR memory controller 216.

[0044] Upon receiving a fetch command, the front-end controller 218 checks whether the relevant data is in its buffer. If the data is not already in the buffer, the front-end controller 218 issues a read command 306 to the HBN228 to load the data into the buffer. When a read command 306 is issued, the front-end controller 218 returns a confirmation 308 to the kernel 212. In one embodiment, the front-end controller 218 also returns an estimated data ready time along with a confirmation 308 if the data is not ready in the buffer. The estimated data preparation time represents the estimated time it takes for the requested data to be in the buffer and ready for direct reading by the LPDDR memory controller 216. Data 312 is loaded from HBN228 into the buffer after the HBN228's read latency or read time 320.

[0045] The kernel 212 issues a pole data command 310 to the front-end controller 218 to check whether the data is in the buffer and therefore ready to be read by the LPDDR memory controller 216. The front-end controller 218 returns a data state 314 to the kernel 212, indicating whether the data is ready or not. For example, if the data is not ready (332), kernel 212 will later issue another pole data command 310 to check again until the data is ready. If the data is ready (334), the kernel 212 issues a load command 316 to the LPDDR memory controller 216, and the LPDDR memory controller 216 issues a load command 318 to the front-end controller 218. During the read time 326 experienced by the LPDDR memory controller 216, the data is loaded from the buffer in response 322 and returned to the LPDDR memory controller 216. Next, in response 324, the data is returned from the LPDDR memory controller 216 to the kernel 212, and then in response 330, it is returned to the application.

[0046] Figure 4 is a diagram illustrating a timing graph 400 of a write operation performed by a system 200 having an LPDDR-compatible HBN according to an embodiment of the present invention. The operational system components are the same as those described in Figure 3.

[0047] Application 230 sends a write request 402 to kernel 212, triggering kernel 212 to issue an allocation command 404 to the front-end controller 218 of memory device 204. In one embodiment, the allocation command 404 is issued to the front-end controller 218 via the LPDDR memory controller 216. In one embodiment, the assignment command 404 is issued to the front-end controller 218 as a command associated with a reserved address of the HBN228 specific to the assignment command. In one embodiment, the allocation command 404 is a handshake operation performed between the memory device 204 and the host 202 prior to a write command issued by the host 202, which enables the memory device 204 to allocate space in a buffer and the LPDDR memory controller 216 to write data to the buffer instead of writing it directly to the HBN228. Writing data directly to the HBN228 results in longer latency than would be possible with the LPDDR memory controller 216. Writing data to the buffer results in shorter latency compared to being compatible with the LPDDR memory controller 216.

[0048] Upon receiving the allocation command 404, the front-end controller 218 checks whether its buffer has sufficient available space for the data. If there is not enough available space in the buffer, the front-end controller 218 initiates an allocation write command 406 to write some existing data in the buffer to the HBN228 in order to allocate space in the buffer for the received data. The front-end controller 218 returns confirmation 408 to the kernel 212. In one embodiment, the front-end controller 218 also returns the estimated buffer ready time along with confirmation 408 if the data is not yet ready. The expected buffer preparation time represents the expected time in which the buffer has available space for data so that the LPDDR memory controller 216 can write data to the buffer. In one embodiment, if existing data is moved from the buffer to the HBN228, the buffer reserve command 412 causes the HBN frontend module to reserve the allocated space on the buffer for the data to be received.

[0049] The kernel 212 issues a pole buffer command 410 to the front-end controller 218 to check whether a buffer is prepared (for example, whether there is available space for the data). The front-end controller 218 returns a buffer state 414 to the kernel 212 indicating whether or not a buffer is available, or whether or not a buffer is available. If the buffer is not prepared (432), the kernel will later issue another pole buffer command (410) to check again until the buffer is prepared. If a buffer is available, the kernel issues a write command to the LPDDR memory controller 216, and the LPDDR memory controller 216 issues a write command to the front-end controller 218 along with the data. The data is stored in a buffer by the front-end controller 216. Therefore, the write time 426 experienced by the LPDDR memory controller 216 is shorter than the write time 420 of the HBN228 and is compatible with the LPDDR memory controller 216. The front-end module returns acknowledgment 422 to the LPDDR memory controller 216. The LPDDR memory controller 216 returns a write acknowledgment 424 to the kernel 212, and the kernel 212 returns an acknowledgment 430 to the application 230.

[0050] Figure 5 is a flowchart illustrating a process 500 that interacts with a memory device 104 via a memory controller 110 of a host 102 according to an embodiment of the present invention. In step S502, host 102 receives a request from application 106. In one embodiment, the request relates to the memory device 104. For example, a request may include a read request to read data from memory 116 (e.g., HBN228) of memory device 104 for consumption by application 106. In one embodiment, the request includes a write request for the application to write data to the memory 116 of the memory device 104.

[0051] In step S504, the host 102 issues a first command to the memory device 104 via the memory controller 110. In one embodiment, the first command is based on the request type of the request from application 106 (for example, the request type is one of a read request or a write request). For example, if the request from the application is a read request, the first command issued by the memory device 104 is a fetch command to fetch the data requested by the application from the memory 116 of the memory device 104. In one embodiment, a fetch command triggers the memory device 104 to load the requested data from memory 116 into a buffer in the front-end controller 114. For example, if the request from the application is a write request, the first command issued by the memory device 104 is an allocation command to allocate space on the buffer of the front-end controller 114 for the data to be written to memory 116. In one embodiment, the allocation command triggers the memory device 104 to begin operations to allocate and / or reserve buffer space for data from the application 106.

[0052] In step S506, the host 102 polls the memory device 104 to determine its status. In one embodiment, the state relates to the readiness of the memory device 104 for the request and to the type of request. For example, if the request from application 106 is a read request, the state of memory device 104 is based on the availability of the requested data in the buffer of memory device 104.

[0053] In step S504, after the memory device 104 receives the first command issued by the host 102, the host 102 continues to poll the memory device 104 until it indicates that the state is in the buffer of the requested data, while the memory device 104 takes time (e.g., several microseconds) to load the requested data from memory 116 into the buffer. If the request from application 106 is a write request, the state of memory device 104 is based on the availability of space in memory device 104's buffer for the data. In one embodiment, in response to receiving a first command issued by the host 102 in step S504, the memory device 104 takes time (e.g., several microseconds) to allocate space in the buffer, for example, by offloading existing data in the buffer. Therefore, host 102 continues polling memory device 104 until the status indicates that space is available in the buffer for data from application 106.

[0054] In step S508, the host 102 determines that the memory device is ready based on the state polled in step S506. In step S510, the host 102 issues a second command to the memory device 104 via the memory controller 110 in order to execute the request. In one embodiment, the second command includes a native read or write command issued by the memory controller 110. For example, in one embodiment, the memory controller 110 is an LPDDR memory controller 216, and the second command (e.g., a native read or write command) is issued by the LPDDR memory controller 216. In one embodiment, the second command issued by the LPDDR memory controller 216 (e.g., native write or write command) is an LPDDR command and is independent of the type of memory 116 of the memory device 104.

[0055] Figure 6 is a flowchart illustrating a process 600 in which a read request is executed on a memory device 104 via a memory controller 110 of a host 102 according to an embodiment of the present invention. In step S602, the host 102 receives a read request from the application to read data consumed by the application 106 from the memory 116 (e.g., HBN228) of the memory device 104.

[0056] In step S604, the host 102 issues a fetch command to the memory device 104 in order to fetch the data requested by the application from the memory 116 of the memory device 104. In one embodiment, a fetch command triggers the memory device 104 to load the requested data from memory 116 into a buffer in the front-end controller 114. In step S606, the host 102 issues a pole command to the memory device 104 in order to determine the state of the memory device 104 in relation to fetching the requested data from memory. In one embodiment, the state of the memory device 104 is based on the availability of the requested data in the buffer of the memory device 104.

[0057] In step S608, the host 102 receives a status from the memory device 104, and in step S610, it determines the status of the data (for example, whether or not the data is in the buffer). If the data is fully ready (for example, if all the requested data is in the buffer), process 600 proceeds to step S612. In step S612, the host 102 issues a read command to the memory device 104. In one embodiment, the memory controller 110 is an LPDDR memory controller 216, and the LPDDR memory controller 216 issues an LPDDR read command to the memory device 104.

[0058] If the data is not ready (for example, if the data is not in the buffer), process 600 proceeds to step S614. In step S614, host 102 waits for a certain period of time before returning to step S606, and then issues another pole command to check the status of the data. In one embodiment, host 102 polls the memory device for status, and if the response from memory device 104 indicates that data is not ready, the response from memory device 104 also includes the amount of time expected to take for the data to be ready, or the amount of time to wait before the host polls again. In one embodiment, the amount of time that host 102 waits before polling again is based on a predetermined polling frequency or schedule.

[0059] In one embodiment, the requested data is partially ready (for example, some of the data exists in a buffer). If this is the case, process 600 proceeds to step S616. In step S616, host 102 issues a read command to memory device 104 for a portion of the prepared data (for example, in a buffer). Next, process 600 proceeds to step S614, in which the host waits for a predetermined amount of time to check whether the remaining data is ready before polling memory device 104 again. Host 102 polls memory device 104 until a read command is issued for all of the requested data.

[0060] The embodiment shown in the figure includes three possible readiness states for the requested data: fully prepared, not prepared, and partially prepared. In one embodiment, the state has only two states, which are either ready or not ready, and a read command is issued by the host 102 when the data is fully ready.

[0061] Figure 7 is a flowchart illustrating a process 700 in which a write request is executed to a memory device via a host memory controller according to an embodiment of the present invention. In step S702, the host 102 receives a write request from application 106 to write data to memory 116 (e.g., HBN228) of memory device 104.

[0062] In step S704, host 102 issues an allocation command to memory device 104 in order to allocate space for data on the buffer of memory device 104. In one embodiment, the allocation command causes the memory device 104 to load the requested data from memory 116 into the buffer of the front-end controller 114. In step S706, the host 102 issues a pole command to the memory device 104 to determine the state of the memory device 104 related to the available space on the buffer. In one embodiment, the state of the memory device 104 is based on whether or not the buffer of the memory device 104 has sufficient available space for data.

[0063] In step S708, the host 102 receives a status from the memory device 104, and in step S710, it determines the state of the buffer (for example, whether the buffer has enough available space for data). If the buffer is fully prepared (for example, if the buffer has enough space for all the data), process 700 proceeds to step 712. In step S712, the host 104 issues a write command to the memory device 104 along with the data. In one embodiment, the memory controller 110 is an LPDDR memory controller 216, and the LPDDR controller 216 issues an LPDDR write command to the memory device 102.

[0064] If a buffer is not prepared (for example, if there is no available space in the buffer), process 700 proceeds to step S714. In step S714, host 102 waits for a certain period of time before returning to step S706, and then issues another pole command to check the buffer status. In one embodiment, if host 102 polls a memory device for status and the response from memory device 104 indicates that the buffer is not ready, the response from memory device 104 also includes the amount of time it is expected to take for the buffer to be ready, or the amount of time to wait before the host polls again. In one embodiment, the amount of time that host 102 waits before polling again is based on a predetermined polling frequency or schedule.

[0065] In one embodiment, the buffer is partially prepared (for example, the buffer has available space for a portion of the data). If this is the case, process 700 proceeds to step S716. In step S716, the host 102 issues a write command to the memory device 104 for a portion of the data that has available space on the buffer. Then, process 700 proceeds to step S714, in which host 102 waits for a predetermined amount of time before polling memory device 104 again to check whether the buffer has been prepared for the remaining data. Host 102 polls memory device 104 until a write command is issued for all of the data. The embodiment shown in the figure includes three possible preparation states of the buffer: fully prepared, unprepared, and partially prepared. In one embodiment, the state may have only two states, which are either ready or not ready, and a write command is issued by the host 102 when the buffer is fully ready.

[0066] Figures 8A and 8B are flowcharts illustrating a process 800 executed by the memory device 204 in response to a request received from the host memory controller according to an embodiment of the present invention. In step S802, the memory device 204 receives a command from the LPDDR memory controller 216.

[0067] A command is either an access-type command or a handshake-type command. Examples of access type commands include read and write commands. Examples of handshake-type commands include fetch commands, allocation commands, pole data commands, pole buffer commands, and reset commands. In step S804, the memory device 204 determines whether the command is an access-type command or a handshake-type command. If the command is an access-type command, process 800 proceeds to step S806.

[0068] In step S806, the memory device 204 determines whether the command is a read command or a write command. If the command is a read command, process 800 proceeds to step S808. In step S808, the memory device 204 reads data from the buffer and returns the data to the LPDDR memory controller 216. If the command is a write command that contains data to be written to the memory of memory device 204, process 800 proceeds to step S810. In step S810, the memory device 204 writes the write command and associated data to the buffer. In step S812, the memory device 204 issues a write command to write data from the buffer to the HBN228.

[0069] In step S804, if the command is a handshake type command, process 800 proceeds to step S814, and memory device 204 determines what type of handshake command the command is. If the command is a fetch command, process 800 proceeds to step S816. In step S816, the memory device 204 issues a read command to the HBN228 to load the requested data from the HBN228 into the buffer. In step S818, the memory device returns confirmation and the estimated data preparation time to the host 202. The estimated data preparation time indicates the estimated time when the requested data is in the buffer and ready for direct reading by the LPDDR memory controller 216.

[0070] If the command is an assigned command, process 800 proceeds to step S820. In step S820, the memory device 204 starts a buffer allocation operation to allocate space on the buffer for the data. In one embodiment, the allocation operation includes offloading old data from a buffer. In step S822, the memory controller 110 returns the expected buffer preparation time to the host 202. The estimated buffer preparation time indicates the estimated time during which there is available space on the buffer so that the LPDDR memory controller 216 can write data to the buffer.

[0071] If the command is a pole data command, process 800 proceeds to step S824. In one embodiment, the pole data command is a handshake operation performed between the memory device 204 and the host 202 prior to a read command issued by the host 202, so that the host 202 can know whether the requested data is in the buffer and therefore ready for direct reading by the LPDDR memory controller 216. In step S824, the memory device 204 checks whether the requested data exists in the buffer. In step S826, the memory device determines whether or not data is prepared. If the data is ready, process 800 proceeds to step S828. In step S828, the memory device 204 returns a data ready status to the host 202. If the data is not ready, in step S830, the memory device 204 returns a data not ready status to the host 202. In one embodiment, the memory device 204 also returns an estimated data preparation time to the host 202.

[0072] If the command is a pole buffer command, process 800 proceeds to step S832. In step S832, the memory device 204 checks whether the buffer has been prepared. In step S834, the memory device 204 determines whether or not the buffer has been prepared. If a buffer is prepared, process 800 proceeds to step S836. In step S836, the memory device returns a buffer ready status to host 202. If the buffer is not prepared, in step S838, memory device 204 returns a buffer not ready status to host 202. In one embodiment, the memory device 204 also returns an estimated buffer preparation time to the host 202.

[0073] If the command is a reset command, process 800 proceeds to step S840. The reset command is issued when an error occurs. In step S840, the memory device 204 resets the buffer metadata and the command queue.

[0074] One embodiment of the present invention may include the features of the following numbered statements: Statement 1 A method for a memory device, comprising the steps of: receiving a request from an application relating to the memory device, wherein the request has a request type; issuing a first command to the memory device via a memory controller, wherein the first command is based on the request type; polling the memory device for the state of the memory device, wherein the state is related to the readiness of the memory device for the request; determining, based on the state, that the memory device is ready; and issuing a second command to the memory device via a memory controller to execute the request.

[0075] Statement 2 The memory controller is the method described in statement 1, including a low-power double data rate (LPDDR) memory controller. Statement 3 The method according to statement 1 or 2, wherein the memory device includes high-bandwidth flash NAND memory and a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from an LPDDR memory controller. Statement 4 The request type is a write request, as described in any one of statements 1-3. Statement 5 The state of the memory device is determined by the method described in statement 4, based on the availability of space within the memory device's buffer. Statement 6 The method of statement 5, further comprising the step of reserving a predetermined space in a buffer for the application. Statement 7 The request type is a read request, as described in any one of statements 1 through 6. Statement 8 The state of the memory device is determined by the method of statement 7, based on the availability of data related to the request in the memory device's buffer.

[0076] Statement 9 A system having a host, the host including a memory controller, a processing circuit including a processor, and memory connected to the processing circuit, the memory storing executable instructions by the processing circuit, and when an instruction is executed by the processing circuit, the processing circuit receives a request from an application relating to the memory, where the request has a request type, and issues a first command to the memory via the memory controller, where the first command is based on the request type, and polls the memory for its state, where the state is related to the readiness of the memory for the request, and based on the state, determines that the memory is ready, and issues a second command to the memory via the memory controller to execute the request.

[0077] Statement 10 The memory controller is a low-power double data rate (LPDDR) memory controller, as described in Statement 9. Statement 11 The system described in statement 10 includes high-bandwidth flash NAND memory and a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from an LPDDR memory controller. Statement 12 The request type is a write request and is associated with one of the systems described in any of statements 9-11. Statement 13 The state of memory is based on the availability of space in the memory buffer, as described in statement 12. Statement 14 The system described in statement 13 further includes a processing circuit that reserves a predetermined space in the buffer for the application. Statement 15 The request type is a read request, as described in one of the statements 9-14. Statement 16 The memory state is based on the availability of data related to the request in the memory buffer, as described in statement 15.

[0078] Statement 17 A memory device comprising high-bandwidth NAND (HBN) and a front-end controller configured to control access to the HBN, wherein the front-end controller includes a buffer, a processing circuit including a processor, and a memory connected to the processing circuit, the memory storing an executable instruction word by the processing circuit, and when an instruction word is executed by the processing circuit, the processing circuit receives a first command from the memory controller of the host device, determines that the state of the buffer satisfies the conditions related to the first command, transfers the state of the buffer to the memory controller, receives a second command from the memory controller, and performs an operation on the buffer based on the second command.

[0079] Statement 18 The second command is a read request for data stored in the HBN, the condition being that the data is in a buffer, as described in statement 17. Statement 19 The second command is a write request for data stored in the HBN, the condition being that the buffer has sufficient available space for the data, as described in statement 17 or 18. Statement 20 The memory device described in statement 19 further performs the processing circuit to reserve a predetermined space in a buffer for data.

[0080] While embodiments of systems and methods for LPDDR-compatible high-bandwidth NAND have been described in detail and illustrated herein, the present invention is not limited to the embodiments described above. It is possible to modify and implement the invention in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0081] 100, 200 systems 102, 202 hosts 104, 204 memory devices 106 Applications 108, 206 processors 110 Memory Controller 114 Front-end controller 116 memory 208 Memory Allocator 210 Device Driver (HBF Device Driver) 212 kernel 214 Application Processors 216 LPDDR memory controllers 218 Front-end controller 220 LPDDR Command Converter 222 Buffer (Staggered Buffer) 224 Buffer Manager (Stagger Buffer Manager) 226 HBN Manager 228 HBN (High-bandwidth NAND) 230 applications 300, 400 Timing Graph 500, 600, 700, 800 processes

Claims

1. A method for memory devices, The step of receiving a request from the application related to the memory device, Here, the request has a request type, The steps include issuing a first command to the memory device via the memory controller, Here, the first command is based on the request type, The steps include: polling the memory device to determine its state, Here, the state is related to whether the memory device is ready for the request (readiness), A step of determining that the memory device has been prepared based on the above state, A method characterized by comprising the step of issuing a second command to the memory device via the memory controller in order to execute the aforementioned request.

2. The method according to claim 1, characterized in that the memory controller includes a low-power double data rate (LPDR) memory controller.

3. The memory device is High-bandwidth flash NAND memory, The method according to claim 1, further comprising a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from the LPDDR memory controller.

4. The method according to claim 1, characterized in that the request type is a write request.

5. The method according to claim 4, characterized in that the state of the memory device is based on the availability of space within the buffer of the memory device.

6. The method according to the 5th, further comprising the step of reserving a predetermined space in the buffer for the application.

7. The method according to claim 1, characterized in that the request type is a read request.

8. The method according to 7, characterized in that the state of the memory device is based on the availability of data related to the request in the buffer of the memory device.

9. It is a system, Having a host, The aforementioned host, Memory controller and Processing circuit including a processor, Includes a memory connected to the processing circuit, The memory stores instruction words that can be executed by the processing circuit, When the instruction word is executed by the processing circuit, The aforementioned processing circuit is The application receives a request related to the aforementioned memory, Here, the request has a request type, A first command is issued to the memory via the memory controller, Here, the first command is based on the request type, The memory is polled to determine its state. Here, the state is related to whether the memory is ready for the request (readiness), Based on the above state, it is determined that the memory has been prepared. A system characterized by issuing a second command to the memory via the memory controller in order to execute the aforementioned request.

10. The system according to claim 9, characterized in that the memory controller includes a low-power double data transfer rate (LPDR) memory controller.

11. The aforementioned memory is High-bandwidth flash NAND memory, The system according to claim 10, further comprising a front-end controller configured to control the high-bandwidth flash NAND memory based on commands from the LPDDR memory controller.

12. The system according to claim 9, characterized in that the request type relates to a write request.

13. The system according to claim 12, characterized in that the state of the memory is based on the availability of space in the buffer of the memory.

14. The system according to claim 13, wherein the processing circuit further reserves a predetermined space in the buffer for the application.

15. The system according to claim 9, characterized in that the request type is a read request.

16. The system according to claim 15, characterized in that the state of the memory is based on the availability of data related to the request in the buffer of the memory.

17. A memory device, High-bandwidth NAND (HBN) and It includes a front-end controller configured to control access to the HBN, The aforementioned front-end controller is Buffer and Processing circuit including a processor, Includes a memory connected to the processing circuit, The memory stores instruction words that can be executed by the processing circuit, When the instruction word is executed by the processing circuit, The aforementioned processing circuit is Upon receiving the first command from the host device's memory controller, It is determined that the state of the buffer satisfies the conditions related to the first command, The state of the buffer is transferred to the memory controller. Upon receiving a second command from the memory controller, A memory device characterized by performing an operation on the buffer based on the second command.

18. The second command is a read request for data stored in the HBN, The memory device according to claim 17, characterized in that the condition includes the data being in the buffer.

19. The second command is a write request to the data stored in the HBN, The memory device according to claim 17, characterized in that the condition includes having sufficient available space for the data in the buffer.

20. The memory device according to claim 19, further characterized in that the processing circuit reserves a predetermined space in the buffer for the data.

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