Method of operating a memory system, memory system, and storage medium

Abstract

An operation method of a memory system, a memory system, and a storage medium, including: providing a logical block management table including a first sequence of identifiers corresponding to M first logical blocks, the identifiers of the M first logical blocks being constructed as a ring queue and managing allocation states of the M first logical blocks through the logical block management table, M being an integer greater than or equal to 2 (S502); and assigning a certain first logical block having an allocation state of a first state indicating unallocated to a certain second logical block among N second logical blocks in order of the identifiers of the M first logical blocks in the ring queue, N being an integer greater than M, and updating the allocation state of the certain first logical block from the first state to a second state indicating allocated in the logical block management table (S504).

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and more specifically, to an operating method of a memory system, a memory system, and a storage medium. Background Technology

[0002] The memory system can perform a mapping from host-recognizable logical addresses associated with data to physical addresses storing data in the memory space. This mapping between logical and physical addresses (L2P mapping) can form an L2P (Logical to Physical) mapping table. The memory controller of the memory system can manage and allocate logical block resources that divide the memory space, recommend suitable logical block resources to the host, and cache the L2P mapping relationships corresponding to suitable logical block resources on the host side, thereby improving the performance of the memory system. It should be noted that the information disclosed in the background section above is only for enhancing the understanding of the background of this disclosure and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0003] The purpose of this disclosure is to provide a method for operating a memory system, a memory system, and a storage medium.

[0004] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0005] This disclosure provides an operation method for a memory system, comprising: providing a logic block management table, the logic block management table including a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks being constructed into a circular queue and the allocation status of the M first logic blocks being managed through the logic block management table, where M is an integer greater than or equal to 2; and allocating a first logic block whose allocation status is a first state indicating unallocated to a second logic block among N second logic blocks according to the order of the identifiers of the M first logic blocks in the circular queue, where N is an integer greater than M, and updating the allocation status of the first logic block from the first state to a second state indicating allocated in the logic block management table.

[0006] In some exemplary embodiments of this disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and N second logic blocks cover the entire physical address of the memory device of the memory system.

[0007] In some exemplary embodiments of this disclosure, the method further includes: if there is no first logical block in the circular queue with a corresponding allocation state of first state, allocating the second logical block corresponding to the first logical block that was first updated to second state, and updating the allocation state corresponding to the first logical block that was first identified as second state to first state.

[0008] In some exemplary embodiments of this disclosure, the circular queue includes a pointer configured to sequentially point to one of the M first logical blocks in the circular queue according to the order of the identifiers of the M first logical blocks; the method further includes: in response to the allocation state of the first logical block pointed to by the pointer being a second state, allocating the second logical block corresponding to the first logical block that was first updated to the second state, and updating the allocation state corresponding to the first logical block that was first identified as the second state to the first state.

[0009] In some exemplary embodiments of this disclosure, the method further includes: assigning the first logic block pointed to by the pointer to one of the N second logic blocks, and pointing the pointer to the next first logic block in the order stated.

[0010] In some exemplary embodiments of this disclosure, the method further includes: allocating Y first logic blocks in a first state to Y second logic blocks out of N second logic blocks, where Y is an integer greater than 1 and less than M, and updating the allocation state of the Y first logic blocks in the logic block management table from the first state to a third state indicating that they have been allocated and are fixed.

[0011] In some exemplary embodiments of this disclosure, allocating Y first logic blocks in a first state to Y second logic blocks out of N second logic blocks includes: allocating the Y consecutive first logic blocks in the circular queue in the first state to the Y second logic blocks.

[0012] In some exemplary embodiments of this disclosure, the first logic blocks whose allocation state is the third state are skipped according to the order of the identifiers of the M first logic blocks in the circular queue.

[0013] In some exemplary embodiments of this disclosure, the logic block management table further includes a second sequence of identifiers corresponding to N second logic blocks; the method further includes updating the identifier of a first logic block or the identifier of a second logic block in the logic block management table.

[0014] In some exemplary embodiments of this disclosure, the number of elements in the circular queue is the same as the number of first logical blocks, and each element stores the identifier of the corresponding first logical block and the allocation status of the first logical block.

[0015] In some exemplary embodiments of this disclosure, the size of the first logic block is the same as the size of the second logic block.

[0016] In some exemplary embodiments of this disclosure, the method further includes sending the updated logical block management table to the host.

[0017] In some exemplary embodiments of this disclosure, the method further includes sending the L2P mapping table corresponding to a certain second logical block to the host.

[0018] This disclosure provides a memory system, including: a memory device and a memory controller coupled to the memory device and used to control the memory device to perform data storage operations; the memory controller includes an interface coupled to a host for communication; the interface is configured to sequentially send at least a portion of mapping information from a first logic block management table and a second logic block management table to the host; wherein the first logic block management table and the second logic block management table each represent the mapping relationship between the first logic block and the second logic block at different times, and both the first logic block management table and the second logic block management table include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed into a circular queue and managed by the logic block management table. The allocation status of the first logic block, where M is an integer greater than or equal to 2; the first logic block management table and the second logic block management table each include the identifiers of K first logic blocks whose allocation status at different times indicates that they have been allocated to the second state, and the identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, where K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M; the first first logic block allocated among the K first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block among the K second logic blocks in the second logic block management table, so as to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0019] In some exemplary embodiments of this disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and N second logic blocks cover the entire physical address of the memory device of the memory system.

[0020] In some exemplary embodiments of this disclosure, both the first logical block management table and the second logical block management table include Y identifiers of first logical blocks whose allocation status is a third state indicating that they have been allocated and are fixed, and Y identifiers of the Y first logical blocks to which they are allocated, where Y is an integer greater than 1, and the sum of Y and K is less than or equal to M; the interface is configured to sequentially send K mapping information from the first logical block management table and K mapping information from the second logical block management table to the host.

[0021] In some exemplary embodiments of this disclosure, the interface is also configured to send the corresponding L2P mapping table in a second logical block to the host.

[0022] This disclosure provides a memory system, including: a memory device and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; the memory controller includes an interface coupled to a host for communication; the interface is configured to sequentially send a first mapping relationship and a second mapping relationship to the host after two consecutive logical block management table updates are triggered; wherein, the first mapping relationship includes K mapping information entries for a first logical block and a second logical block, the K mapping information entries being included in the first logical block management table, and the second mapping relationship includes L mapping information entries for the first logical block and the second logical block, the L mapping information entries being included in the second logical block management table. Both the first and second logical block management tables include a first sequence of identifiers corresponding to M first logical blocks. The identifiers of the M first logical blocks are constructed into a circular queue and the allocation status of the M first logical blocks is managed through the logical block management table. M is an integer greater than or equal to 2, and K and L are integers greater than or equal to 1 and less than or equal to M. The first first logical block that is allocated first among the M first logical blocks corresponding to the first logical block management table is updated and allocated to a second logical block among the L second logical blocks in the second logical block management table, so as to reflect the update of the mapping relationship in the second logical block management table relative to the mapping relationship in the first logical block management table.

[0023] In some exemplary embodiments of this disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and there are N second logic blocks, where N is an integer greater than M, and the N second logic blocks cover all physical addresses of the memory device of the memory system.

[0024] In some exemplary embodiments of this disclosure, the interface is further configured to send an L2P mapping table corresponding to a certain second logical block to the host.

[0025] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions thereon, wherein the computer instructions, when executed, perform the operation method of any of the memory systems described above.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0029] Figure 2a A schematic diagram of a memory card integrating a memory controller and a memory device according to some aspects of this disclosure is shown.

[0030] Figure 2b A schematic diagram of an SSD integrating a memory controller and a memory device according to some aspects of this disclosure is shown.

[0031] Figure 3 A schematic diagram of a system including a host and a memory system according to an embodiment is shown.

[0032] Figure 4 This diagram illustrates the management of a memory system selectively providing a portion of its L2P mapping table to the host.

[0033] Figure 5 This diagram illustrates a flowchart of an operation method for a memory system according to an embodiment of the present disclosure.

[0034] Figure 6 A schematic diagram of a circular queue is shown in an embodiment of this disclosure.

[0035] Figure 7 A schematic diagram of a circular queue is shown in an embodiment of this disclosure.

[0036] Figure 8 A schematic diagram of a circular queue is shown in an embodiment of this disclosure.

[0037] Figure 9 A schematic diagram of a circular queue is shown in an embodiment of this disclosure.

[0038] Figure 10 A schematic diagram of a circular queue is shown in an embodiment of this disclosure.

[0039] Figure 11 This diagram illustrates a logic block management table according to an embodiment of the present disclosure.

[0040] Figure 12 This diagram illustrates a logic block management table according to an embodiment of the present disclosure.

[0041] Figure 13 This diagram illustrates a logic block management table according to an embodiment of the present disclosure.

[0042] Figure 14 This diagram illustrates a logic block management table according to an embodiment of the present disclosure.

[0043] Figure 15 This diagram illustrates a logic block management table according to an embodiment of the present disclosure.

[0044] Figure 16 This diagram illustrates another logical block management table in an embodiment of the present disclosure.

[0045] Figure 17 This diagram illustrates another logical block management table in an embodiment of the present disclosure.

[0046] Figure 18 This diagram illustrates another logical block management table in an embodiment of the present disclosure.

[0047] Figure 19 This diagram illustrates another logical block management table in an embodiment of the present disclosure.

[0048] Figure 20 This diagram illustrates another logical block management table in an embodiment of the present disclosure.

[0049] Figure 21 A flowchart illustrating an operation method of another memory system according to an embodiment of this disclosure is shown.

[0050] Figure 22 A flowchart illustrating an operation method of another memory system according to an embodiment of the present disclosure is shown.

[0051] Figure 23 This diagram illustrates the interaction between a host and memory system according to an embodiment of the present disclosure. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0053] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0054] Furthermore, in the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0055] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0056] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0057] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0058] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0059] Figure 3 A diagram showing a system 300 including a host 310 and a memory system 320 according to an embodiment is shown. Figure 3 System 300 in the above reference can correspond to the above reference. Figure 1 System 100, Figure 3 The host 310 in the above reference can correspond to the host 310 in the above reference. Figure 1 Host 108, Figure 3 The memory system 320 in the above reference can correspond to the memory system 320 in the above reference. Figure 1 The memory system 102.

[0060] The memory system 320 may include a memory controller 330 and a memory device 340. The memory controller 330 may include a host interface 332, a processor 334, a cache 336, and a memory device interface 338. The memory controller 330 can receive commands from the host 310 through the host interface 332 and can control the operation of the memory device 340 based on the received commands through the processor 334. The memory controller 330 can communicate with the memory device 340 through the memory device interface 338 to control the operation of the memory device 340. The commands received by the memory controller 330 through the host interface 332 and the data involved in the commands can be temporarily stored in the cache 336. The cache 336 can also be configured to temporarily store data read by the memory device 340 and to be transmitted to the host 310. In some embodiments, the cache 336 can also be configured to cache other related information of the memory system 320.

[0061] In some embodiments, the memory controller 330 can receive write commands, read commands, etc., from the host 310 via the host interface 332, and the processor 334 can generate commands for controlling the operation of the memory device 340 based on the received commands, and transmit the commands to the memory device 340 via the memory device interface 338. The memory device 340 is configured to receive commands and addresses from the memory controller 330, and access a region selected by the address in the memory cell array of the memory controller 330. That is, the memory device 340 performs internal operations corresponding to the commands on the region selected by the address. For example, the memory device 340 can perform programming operations, read operations, and erase operations. During a programming operation, the memory device 340 can program data into the region selected by the address. During a read operation, the memory device 340 can read data from the region selected by the address. During an erase operation, the memory device 340 can erase the data stored in the region selected by the address. In some embodiments, the memory device 340 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). The memory device 340 can perform write and read operations on a page-by-page basis and can perform erase operations on a block-by-block basis.

[0062] In some embodiments, the memory system 320 may have a Flash Translation Layer (FTL) in the memory controller 330, and one or more command operations, internal operations, etc., can be performed through the FTL. For example, the memory controller 330 may control the memory device 340 in response to a request from the host 310. Simultaneously, the memory controller 330 may perform internal operations (e.g., garbage collection operations, read recycling operations, and wear leveling operations) independently of requests from the host 310. For example, the memory controller 330 may perform these operations by running the FTL using software. The FTL may be run by the processor 334 of the memory controller 330. Therefore, the various operations of the FTL can be executed by the processor 334.

[0063] An important operation of FTL includes mapping the logical address space of host 310 to the physical address space of memory device 340. Every time the memory system 320 writes a piece of user data into the memory device 340, it records the mapping from the logical address of the user data to the physical address of the data in the memory device 340. When host 310 reads the data, the memory system 320 will read the data from the memory device 340 according to this mapping and then return the data to host 310.

[0064] In some embodiments, operations executed via commands and internal operations can be performed via FTL, and address mapping operations that translate or convert logical addresses (LA) provided by host 310 to physical addresses (PA) of memory device 340 can be performed. L2P mapping information can be provided in a logical-to-physical mapping table (i.e., an L2P mapping table) that includes logical address-to-physical address mapping data. As the memory system 320 expands, the size of the L2P mapping table inevitably increases. Therefore, the time spent by the memory system 320 searching the L2P mapping table increases, which may reduce the operating speed of the memory system 320, especially for memory systems 320 without DRAM.

[0065] In some embodiments, the system 300, including a host 310 and a memory system 320, may have a host memory 312 in the host 310, and at least a portion of the L2P mapping table in the memory system 320 may be synchronized to the host memory 312 to enable address mapping operations to be performed preferentially in the host 310, thereby improving the performance of the memory system 320. For example, the host 310 transmits the L2P mapping information searched from the host memory 312 along with a read command to the memory system 320. The host interface 332 receives the read command and the L2P mapping information, and the processor 334 transmits the read command for reading user data and the physical address corresponding to the read command to the memory device 340. The memory device 340 reads the user data corresponding to the received read command. The read user data may be transmitted to the memory controller 330 and may be transmitted from the memory controller 330 to the host 310.

[0066] To synchronize at least a portion of the L2P mapping information in memory system 320 to host memory 312, host 310 and memory system 320 need to be configured to support this operation, which can be an HPB (Host Performance Booster) operation or an HMB (Host Memory Buffer) operation. When memory system 320 provides host 310 with the entire L2P mapping table stored in memory system 320, the ability of memory system 320 to support the corresponding operation may be limited, or host 310 may have difficulty allocating storage space in host memory 312 to store the entire L2P mapping information, or, due to other functional limitations, memory system 320 may selectively provide host 310 with a portion of the L2P mapping table instead of providing all of the L2P mapping table.

[0067] Figure 4This diagram illustrates the management of the memory system 320 when selectively providing a portion of the L2P mapping table to the host 310. The memory controller 330 can represent the physical address space of the memory device 340 by correspondingly overwriting the logical address space of the application, which is divided into multiple logical blocks. See [reference needed]. Figure 4 The logical address space can cover all physical addresses of the memory device 340. The logical address space can be evenly divided into multiple second logical blocks 121, each of equal size. These multiple second logical blocks 121 are encoded into a second logical block table 120 (Region table). The size of each second logical block 121 can be set according to actual needs, and the number of second logical blocks 121 is determined based on the size of the memory device 340 and the size of each second logical block 121. For example, see... Figure 4 The memory device 340 is 512G in size, the second logic block 121 is 16M in size, the number of second logic blocks 121 is 32K, and the length of the second logic block table 120 is 32K.

[0068] When the memory system 320 selectively provides a portion of the L2P mapping table to the host 310, it needs to select a portion of the second logic blocks 121 from the plurality of second logic blocks 121, and send the L2P mapping table corresponding to the selected portion of the second logic blocks 121 to the host 310 for storage in the host memory 312, so that the host 310 can access it when making a read request. The memory system 320 can be configured with a logical space to support the aforementioned operations, and the logical space can be divided into a plurality of first logical blocks, wherein the number of first logical blocks is less than the number of second logical blocks. See also Figure 4 Multiple first logical blocks 111 can be organized into a first logical block table (Sub-region table). The size of the first logical block 111 can be set according to actual needs; for example, the size of the first logical block 111 can be the same as the size of the second logical block 121. For example, see... Figure 4 The size of the first logical block 111 can be 16M. The memory system 320 can be configured to support a logical space of 128G. Then the number of first logical blocks 111 is 8K, and the length of the first logical table 110 is 8K. The memory system 320 can be configured to support the logical space of the aforementioned operation and can only recommend the L2P mapping table corresponding to the 128G physical address space in the memory device 340 to the host 310.

[0069] When the memory system 320 selectively provides a portion of the L2P mapping table to the host 310, it can select at least one second logic block 121 that meets the recommended criteria from the second logic block table 120 and map it with at least one first logic block 111 in the first logic block table 110. The mapping relationship between the first logic block 111 and the second logic block 121 is then recommended to the host 310. After receiving the mapping relationship between the first logic block 111 and the second logic block 121, the host 310 requests the L2P mapping table corresponding to the second logic block 121 from the memory system 320. In response to the request, the memory system 320 sends the L2P mapping table corresponding to the second logic block 121 to the host 310 for storage in the host memory 312.

[0070] When it is necessary for the memory system 320 to selectively provide a portion of the L2P mapping table to the host 310 for updating, see [reference needed]. Figure 4 Before the update, the first 8K second logic blocks 121 are selected as the 8K second logic blocks 121 that meet the recommended criteria. These are mapped one-to-one with the 8K first logic blocks 111 in the first logic block table 110, forming a mapping relationship 110A between the 8K first logic blocks 111 and the second logic blocks 121. This mapping relationship 110A is recommended to the host 310, and the L2P mapping tables corresponding to the first 8K second logic blocks 121 are stored in the host memory 312. When a new second logic block 121 meets the recommended criteria, for example... Figure 4 For the 8K+1 and 8K+2 second logic blocks 121, it is necessary to find the mapping between the first logic block 111 and the new second logic block 121 that meets the recommended criteria in the first logic block table 110. For example, see Figure 4 The first first logic block 111 is mapped to the 8K+1th second logic block 121, and the second first logic block 111 is mapped to the 8K+2th second logic block 121, thus forming a new mapping relationship 110B of 8K first logic blocks 111 and second logic blocks 121. The mapping relationship 110B of first logic blocks 111 and second logic blocks 121 is recommended to the host 310, and the L2P mapping table stored in the host memory 312 is updated.

[0071] When the memory system 320 selectively provides a portion of the L2P mapping table to the host 310, the management of the mapping relationship is relatively complex when searching for the first logical block 111 in the first logical block table 110 to map it with the second logical block 121 that meets the recommended criteria. Some embodiments of this disclosure provide a way to quickly update the mapping relationship between the first logical block 111 and the second logical block 121 and improve resource management efficiency.

[0072] In this embodiment of the disclosure, the memory controller 330 in the memory system 320 stores a logical block management table of first logical blocks (e.g., Sub-Regions) and second logical blocks (e.g., Regions). The memory controller 330 can manage and allocate multiple first logical blocks through this logical block management table. In some embodiments, when a certain second logical block among multiple second logical blocks meets the recommended criteria, a certain first logical block among multiple first logical blocks is allocated to that certain second logical block, and the correspondence is sent to the host 310. After receiving the correspondence, the host 310 can obtain the L2P mapping table corresponding to that certain second logical block stored in the memory system 320, thereby updating the L2P mapping table to the host 310, which can improve data reading efficiency and system performance.

[0073] Figure 5 The diagram illustrates a flowchart of an operation method for a memory system according to an embodiment of this disclosure. The execution entity of this method may be the memory controller 330 in the memory system 320, such as... Figure 5 As shown, the operation method of the memory system provided in this embodiment may include the following steps.

[0074] In step S502, a logic block management table is provided. The logic block management table includes a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table. M is an integer greater than or equal to 2.

[0075] In this embodiment, the logic block management table includes a mapping relationship between first logic blocks and second logic blocks. There can be M first logic blocks. M can represent the number of logic blocks supported by the memory controller 330 in the memory system 320 under HPB mode; M can also represent the number of logic blocks supported by the memory controller 330 in the memory system 320 under HMB mode. The M first logic blocks can cover a portion of the physical address space of the memory device 340 in the memory system 320. There can be N second logic blocks, which can cover part or all of the physical address space of the memory device 340 in the memory system 320. It should be noted that M is an integer greater than or equal to 1, which can be specifically configured in the memory controller 330, and N is an integer greater than M. The amount of physical address space covered by the M first logic blocks in the memory system 320 is less than the amount covered by the N second logic blocks in the memory system 320.

[0076] For example, for a 512G memory system 320, the physical address space of memory device 340 is 512G. The storage space corresponding to the entire physical address space of memory device 340 that can be covered by N second logic blocks can be 512G. The storage space corresponding to a portion of the physical address space of memory device 340 that can be covered by M first logic blocks can be, for example, 128G.

[0077] In this embodiment of the disclosure, the size of the first logic block and the size of the second logic block can be the same, for example, both being 16M. In some embodiments, the size of the first logic block and the size of the second logic block can also be different.

[0078] In this embodiment of the disclosure, the logic block management table may include a first sequence of identifiers corresponding to M first logic blocks. The identifier of a first logic block may be its ID (Identity Document), and each first logic block has a corresponding identifier. The first sequence may be a column in the logic block management table, for example, ... Figures 11-15 The first column in the logical block management table A shown, or for example, as Figures 16-20 The second column in the logic block management table B shown; the logic block management table may also include a second sequence for identifying the second logic block, the identifier of the second logic block may be the ID of the second logic block, and each second logic block has a corresponding identifier; wherein, the second sequence includes the identifier of the second logic block assigned to each first logic block (when the first logic block is not assigned, the identifier of the second logic block corresponding to the second logic block in the second sequence may be an initial value or a preset value, such as 0), the logic block management table may also include a third sequence, the third sequence including the allocation status of each first logic block.

[0079] Specifically, the allocation state of the first logical block may include, but is not limited to, a first state, a second state, and a third state. The first state may represent an "unallocated" state, the second state may represent an "allocated" state, and the third state may represent an "allocated and fixed" state. The "allocated" state may refer to the state in which the first logical block has been allocated to an available second logical block (e.g., a second logical block that meets the recommended criteria). The "allocated and fixed" state may refer to the state in which the first logical block has been fixedly allocated to a certain second logical block, and the second logical block to which the first logical block is allocated will not change significantly.

[0080] In this embodiment of the disclosure, a circular queue can be constructed based on the number of first logic blocks, wherein the number of elements in the circular queue is the same as the number of first logic blocks; for example, a FIFO (First Input First Output) circular queue 600 with a depth of M is initialized to manage the resources of the first logic blocks, such as... Figures 6-10As shown; each element in the circular queue 600 can store the identifier of the corresponding first logical block and the allocation status of the first logical block. For example, the first element of the circular queue 600 stores the identifier of the first first logical block (ID=1), the second element stores the identifier of the second first logical block (ID=2), ..., the Mth element stores the identifier of the Mth first logical block (ID=M). The initial allocation status of each first logical block can be set to the first state of "unallocated".

[0081] In some embodiments, the circular queue 600 may include a pointer 601, which, in an initial state, points to the first logical block in the circular queue 600, for example, as... Figure 6 As shown, in the initial state, pointer 601 points to the first logic block corresponding to identifier 1.

[0082] In step S504, according to the order of the identifiers of the M first logic blocks in the circular queue, a first logic block with an allocation status of "unallocated" is allocated to a second logic block among the N second logic blocks, where N is an integer greater than M. The allocation status of the first logic block is then updated from the first state to the second state of "allocated" in the logic block management table.

[0083] In this embodiment of the disclosure, the first logic block in the first state can be allocated to one of the N second logic blocks in the order of the identifiers of the M first logic blocks in the circular queue, that is, in the order of the M elements in the circular queue (for example, the first one is identifier 1 (corresponding to the first first logic block), the second one is identifier 2 (corresponding to the second first logic block), ..., the Mth one is identifier M (corresponding to the Mth first logic block)). The allocation state of the first logic block in the first state is then updated to the second state in the logic block management table.

[0084] In some embodiments, when one of the N second logical blocks meets the recommended criteria, the first logical block whose allocation state is in the first state, pointed to by the pointer of the circular queue, can be allocated to the second logical block that meets the recommended criteria (the L2P mapping table corresponding to this second logical block is activated after being stored in the host memory 312, and can also be referred to as the active second logical block). The pointer of the circular queue can point to the first logical block whose allocation state is in the first state according to the order of the identifiers of the M first logical blocks in the circular queue.

[0085] In an exemplary embodiment, M first logic blocks may establish mapping relationships with corresponding M second logic blocks respectively, that is, all first logic blocks in the logic block management table have been allocated. At this time, there is no corresponding first logic block with the allocation status of the first state in the circular queue. The above method may further include: allocating the second logic block corresponding to the first logic block that was first updated to the second state in the circular queue, and updating the allocation status corresponding to the first logic block that was first identified as the second state to the first state.

[0086] In some embodiments, there may be no corresponding first logical block with a first allocation state in the circular queue. That is, all the corresponding first logical blocks in the circular queue are in the second or third state, meaning that all the first logical blocks have been allocated to second logical blocks that meet the recommended criteria or are fixed second logical blocks. In this case, the first logical block that is updated to the second state first is determined, that is, the first logical block that is allocated to the second logical block that meets the recommended criteria first. The second logical block corresponding to the first logical block is then de-allocated (also known as deactivation), that is, the mapping relationship between the first logical block and its corresponding second logical block is released, and the allocation state of the first logical block in the logical block management table is updated from the second state to the first state, so as to facilitate the re-allocation of the first logical block to other second logical blocks that meet the recommended criteria.

[0087] In some embodiments, when there is no corresponding first logic block with a first allocation state in the circular queue, the first logic block to be allocated first can be determined according to the order of the identifiers of the M first logic blocks in the circular queue; for example, refer to Figure 9 The circular queue 600 includes M identifiers, and the allocation status of the M first logical blocks corresponding to these M identifiers is not the first state; among them, the first identifier is identifier 1, and the first logical block corresponding to identifier 1 is the first first logical block, so the first first logical block is the first logical block that is allocated first.

[0088] Figure 21 This illustration shows a flowchart of another method for operating a memory system according to an embodiment of the present disclosure, such as... Figure 21 As shown, the operation method of the memory system provided in this embodiment may include the following steps.

[0089] In step S2102, a second logic block that meets the recommended criteria is determined.

[0090] In some embodiments, when it is determined that a second logical block that meets the recommended criteria exists, the following step S2104 may be performed.

[0091] In step S2104, it is determined whether the circular queue has a corresponding first logic block with the first allocation state.

[0092] In some embodiments, if there is a first logical block in the circular queue with a corresponding allocation state of the first state, then step S2106 is executed; if there is no first logical block in the circular queue with a corresponding allocation state of the first state, then step S2108 is executed.

[0093] In step S2106, according to the order of the identifiers of the M first logic blocks in the circular queue, the first logic block with the first allocation state is allocated to the second logic block that meets the recommended criteria.

[0094] In step S2108, the second logic block corresponding to the first logic block that was first updated to the second state is allocated, the allocation state corresponding to the first logic block that was first identified as the second state is updated to the first state, and the first logic block is allocated to the second logic block that meets the recommended criteria.

[0095] In step S2110, the allocation status of the first logic block that is allocated to the second logic block that meets the recommended criteria is updated from the first state to the second state.

[0096] Figure 21 Other details of the embodiments can be found in the textual description of the above method embodiments, and repeated details will not be repeated.

[0097] In an exemplary embodiment, the circular queue includes pointers configured to point sequentially to one of the M first logical blocks in the order of their identifiers in the circular queue.

[0098] For example, in the initial state, reference Figure 6 Pointer 601 points to the first logical block in the circular queue 600, i.e., the first logical block corresponding to identifier 1; after the first logical block is allocated, refer to Figure 8 Pointer 601 points to the second first logical block in the circular queue 600, that is, the first logical block corresponding to identifier 2; and so on, after the current first logical block pointed to by pointer 601 is allocated, it points to the next first logical block in sequence.

[0099] In an exemplary embodiment, in response to the allocation state corresponding to the first logical block pointed to by the pointer being a first state, the first logical block pointed to by the pointer is allocated to a certain second logical block, and the pointer is sequentially pointed to the next first logical block.

[0100] In some embodiments, if the allocation state corresponding to the first logical block pointed to by the pointer is in the first state, it indicates that the first logical block is allocable, and the first logical block can be directly allocated to the second logical block that currently meets the recommended criteria, and the pointer is sequentially pointed to the next first logical block.

[0101] In an exemplary embodiment, the method may further include: in response to the allocation state of the first logical block pointed to by the pointer being a second state, allocating a second logical block corresponding to the first logical block that was first updated to the second state, and updating the allocation state corresponding to the first logical block that was first identified as the second state to the first state.

[0102] In some embodiments, when the allocation state of the first logical block pointed to by the pointer is the second state, the first logical block pointed to by the pointer is the first logical block that is updated to the second state first, and the second logical block corresponding to the first logical block pointed to by the pointer can be allocated; thus, the first logical block to be allocated can be quickly located through the pointer.

[0103] In an exemplary embodiment, the method may further include: assigning the first logic block pointed to by the pointer to one of the N second logic blocks, and sequentially pointing the pointer to the next first logic block.

[0104] For example, if the pointer points to the first logical block that corresponds to identifier 1 and the allocation status of the first logical block is in the second state, then it is necessary to first de-allocate the second logical block that the first logical block has been allocated to, update the allocation status of the first logical block to the first state, then allocate the first logical block to the second logical block that currently meets the recommendation criteria (which is not the same second logical block that was previously allocated), update the allocation status of the first logical block to the second state, and then point the pointer to the second logical block that corresponds to identifier 2.

[0105] Figure 22 This illustration shows a flowchart of another method of operating a memory system according to an embodiment of the present disclosure, such as... Figure 22 As shown, the operation method of the memory system provided in this embodiment may include the following steps.

[0106] In step S2202, a second logic block that meets the recommended criteria is identified.

[0107] In some embodiments, when it is determined that a second logical block that meets the recommended criteria exists, the following step S2204 may be performed.

[0108] In step S2204, it is determined whether the allocation state of the first logic block currently pointed to by the pointer is the first state.

[0109] In some embodiments, if the allocation state of the first logical block currently pointed to by the pointer is a first state, then step S2206 is executed; if the allocation state of the first logical block currently pointed to by the pointer is not a first state, then step S2208 is executed.

[0110] In step S2206, the first logic block currently pointed to by the pointer is assigned to the second logic block that meets the recommended criteria.

[0111] In step S2208, the second logical block corresponding to the first logical block currently pointed to by the pointer is allocated, the allocation state of the first logical block currently pointed to by the pointer is updated to the first state, and the first logical block currently pointed to by the pointer is allocated to the second logical block that meets the recommended criteria.

[0112] In step S2210, the allocation state of the first logical block currently pointed to by the pointer is updated from the first state to the second state.

[0113] In step S2212, the pointer is moved to the next first logic block according to the order of the identifiers of the M first logic blocks in the circular queue.

[0114] Figure 22 Other details of the embodiments can be found in the textual description of the above method embodiments, and repeated details will not be repeated.

[0115] In an exemplary embodiment, the method further includes: allocating Y first logic blocks in the first allocation state to Y second logic blocks out of N second logic blocks, where Y is an integer greater than 1 and less than M, and updating the allocation state of the Y first logic blocks in the logic block management table from the first state to a third state indicating "allocated and fixed".

[0116] In some embodiments, when the system is initialized, Y of the N second logical blocks are used to store relevant configuration information. That is, these Y second logical blocks are logical blocks used to store configuration information (also called Pinned Regions). After initialization, the information stored in these Y second logical blocks (Pinned Regions) will not change significantly.

[0117] In some embodiments, for the Y second logical blocks (Pinned Regions), Y first logical blocks in a first state are allocated to them, and the allocation status of these Y first logical blocks in the logical block management table is updated to a third state. After the Y first logical blocks are allocated to the Y second logical blocks (Pinned Regions), the allocation status of these Y first logical blocks basically does not change. The mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) is sent to the host 310. The host 310 then requests the L2P mapping tables corresponding to the Y second logical blocks (Pinned Regions) according to the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions). The memory system 320 then sends the L2P mapping tables corresponding to the Y second logical blocks (Pinned Regions) to the host 310 for storage in the host memory 312. The mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) will remain largely unchanged after initialization. Therefore, when updating the mapping relationship between the first logical blocks and the second logical blocks in the future, the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) does not need to be repeatedly sent to host 310.

[0118] In an exemplary embodiment, Y consecutive first logic blocks in the circular queue, each in a first state, can be fixedly assigned to Y second logic blocks (Pinned Regions).

[0119] In some embodiments, Y consecutive first logic blocks at the head of the circular queue with a first allocation state can be fixedly assigned to Y second logic blocks (Pinned Regions). Alternatively, Y consecutive first logic blocks at the tail of the circular queue with a first allocation state can be fixedly assigned to Y second logic blocks (Pinned Regions). Or, Y consecutive first logic blocks at the middle of the circular queue with a first allocation state can be fixedly assigned to Y second logic blocks (Pinned Regions).

[0120] For example, refer to Figure 7The Y consecutive first logic blocks 602 corresponding to the identifiers of the (M-Y+1)th to the Mth first logic blocks in the circular queue are allocated to the Y second logic blocks (Pinned Regions). Alternatively, the Y first logic blocks corresponding to the identifiers of the 1st to the Yth consecutive first logic blocks in the circular queue can also be allocated to the Y second logic blocks (Pinned Regions). In other alternative embodiments, the Y first logic blocks fixed to be allocated to the Y second logic blocks (Pinned Regions) can be randomly determined in advance in the circular queue.

[0121] In an exemplary embodiment, when allocating a first logic block to a second logic block that meets the recommended criteria, the allocation of first logic blocks in the third state can be skipped according to the order of the identifiers of the M first logic blocks in the circular queue.

[0122] In some embodiments, after determining Y first logic blocks whose allocation state is the third state, the identifiers of these Y first logic blocks can be recorded; when allocating the first logic blocks corresponding to the identifiers of these Y first logic blocks according to the order of the identifiers of the M first logic blocks in the circular queue, these Y first logic blocks are skipped.

[0123] For example, refer to Figure 7 In the circular queue 600, the first logic blocks 602 from (M-Y+1) to M are in the third state. After the (MY)th first logic block is assigned to the corresponding second logic block, the first logic blocks from (M-Y+1) to M are skipped, and the first logic block is assigned to the corresponding second logic block.

[0124] In some embodiments, the circular queue includes pointers that can be used to skip the first logical block whose allocation state is in the third state.

[0125] For example, after assigning the Y consecutive first logic blocks corresponding to the identifiers of the (M-Y+1)th to Mth first logic blocks in the circular queue to the Y second logic blocks, if a certain first logic block belongs to the 1st to (MY-1)th first logic blocks, the pointer is pointed to the next first logic block of that first logic block.

[0126] For example, refer to Figure 7 If the first logical block pointed to by pointer 601 is the first first logical block and its allocation status is in the first state, then the first first logical block can be directly allocated to the second logical block that currently meets the recommended criteria, and the allocation status of the first first logical block can be updated to the second state. Then, pointer 601 can be set to point to the second first logical block. Figure 8As shown; for example, if the first logical block pointed to by pointer 601 is the second first logical block, the second first logical block can be directly assigned to the second logical block that currently meets the recommended criteria, and the assignment status of the second first logical block can be updated to the second status, and pointer 601 can be pointed to the third first logical block, and so on.

[0127] In some embodiments, when a first logic block is the (MY)th first logic block, the pointer is pointed to the first first logic block.

[0128] For example, refer to Figure 9 When the first logical block pointed to by pointer 601 is the (MY)th first logical block and the allocation state of the (MY)th first logical block is the first state, the (MY)th first logical block can be directly allocated to the second logical block that currently meets the recommendation criteria, and the allocation state of the (MY)th first logical block is updated to the second state. Then, pointer 601 is pointed to the first first logical block. At this time, the pointer skips the (M-Y+1)th to the Mth first logical blocks 602 in the circular queue whose allocation state is the third state.

[0129] refer to Figure 9 and Figure 10 When the first logical block pointed to by pointer 601 is the first first logical block and the allocation status of the first first logical block is the second state, it is necessary to first allocate the second logical block that the first first logical block has been allocated to, update the allocation status of the first first logical block to the first state, then allocate the first first logical block to the second logical block that currently meets the recommendation criteria (which is not the same second logical block that has been previously allocated), update the allocation status of the first first logical block to the second state, and point pointer 601 to the second first logical block. In this way, the circular queue can be used to quickly manage and allocate logical block resources.

[0130] In an exemplary embodiment, the method further includes updating the identifier of a first logical block or the identifier of a second logical block in the logical block management table.

[0131] The logic block management table in this embodiment of the disclosure can be as follows: Figures 11-15 The logical block management table A shown can also be as follows: Figures 16-20 The logical block management table B shown can be 8K or N can be 32K.

[0132] The following is based on Figures 11-15 Taking the logic block management table A shown as an example, this section explains how to update the identifier of the second logic block in the logic block management table.

[0133] Reference Figure 6 and Figure 11 In the logic block management table A, the first column is the identifier of the first logic block, the second column is the identifier of the second logic block to which the first logic block is allocated, and the third column is the allocation status of the first logic block. In the initial stage, the first column is the identifier of the first logic block 1~M. At this time, the first logic block has not been allocated. Therefore, the identifier of the second logic block in the second column is the initial value, such as 0. The allocation status in the third column is the first state, that is, the unallocated state.

[0134] Reference Figure 7 and Figure 12 Assign the Y first logical blocks 602 corresponding to the identifiers of the (M-Y+1)th to Mth first logical blocks in the circular queue 600 to the Y second logical blocks (Pinned Region); update the identifiers of the second logical blocks corresponding to the identifiers of the (M-Y+1)th to Mth first logical blocks in the logical block management table A to X to Z, and update the allocation status corresponding to the identifiers of the (M-Y+1)th to Mth first logical blocks in the logical block management table A to the third status.

[0135] Reference Figure 7 , Figure 8 and Figure 13 For example, if the second logical block that currently meets the recommended criteria is the second logical block marked as 1; and if the first logical block pointed to by pointer 601 is the first first logical block and the allocation status of the first first logical block is in the first state, then the first first logical block can be directly allocated to the second logical block marked as 1; the identifier of the second logical block corresponding to the identifier of the first first logical block in the logical block management table A is updated to 1, the allocation status corresponding to the identifier of the first first logical block in the logical block management table A is updated to the second state, and pointer 601 is set to point to the second first logical block, and so on, ... (refer to the reference). Figure 9 and Figure 14 For example, if the second logical block that currently meets the recommended criteria is the second logical block identified as (MY); and if the first logical block pointed to by pointer 601 is the (MY)th first logical block and the allocation status of the (MY)th first logical block is in the first state, then the (MY)th first logical block can be directly allocated to the second logical block identified as (MY), the identifier of the second logical block corresponding to the identifier of the (MY)th first logical block in the logical block management table A is updated to (MY), the allocation status of the (MY)th first logical block is updated to the second state, and pointer 601 is set to point to the first first logical block; in conjunction with reference... Figure 9 , Figure 10 and Figure 15For example, the second logical block that currently meets the recommended criteria is the second logical block identified as (M-Y+1). When the first logical block pointed to by pointer 601 is the first first logical block and the allocation status of the first first logical block is the second state, it is necessary to first allocate the second logical block that the first first logical block has been allocated to (i.e., the second logical block identified as 1), and then allocate the first first logical block to the second logical block identified as (M-Y+1). The identifier of the second logical block corresponding to the identifier of the first first logical block in the logical block management table A is updated from 1 to (M-Y+1), and the pointer is pointed to the second first logical block.

[0136] The following is based on Figures 16-20 Taking the logic block management table B shown as an example, this section explains how to update the identifier of the first logic block in the logic block management table.

[0137] Reference Figure 6 and Figure 16 In the logical block management table B, the first column is the identifier of the second logical block, the second column is the identifier of the first logical block that has been allocated to the second logical block, and the third column is the allocation status of the first logical block. In the initial stage, the first column is the identifier of the second logical block from 1 to N. At this time, the first logical blocks have not been allocated, so the identifier of the first logical block in the second column is the initial value, for example, all are 0. The allocation status in the third column is the first state, that is, the unallocated state.

[0138] Reference Figure 7 and Figure 17 Assign the Y first logical blocks corresponding to the identifiers of the (M-Y+1)th to the Mth first logical blocks in the circular queue 600 to the Y second logical blocks (Pinned Region); update the identifiers of the first logical blocks corresponding to the identifiers of the Xth to Zth second logical blocks in the logical block management table B to (M-Y+1) to M, and update the allocation status corresponding to the identifiers of the (M-Y+1)th to Mth first logical blocks in the logical block management table B to the third status.

[0139] Reference Figure 7 , Figure 8 and Figure 18 For example, if the second logical block that currently meets the recommendation criteria is the second logical block marked as 1; and if the first logical block pointed to by pointer 601 is the first first logical block and the allocation status of the first first logical block is in the first state, then the first first logical block can be directly allocated to the second logical block marked as 1; the identifier of the first logical block corresponding to the identifier of the first second logical block in the logical block management table B is updated to 1, the allocation status corresponding to the first logical block marked as 1 in the logical block management table B is updated to the second state, and pointer 601 is pointed to the second first logical block, and so on, ..., in conjunction with the reference Figure 9 and Figure 19 For example, if the second logical block that currently meets the recommended criteria is the second logical block identified as 0x5999; and if the first logical block pointed to by pointer 601 is the (MY)th first logical block and the allocation status of the (MY)th first logical block is in the first state, then the (MY)th first logical block can be directly allocated to the second logical block identified as 0x5999. The identifier of the first logical block corresponding to the second logical block identified as 0x5999 in the logical block management table B will be updated to (MY), the allocation status of the (MY)th first logical block will be updated to the second state, and pointer 601 will be set to point to the first first logical block; (Refer to the reference...) Figure 9 , Figure 10 and Figure 20 For example, if the second logical block that currently meets the recommended criteria is the second logical block identified as 0x6E2D; and if the first logical block pointed to by pointer 601 is the first first logical block and the allocation status of the first first logical block is the second status, then it is necessary to first allocate the second logical block that the first first logical block has already been allocated to (i.e., the second logical block identified as 1), update the identifier of the first logical block corresponding to the second logical block identified as 1 in the logical block management table B to an invalid value (e.g., it could be 0x7FFF), and update the status of the first logical block identified as invalid to the first status; then allocate the first first logical block to the second logical block identified as 0x6E2D, update the identifier of the first logical block corresponding to the second logical block identified as 0x6E2D in the logical block management table B to 1, and point the pointer to the second first logical block.

[0140] In an exemplary embodiment, the above method may further include: sending the updated logical block management table to the host, and sending the logical address-physical address mapping table (L2P mapping table) corresponding to a certain second logical block in the logical block management table to the host.

[0141] In this embodiment of the present disclosure, the memory controller 330 may send a logic block management table to the host 310 at preset time intervals, or it may obtain an updated logic block management table after allocating a first logic block to the new second logic block that conforms to the recommended criteria each time a new second logic block conforming to the recommended criteria appears, and then send the updated logic block management table to the host 310; after receiving the recommended second logic block and the mapping relationship between the first logic block and the second logic block, the host 310 may obtain the logical address-physical address mapping table (i.e., L2P mapping table) corresponding to the recommended second logic block from the memory system 320, and store the L2P mapping table in the host memory 312.

[0142] The memory system operation method provided in this disclosure has the following advantages: First, it enables dynamic management of the allocation status of the first logical block and the allocation relationship between the first and second logical blocks through a logical block management table. Second, it enables fast and efficient searching of the first logical block by constructing a circular queue based on the identifiers of the M first logical blocks, and enables rapid allocation of the corresponding first logical block to the second logical block that meets the recommended criteria among the N second logical blocks, thereby improving resource allocation efficiency, random read performance, and system performance.

[0143] In some embodiments, when there is no first logical block in the first allocation state, the earliest allocated first logical block can be located quickly and efficiently through a circular queue, thereby enabling the rapid allocation of the corresponding first logical block to the second logical block that meets the recommended criteria among N second logical blocks.

[0144] refer to Figure 3 This disclosure provides a memory system 320, including: a memory device 340, and a memory controller 330 coupled to the memory device 340 and controlling the memory device 340 to perform data storage operations; the memory controller 330 includes an interface (i.e., a host interface 332) coupled to and communicating with a host 310; the host interface 332 coupled to and communicating with the host 310 is configured to sequentially send at least a portion of the mapping information from a first logic block management table and a second logic block management table to the host 310.

[0145] The first and second logic block management tables each represent the mapping relationship between the first and second logic blocks at different times. Both tables include a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table, where M is an integer greater than or equal to 2. Each table includes the identifiers of K first logic blocks whose allocation status at different times indicates that they have been allocated, and the identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, where K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M. The first logic block that is allocated first among the K first logic blocks in the first logic block management table is updated and allocated to a second logic block among the K second logic blocks in the second logic block management table, reflecting the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0146] In this embodiment of the present disclosure, the host interface 332 may send all the mapping information in the first logical block management table and the second logical block management table to the host 310 in sequence, or it may send part of the mapping information in the first logical block management table and the second logical block management table (e.g., the mapping information in the second logical block management table that has been updated relative to the first logical block management table).

[0147] In one embodiment, the first logical block management table may be Figure 11 The logical block management table shown (i.e., the initial state of the logical block management table, where the allocation state corresponding to the first logical block is always unallocated) and the second logical block management table can be... Figure 12 The logical block management table shown may include... Figure 12 The bolded entries in the logical block management table shown here represent the fixed allocation of Y first logical blocks to Y second logical blocks (Pinned Regions).

[0148] The table managed by the first logical block is as follows Figure 11 The logic block management table and the second logic block management table shown are as follows: Figure 12 Taking the logical block management table shown as an example, when the host interface 332 sends the first logical block management table to the host 310, because... Figure 11 The logical block management table shown is in its initial state. At this time, host interface 332 sends data to host 310. Figure 11 The logical block management table shown contains all mapping entries; then host interface 332 sends the second logical block management table to host 310, at which point host interface 332 can send... Figure 12 All mapping entries in the logical block management table shown can also be sent. Figure 12 The logical block management table shown is relative to Figure 11 The mapping entries updated in the logical block management table shown (i.e. Figure 12 The bold entries in the logical block management table shown (i.e., the mapping entries corresponding to Y fixed first logical blocks and Y fixed allocations of the first logical blocks to Y second logical blocks (Pinned Regions)) indicate that the allocation status of these Y first logical blocks basically no longer changes. After sending the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) to host 310, the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) does not need to be repeatedly sent to host 310 when updating the mapping relationship between the first logical blocks and the second logical blocks in the future.

[0149] In one embodiment, the first logical block management table may be Figure 12 The logical block management table shown may include... Figure 12The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 13 The logical block management table shown may include... Figure 13 The bolded entries in the logic block management table shown here (i.e., the first first logic block is assigned to the first second logic block).

[0150] The table managed by the first logical block is as follows Figure 12 The logical block management table and the second logical block management table shown are examples of the logical block management table shown in Figure 13. When the host interface 332 sends the first logical block management table to the host 310, the host interface 332 can send... Figure 12 All mapping entries in the logical block management table shown can also be sent. Figure 12 The logical block management table shown is relative to Figure 11 The mapping entries updated in the logical block management table shown (i.e. Figure 12 The bolded entries in the logical block management table shown (i.e., the mapping entries corresponding to the Y fixed first logical blocks and the Y fixed allocation of the Y first logical blocks to the Y second logical blocks (Pinned Regions)) are then sent by host interface 332 to host 310. At this time, host interface 332 can send the second logical block management table to host 310. Figure 13 All mapping entries in the logical block management table shown can also be sent. Figure 13 The logical block management table shown is relative to Figure 12 The mapping entries updated in the logical block management table shown (i.e. Figure 13 The bolded entries in the logic block management table shown (i.e., the mapping entries corresponding to the first logic block identifier being 1 and the second logic block identifier being 1)).

[0151] In one embodiment, the first logical block management table may be Figure 13 The logical block management table shown may include... Figure 13 The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 14 The logical block management table shown may include... Figure 14 The first logical block identifier in the logical block management table shown is the mapping entry corresponding to 1~MY (that is, the first to (MY)th first logical blocks are respectively assigned to the first to (MY)th second logical blocks).

[0152] Taking a first logical block management table as shown in Figure 13 and a second logical block management table as shown in Figure 14 as an example, when host interface 332 sends the first logical block management table to host 310, host interface 332 can send to host 310... Figure 13 All mapping entries in the logical block management table shown can also be sent. Figure 13The logical block management table shown is relative to Figure 12 The mapping entries updated in the logical block management table shown (i.e. Figure 13 The bold entries in the logical block management table are shown; then host interface 332 sends the second logical block management table to host 310, at which point host interface 332 can send... Figure 14 All mapping entries in the logical block management table shown can also be sent. Figure 14 The logical block management table shown is relative to Figure 13 The mapping entries updated in the logical block management table shown (i.e. Figure 14 The first logical block identifier in the logical block management table shown is the mapping entry corresponding to 1~MY.

[0153] In one embodiment, the first logical block management table may be Figure 14 The logical block management table shown may include... Figure 14 The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 15 The logical block management table shown may include... Figure 15 The bolded entries in the logic block management table shown.

[0154] Taking a first logical block management table as shown in Figure 14 and a second logical block management table as shown in Figure 15 as an example, when host interface 332 sends the first logical block management table to host 310, host interface 332 can send to host 310... Figure 14 All mapping entries in the logical block management table shown can also be sent. Figure 14 The logical block management table shown is relative to Figure 13 The mapping entries updated in the logical block management table shown (i.e. Figure 14 The first logical block identifier in the logical block management table shown is the mapping entry corresponding to 1~MY); then the host interface 332 sends the second logical block management table to the host 310. At this time, the host interface 332 can send the second logical block management table to the host 310. Figure 15 All mapping entries in the logical block management table shown can also be sent. Figure 15 The logical block management table shown is relative to Figure 14 The mapping entries updated in the logical block management table shown (i.e. Figure 15 (The bolded entries in the logical block management table shown).

[0155] The first logical block manages the table. Figure 14 The logic block management table and the second logic block management table shown are Figure 15 Taking the logical block management table shown as an example, in Figure 14The first logical block that is allocated first among the K first logical blocks in the first logical block management table shown (i.e., the first logical block corresponding to identifier 1) is updated and allocated to a certain second logical block among the K second logical blocks in the second logical block management table (i.e., the second logical block corresponding to identifier (M-Y+1)).

[0156] In one embodiment, the first logical block management table may be Figure 16 The logical block management table shown can be a second logical block management table. Figure 17 The logical block management table shown may include... Figure 17 The bolded entries in the logic block management table shown.

[0157] In one embodiment, the first logical block management table may be Figure 17 The logical block management table shown may include... Figure 17 The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 18 The logical block management table shown may include... Figure 18 The bolded entries in the logic block management table shown.

[0158] In one embodiment, the first logical block management table may be Figure 18 The logical block management table shown may include... Figure 18 The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 19 The logical block management table shown may include... Figure 19 The bolded entries in the logic block management table shown.

[0159] In one embodiment, the first logical block management table may be Figure 19 The logical block management table shown may include... Figure 19 The bolded portion of the logic block management table shown indicates that the second logic block management table can be... Figure 20 The logical block management table shown may include... Figure 20 The bolded entries in the logic block management table shown.

[0160] In some embodiments, the first logical block management table and the second logical block management table can be the logical block management table between two consecutive updates of the first logical block and the second logical block sent by the host interface 332 to the host 310. The memory controller 330 can update the logical block management table at preset time intervals and send the updated logical block management table to the host via the host interface 332. In this case, the first logical block management table is the logical block management table sent by the host interface 332 to the host 310 at time T1 to update the L2P mapping table stored in the host memory 312, and the second logical block management table is the logical block management table sent by the host interface 332 to the host 310 at time T2. The time difference between time T1 and time T2 is the preset time interval. The memory controller 330 can also send the updated logical block management table to the host 310 via the host interface 332 after each logical block management table update to update the L2P mapping table stored in the host memory 312. The memory controller 330 can also send the updated logical block management table to the host 310 via the host interface 332 after the number of updated mapping relationships between the first and second logical blocks reaches a certain number to update the L2P mapping table stored in the host memory 312.

[0161] In some embodiments, the first logic block management table includes a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table. The first logic block management table may include the identifiers of K first logic blocks whose allocation status at a first time is a second state indicating that they have been allocated, and the identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated at the first time. The second logic block management table includes a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table. The second logic block management table may include the identifiers of the K first logic blocks whose allocation status at the second time step indicates that they have been allocated (the identifiers of the K first logic blocks in the second logic block management table are different from those of the K first logic blocks in the first logic block management table), and the identifiers of the K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated at the second time step; the first first logic block that is allocated first among the K first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block among the K second logic blocks in the second logic block management table, so as to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0162] In some exemplary embodiments of this disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and N second logic blocks cover the entire physical address of the memory device of the memory system.

[0163] In some exemplary embodiments of this disclosure, both the first logical block management table and the second logical block management table include Y identifiers of first logical blocks whose allocation status is a third state indicating that they have been allocated and are fixed, and Y identifiers of the first logical blocks to which Y second logical blocks are allocated, where Y is an integer greater than 1, and the sum of Y and K is less than or equal to M; the host interface 332 is configured to send K mapping information updated relative to the first logical block management table in the second logical block management table to the host 310.

[0164] In this embodiment of the disclosure, when Y first logical blocks are fixedly allocated to Y second logical blocks (PinnedRegions), the allocation status of these Y first logical blocks in the logical block management table is updated to the third status. After updating the logical block management table, the host interface 332 sends the updated logical block management table to the host 310 (e.g., as shown in the image). Figure 12 The logical block management table shown may include, for example, a table containing, logical blocks. Figure 12 (The bolded entries in the logical block management table shown). When updating and sending the logical block management table later, only the updated entries (e.g., the K updated mapping information) can be sent, without repeatedly sending the Y mapping information corresponding to the first Y logical blocks in the logical block management table and other unupdated entries.

[0165] In some exemplary embodiments of this disclosure, host interface 332 is also configured to send a logical address-physical address mapping table corresponding to a certain second logical block to host 310.

[0166] Figure 23 This diagram illustrates the interaction between a host and memory system according to an embodiment of the present disclosure.

[0167] In this embodiment of the disclosure, reference is made to Figure 23 The interaction process between the host 310 and the memory system 320 may include the following steps.

[0168] In step S2301, the host interface 332 in the memory controller 330 sends the first logical block management table to the host 310.

[0169] In this embodiment of the present disclosure, the host interface 332 may send a first logical block management table to the host 310, or send partial mapping information in the first logical block management table to the host 310; the first logical block management table (or partial mapping information in the first logical block management table) sent by the host interface 332 to the host 310 includes at least one mapping relationship between the first logical block and the second logical block.

[0170] In step S2302, the host 310 requests the L2P mapping table corresponding to the second logical block included in the first logical block management table from the memory system 320.

[0171] In this embodiment of the present disclosure, after the host 310 receives the first logical block management table (or part of the mapping information in the first logical block management table), it requests the memory system 320 the L2P mapping table corresponding to the second logical block included in the received first logical block management table (or part of the mapping information in the first logical block management table).

[0172] In step S2303, the host interface 332 in the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the first logical block management table to the host 310. The L2P mapping table corresponding to the second logical block included in the first logical block management table is stored in the host memory 312 in the host 310.

[0173] In this embodiment of the present disclosure, in response to a request for an L2P mapping table sent by the host 310, the memory system 320 sends the L2P mapping table corresponding to the second logical block included in the first logical block management table (or part of the mapping information in the first logical block management table) to the host 310 for storage in the host memory 312.

[0174] In step S2304, the host interface 332 in the memory controller 330 sends the second logic block management table to the host 310.

[0175] In this embodiment of the present disclosure, the memory controller 330 may send a logic block management table to the host 310 at preset time intervals. The logic block management tables sent sequentially at preset time intervals are the first logic block management table and the second logic block management table.

[0176] In this embodiment of the disclosure, the memory controller 330 may also, after allocating a first logic block to the new second logic block that conforms to the recommended criteria each time a new second logic block that conforms to the recommended criteria appears, obtain an updated logic block management table, and send the updated logic block management table to the host 310. The logic block management table before each update is the first logic block management table, and the logic block management table after the update is the second logic block management table.

[0177] In this embodiment of the present disclosure, the host interface 332 may send a second logical block management table to the host 310, or send partial mapping information in the second logical block management table to the host 310; the second logical block management table (or partial mapping information in the second logical block management table) sent by the host interface 332 to the host 310 includes at least one mapping relationship between the first logical block and the second logical block.

[0178] In step S2305, the host 310 requests the L2P mapping table corresponding to the second logical block included in the second logical block management table from the memory system 320.

[0179] In this embodiment of the present disclosure, after the host 310 receives the second logical block management table (or part of the mapping information in the second logical block management table), it requests the memory system 320 the L2P mapping table corresponding to the second logical block included in the received second logical block management table (or part of the mapping information in the second logical block management table).

[0180] In step S2306, the host interface 332 in the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the second logical block management table to the host 310. The L2P mapping table corresponding to the second logical block included in the second logical block management table is stored in the host memory 312 in the host 310.

[0181] In this embodiment of the present disclosure, in response to a request for an L2P mapping table sent by the host 310, the memory system 320 sends the L2P mapping table corresponding to the second logical block included in the second logical block management table (or part of the mapping information in the second logical block management table) to the host 310 for storage in the host memory 312.

[0182] refer to Figure 3 This disclosure provides a memory system 320, including: a memory device 340, and a memory controller 330 coupled to the memory device 340 and controlling the memory device 340 to perform data storage operations; the memory controller 330 includes an interface (i.e., a host interface 332) coupled to and communicating with a host 310; the host interface 332 is configured to send a first mapping relationship and a second mapping relationship to the host 310 sequentially after two consecutive logical block management table updates are triggered.

[0183] The first mapping relationship includes P mapping information entries for the first and second logical blocks, which are included in the first logical block management table. The second mapping relationship includes Q mapping information entries for the first and second logical blocks, which are included in the second logical block management table. Both the first and second logical block management tables include a first sequence of identifiers corresponding to M first logical blocks. The identifiers of the M first logical blocks are constructed into a circular queue, and the allocation status of the M first logical blocks is managed through the logical block management table. M is an integer greater than or equal to 2, and P and Q are integers greater than or equal to 1 and less than or equal to M. The first first logical block that is allocated first among the M first logical blocks corresponding to the first logical block management table is updated and allocated to a second logical block among the Q second logical blocks in the second logical block management table, so as to reflect the update of the mapping relationship in the second logical block management table relative to the mapping relationship in the first logical block management table.

[0184] In this embodiment of the disclosure, after a certain update of the logical block management table (the updated logical block management table is referred to as the first logical block management table), the host interface 332 sends the updated mapping information (e.g., P mapping information) in the first logical block management table to the host 310; after a certain next update (the updated logical block management table is referred to as the second logical block management table), the host interface 332 sends the updated mapping information (e.g., Q mapping information) in the second logical block management table to the host 310.

[0185] In one embodiment, the first logical block management table obtained in a certain update may be Figure 12 The logical block management table shown can contain updated mapping information. Figure 12 The mapping information in bold can be sent from host interface 332 to host 310. Figure 12 The mapping information in bold; the second logical block management table obtained in the next update can be... Figure 13 The logical block management table shown can contain updated mapping information. Figure 13 The mapping information in bold can be sent from host interface 332 to host 310. Figure 13 The mapping information in bold.

[0186] In this embodiment of the disclosure, when the host interface 332 sends updated mapping information to the host 310, it can send the information to the host 310 one by one in the form of mapping entries. Each mapping entry can include at least the identifier of the first logical block and the identifier of the second logical block.

[0187] The updated mapping information is Figure 12 Taking the mapping information of the bold symbol as an example, host interface 332 can send to host 310 Figure 12 The mapping entry with the first logical block identified as M-Y+1 and the second logical block identified as X is then sent from host interface 332 to host 310. Figure 12 The mapping entries are as follows: the first logical block is identified as M-Y+2, the second logical block is identified as X+1, ..., and then the host interface 332 sends to the host 310. Figure 12 The mapping entries are identified as M for the first logical block and Z for the second logical block.

[0188] The updated mapping information is Figure 14 Taking the mapping information corresponding to the first logical block identifier 1~MY as an example, host interface 332 can send to host 310. Figure 14 The mapping entries are set with the first logical block identified as 1 and the second logical block identified as 1. Then, host interface 332 can send to host 310. Figure 14The mapping entries with identifier 2 for the first logical block, identifier 2 for the second logical block, ..., can be sent from host interface 332 to host 310. Figure 14 The first logical block is identified as MY and the second logical block is identified as MY. That is, the host interface can send the updated mapping information to the host 310 one by one in the form of mapping entries.

[0189] In one embodiment, the first logical block management table obtained in a certain update may be Figure 14 The logical block management table shown can contain updated mapping information. Figure 14 The mapping information in bold can be sent from host interface 332 to host 310. Figure 14 The mapping information in bold; the second logical block management table obtained in the next update can be... Figure 15 The logical block management table shown can contain updated mapping information. Figure 15 The mapping information in bold can be sent from host interface 332 to host 310. Figure 15 The mapping information in bold.

[0190] The first logical block manages the table. Figure 14 The logic block management table and the second logic block management table shown are Figure 15 Taking the logical block management table shown as an example, in Figure 14 The first logical block that is allocated first among the M first logical blocks in the first logical block management table shown (i.e., the first logical block corresponding to identifier 1) is updated and allocated to a certain second logical block among the Q second logical blocks in the second logical block management table (i.e., the second logical block corresponding to identifier (M-Y+1)).

[0191] In one embodiment, the first logical block management table obtained in a certain update may be Figure 17 The logical block management table shown can contain updated mapping information. Figure 17 The mapping information in bold can be sent from host interface 332 to host 310. Figure 17 The mapping information in bold; the second logical block management table obtained in the next update can be... Figure 18 The logical block management table shown can contain updated mapping information. Figure 18 The mapping information in bold can be sent from host interface 332 to host 310. Figure 18 The mapping information in bold.

[0192] Since the principle of solving the problem in this system embodiment is similar to that in the above method embodiment, the implementation of this system embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be described again.

[0193] This disclosure provides a non-transitory computer-readable storage medium storing computer instructions thereon, wherein the computer instructions, when executed, perform the operation method of any of the memory systems described above. The computer instructions are adapted to be loaded by a processor and execute the operation method of the memory system provided in each step of any of the above embodiments; specific implementations of each step in any of the above embodiments can be found therein, and will not be repeated here. Furthermore, descriptions of the beneficial effects of using the same method will not be repeated here either. For technical details not disclosed in the embodiments of the computer-readable storage medium involved in this disclosure, please refer to the description of the method embodiments of this disclosure. As an example, a computer program may be deployed to execute on a single computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed across multiple locations and interconnected via a communication network.

[0194] This disclosure also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in various alternative embodiments described above.

[0195] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0196] The methods and related apparatus provided in this disclosure are described with reference to the method flowcharts and / or structural diagrams provided in this disclosure. Specifically, each block of the method flowchart and / or structural diagram, as well as combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable application display device to create a machine, such that the instructions, which execute via the processor of the computer or other programmable application display device, generate instructions for implementing the process... Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable application display device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable application display device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 A process or multiple processes and / or structures illustrate the steps of the functions specified in one or more boxes.

[0197] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope of this disclosure is indicated by the appended claims.

Claims

1. A method of operating a memory system, comprising: A logic block management table is provided, which includes a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table, where M is an integer greater than or equal to 2. as well as According to the order of the identifiers of the M first logic blocks in the circular queue, a first logic block whose allocation status is an unallocated first state is allocated to a second logic block among N second logic blocks, where N is an integer greater than M, and the allocation status of the first logic block is updated from the first state to a second state indicating that it has been allocated in the logic block management table.

2. The method as described in claim 1, wherein, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system.

3. The method as described in claim 1, wherein, Also includes: If there is no corresponding first logical block with the first allocation state in the circular queue, the second logical block corresponding to the first logical block that was first updated to the second state will be allocated, and the allocation state corresponding to the first logical block that was first identified as the second state will be updated to the first state.

4. The method of claim 1, wherein, The circular queue includes pointers configured to point sequentially to one of the M first logical blocks in the order of their identifiers in the circular queue. The method further includes: In response to the first logical block pointed to by the pointer being allocated to the second state, the second logical block corresponding to the first logical block that was first updated to the second state is allocated, and the allocation state corresponding to the first logical block that was first identified as the second state is updated to the first state.

5. The method of claim 4, wherein, Also includes: The pointer is assigned to a first logic block among the N second logic blocks, and the pointer is then assigned to the next first logic block in the specified order.

6. The method according to any one of claims 1-5, wherein, Also includes: The Y first logic blocks, which are in the first allocation state, are allocated to Y second logic blocks out of N second logic blocks, where Y is an integer greater than 1 and less than M. The allocation state of the Y first logic blocks is then updated in the logic block management table from the first state to a third state, which indicates that the blocks have been allocated and are fixed.

7. The method according to claim 6, wherein, Assigning the Y first logic blocks, which are in the first allocation state, to the Y second logic blocks out of the N second logic blocks includes: The Y consecutive first logic blocks in the circular queue that are in the first allocation state are allocated to the Y second logic blocks.

8. The method according to claim 6, wherein, According to the order of the identifiers of the M first logic blocks in the circular queue, skip the first logic blocks whose allocation state is the third state.

9. The method according to claim 1, wherein, The logic block management table also includes a second sequence of identifiers corresponding to the N second logic blocks; The method further includes: Update the identifier of a first logical block or the identifier of a second logical block in the logical block management table.

10. The method according to claim 1, wherein, The number of elements in the circular queue is the same as the number of the first logical blocks, and each element stores the identifier of the corresponding first logical block and the allocation status of the first logical block.

11. The method according to claim 1, wherein, The size of the first logic block is the same as the size of the second logic block.

12. The method according to claim 1, wherein, Also includes: Send the updated logical block management table to the host.

13. The method according to claim 12, wherein, Also includes: Send the L2P mapping table corresponding to a certain second logical block to the host.

14. A memory system, comprising: A memory device, and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; The memory controller includes an interface for communication with a host computer; The interface is configured to send at least a portion of the mapping information from the first logical block management table and the second logical block management table to the host in sequence; Wherein, the first logic block management table and the second logic block management table each represent the mapping relationship between the first logic block and the second logic block at different times. The first logic block management table and the second logic block management table each include a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table. M is an integer greater than or equal to 2. The first logic block management table and the second logic block management table each include the identifiers of K first logic blocks whose allocation status at different times indicates that they have been allocated in the second state, and the identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, where K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M. The first first logical block that is allocated in the K first logical blocks corresponding to the first logical block management table is updated and allocated to a second logical block among the K second logical blocks in the second logical block management table, so as to reflect the update of the mapping relationship of the second logical block management table relative to the mapping relationship of the first logical block management table.

15. The system of claim 14, wherein, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system.

16. The system of claim 14, wherein, Both the first logic block management table and the second logic block management table include Y identifiers of first logic blocks whose allocation status is a third state indicating that they have been allocated and are fixed, and Y identifiers of the Y first logic blocks to which they are allocated to Y second logic blocks, where Y is an integer greater than 1, and the sum of Y and K is less than or equal to M. The interface is configured to send K mapping entries from the second logical block management table that are updated relative to the first logical block management table to the host.

17. The system of claim 14, wherein, The interface is also configured to send the L2P mapping table corresponding to a certain second logical block to the host.

18. A memory system comprising: A memory device, and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; The memory controller includes an interface for communication with a host computer; The interface is configured to send the first mapping relationship and the second mapping relationship to the host sequentially after two consecutive logical block management table updates are triggered. Wherein, the first mapping relationship includes P mapping information of the first logic block and the second logic block, the P mapping information is included in the first logic block management table, the second mapping relationship includes Q mapping information of the first logic block and the second logic block, the Q mapping information is included in the second logic block management table, the first logic block management table and the second logic block management table both include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed into a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table, M is an integer greater than or equal to 2, and P and Q are both integers greater than or equal to 1 and less than or equal to M; The first first logical block that is allocated first among the M first logical blocks corresponding to the first logical block management table is updated and allocated to a second logical block among the Q second logical blocks in the second logical block management table, so as to reflect the update of the mapping relationship in the second logical block management table relative to the mapping relationship in the first logical block management table.

19. The system of claim 18, wherein, M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode. There are N second logic blocks, where N is an integer greater than M. The N second logic blocks cover all physical addresses of the memory devices of the memory system.

20. The system of claim 18, wherein, The interface is also configured to send the L2P mapping table corresponding to a certain second logical block to the host.

21. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, When the computer instructions are executed, they perform the steps of the method according to any one of claims 1 to 13.

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