Semiconductor substrate manufacturing method

Abstract

The purpose of the present invention is to provide a production method for semiconductor substrates that makes it possible to achieve sufficient levels of sensitivity, LWR performance, and the like.　According to the present invention, a production method for semiconductor substrates includes a step for directly or indirectly vapor depositing a metal or a metal compound on a substrate to form a metal-containing resist film and a step for exposing the resist film, the metal or metal compound including Au atoms, Cr atoms, Ag atoms, In atoms, or any of those.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor substrate.

Background Art

[0002] In a general pattern formation method used for lithographic microfabrication, a resist film formed from a radiation-sensitive composition for forming a resist film is exposed to electromagnetic waves such as far ultraviolet rays (e.g., ArF excimer laser light, KrF excimer laser light, etc.), extreme ultraviolet rays (EUV), or charged particle beams such as electron beams, to generate acid in the exposed areas. Then, a chemical reaction catalyzed by this acid causes a difference in the dissolution rate with respect to the developer between the exposed and unexposed areas, forming a pattern on the substrate. The formed pattern can be used as a mask or the like in substrate processing. In the above pattern formation method, it is required to improve the resist performance with the miniaturization of processing technology. In response to this requirement, the types, molecular structures, etc. of the organic polymer, acid generator, and other components used in the radiation-sensitive composition for forming the resist film have been studied, and further, their combinations have also been studied in detail (for example, see Patent Document 1). Also, using a metal-containing compound instead of the organic polymer has been studied.

Prior Art Documentation

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the resist pattern formed using the above metal-containing compound, the resist pattern may collapse or the pattern may be pulled at the bottom of the resist film.

[0005] The present invention aims to solve the above problems by providing a method for manufacturing a semiconductor substrate that can exhibit sufficient levels of sensitivity, LWR performance, and the like. [Means for solving the problem]

[0006] In one embodiment, the present invention is A process of forming a metal-containing resist film by directly or indirectly depositing a metal compound or metal in the vapor phase onto a substrate, The process of exposing the above-mentioned resist film and A method for manufacturing a semiconductor substrate, including The above metal compound or metal contains an Au atom, a Cr atom, an Ag atom, an In atom, or any of these atoms. Regarding the method. [Effects of the Invention]

[0007] This semiconductor substrate manufacturing method employs a process of vapor-depositing a specific metal compound or metal to form a metal-containing resist film, thereby enabling the efficient production of semiconductor substrates with a good pattern shape. Therefore, this semiconductor substrate manufacturing method can be suitably used in the production of semiconductor devices, for which further miniaturization is expected in the future. [Modes for carrying out the invention]

[0008] The following describes in detail the methods for manufacturing semiconductor substrates according to each embodiment of the present invention.

[0009] Method for manufacturing semiconductor substrates The method for manufacturing the semiconductor substrate comprises a step of forming a metal-containing resist film by directly or indirectly depositing a metal compound or metal in the vapor phase onto the substrate (hereinafter also referred to as the "metal-containing resist film formation step"), and a step of exposing the metal-containing resist film formed in the metal-containing resist film formation step (hereinafter also referred to as the "exposure step"). Furthermore, the method may also include a step of preparing a developer (hereinafter also referred to as the "developer preparation step") and a step of dissolving the exposed portion of the exposed metal-containing resist film with the developer to form a resist pattern (hereinafter also referred to as the "resist pattern formation step"). Furthermore, the method may also include a step of directly or indirectly coating the substrate with a resist underlayer film forming composition (hereinafter also referred to as the "resist underlayer film forming composition coating step").

[0010] The following describes each step in the manufacturing method of the semiconductor substrate.

[0011] [Coating process for composition to form a resist underlayer film] When forming a resist underlayer film directly or indirectly on a substrate, a resist underlayer film formation composition coating step may be included prior to the metal-containing resist film formation step. In this step, the resist underlayer film formation composition is coated directly or indirectly on the substrate. Known compositions can be used as appropriate. The coating method for the resist underlayer film formation composition is not particularly limited and can be carried out by appropriate methods such as rotary coating, casting coating, or roll coating. A coating film is formed, and the resist underlayer film is formed by the volatilization of the solvent in the resist underlayer film formation composition. The resist underlayer film formation composition will be described later.

[0012] Next, the coating film formed by the above coating process is heated. Heating the coating film promotes the formation of the resist underlayer film. More specifically, heating the coating film promotes the volatilization of the solvent in the resist underlayer film forming composition.

[0013] The above-mentioned coating film may be heated under an atmospheric environment or under a nitrogen atmosphere. The lower limit of the heating temperature is preferably 100°C, more preferably 150°C, and even more preferably 200°C. The upper limit of the heating temperature is preferably 400°C, more preferably 350°C, and even more preferably 280°C. The lower limit of the heating time is preferably 15 seconds, more preferably 30 seconds. The upper limit of the heating time is preferably 1,200 seconds, and even more preferably 600 seconds.

[0014] The lower limit of the average thickness of the resist underlayer film formed is preferably 0.5 nm, more preferably 1 nm, and still more preferably 2 nm. The upper limit of the average thickness is preferably 50 nm, more preferably 20 nm, still more preferably 10 nm, and particularly preferably 7 nm. The method for measuring the average thickness is as described in the examples.

[0015] [Metal-containing resist film formation process] In this process, a metal-containing resist film is formed on the resist underlayer film arbitrarily formed by the resist underlayer film formation composition coating process described above.

[0016] A metal-containing resist film can be formed by depositing a metal compound onto the resist underlayer film which is arbitrarily formed.

[0017] The deposition of the above metal compounds may be carried out by physical vapor deposition (PVD) or chemical vapor deposition (CVD). CVD is preferred, and may be carried out by plasma-enhanced (PE) CVD.

[0018] Deposition by CVD may be performed by atomic layer deposition (ALD). The deposition temperature by ALD may be 50°C to 600°C. The deposition pressure by ALD may be 100 to 6000 mTorr. The flow rate of the metal compound by ALD may be 0.01 to 10 ccm, and the gas flow rates (CO2, CO, Ar, N2) may be 100 to 10000 sccm. The plasma power by ALD may be 200 to 1000 W per 300 mm wafer station using high-frequency plasma (e.g., 13.56 MHz, 27.1 MHz, or higher frequencies).

[0019] Processing conditions suitable for deposition by CVD include a deposition temperature of about 250°C to 350°C (e.g., 350°C), a reactor pressure of less than 6 Torr (e.g., maintained at 1.5 to 2.5 Torr at 350°C), a plasma power / bias of 200 W per 300 mm wafer station using high-frequency plasma (e.g., 13.56 MHz or higher), a metal compound flow rate of about 100 to 500 ccm, and a CO2 flow rate of about 1000 to 2000 sccm.

[0020] The metal-containing resist film contains Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms. In other words, the metal-containing resist film of the present invention contains at least one kind of atom selected from the group consisting of Au atoms, Cr atoms, Ag atoms, and In atoms. Such a metal-containing resist film can be formed using a metal compound or a metal alone that contains Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms.

[0021] Examples of the metal compound include metal complexes, metal halides, or organometals, etc.

[0022] Examples of the metal complex include gold complexes, chromium complexes, silver complexes, or indium complexes, etc.

[0023] Examples of the metal halide include indium halide, etc.

[0024] Examples of organometallic compounds include alkylindium.

[0025] Examples of metal compounds containing Au atoms include gold complexes such as chloro(triphenylphosphine)gold(I). Gold sputtering targets can also be used.

[0026] Examples of metal compounds containing Cr atoms include chromium(III) acetylacetonate, chromium(III) acetate hydroxide, chromium(III) tris(2,2,6,6-tetramethyl-3,5-heptazionate), hexacarbonylchromium, and bis(pentamethylcyclopentadienyl)chromium(III) complexes. Chromium sputtering targets can also be used.

[0027] Examples of metal compounds containing Ag atoms include silver acetate, silver trifluoroacetate, silver acetylacetonate, and silver(I) complexes such as (1,5-cyclooctadiene)(hexafluoroacetylacetonate). Silver sputtering targets can also be used.

[0028] Examples of metal compounds containing an indium atom include indium halides such as indium(III) chloride, indium complexes such as indium(III) acetylacetonate, and organic indium compounds such as indium(III) acetate, indium(III) acetate hydrate, and trimethylindium. Among organic indium compounds, alkylindium compounds such as trimethylindium are preferred. Sputtering targets can also be made of indium, ITO (a mixture of indium oxide and tin oxide), or IGZO (a mixture of indium oxide, gallium oxide, and zinc oxide).

[0029] The metal-containing resist film of the present invention may contain metal atoms other than Au atoms, Cr atoms, Ag atoms, or In atoms. Examples of such other metal atoms include Sn atoms, Ge atoms, Pb atoms, and Hf atoms, with Sn atoms being preferred.

[0030] [Synthesis process] In this step, the metal-containing resist film formed in the above-mentioned metal-containing resist film formation step is exposed to light. This step can cause differences in solubility in the developer between the exposed and unexposed areas of the metal-containing resist film, and differences in the amount of material removed by heating during development between the exposed and unexposed areas.

[0031] The radiation used for exposure can be appropriately selected depending on the type of metal-containing resist film used. Examples include electromagnetic waves such as visible light, ultraviolet light, far ultraviolet light, X-rays, and gamma rays, as well as particle beams such as electron beams, molecular beams, and ion beams. Among these, far ultraviolet light is preferred, with KrF excimer laser light (wavelength 248 nm), ArF excimer laser light (wavelength 193 nm), F2 excimer laser light (wavelength 157 nm), Kr2 excimer laser light (wavelength 147 nm), ArKr excimer laser light (wavelength 134 nm), or extreme ultraviolet light (wavelength 13.5 nm, also called "EUV") being more preferred, and EUV being even more preferred. Furthermore, the exposure conditions can be appropriately determined depending on the type of metal-containing resist film used.

[0032] EUV exposure induces chemical reactions, such as dimerization and decomposition reactions of metal compounds, in the exposed areas of metal-containing resist films. For example, in the case of indium(III) chloride, an indium halide compound, a decomposition reaction such as 2InCl3 → 2In + 3Cl2 may occur in the exposed area.

[0033] Furthermore, in this process, after exposure, post-exposure baking (hereinafter also referred to as "PEB") can be performed to improve the performance of the resist film, such as resolution, pattern profile, and developability. The PEB temperature and PEB time can be appropriately determined according to the type of metal-containing resist film formation material used. The lower limit of the PEB temperature is preferably 50°C, and more preferably 70°C. The upper limit of the PEB temperature is preferably 500°C, and more preferably 300°C. The lower limit of the PEB time is preferably 10 seconds, and more preferably 30 seconds. The upper limit of the PEB time is preferably 600 seconds, and more preferably 300 seconds.

[0034] [Developer preparation process] In this step, the developing solution is prepared. Examples of developing solutions include water, alcohol-based liquids, and ether-based liquids, and two or more types can be used in combination.

[0035] Examples of the above alcohol-based liquids include: Examples include monoalcohol liquids such as methanol, ethanol, n-propanol, iso-propanol, n-butanol, iso-butanol, sec-butanol, t-butanol, n-pentanol, iso-pentanol, sec-pentanol, t-pentanol, 2-methylpentanol, and 4-methyl-2-pentanol.

[0036] Examples of the above ether-based liquids include Examples include polyhydric alcohol partial ether solvents such as ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol dimethyl ether, and propylene glycol monoethyl ether, and polyhydric alcohol partial ether acetate liquids such as ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate (PGMEA), and propylene glycol monoethyl ether acetate.

[0037] As the developing solution, water or an alcohol-based liquid is preferred, and water, ethanol, or a combination thereof is more preferred.

[0038] [Resist pattern formation process] In this process, the exposed metal-containing resist film is developed to form a resist pattern. For example, in the case of indium(III) chloride, an indium halide compound, elemental indium that may form in the exposed area is difficult to remove with developer or heat, whereas indium(III) chloride in the unexposed area can be removed with developer or heat. Therefore, a resist pattern can be formed by development with developer or heat.

[0039] The temperature of the developer solution can be appropriately determined depending on the type of material used to form the metal-containing resist film. The lower limit of the developer solution temperature is preferably 20°C, more preferably 30°C. The upper limit of the developer solution temperature is preferably 70°C, more preferably 60°C. The lower limit of the development time is preferably 10 seconds, more preferably 30 seconds. The upper limit of the development time is preferably 600 seconds, more preferably 300 seconds.

[0040] The temperature used for development by heating can be appropriately determined depending on the type of metal-containing resist film formation material used. The heating temperature may be between 50°C and 600°C.

[0041] In this process, washing and / or drying may be performed after development.

[0042] [Etching process] In this process, etching is performed using the resist pattern described above as a mask. The etching may be performed once or multiple times, i.e., sequentially using the patterns obtained by etching as masks. Examples of etching methods include dry etching and wet etching. Through the above etching, a semiconductor substrate having a predetermined pattern is obtained.

[0043] Dry etching can be performed, for example, using a known dry etching apparatus. The etching gas used for dry etching can be appropriately selected depending on the mask pattern, the elemental composition of the film to be etched, etc. Examples include fluorine-based gases such as CHF3, CF4, C2F6, C3F8, SF6; chlorine-based gases such as Cl2, BCl3; oxygen-based gases such as O2, O3, H2O; reducing gases such as H2, NH3, CO, CO2, CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HF, HI, HBr, HCl, NO, NH3, BCl3; and inert gases such as He, N2, Ar. These gases can also be used in mixtures. [Examples]

[0044] The present invention will be described in detail below based on examples, but the present invention is not limited to these examples. The methods for measuring various physical properties are shown below.

[0045] <Preparation of evaluation board> [Example 1] A plasma CVD raw material was prepared by mixing 2,4,6,8-tetramethylcyclotetrasiloxane and chloro(triphenylphosphine)gold(I) to achieve a gold concentration of 3 μg / L. Next, a substrate with a silicon dioxide film of 20 nm thickness formed on its surface was placed in a plasma CVD apparatus and evacuated. Subsequently, a metal-containing resist film with a thickness of 5 nm and containing Au atoms was fabricated on one side of the substrate using the plasma CVD raw material described above.

[0046] This metal-containing resist film was irradiated with extreme ultraviolet light using an EUV scanner (ASML's "TWINSCAN NXE:3300B" (NA 0.3, sigma 0.9, quadruple pole illumination, wafer-mounted 1:1 line-and-space mask with a line width of 16 nm)). The substrate was then developed with 4-methyl-2-pentanol and dried. In this way, an evaluation substrate with a resist pattern containing Au atoms was fabricated.

[0047] [Example 2] A substrate with a 20 nm thick silicon dioxide film formed on its surface was placed in a CVD apparatus and evacuated. Subsequently, a 7 nm thick metal-containing resist film containing Cr atoms was formed on one side of the substrate using hexacarbonylchromium.

[0048] This metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner described above. The substrate was then developed with 4-methyl-2-pentanol and dried. In this way, an evaluation substrate with a resist pattern containing Cr atoms was fabricated.

[0049] [Example 3] A substrate with a 20 nm thick silicon dioxide film formed on its surface was placed in an ALD apparatus and evacuated. Subsequently, a 3 nm thick metal-containing resist film containing Ag atoms was formed on one side of the substrate using a 0.1 M toluene solution of (1,5-cyclooctadiene)(hexafluoroacetylacetonate)silver(I).

[0050] This metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner described above. Subsequently, it was developed using the paddle method with n-propanol for 60 seconds.

[0051] An etching solution with a phosphoric acid / nitric acid / acetic acid ratio of 45 / 2.2 / 30 (by weight) was prepared by mixing 85% by weight phosphoric acid, 70% by weight nitric acid, 99% by weight acetic acid, and ultrapure water. The developed substrate was immersed in this etching solution, adjusted to 30°C, for 60 seconds. In this way, an evaluation substrate with a resist pattern containing Ag atoms was obtained.

[0052] [Example 4] A substrate with a 20 nm thick silicon dioxide film formed on its surface was placed in a CVD apparatus and evacuated. Subsequently, a 5 nm thick metal-containing resist film containing in atoms was formed on one side of the substrate using trimethylindium.

[0053] This metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner described above. The substrate was then developed by heating it at 150°C for 2 minutes. In this way, an evaluation substrate with a resist pattern containing In atoms was obtained.

[0054] [Example 5] In Example 4, the procedure was the same as in Example 4, except that indium(III) chloride was used instead of trimethylindium, and development was performed using ultrapure water instead of heating at 150°C for 2 minutes. In this way, an evaluation substrate with a resist pattern containing In atoms was obtained.

[0055] [Comparative Example 1] An evaluation substrate with a resist pattern containing Sn atoms was obtained in the same manner as in Example 4, except that tetramethyltin was used instead of trimethylindium.

[0056] [Comparative Example 2] A substrate with a 20 nm thick silicon dioxide film formed on its surface was placed in a plasma CVD apparatus and evacuated. Subsequently, a 20 nm thick metal-containing resist film containing Sn atoms was formed on one side of the substrate by CVD with trimethyltin chloride and carbon dioxide.

[0057] The metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner described above. The substrate was then developed by heating it in ethanol at 60°C for 60 seconds. In this way, an evaluation substrate with a resist pattern containing Sn atoms was obtained.

[0058] <Rating> The rectangularity of the pattern was evaluated according to the following method. The evaluation results are shown in Table 1 below.

[0059] [LWR] Fifty points were measured for the above pattern, and the 3-sigma value was calculated from the distribution of the measured values, which was defined as LWR (nm). A smaller LWR value indicates better performance. The LWR was evaluated using the LWR value of Comparative Example 1 as the baseline. If the LWR was 95% or less of the baseline, it was rated as "A"; if it was between 95% and 99%, it was rated as "B"; and if it was above 99%, it was rated as "C". In Table 1 below, in the "LWR" column, "***" indicates the baseline used for LWR evaluation.

[0060] [Table 1]

[0061] [Example 6] 2,4,6,8-tetramethylcyclotetrasiloxane, chloro(triphenylphosphine)gold(I), and tris(dimethylamino)methyltin(IV) were mixed to prepare a raw material for plasma CVD, with gold and tin concentrations of 1 μg / L and 4 μg / L, respectively.

[0062] An evaluation substrate was prepared in the same manner as in Example 1, except for the use of this raw material, with a resist pattern containing Au atoms and Sn atoms and having a film thickness of 5 nm. When evaluated in the same manner as above, the LWR was "A".

[0063] As can be seen from Table 1 and the results of Example 6, resist patterns formed from metal-containing resist films containing Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms exhibited superior LWR compared to resist patterns formed from metal-containing resist films that did not contain these atoms. [Industrial applicability]

[0064] The semiconductor substrate manufacturing method of the present invention makes it possible to form a resist pattern with excellent LWR (low wave resistance). Therefore, this semiconductor substrate manufacturing method can be suitably used in the manufacture of semiconductor devices, for which further miniaturization is expected in the future.

Claims

1. A process of forming a metal-containing resist film by directly or indirectly depositing a metal compound or metal in the vapor phase onto a substrate, The process of exposing the above-mentioned resist film and A method for manufacturing a semiconductor substrate, including The above metal compound or metal contains an Au atom. method.

2. The method according to claim 1, further comprising the step of developing the exposed resist film after the exposure step.

3. The method according to claim 1 or 2, wherein the deposition is carried out by PVD or CVD.

4. The method according to any one of claims 1 to 3, wherein the metal compound includes a metal complex, a metal halide, or an organometallic compound.

5. The method according to claim 4, wherein the metal complex includes a gold complex.

6. The method according to any one of claims 1 to 5, wherein the exposure is exposure with extreme ultraviolet light.

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