Indication device

Abstract

To provide a display device with high quality and a display device with high definition.SOLUTION: A display device includes a plurality of pixels. Each pixel includes a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor element. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor element. A gate of the second transistor is electrically connected to the other electrode of the first capacitor element, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. Each pixel includes a period in which each of the firsts transistor and the fourth transistor is in a conductive state in one frame period.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device and an electronic device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 discloses a semiconductor device in which multiple oxide semiconductor layers are stacked, and in which the channel oxide semiconductor layer among the multiple oxide semiconductor layers contains indium and gallium, and the proportion of indium is greater than the proportion of gallium, thereby increasing the field-effect mobility (sometimes simply called mobility, μFE, or μ).

[0004] Metal oxides that can be used in semiconductor layers can be formed using sputtering methods, and therefore can be used in transistors that make up large display devices. Furthermore, it is possible to modify and utilize some of the production equipment for transistors using polycrystalline silicon or amorphous silicon, thus reducing capital investment. In addition, transistors using metal oxides have a higher field-effect mobility than those using amorphous silicon, enabling the realization of high-performance display devices equipped with drive circuits.

[0005] By the way, wearable and stationary display devices are becoming increasingly popular as display devices for augmented reality (AR) or virtual reality (VR). Examples of wearable display devices include head-mounted displays (HMDs) and glasses-type display devices. Examples of stationary display devices include head-up displays (HUDs).

[0006] In electronic devices equipped with imaging devices such as digital cameras, a viewfinder is used to confirm the image to be captured before it is captured. Furthermore, electronic viewfinders are used as viewfinders. Electronic viewfinders are provided with a display unit, which can display the image obtained by the imaging device as an image on the display unit. For example, Patent Document 2 discloses an electronic viewfinder that can obtain a good diopter state from the center to the periphery of the image. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Patent Document 2] Japanese Patent Publication No. 2012-42569 [Overview of the project] [Problems that the invention aims to solve]

[0008] In display devices such as HMDs, where the user is in close proximity to the display unit, the user may easily perceive individual pixels, resulting in a strong sense of graininess, which can diminish the immersive and immersive experience of AR and VR. Therefore, there is a need for display devices with fine pixels that are not easily visible to the user, i.e., high resolution displays. However, as resolution increases, the area of ​​each individual pixel decreases, which can reduce the number of elements such as transistors and capacitive elements provided in each pixel. Therefore, in high-resolution display devices, it is desirable to construct pixels with a small number of elements.

[0009] When viewing light emitted from a display device, a phenomenon sometimes occurs where the previously viewed light remains visible even after it has disappeared (also known as afterimage). When afterimage occurs, the user perceives the previously displayed image as an afterimage, which degrades the display quality. In particular, the effect of afterimage is greater with videos, which can significantly reduce display quality.

[0010] In view of the above, one aspect of the present invention aims to provide a display device with high resolution. Alternatively, one aspect of the present invention aims to provide a display device with minimal afterimages. Alternatively, one aspect of the present invention aims to provide a display device with high display quality. Alternatively, one aspect of the present invention aims to provide a display device with low power consumption. Alternatively, one aspect of the present invention aims to provide a display device with a narrow bezel. Alternatively, one aspect of the present invention aims to provide a compact display device. Alternatively, one aspect of the present invention aims to provide a novel display device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention is a display device having a pixel section having a plurality of pixels, a first wiring, a first scan line, a second scan line, a third scan line, and a signal line. Each pixel has a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitive element. One electrode of the light-emitting device is electrically connected to one of the source or drain of the first transistor, one of the source or drain of the second transistor, and one electrode of the first capacitive element. The gate of the second transistor is electrically connected to the other electrode of the first capacitive element, one of the source or drain of the third transistor, and one of the source or drain of the fourth transistor. The other source or drain of the first transistor and the other source or drain of the fourth transistor are each electrically connected to a first wiring that has the function of supplying a first potential. The gate of the first transistor is electrically connected to a first scan line. The gate of the third transistor is electrically connected to the second scan line. The gate of the fourth transistor is electrically connected to the third scan line. The other end of the source or drain of the third transistor is electrically connected to the signal line. In addition, for each pixel, there is a period during one frame in which both the first and fourth transistors are conducting.

[0013] In the aforementioned display device, it is preferable to have a second capacitive element. One electrode of the second capacitive element is electrically connected to the gate of the second transistor. The other electrode of the second capacitive element is electrically connected to the other side of the source or drain of the second transistor.

[0014] One aspect of the present invention is a display device having a pixel section having a plurality of pixels, a first wiring, a first scan line, a second scan line, a third scan line, and a signal line. Each pixel has a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitive element. One electrode of the light-emitting device is electrically connected to one source or drain of the first transistor, one source or drain of the second transistor, one source or drain of the fourth transistor, and one electrode of the first capacitive element. The gate of the second transistor is electrically connected to the other electrode of the first capacitive element, one source or drain of the third transistor, and the other source or drain of the fourth transistor. The other source or drain of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the first scan line. The gate of the third transistor is electrically connected to the second scan line. The gate of the fourth transistor is electrically connected to the third scan line. The other end of the source or drain of the third transistor is electrically connected to the signal line. In addition, for each pixel, there is a period during one frame in which the first and third transistors are non-conductive and the fourth transistor is conductive.

[0015] One aspect of the present invention is a display device having a pixel section having a plurality of pixels, a first wiring, a second wiring, a first scan line, a second scan line, a third scan line, and a signal line. Each pixel has a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitive element. One electrode of the light-emitting device is electrically connected to one of the source or drain of the first transistor, one of the source or drain of the second transistor, one of the source or drain of the fourth transistor, and one electrode of the first capacitive element. The gate of the second transistor is electrically connected to the other electrode of the first capacitive element and one of the source or drain of the third transistor. The other source or drain of the first transistor is electrically connected to the first wiring. The other source or drain of the fourth transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first scan line. The gate of the third transistor is electrically connected to the second scan line. The gate of the fourth transistor is electrically connected to the third scan line. The other end of the source or drain of the third transistor is electrically connected to the signal line. In addition, for each pixel, there is a period during one frame in which the first and third transistors are non-conductive and the fourth transistor is conductive.

[0016] One aspect of the present invention is a display device having a pixel section having a plurality of pixels, a first wiring, a first scan line, a second scan line, a third scan line, and a signal line. Each pixel has a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitive element. One electrode of the light-emitting device is electrically connected to one of the sources or drains of the fourth transistor. The other source or drain of the fourth transistor is electrically connected to one of the sources or drains of the first transistor, one of the sources or drains of the second transistor, and one electrode of the first capacitive element. The gate of the second transistor is electrically connected to the other electrode of the first capacitive element and one of the sources or drains of the third transistor. The other source or drain of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the first scan line. The gate of the third transistor is electrically connected to the second scan line. The gate of the fourth transistor is electrically connected to the third scan line. The other end of the source or drain of the third transistor is electrically connected to the signal line. In addition, for each pixel, there are periods during one frame in which the first transistor, the third transistor, and the fourth transistor are each in a non-conducting state.

[0017] One aspect of the present invention is a display device having a pixel section having a plurality of pixels, a first wiring, a first scan line, a second scan line, a third scan line, and a signal line. Each pixel has a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitive element. One electrode of the light-emitting device is electrically connected to one of the source or drain of the first transistor, one of the source or drain of the second transistor, and one electrode of the first capacitive element. The gate of the second transistor is electrically connected to the other electrode of the first capacitive element and one of the source or drain of the third transistor. The other source or drain of the second transistor is electrically connected to one of the source or drain of the fourth transistor. The other source or drain of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the first scan line. The gate of the third transistor is electrically connected to the second scan line. The gate of the fourth transistor is electrically connected to the third scan line. The other end of the source or drain of the third transistor is electrically connected to the signal line. In each pixel, there is a period during one frame in which the first transistor, the third transistor, and the fourth transistor are each in a non-conducting state.

[0018] In the aforementioned display device, the second transistor preferably has a back gate. The back gate is electrically connected to either the source or the drain of the second transistor.

[0019] In the aforementioned display device, it is preferable that the second transistor has a back gate. The back gate is electrically connected to the gate of the second transistor.

[0020] In the aforementioned display device, it is preferable that the other electrode of the light-emitting device is electrically connected to a third wiring. A first potential is supplied to the first wiring. A third potential is supplied to the third wiring, and it is preferable that the third potential is lower than the first potential.

[0021] In the aforementioned display device, the light-emitting device is preferably an organic light-emitting diode.

[0022] In the aforementioned display device, it is preferable that the first drive circuit section has a region that overlaps with the pixel section and is electrically connected to the signal line.

[0023] In the aforementioned display device, it is preferable to have a first layer and a second layer on the first layer. The first layer has a first drive circuit section and a second drive circuit section, and the second layer has a pixel section. The second drive circuit section is electrically connected to the first scan line.

[0024] In the aforementioned display device, it is preferable that the first transistor, the second transistor, the third transistor, and the fourth transistor each have a metal oxide in their channel-forming region. The metal oxide comprises indium, zinc, and element M (one or more selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0025] One aspect of the present invention is an electronic device having the aforementioned display device and a camera. [Effects of the Invention]

[0026] According to one aspect of the present invention, a display device with high resolution can be provided. Alternatively, according to one aspect of the present invention, a display device with minimal afterimages can be provided. Alternatively, according to one aspect of the present invention, a display device with high display quality can be provided. Alternatively, according to one aspect of the present invention, a display device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a display device with a narrow bezel can be provided. Alternatively, according to one aspect of the present invention, a compact display device can be provided. Alternatively, according to one aspect of the present invention, a novel display device can be provided.

[0027] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0028] [Figure 1] Figures 1A and 1B are circuit diagrams showing examples of pixel configurations. [Figure 2] Figure 2 is a timing chart illustrating the operation of the pixel circuit. [Figure 3] Figure 3A is a circuit diagram showing an example of a pixel configuration. Figure 3B is a timing chart explaining the operation of the pixel circuit. [Figure 4] Figure 4A is a circuit diagram showing an example of a pixel configuration. Figure 4B is a timing chart explaining the operation of the pixel circuit. [Figure 5] Figures 5A and 5B are circuit diagrams showing examples of pixel configurations. [Figure 6] Figure 6 is a timing chart illustrating the operation of the pixel circuit. [Figure 7] Figure 7A is a circuit diagram showing an example of a pixel configuration. Figure 7B is a timing chart explaining the operation of the pixel circuit. [Figure 8] Figures 8A to 8C show the operation of the display device. [Figure 9] Figure 9A is a circuit diagram showing an example of pixel configuration. Figure 9B is a diagram showing the operation of the display device. [Figure 10] Figure 10 shows the operation of the display device. [Figure 11] Figures 11A and 11B show examples of pixel layouts. [Figure 12] Figures 12A and 12B are schematic diagrams showing examples of pixel configurations. [Figure 13] Figures 13A and 13B are schematic diagrams showing examples of pixel configurations. [Figure 14] Figure 14 is a block diagram showing an example of a display device configuration. [Figure 15] Figure 15A is a schematic diagram showing an example of the configuration of a display device. Figure 15B is a block diagram showing an example of the configuration of a display device. [Figure 16] Figure 16A is a schematic diagram showing an example of the configuration of a display device. Figure 16B is a block diagram showing an example of the configuration of a display device. [Figure 17] Figure 17 is a cross-sectional view showing an example of the configuration of a display device. [Figure 18] Figure 18 is a cross-sectional view showing an example of the configuration of a display device. [Figure 19] Figure 19 is a cross-sectional view showing an example of the configuration of a display device. [Figure 20] Figure 20 is a cross-sectional view showing an example of the configuration of a display device. [Figure 21] Figure 21 is a cross-sectional view showing an example of the configuration of a display device. [Figure 22] Figures 22A to 22E show examples of the configuration of a light-emitting device. [Figure 23] Figure 23A is a top view showing an example of a transistor configuration. Figures 23B and 23C are cross-sectional views showing an example of a transistor configuration. [Figure 24] Figure 24A is a top view showing an example of a transistor configuration. Figures 24B and 24C are cross-sectional views showing an example of a transistor configuration. [Figure 25] Figure 25A is a top view showing an example of a transistor configuration. Figures 25B and 25C are cross-sectional views showing an example of a transistor configuration. [Figure 26] Figure 26A is a top view showing an example of a transistor configuration. Figures 26B and 26C are cross-sectional views showing an example of a transistor configuration. [Figure 27] Figure 27A illustrates the classification of IGZO crystal structures. Figure 27B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 27C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 28] Figures 28A to 28E are perspective views showing examples of electronic devices. [Figure 29]Figures 29A to 29G are perspective views showing examples of electronic devices. [Figure 30] Figure 30 is a diagram illustrating the simulation results. [Figure 31] Figures 31A and 31B are photographs of the display device. [Figure 32] Figure 32A shows the correlation between the duty cycle and brightness of a display device. Figure 32B shows the change in brightness of a display device over time. [Modes for carrying out the invention]

[0029] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be construed as being limited to the contents of the following embodiments.

[0030] In the figures described herein, the size of each component, the thickness of each layer, or the area may be exaggerated for clarity.

[0031] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0032] In this specification, terms such as "above" and "below" are used for convenience to explain the positional relationships between components with reference to the drawings. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0033] In this specification, the source and drain functions of a transistor may be reversed depending on the transistor's polarity or the direction of current during circuit operation. Therefore, the terms source and drain may be used interchangeably.

[0034] In this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0035] In this specification, the term "resistance" may be defined as the resistance value determined by the length of the wiring. Alternatively, it may be defined as the resistance value formed by connecting a conductor with lower efficiency than the conductor used in the wiring via a contact. Alternatively, the resistance value may be determined by doping a semiconductor with impurities.

[0036] In this specification, "electrically connected" includes both direct connections and connections made via "something that has some electrical function." Here, "something that has some electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in a real circuit there may be no physical connection part, and only wiring may extend. Also, even when it is expressed as "direct connection," it includes cases where wiring is formed via contacts between different conductors. Note that the wiring may consist of different conductors that contain one or more of the same element, or different elements.

[0037] In this specification, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0038] In this specification, unless otherwise specified, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V th This refers to a state that is higher than [a certain value].

[0039] In drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited. Furthermore, the drawings are schematic and not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks may unintentionally decrease due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Also, in drawings, the same reference numerals may be used across different drawings for identical parts or parts with similar functions or materials, and repeated explanations may be omitted. Additionally, when referring to similar functions or materials, the hatch patterns may be the same, and no specific reference numeral may be assigned.

[0040] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having an oxide or oxide semiconductor.

[0041] In this specification, a pixel refers to, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by that single color element. Accordingly, in the case of a color display device consisting of R (red), G (green), and B (blue) color elements, the smallest unit of an image consists of three pixels: an R pixel, a G pixel, and a B pixel. In this case, each of the RGB pixels is called a subpixel, and the RGB subpixels together are sometimes referred to as a pixel.

[0042] (Embodiment 1) In this embodiment, a display device that is one aspect of the present invention will be described.

[0043] A display device according to one aspect of the present invention has a pixel section. The pixel section has a plurality of pixels, each pixel having a light-emitting device and a drive transistor that controls the amount of current flowing to the light-emitting device. A display device according to one aspect of the present invention can have a period during one frame in which the light-emitting device is turned off. By providing such a period and displaying black, afterimages can be reduced and display quality can be improved.

[0044] In one aspect of the present invention, a display device is supplied with a potential "Vdata" corresponding to the image data from a source driver to each pixel. Furthermore, current flows to a light-emitting device via a drive transistor, and the brightness of the light-emitting device is controlled by the amount of this current. In other words, the display device can represent the gradation of an image by varying the height of the potential "Vdata" supplied to the pixels.

[0045] As the resolution of a display device increases, the area of ​​each pixel decreases, which in turn reduces the size of the light-emitting device and the current required to illuminate it. In other words, as the resolution of the display device increases, the current flowing from the drive transistor to the light-emitting device decreases, and the voltage required to operate the drive transistor also decreases. However, if the range of the potential supplied to the pixels, "Vdata," is reduced, the potential per grayscale level becomes smaller, meaning that the potential difference between grayscale levels becomes smaller, which can make grayscale control difficult in some cases.

[0046] One embodiment of the present invention is a display device that has the function of applying a potential lower than the potential "Vdata" supplied to the pixels to the drive transistor. Therefore, it is possible to display multi-gradation images without reducing the range of the potential "Vdata", thereby improving display quality.

[0047] <Example of pixel configuration 1> Figure 1A shows an example of the configuration of a pixel 10 that can be used in a display device according to one aspect of the present invention. The pixel 10 includes a light-emitting device 114, a transistor 101, a transistor 102, a transistor 103, a transistor 104, and a capacitive element 111.

[0048] One electrode of the light-emitting device 114 is electrically connected to either the source or drain of transistor 101, either the source or drain of transistor 102, and one electrode of the capacitive element 111. The gate of transistor 102 is electrically connected to the other electrode of the capacitive element 111, either the source or drain of transistor 103, and either the source or drain of transistor 104.

[0049] The other end of either the source or drain of transistor 101, and the other end of either the source or drain of transistor 104, are electrically connected to wiring 161. The gate of transistor 101 is electrically connected to wiring 121. The gate of transistor 103 is electrically connected to wiring 122. The gate of transistor 104 is electrically connected to wiring 123. The other end of either the source or drain of transistor 103 is electrically connected to wiring 131.

[0050] Wiring 161 has the function of supplying a specific potential (hereinafter also referred to as the first potential or reference potential) "Vref". Wirings 121, 122, and 123 each function as scan lines to control the operation of transistors 101, 103, and 104, respectively. The scan signals supplied to the scan lines are signals to control the conduction or non-conduction state (on or off) of transistors 101, 103, and 104, which function as switches within the pixel 10. Wiring 131 has the function of supplying a potential "Vdata" corresponding to the image data.

[0051] The source or drain of transistor 102 is electrically connected to wiring 128. Preferably, wiring 128 has the function of supplying a specific potential. Also, the other electrode of light-emitting device 114 is electrically connected to wiring 129. Wirings 128 and 129 can each function as wirings to which a power supply potential is supplied (power lines). For example, wiring 128 can function as a high-potential power line supplying a higher potential than wiring 129. Wiring 129 can function as a low-potential power line supplying a lower potential than wiring 128.

[0052] Transistor 102 functions as a drive transistor that controls the amount of current flowing to the light-emitting device 114. Transistor 103 functions as a selection transistor that selects pixels. Transistors 101 and 104 each function as switches for writing a specific potential (reference potential) "Vref" to the pixel 10.

[0053] Examples of light-emitting devices 114 include self-luminous light-emitting devices such as light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), light-emitting diodes using quantum dots in the light-emitting layer (QLEDs), and semiconductor lasers.

[0054] One aspect of the present invention is a display device that can include a period during one frame in which the light-emitting device is turned off. By including this period and displaying black, afterimages can be reduced and display quality can be improved.

[0055] Preferably, the pixel 10 further has a capacitive element 112. One electrode of the capacitive element 112 is electrically connected to the gate of the transistor 102. The other electrode of the capacitive element 112 is electrically connected to the other source or drain of the transistor 102. By having the capacitive element 112 in the pixel 10, a potential lower than the potential "Vdata" supplied to the pixel 10 can be applied to the transistor 102, which functions as a driving transistor. Therefore, multi-tone images can be displayed without reducing the range of the potential "Vdata", and the display quality can be improved.

[0056] Here, the wiring to which the gate of transistor 102, one of the source or drain of transistor 103, the other electrode of capacitive element 111, and the other electrode of capacitive element 112 are connected is defined as node ND11. Node ND11 has the function of holding the potential of the gate of transistor 103, which functions as a driving transistor. The current flowing through the light-emitting device 114 can be controlled by the potential of node ND11, thereby controlling the luminescence brightness of the light-emitting device 114. The wiring to which one of the source or drain of transistor 101, one of the source or drain of transistor 102, and one electrode of capacitive element 111 are connected is defined as node ND12. Node ND12 has the function of holding the potential of one of the source or drain of transistor 102, which functions as a driving transistor.

[0057] In the pixel 10 shown in Figure 1A, the gate and source of transistor 102, which functions as a driving transistor, are electrically connected via capacitive element 111. The gate and drain of transistor 102 are electrically connected via capacitive element 112. Furthermore, the potential of node ND11 is maintained by the capacitance between the gate and source of transistor 102 (capacitive element 111) and the capacitance between the gate and drain of transistor 102 (capacitive element 112).

[0058] By making transistor 103 conductive, the potential supplied to wiring 131 can be written to node ND11. Similarly, by making transistor 104 conductive, the potential supplied to wiring 161 can be written to node ND11. By making transistors 103 and 104 non-conductive, the potential written to node ND11 can be retained.

[0059] By making transistor 101 conductive, the data supplied to wiring 161 can be written to node ND12. By making transistor 101 non-conductive, the data written to node ND12 can be retained.

[0060] It is preferable to use transistors with extremely low off-currents for one or more of transistors 101, 102, 103, and 104. In particular, by using transistors with extremely low off-currents for transistors 101, 103, and 104, it becomes possible to maintain the potentials of nodes ND11 and ND12 for a long time. For example, transistors using a metal oxide in the channel formation region (hereinafter referred to as OS transistors) can be suitably used as such transistors.

[0061] Furthermore, it is even more preferable to apply OS transistors to all of transistors 101, 102, 103, and 104. Alternatively, OS transistors may be applied to transistors other than 101, 102, 103, and 104. Also, if operation is performed within an acceptable range for leakage current, transistors with silicon in the channel formation region (hereinafter referred to as Si transistors) may be used. Alternatively, OS transistors and Si transistors may be used in combination. Examples of Si transistors include transistors with amorphous silicon and transistors with crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystal silicon). Although the transistors shown in Figure 1A are all n-channel type transistors, p-channel type transistors can also be used.

[0062] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.2 eV or more, and more preferably 2.5 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), which will be described later. CAAC-OS has a stable crystal structure and is suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics and is suitable for transistors that require high-speed operation.

[0063] Because OS transistors have a large energy gap in the semiconductor layer, the off-current value per 1 μm of channel width is several yA / μm (where y is 10). -24It can exhibit an extremely small off-state current characteristic. Also, the OS transistor has characteristics different from those of Si transistors, such as no impact ionization, avalanche breakdown, and short-channel effects occurring, and a highly reliable circuit can be formed. Further, variations in electrical characteristics due to non-uniform crystallinity, which are problematic in Si transistors, are less likely to occur in OS transistors.

[0064] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and an element M (M is one or more of aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0065] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:8, etc. are preferable. Note that the atomic ratio of the formed semiconductor layer includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0066] An oxide semiconductor with a low carrier concentration is used as the semiconductor layer. For example, the semiconductor layer has a carrier concentration of 1×10 17 / cm[[ID=!5]] 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm3 More preferably 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 Oxide semiconductors with the carrier concentrations mentioned above can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. These oxide semiconductors can be said to have a low defect level density and stable properties.

[0067] However, this is not limited to these, and any composition appropriate to the semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor should be used. Furthermore, in order to obtain the semiconductor characteristics of the transistor, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriately.

[0068] In oxide semiconductors that make up semiconductor layers, the presence of silicon or carbon, which are among the Group 14 elements, increases oxygen vacancies and causes n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0069] Alkali metals and alkaline earth metals can generate carriers when they combine with components in oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0070] When nitrogen is present in the oxide semiconductor that constitutes the semiconductor layer, electrons that act as carriers are generated in the oxide semiconductor, increasing the carrier concentration and making it easier for it to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferable:

[0071] If the oxide semiconductor constituting the semiconductor layer contains hydrogen, it can react with oxygen bonded to metal atoms in the oxide semiconductor to form water, thus creating oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects containing hydrogen can function as donors, generating electrons as carriers. In addition, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics.

[0072] Defects where hydrogen fills an oxygen vacancy can function as donors in oxide semiconductors. However, quantitatively evaluating such defects is difficult. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0073] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 1019 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0074] Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors. In non-single-crystal structures, amorphous structures have the highest defect level density, while CAAC-OS has the lowest defect level density.

[0075] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide semiconductor film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0076] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0077] The following describes the structure of CAC-OS, which is one form of a non-single-crystal semiconductor layer.

[0078] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0079] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0080] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0081] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0082] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is any number).

[0083] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0084] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0085] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0086] Note that GaO X3The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0087] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0088] CAC-OS can be formed, for example, by sputtering under conditions where the substrate is not heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. Furthermore, it is preferable that the ratio of oxygen gas flow rate to the total flow rate of the film-forming gas during film formation be as low as possible. For example, it is preferable that the oxygen gas flow rate ratio be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0089] CAC-OS is characterized by the absence of a clear peak when measured using the out-of-plane method with a θ / 2θ scan, which is one of the X-ray diffraction (XRD) measurement methods. In other words, X-ray diffraction measurements show that there is no orientation in the ab-plane direction or the c-axis direction of the measurement region.

[0090] In the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness (ring region) and multiple bright spots are observed within this ring region. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0091] For example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0092] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0093] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1 In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, In X2Zn Y2 O Z2 、 or InO X1 By having regions mainly composed of [these substances] distributed in a cloud-like manner in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0094] On the other hand, regions mainly composed of GaO X3 etc. are regions with higher insulation compared to regions mainly composed of In X2 Zn Y2 O Z2 、 or InO X1 That is, when regions mainly composed of GaO X3 etc. are distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.

[0095] Therefore, when using CAC-OS in a semiconductor device, the insulation caused by GaO X3 etc. and the conductivity caused by In X2 Zn Y2 O Z2 、 or InO X1 act complementarily to achieve a high on-current (I on ), and a high field-effect mobility (μ).

[0096] The semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0097] A configuration different from the pixel 10 shown in FIG. 1A is shown in FIG. 1B.

[0098] As shown in FIG. 1B, the transistors 101, 102, 103, and 104 may each have a back gate configuration. In particular, the transistor 102 that functions as a driving transistor for the light-emitting device 114 preferably has a back gate. FIG. 1B shows a configuration in which the back gate of the transistor 102 is electrically connected to one of the source or drain, which has the effect of enhancing the saturation of transistor characteristics. Also, FIG. 1B shows a configuration in which the back gates of the transistors 101, 103, and 104 are each electrically connected to the gate (which may be called the front gate), which has the effect of increasing the on-current.

[0099] The back gate of the transistor 102 may be electrically connected to the front gate. With such a configuration, it has the effect of increasing the on-current of the transistor 102. Also, the back gate can be electrically connected to a wiring that can supply a fixed potential, and a configuration can be adopted to control the threshold voltage of the transistor. In FIG. 1B, a configuration in which all transistors are provided with back gates is illustrated, but one or more transistors without back gates may be provided.

[0100] An example of the operation of the pixel 10 will be described using the timing chart shown in FIG. 2. In FIG. 2, the variation in the potential V ND11 of the node ND11 and the potential V ND12 of the node ND12 are also shown.

[0101] In the following explanation, high potentials are represented as "High" and low potentials as "Low". The potential corresponding to the image data is "Vdata", and the potential of wiring 161 is "Vref". "Vref" can be, for example, 0V, GND potential, or a specific reference potential. The potential of wiring 128 is "Vano". "Vano" is preferably set to the potential at which transistor 102 operates in the saturation region when the brightness of light-emitting device 114 is at its maximum. The potential of wiring 129 is "Vcath". "Vcath" is preferably set to the potential at which light-emitting device 114 does not emit light when the potential of node ND12 is at its lowest potential.

[0102] First, at time T31, if the potential of wire 121 is set to "High", the potential of wire 122 to "High", the potential of wire 123 to "Low", the potential of wire 131 to "Vdata", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0103] At this time, if the potential difference across the capacitive element 111 is V1, the potential difference V1 can be expressed by equation (1). Similarly, if the potential difference across the capacitive element 112 is V2, the potential difference V2 can be expressed by equation (2). Also, the gate-source voltage Vgs of transistor 102 is the potential V at node ND11. ND11 and the potential V of node ND12 ND12 The difference is given by equation (3), and the voltage Vgs can be expressed by equation (3).

[0104] V1 = Vdata - Vref (1)

[0105] V2 = Vano - Vdata (2)

[0106] Vgs = Vdata - Vref (3)

[0107] Next, at time T32, if the potential of wiring 121 is set to "Low", the potential of wiring 122 is set to "Low", and the potential of wiring 123 is set to "Low", transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by capacitive elements 111 and 112, and a current corresponding to the voltage Vgs flows to the light-emitting device 114. Then, the light-emitting device 114 lights up. The brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0108] At this time, the potential V of node ND12 is maintained until the current flowing through the light-emitting device 114 and the current flowing through the transistor 102 become equal. ND12 The voltage will increase. Also, the potential V of node ND12 ND12 As the voltage increases, the potential V of node ND11 through the capacitive element 111 increases. ND11 The potential V of node ND11 is also increased. In a pixel 10 according to one aspect of the present invention, the potential V of node ND11 is increased by the capacitive element 112. ND11 The amount of increase can be reduced. Therefore, the potential V of node ND11 ND11 and the potential V of node ND12 ND12 The difference becomes smaller. In other words, the gate-source voltage Vgs of transistor 102 can be reduced.

[0109] Potential V at node ND12 ND12 This is determined by the operating point of transistor 102 and light-emitting device 114. The potential V at node ND12 ND12 The capacitance changes from Vref to V0, and the capacitance of the capacitive element 111 changes to C 111 The capacitance of the capacitive element 112 is C 112 Therefore, the potential V of node ND11 ND11 This can be expressed by equation (4). Also, the gate-source voltage Vgs of transistor 102 can be expressed by equation (5). As shown in equation (5), the capacitance C of the capacitive element 111. 111 and the capacitance C of the capacitive element 112 112 By changing the ratio, the gate-source voltage Vgs of transistor 102 can be changed.

[0110] V ND11 =Vdata+(C 111 / (C 111 +C 112 ))×(V0-Vref) (4)

[0111] Vgs=Vdata-(C 111 / (C 111 +C 112 ))×Vref-(C 112 / (C 111 +C 112 )) × V0 (5)

[0112] The period P21a between time T31 and time T32 is the period during which data is written to cause the light-emitting device 114 to emit light, and the period P21b between time T32 and time T33 is the period during which the light-emitting device 114 is emitting light. Furthermore, the period between time T31 and time T33, that is, the period P21 which is the sum of period P21a and period P21b, can be called the illumination period or light emission period. In this specification, the ratio of period P21 to the frame period FP may be referred to as the duty cycle. The duty cycle is the ratio within the frame period FP of the period during which data is written to cause the light-emitting device 114 to emit light and the period during which the light-emitting device 114 is emitting light.

[0113] In addition, the configuration may include the light-emitting device 114 emitting light during period P21a. Alternatively, the configuration may include the light-emitting device 114 not emitting light during period P21a. If the configuration is such that the light-emitting device 114 does not emit light during period P21a, the potential of wiring 129 "Vcath" and the potential of wiring 161 "Vref" should be set such that the potential difference "Vref-Vcath" between the potential of wiring 129 and wiring 161 does not exceed the threshold voltage of the light-emitting device 114.

[0114] Next, at time T33, if the potential of wiring 121 is set to "High", the potential of wiring 122 to "Low", and the potential of wiring 123 to "High", then transistors 101 and 104 will become conductive. The potential of wiring 131, "Vref", is written to node ND11, and the potential of wiring 131, "Vref", is written to node ND12, and the potential of node ND11, V ND11 and the potential V of node ND12 ND12 These become the same. Therefore, the gate-source voltage Vgs of transistor 102 becomes 0V, the light-emitting device 114 turns off, and black can be displayed (hereinafter also referred to as black display or black insertion).

[0115] Next, at time T34, when the potential of wiring 121 is set to "Low", the potential of wiring 122 is set to "Low", and the potential of wiring 123 is set to "Low", transistors 101, 103, and 104 become non-conductive. Also, the light-emitting device 114 remains off.

[0116] Then, at time T35, the operation of one frame ends. Time T35 is the time T31 of the next frame, and the operation of the next frame starts at time T35.

[0117] The period P22a between time T33 and time T34 is the period during which data is written to turn off the light-emitting device 114, and the period P22b between time T34 and time T35 is the period during which the light-emitting device 114 is turned off. Furthermore, the period between time T33 and time T35, that is, the combined period P22a and P22b, can be called the off period or non-light-emitting period.

[0118] One aspect of the present invention is a display device that reduces afterimages and improves display quality by providing a blackout period (period P22) during one frame period to display black.

[0119] <Example of pixel configuration 2> Figure 3A shows a different configuration of pixel 10 from that shown in Figure 1B.

[0120] Pixel 10a shown in Figure 3A differs from pixel 10 shown in Figure 1B in that it does not have a capacitive element 112, one of the source or drain of transistor 104 is electrically connected to one electrode of light-emitting device 114 without going through the capacitive element 111, and the other of the source or drain of transistor 104 is electrically connected to the gate of transistor 102. Regarding the light-emitting device 114, transistors 101, 102, 103, and capacitive element 111, detailed explanations are omitted as the connection relationships between these elements and their respective wirings can be found in the description of pixel 10 shown in Figure 1B.

[0121] An example of the operation of pixel 10a will be explained using the timing chart shown in Figure 3B. Note that wiring 161 is omitted in Figure 3B because its explanation can be found in Figure 2.

[0122] First, at time T31, if the potential of wire 121 is set to "High", the potential of wire 122 to "High", the potential of wire 123 to "Low", the potential of wire 131 to "Vdata", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0123] Next, at time T32, when the potential of wiring 121, wiring 122, and wiring 123 are set to "Low," transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114. Then, the light-emitting device 114 lights up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0124] Next, at time T33, if the potential of wiring 121 is set to "Low", the potential of wiring 122 is set to "Low", and the potential of wiring 123 is set to "High", then transistors 101 and 103 become non-conductive, and transistor 104 becomes conductive. With transistor 104 conductive, nodes ND11 and ND12 are electrically connected via transistor 104, and the potential V of node ND11 ND11 and the potential V of node ND12 ND12 The values ​​become the same. In other words, the gate-source voltage Vgs of transistor 102 becomes 0V, so the light-emitting device 114 turns off and black can be displayed.

[0125] Next, at time T34, when the potential of wiring 121 is set to "Low", the potential of wiring 122 is set to "Low", and the potential of wiring 123 is set to "Low", transistors 101, 103, and 104 become non-conductive. Also, the light-emitting device 114 remains off.

[0126] <Example of pixel configuration 3> Figure 4A shows a different configuration of pixel 10 from that shown in Figure 1B.

[0127] Pixel 10b shown in Figure 4A differs from pixel 10 shown in Figure 1B in that it does not have a capacitive element 112, has wiring 162, one of the source or drain of transistor 104 is electrically connected to one electrode of light-emitting device 114 without going through the capacitive element 111, and the other of the source or drain of transistor 104 is electrically connected to wiring 162. Regarding the light-emitting device 114, transistors 101, 102, 103, and capacitive element 111, detailed explanations are omitted as the connection relationships between these elements and their connections to each wiring can be found in the description of pixel 10 shown in Figure 1B.

[0128] Wiring 162 has the function of supplying a specific potential (hereinafter also referred to as the second potential). The potential of wiring 162 can be, for example, 0V, GND potential, or a specific reference potential.

[0129] An example of the operation of pixel 10b will be explained using the timing chart shown in Figure 4B. Note that wiring 161 is omitted in Figure 4B because its explanation can be found in Figure 2.

[0130] First, at time T31, if the potential of wire 121 is set to "High", the potential of wire 122 to "High", the potential of wire 123 to "Low", the potential of wire 131 to "Vdata", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0131] Next, at time T32, if the potential of wiring 121, wiring 122, and wiring 123 are set to "Low," transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114, causing the light-emitting device 114 to light up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0132] Next, at time T33, if the potential of wiring 121 is set to "Low", the potential of wiring 122 to "Low", and the potential of wiring 123 to "High", transistors 101 and 103 become non-conductive, and transistor 104 becomes conductive. It is preferable that the potential of wiring 162 be set to a potential at which the light-emitting device 114 does not emit light. By setting the potential of wiring 162 to a potential at which the light-emitting device 114 does not emit light, the current flowing through transistor 102 flows through transistor 104 to wiring 162, causing the light-emitting device 114 to turn off and display black. Wiring 162 has the function of supplying current to transistor 102 during period P22. Note that during the period when the potential of wiring 123 is "High", the light-emitting device 114 remains off.

[0133] In Figure 4A, the other source or drain of transistor 101 is electrically connected to wiring 161, and the other source or drain of transistor 104 is electrically connected to wiring 162. However, the present invention is not limited to this configuration. Wiring 162 may be omitted, and both the other source or drain of transistor 101 and the other source or drain of transistor 104 may be electrically connected to wiring 161.

[0134] <Example of pixel configuration 4> Figures 5A and 5B show a different configuration of pixel 10 from that shown in Figure 1B.

[0135] The pixel 10c shown in Figure 5A differs from the pixel 10 shown in Figure 1B in that it does not have a capacitive element 112, one of the source or drain of the transistor 104 is electrically connected to one electrode of the light-emitting device 114 without going through the capacitive element 111, and the other of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 101.

[0136] The pixel 10d shown in Figure 5B differs from the pixel 10 shown in Figure 1B in that it does not have a capacitive element 112, one of the sources or drains of transistor 104 is electrically connected to the other source or drain of transistor 102, and the other source or drain of transistor 104 is electrically connected to wiring 128.

[0137] Regarding the light-emitting device 114, transistors 101, 102, 103, and capacitive element 111, the connection relationships between these elements and their connections to each wiring can be found in the description of pixel 10 shown in Figure 1B, so a detailed explanation is omitted.

[0138] An example of the operation of pixels 10c and 10d will be explained using the timing chart shown in Figure 6. Note that wiring 161 is omitted in Figure 6 as its explanation can be found in Figure 2.

[0139] First, at time T31, if the potential of wire 121 is set to "High", the potential of wire 122 to "High", the potential of wire 123 to "Low", the potential of wire 131 to "Vdata", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0140] Next, at time T32, if the potential of wiring 121 is set to "Low", the potential of wiring 122 to "Low", and the potential of wiring 123 to "High", transistors 101 and 103 become non-conductive, and transistor 104 becomes conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114, causing the light-emitting device 114 to light up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0141] Next, at time T33, if the potential of wiring 121 is set to "Low", the potential of wiring 122 is set to "Low", and the potential of wiring 123 is set to "Low", then transistors 101, 103, and 104 will become non-conductive. When transistor 104 becomes non-conductive, no current flows to the light-emitting device 114, the light-emitting device 114 turns off, and black can be displayed (also called black display or black insertion).

[0142] <Pixel configuration example 5> Figure 7A shows a different configuration of pixel 10 from that shown in Figure 1B.

[0143] The pixel 10e shown in Figure 7A differs from the pixel 10 shown in Figure 1B in that it does not have a transistor 104, a capacitive element 112, and wiring 123. Regarding the light-emitting device 114, transistors 101, 102, 103, and capacitive element 111, detailed explanations are omitted as the connections between these elements and to their respective wirings can be found in the description of the pixel 10 shown in Figure 1B.

[0144] An example of the operation of pixel 10e will be explained using the timing chart shown in Figure 7B. Note that wiring 161 is omitted in Figure 7B because its explanation can be found in Figure 2.

[0145] First, at time T31, if the potential of wire 121 is set to "High", the potential of wire 122 to "High", the potential of wire 131 to "Vdata", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0146] Next, at time T32, when the potential of wiring 121 is set to "Low" and the potential of wiring 122 is set to "Low", transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114, causing the light-emitting device 114 to light up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0147] Next, at time T33, if the potential of wire 121 is set to "High" and the potential of wire 122 is set to "Low", transistor 101 becomes conductive and transistor 103 becomes non-conductive. The potential of wire 161, "Vref", is written to node ND12, the light-emitting device 114 turns off, and black can be displayed. Here, it is preferable to set the potential of wire 129, "Vcath", and the potential of wire 161, "Vref", such that the potential difference between the potential of wire 129 and wire 161, "Vref-Vcath", does not exceed the threshold voltage of the light-emitting device 114. Note that the light-emitting device 114 remains off while the potential of wire 121 is "High".

[0148] Pixel 10e, shown in Figure 7A, has fewer transistors, capacitive elements, and wiring compared to the aforementioned pixels 10 to 10d, and therefore can be suitably used in high-resolution display devices with small pixels.

[0149] <Example of display device operation> An example of the operation of a display device according to one aspect of the present invention will be explained with reference to Figures 8A to 8C.

[0150] A display device according to one aspect of the present invention has a plurality of pixels arranged in a matrix of m rows and n columns (where m and n are each independent integers of 1 or more). The aforementioned pixels 10, 10a, 10b, 10c, 10d, or 10e can be used as such pixels.

[0151] Figure 8A shows an overview diagram illustrating the operation of the display device. In Figure 8A, the vertical axis represents the number of pixel rows i (where i is an integer between 1 and m), and the horizontal axis represents time. Figure 8A also shows excerpts from the first frame (FL=1) to the fourth frame (FL=4).

[0152] One aspect of the present invention is a display device that can display black by providing a period P22 within one frame period. Furthermore, as shown in Figure 8A, it can be configured to display black row by row. In this specification, the method of driving pixels row by row may be referred to as line-sequential driving. By displaying black using line-sequential driving, one aspect of the present invention can increase the selection time per row (also called one horizontal period) for writing image data compared to the case where all pixels are displayed black simultaneously. Therefore, reliable writing of image data to pixels can be ensured, thereby improving the display quality of the display device. For example, even during high-speed operation with a high frame frequency, insufficient writing of image data can be prevented.

[0153] The duty cycle can be set to any value. Figure 8A shows an example configuration with a duty cycle of 80%. Figure 8B shows an example configuration with a duty cycle of 50%. Figure 8C shows an example configuration with a duty cycle of 20%. Increasing the duty cycle increases the proportion of time the display is lit, allowing for higher brightness of the display device. Decreasing the duty cycle increases the proportion of time the display is black (off), further reducing afterimages.

[0154] <Pixel configuration example 6> A different configuration of pixel 10 from that shown in Figure 1B is shown in Figure 9A.

[0155] Pixel 10f shown in Figure 9A differs from pixel 10 shown in Figure 1B in that it does not have transistor 104, capacitive element 112, wiring 122 and wiring 123, and the gate of transistor 103 is electrically connected to wiring 121. In pixel 10f, the gates of transistor 101 and transistor 102 are electrically connected to wiring 121, respectively.

[0156] Pixel 10f, shown in Figure 9A, has fewer transistors, capacitive elements, and wiring compared to pixels 10 to 10e mentioned above, and therefore can be suitably used in high-resolution display devices with small pixels.

[0157] An example of the operation of pixel 10f will be explained using the timing chart shown in Figure 9B. Note that wiring 161 is omitted in Figure 9B because its explanation can be found in Figure 2.

[0158] First, at time T31, if the potential of wiring 121 is set to "High", the potential of wiring 131 to "Vdata_1", and the potential of wiring 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wiring 131 "Vdata_1" will be written to node ND11, and the potential of wiring 161 "Vref" will be written to node ND12. The potential of wiring 131 "Vdata_1" will be the potential corresponding to the image data.

[0159] Next, at time T32, when the potential of wiring 121 is set to "Low", transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114, causing the light-emitting device 114 to light up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it.

[0160] Next, at time T33, if the potential of wiring 121 is set to "High" and the potential of wiring 131 is set to "Vdata_2", transistors 101 and 103 become conductive, and the potential of wiring 131 "Vdata_2" is written to node ND11, and the potential of wiring 161 "Vref" is written to node ND12. By setting the potential "Vdata_2" to, for example, the potential corresponding to the black image data, which is the smallest grayscale, the light-emitting device 114 can be turned off, and black can be displayed.

[0161] Next, at time T34, when the potential of wiring 121 is set to "Low," transistors 101 and 103 become non-conductive. Also, the light-emitting device 114 remains off.

[0162] It is preferable that the potential of wiring 131 be set to "Vdata_1" during period P21 and to "Vdata_2" during period P22.

[0163] An example of the operation of pixel 10f, which differs from the timing chart shown in Figure 9B, will be explained. An example of the timing chart for pixel 10f is shown in Figure 10. Potentials "Vdata_1" and "Vdata_2" are supplied alternately to wiring 131. Note that wiring 161 is omitted in Figure 10 because its explanation can be found in Figure 2.

[0164] The period P21c between time T31a and time T32 is the period (1 horizontal period) for selecting the row on which to write data to cause the light-emitting device 114 to emit light. Furthermore, period P21c is divided into the period during which potential "Vdata_1" is supplied from wiring 131 and the period during which potential "Vdata_2" is supplied.

[0165] At time T31a, if the potential of wiring 121 is set to "Low", transistors 101 and 103 become non-conductive, and the light-emitting device 114 does not emit light.

[0166] Next, at time T31, if the potential of wire 121 is set to "High", the potential of wire 131 to "Vdata_1", and the potential of wire 161 to "Vref", then transistors 101 and 103 will become conductive, and the potential of wire 131 "Vdata_1" will be written to node ND11, and the potential of wire 161 "Vref" will be written to node ND12.

[0167] Next, at time T32, when the potential of wiring 121 is set to "Low", transistors 101 and 103 become non-conductive. The gate-source voltage Vgs of transistor 102 becomes the voltage held by the capacitive element 111, and a current corresponding to the voltage Vgs flows to the light-emitting device 114, causing the light-emitting device 114 to light up. Furthermore, the brightness of the light-emitting device 114 can be controlled by the amount of current flowing through it. The period P21a between time T31 and time T32 is the period for writing data to cause the light-emitting device 114 to light up.

[0168] The period P22c between time T33 and time T34a is the period for selecting the row on which to write data to turn off the light-emitting device 114. Furthermore, period P22c is divided into a period during which the potential "Vdata_1" is supplied from wiring 131 and a period during which the potential "Vdata_2" is supplied.

[0169] Next, at time T33, if the potential of wiring 121 is set to "High" and the potential of wiring 131 is set to "Vdata_2", transistors 101 and 103 become conductive, and the potential of wiring 131 "Vdata_2" is written to node ND11 and the potential of wiring 161 "Vref" is written to node ND12, causing the light-emitting device 114 to turn off and display black.

[0170] Next, at time T34, when the potential of wiring 121 is set to "Low," transistors 101 and 103 become non-conductive. Also, the light-emitting device 114 remains off.

[0171] <Example of pixel layout> The following describes an example layout for pixel 10.

[0172] An example of the layout of pixel 10 shown in Figure 1B is shown in Figures 11A and 11B.

[0173] Figure 11A shows transistors 101, 102, 103, and 104, capacitive element 111, capacitive element 112, wiring 121, 122, 123, 128, 131, and 161. Note that in Figure 11A, the light-emitting device 114 and wiring 129 are omitted for clarity.

[0174] Figure 11B shows a configuration in which a pixel electrode 53 is added to the configuration shown in Figure 11A. The pixel electrode 53 is electrically connected to the light-emitting device 114. The light-emitting device 114 can also be mounted on the pixel electrode 53.

[0175] In Figure 11B, the pixel electrode 53 is positioned overlapping with some of the elements and wiring that make up the pixel 10, such as the transistor 101 and the capacitive element 111. This configuration is particularly effective when using a top-emission type light-emitting device. By positioning the transistor 101 and other elements below the pixel electrode 53 in this way, a large aperture ratio can be achieved even if the occupied area of ​​the pixel 10 is reduced.

[0176] As shown in Figure 11B, it is preferable that the pixel electrode 53 does not overlap with the wiring 131 which functions as a signal line. By preventing the pixel electrode 53 and the wiring 131 from overlapping, it is possible to suppress the effect of changes in the potential of the wiring 131 on the potential of the pixel electrode 53. If it is necessary to place the pixel electrode 53 in overlap with the wiring 131, the ratio of the overlapping area to the area of ​​the pixel electrode 53 should be 10% or less, preferably 5% or less.

[0177] <Example of sub-pixel configuration> Examples of sub-pixel configurations applicable to a display device according to one embodiment of the present invention are shown in Figures 12A, 12B, 13A, and 13B.

[0178] The pixel 10 shown in Figure 12A has sub-pixels 10R that emit red light, sub-pixels 10G that emit green light, and sub-pixels 10B that emit blue light, and this shows an example in which these three sub-pixels constitute one pixel 10. The pixel 10 shown in Figure 12A has a strip-like shape in which the length of the sub-pixels is longer in the direction of extension of the wiring 131, and is arranged in a stripe pattern in the direction of extension of wirings 121, 122, and 123.

[0179] Figure 12B shows wirings 121, 122, 123, and 131 along with subpixels (two pixels 10) arranged in a 2x3 matrix. Note that in Figures 12A and 12B, wirings 121, 122, and 123 in row i are denoted as wiring 121[i], wiring 122[i], and wiring 123[i], respectively. Wirings 121, 122, and 123 in row (i-1) are denoted as wiring 121[i-1], wiring 122[i-1], and wiring 123[i-1], respectively. Wirings 131 in columns (j-6) through j are denoted as wiring 131[j-6] through wiring 131[j], respectively.

[0180] Sub-pixel 10R has a pixel electrode 53a, and the display area 51a of sub-pixel 10R is located inside the pixel electrode 53a. Sub-pixel 10G has a pixel electrode 53b, and the display area 51b of sub-pixel 10G is located inside the pixel electrode 53b. Sub-pixel 10B has a pixel electrode 53c, and the display area 51c of sub-pixel 10B is located inside the pixel electrode 53c. In Figure 12B, an example is shown where the pixel electrodes 53a, 53b, and 53c have the same area, but they may each have different areas. Also, the display areas 51a, 51b, and 51c may each have different areas.

[0181] Pixel 10, shown in Figure 12B, illustrates an example where the positions of subpixels of the same color are shifted in the direction of extension of wiring 121 and wiring 122. In other words, in pixel 10, subpixels of the same color are arranged in a zigzag pattern in the direction of extension of wiring 121 and wiring 122.

[0182] The pixel 10 shown in Figure 13A has a strip-like shape with a longer subpixel length in the direction of extension of wiring 131, and is arranged in a stripe pattern in the direction of extension of wiring 121 and wiring 122. An example is also shown where subpixels 10R, 10G, and 10B are aligned in the direction of extension of wiring 121 and wiring 122.

[0183] Pixel 10 shown in Figure 13B illustrates an example where subpixels are arranged in a stripe pattern, and the positions of subpixels of the same color are shifted in the direction of extension of wirings 121 and 122. In other words, in pixel 10, subpixels of the same color are arranged in a zigzag pattern in the direction of extension of wirings 121 and 122.

[0184] In Figures 12A, 12B, 13A, and 13B, examples are shown where the subpixel emits light in a combination of three colors: red (R), green (G), and blue (B). However, the combination and number of colors are not limited to these. The subpixel may emit light in a combination of four colors: red (R), green (G), blue (B), and white (W), or red (R), green (G), blue (B), and yellow (Y). The color elements applied to the subpixel are not limited to those mentioned above, and combinations of cyan (C) and magenta (M), etc., may also be used.

[0185] In this specification, the blue wavelength range is 400 nm or more and less than 490 nm, and the blue emission has at least one emission spectral peak in this wavelength range. The green wavelength range is 490 nm or more and less than 580 nm, and the green emission has at least one emission spectral peak in this wavelength range. The red wavelength range is 580 nm or more and 680 nm or less, and the red emission has at least one emission spectral peak in this wavelength range.

[0186] <Example of display device configuration 1> The following describes in detail a display device according to one embodiment of the present invention.

[0187] Figure 14 shows a block diagram illustrating an example configuration of the display device 100. The display device 100 includes a pixel section 150 having a plurality of pixels 10, a drive circuit section 130, a drive circuit section 140a, a drive circuit section 140b, wiring 121, wiring 122, wiring 123, and wiring 131.

[0188] The pixel unit 150 has multiple pixels 10, and each pixel 10 can be arranged in a matrix. The drive circuit unit 130 is electrically connected to the pixels 10 via wiring 121. The drive circuit unit 130 is electrically connected to the pixels 10 via wiring 122. The drive circuit unit 130 is also electrically connected to the pixels 10 via wiring 123. The drive circuit unit 130 functions as a gate line drive circuit (also called a gate driver). Each of the multiple pixels 10 is controlled by a signal supplied from the drive circuit unit 130 via wiring 121 and wiring 122. The drive circuit units 140a and 140b are each electrically connected to the pixels 10 via wiring 131. The drive circuit units 140a and 140b each function as source line drive circuits (also called source drivers). Each of the multiple pixels 10 is controlled by a signal supplied from either the drive circuit unit 140a or the drive circuit unit 140b via wiring 131. Figure 14 shows an example where the pixels 10 in odd-numbered rows are electrically connected to the drive circuit unit 140a, and the pixels 10 in even-numbered rows are electrically connected to the drive circuit unit 140b.

[0189] A display device according to one aspect of the present invention has multiple drive circuit units that function as source drivers, enabling high-speed operation even in display devices with a large number of pixels. A display device according to one aspect of the present invention can be suitably used in high-definition display devices with resolutions of 1000 ppi or more, 2000 ppi or more, or 5000 ppi or more.

[0190] Although Figure 14 shows an example in which two drive circuits, drive circuit 140a and drive circuit 140b, are provided as source drivers, the present invention is not limited to this. Three or more drive circuits that function as source drivers may be provided. Alternatively, only one drive circuit that functions as a source driver may be provided.

[0191] Figure 15 shows a schematic diagram illustrating an example configuration of the display device 100. The display device 100 has a laminated structure comprising a first layer 20 and a second layer 30 on the first layer 20. Figure 15A shows a configuration in which the second layer 30 is provided on the first layer 20, but the present invention is not limited to this. The first layer 20 may be provided on the second layer 30. One or more interlayer insulating layers and wiring layers may be provided between the first layer 20 and the second layer 30. Furthermore, there may be multiple interlayer insulating layers and wiring layers provided between the first layer 20 and the second layer 30.

[0192] The first layer 20 has a drive circuit section 140a and a drive circuit section 140b. The second layer 30 has a drive circuit section 130 and a pixel section 150.

[0193] Figure 15B shows an example configuration of the first layer 20 and the second layer 30 shown in Figure 15A. In Figure 15B, the positional relationship between the first layer 20 and the second layer 30 is indicated by white circles and dashed lines, with the white circles of the first layer 20 and the white circles of the second layer 30 overlapping and connected by the dashed line. The same notation is used in other figures. Note that, in order to make the figure clearer, wiring other than wiring 121, 122, 123, and 131 is omitted in Figure 15B.

[0194] Preferably, the display device 100 has a drive circuit section 140a and a drive circuit section 140b provided on the first layer 20, each having an area that overlaps with the pixel section 150. By stacking the display device 100 so that the pixel section 150 and the drive circuit sections 140a and 140b have overlapping areas, the area of ​​the bezel, which is the area where the pixel section 150 is not provided, can be reduced. Therefore, the bezel of the display device 100 can be made narrower. Furthermore, by making the bezel of the display device 100 narrower, the display device 100 can be made more compact.

[0195] Figure 15B shows an example where the first layer 20 and the second layer 30 are approximately the same size, but the outline of the present invention is not limited to this. The sizes of the first layer 20 and the second layer 30 may be different. For example, the first layer 20 may be larger than the second layer 30. Alternatively, the first layer 20 may be smaller than the second layer 30.

[0196] The display device 100 can be manufactured by forming the first layer 20 and then forming the second layer 30 on top of the first layer 20. By forming the second layer 30 on top of the first layer 20, the alignment accuracy between the first layer 20 and the second layer 30 can be improved. Therefore, the productivity of the display device 100 can be increased.

[0197] The display device 100 may be manufactured by forming the first layer 20 and the second layer 30 separately, and then bonding the first layer 20 and the second layer 30 together. When manufacturing the display device 100 by bonding the first layer 20 and the second layer 30 together, the sizes of the first layer 20 and the second layer 30 may be different. Therefore, the first layer 20 and the second layer 30 can be formed without being affected by each other's size. For example, the display device 100 can be manufactured by forming multiple first layers 20 on a substrate to which the first layer 20 is formed, dividing each first layer 20, and then bonding them with the second layer 30. Similarly, the display device 100 can be manufactured by forming multiple second layers 30 on a substrate to which the second layer 30 is formed, dividing each second layer 30, and then bonding them with the first layer 20. In other words, it is possible to increase the productivity of the first layer 20 and the second layer 30, as well as the productivity of the display device 100.

[0198] <Example of display device configuration 2> A configuration example different from the display device 100 shown in FIGS. 15A and 15B is shown in FIGS. 16A and 16B. The display device 100 shown in FIGS. 16A and 16B is mainly different from the display device 100 shown in FIGS. 15A and 15B in that the first layer 20 has a drive circuit section 130. By providing the drive circuit section 130 in the same first layer 20 as the drive circuit sections 140a and 140b, the manufacturing processes of the drive circuit section 130 and the drive circuit sections 140a and 140b can be made common, and productivity can be increased.

[0199] In addition, in FIG. 16B, an example in which the pixel section 150 does not have an area overlapping with the drive circuit section 130 is shown, but one aspect of the present invention is not limited to this. The pixel section 150 may have an area overlapping with the drive circuit section 130. Also, the pixel section 150 may have an area overlapping with any of the drive circuit section 130, the drive circuit section 140a, and the drive circuit section 140b. With such a configuration, the frame of the display device 100 can be narrowed. Also, by narrowing the frame of the display device 100, the display device 100 can be made smaller.

[0200] <Cross-sectional configuration example 1 of display device> A cross-sectional view showing a configuration example of the display device 100 is shown in FIG. 17. The display device 100 has a substrate 701 and a substrate 705, and the substrate 701 and the substrate 705 are bonded together by a sealing material 712.

[0201] As the substrate 701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. Note that a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 701.

[0202] Transistors 441 and 601 are provided on substrate 701. Transistors 441 and 601 can be the transistors provided in the first layer 20. For example, in display device 100 shown in FIGS. 15A and 15B, transistors 441 and 601 can be the transistors provided in driving circuit portion 140a or driving circuit portion 140b. For example, in display device 100 shown in FIGS. 16A and 16B, transistors 441 and 601 can be the transistors provided in driving circuit portion 130, driving circuit portion 140a or driving circuit portion 140b.

[0203] Transistor 441 is composed of conductor 443 having a function as a gate electrode, insulator 445 having a function as a gate insulator, and a part of substrate 701, and has semiconductor region 447 including a channel formation region, low resistance region 449a having a function as one of a source region or a drain region, and low resistance region 449b having a function as the other of the source region or the drain region. Transistor 441 can be either p-channel type or n-channel type.

[0204] Transistor 441 is electrically separated from other transistors by element isolation layer 403. FIG. 17 shows a case where transistor 441 and transistor 601 are electrically separated by element isolation layer 403. Element isolation layer 403 can be formed using a method such as the LOCOS (Local Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method.

[0205] Here, semiconductor region 447 of transistor 441 shown in FIG. 17 has a convex shape. Also, the side surface and the upper surface of semiconductor region 447 are provided so as to be covered by conductor 443 via insulator 445. Note that in FIG. 17, the state where conductor 443 covers the side surface of semiconductor region 447 is not illustrated. Also, a material for adjusting the work function can be used for conductor 443.

[0206] A transistor with a convex semiconductor region, such as transistor 441, can be called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. Furthermore, while Figure 17 shows a configuration where a portion of the substrate 701 is processed to form the convex portion, a semiconductor with a convex shape may also be formed by processing an SOI substrate.

[0207] Note that the configuration of transistor 441 shown in Figure 17 is just one example, and the system is not limited to this configuration. An appropriate configuration may be used depending on the circuit configuration or the way the circuit operates. For example, transistor 441 may be a planar transistor.

[0208] Transistor 601 can have the same configuration as transistor 441.

[0209] On the substrate 701, in addition to the element isolation layer 403, transistors 441 and 601, insulators 405, 407, 409, and 411 are provided. Conductors 451 are embedded in insulators 405, 407, 409, and 411. Here, the height of the upper surface of the conductor 451 and the height of the upper surface of the insulator 411 can be made to be approximately the same.

[0210] Insulators 413 and 415 are provided on the conductor 451 and on the insulator 411, respectively. Furthermore, a conductor 457 is embedded in insulators 413 and 415. Here, the height of the upper surface of conductor 457 and the height of the upper surface of insulator 415 can be made to be approximately the same.

[0211] Insulators 417 and 419 are provided on the conductor 457 and on the insulator 415, respectively. Furthermore, the conductor 459 is embedded in the insulator 417 and in the insulator 419. Here, the height of the upper surface of the conductor 459 and the height of the upper surface of the insulator 419 can be made to be approximately the same.

[0212] Insulators 421 and 214 are provided on the conductor 459 and the insulator 419, respectively. The conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the upper surface of the conductor 453 and the height of the upper surface of the insulator 214 can be made to be approximately the same.

[0213] An insulator 216 is provided on the conductor 453 and on the insulator 214. The conductor 455 is embedded in the insulator 216. Here, the height of the upper surface of the conductor 455 and the height of the upper surface of the insulator 216 can be made to be approximately the same.

[0214] Insulators 222, 224, 254, 244, 280, 274, and 281 are provided on the conductor 455 and on the insulator 216. The conductor 305 is embedded in insulators 222, 224, 254, 244, 280, 274, and 281. Here, the height of the upper surface of the conductor 305 and the height of the upper surface of the insulator 281 can be made to be approximately the same.

[0215] An insulator 361 is provided on the conductor 305 and on the insulator 281. Conductors 317 and 337 are embedded in the insulator 361. Here, the height of the upper surface of the conductor 337 and the height of the upper surface of the insulator 361 can be made to be approximately the same.

[0216] An insulator 363 is provided on the conductor 337 and on the insulator 361. Conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the upper surfaces of conductors 353, 355, and 357 can be made to be approximately the same as the height of the upper surface of the insulator 363.

[0217] Connecting electrodes 760 are provided on the conductor 353, conductor 355, conductor 357, and insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connecting electrodes 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 100 from outside the display device 100 via the FPC 716.

[0218] As shown in Figure 17, the low-resistance region 449b of transistor 441, which functions as either the source region or the drain region, is electrically connected to the FPC 716 via conductors 451, 457, 459, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780. Here, Figure 17 shows three conductors, conductors 353, 355, and 357, which have the function of electrically connecting the connecting electrode 760 and conductor 347, but the present invention is not limited to these. There may be one, two, or four or more conductors that have the function of electrically connecting the connecting electrode 760 and conductor 347. By providing multiple conductors that have the function of electrically connecting the connecting electrode 760 and the conductor 347, the contact resistance can be reduced.

[0219] A transistor 750 is provided on the insulator 214. The transistor 750 can be a transistor provided on the second layer 30. For example, in the display device 100 shown in Figures 15A, 15B, 16A, and 16B, the transistor 750 can be a transistor provided on the pixel section 150. An OS transistor can preferably be used for the transistor 750. OS transistors have the characteristic of having an extremely small off-current. Therefore, the holding time of image signals, etc. can be extended, and the frequency of refresh operations can be reduced. Therefore, the power consumption of the display device 100 can be reduced.

[0220] Conductors 301a and 301b are embedded in insulators 254, 244, 280, 274, and 281, respectively. Conductor 301a is electrically connected to either the source or drain of transistor 750, and conductor 301b is electrically connected to the other source or drain of transistor 750. Here, the height of the upper surfaces of conductors 301a and 301b can be made to be approximately the same as the height of the upper surface of insulator 281.

[0221] Conductors 311, 313, 331, capacitive element 790, 333, and 335 are embedded in the insulator 361. Conductors 311 and 313 are electrically connected to the transistor 750 and function as wiring. Conductors 333 and 335 are electrically connected to the capacitive element 790. Here, the height of the upper surfaces of conductors 331, 333, and 335 can be made to be approximately the same as the height of the upper surface of the insulator 361.

[0222] Conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the upper surface of conductor 351 and the height of the upper surface of insulator 363 can be made to be approximately the same.

[0223] Insulators 405, 407, 409, 411, 413, 415, 417, 419, 421, 214, 280, 274, 281, 361, and 363 may function as interlayer films and as planarizing films that cover the uneven shapes beneath them. For example, the upper surface of insulator 363 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0224] For example, in the display device 100 shown in Figures 15 and 16, the capacitive element 790 can be a capacitive element 111 or a capacitive element 112 provided in the pixel section 150.

[0225] As shown in FIG. 17, the capacitive element 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitive element 790 has a stacked structure in which an insulator 323 that functions as a dielectric is sandwiched between a pair of electrodes. Although FIG. 17 shows an example in which the capacitive element 790 is provided on the insulator 281, the capacitive element 790 may be provided on an insulator different from the insulator 281.

[0226] In FIG. 17, an example in which the conductors 301a, 301b, and 305 are formed in the same layer is shown. Also shown is an example in which the conductors 311, 313, 317, and the lower electrode 321 are formed in the same layer. Also shown is an example in which the conductors 331, 333, 335, and 337 are formed in the same layer. Also shown is an example in which the conductors 341, 343, and 347 are formed in the same layer. Further, an example in which the conductors 351, 353, 355, and 357 are formed in the same layer is shown. By forming a plurality of conductors in the same layer, the manufacturing process of the display device 100 can be simplified, and thus the manufacturing cost of the display device 100 can be reduced. Note that these may be formed in different layers and may have different types of materials.

[0227] The display device 100 shown in FIG. 17 has a light-emitting device 782. The light-emitting device 782 has a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 contains an organic compound or an inorganic compound such as quantum dots.

[0228] Examples of materials that can be used for the organic compound include a fluorescent material or a phosphorescent material. Examples of materials that can be used for the quantum dots include a colloidal quantum dot material, an alloy-type quantum dot material, a core-shell-type quantum dot material, and a core-type quantum dot material.

[0229] The conductor 772 is electrically connected to the other side of the source or drain of the transistor 750 via conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed on the insulator 363 and functions as a pixel electrode.

[0230] The conductor 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. As a transparent material, for example, an oxide material containing indium, zinc, tin, etc., may be used. As a reflective material, for example, a material containing aluminum, silver, etc., may be used.

[0231] Although not shown in Figure 17, the display device 100 can be equipped with optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members.

[0232] On the substrate 705 side, a light-shielding layer 738 and an insulator 734 in contact with them are provided. The light-shielding layer 738 has the function of blocking light emitted from adjacent areas. Alternatively, the light-shielding layer 738 has the function of preventing ambient light from reaching the transistor 750, etc.

[0233] In the display device 100 shown in Figure 17, an insulator 730 is provided on the insulator 363. Here, the insulator 730 can be configured to cover a portion of the conductor 772. The light-emitting device 782 has a translucent conductor 788 and can be a top-emission type light-emitting device. The light-emitting device 782 may have a bottom-emission structure that emits light towards the conductor 772, or a dual-emission structure that emits light towards both the conductor 772 and the conductor 788.

[0234] The light-shielding layer 738 is provided so as to have an overlapping region with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. Furthermore, the space between the light-emitting device 782 and the insulator 734 is filled with a sealing layer 732.

[0235] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. Also, the structure 778 is provided between the insulator 730 and the insulator 734.

[0236] Figure 18 shows a modified version of the display device 100 shown in Figure 17. The display device 100 shown in Figure 18 differs from the display device 100 shown in Figure 17 in that it has a colored layer 736. The colored layer 736 is provided so as to have an area that overlaps with the light-emitting device 782. By providing the colored layer 736, the color purity of the light extracted from the light-emitting device 782 can be increased. As a result, the display device 100 can display high-resolution images. Furthermore, since, for example, all of the light-emitting devices 782 of the display device 100 can be light-emitting devices that emit white light, it is not necessary to form the EL layer 786 by painting, and the display device 100 can be made high-resolution.

[0237] The light-emitting device 782 can have a microcavity structure. This allows light of a predetermined color (e.g., RGB) to be extracted without the need for a colored layer, enabling the display device 100 to display in color. By omitting the colored layer, light absorption by the colored layer can be suppressed. This allows the display device 100 to display high-brightness images and reduces the power consumption of the display device 100. Furthermore, even when the EL layer 786 is formed in an island-like pattern for each pixel or in a striped pattern for each row of pixels, i.e., formed by color separation, the display device 100 can still be configured without a colored layer.

[0238] Figures 17 and 18 show a configuration in which transistors 441 and 601 are arranged inside a substrate 701 such that a channel formation region is formed, and transistor 750 is stacked on top of transistors 441 and 601. However, the present invention is not limited to this. A modified example of Figure 18 is shown in Figure 19. The main difference between the display device 100 shown in Figure 18 and the display device 100 shown in Figure 19 is that it has OS transistors, transistors 602 and 603, instead of transistors 441 and 601. Also, transistor 750 can be an OS transistor. In other words, the display device 100 shown in Figure 19 has OS transistors stacked on top of each other.

[0239] Insulators 613 and 614 are provided on the substrate 701, and transistors 602 and 603 are provided on the insulator 614. Note that transistors or the like may be provided between the substrate 701 and the insulator 613. For example, a transistor with the same configuration as transistors 441 and 601 shown in Figure 18 may be provided between the substrate 701 and the insulator 613.

[0240] Transistors 602 and 603 can be transistors provided in the first layer 20. For example, in the display device 100 shown in Figures 15A and 15B, transistors 602 and 603 can be transistors provided in the drive circuit section 140a or drive circuit section 140b. For example, in the display device 100 shown in Figures 16A and 16B, transistors 602 and 603 can be transistors provided in the drive circuit section 130, drive circuit section 140a or drive circuit section 140b.

[0241] Transistors 602 and 603 can be transistors with the same configuration as transistor 750. Alternatively, transistors 602 and 603 may be OS transistors with a different configuration than transistor 750.

[0242] On the insulator 614, in addition to transistors 602 and 603, insulators 616, 622, 624, 654, 644, 680, 674, and 681 are provided. Conductors 461 are embedded in insulators 654, 644, 680, 674, and 681. Here, the height of the upper surface of the conductor 461 and the height of the upper surface of the insulator 681 can be made to be approximately the same.

[0243] An insulator 501 is provided on the conductor 461 and on the insulator 681. The conductor 463 is embedded in the insulator 501. Here, the height of the upper surface of the conductor 463 and the height of the upper surface of the insulator 501 can be made to be approximately the same.

[0244] An insulator 503 is provided on the conductor 463 and on the insulator 501. The conductor 465 is embedded in the insulator 503. Here, the height of the upper surface of the conductor 465 and the height of the upper surface of the insulator 503 can be made to be approximately the same.

[0245] An insulator 505 is provided on the conductor 465 and on the insulator 503. Furthermore, a conductor 467 is embedded within the insulator 505. Here, the height of the upper surface of the conductor 467 and the height of the upper surface of the insulator 505 can be made approximately the same.

[0246] An insulator 507 is provided on the conductor 467 and on the insulator 505. The conductor 469 is embedded in the insulator 507. Here, the height of the upper surface of the conductor 469 and the height of the upper surface of the insulator 507 can be made to be approximately the same.

[0247] An insulator 509 is provided on the conductor 469 and on the insulator 507. Furthermore, a conductor 471 is embedded within the insulator 509. Here, the height of the upper surface of the conductor 471 and the height of the upper surface of the insulator 509 can be made approximately the same.

[0248] Insulators 421 and 214 are provided on the conductor 471 and the insulator 509, respectively. Conductors 453 are embedded in insulators 421 and 214. Here, the height of the upper surface of conductor 453 and the height of the upper surface of insulator 214 can be made to be approximately the same.

[0249] As shown in Figure 19, either the source or drain of transistor 602 is electrically connected to FPC 716 via conductors 461, 463, 465, 467, 469, 471, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780.

[0250] Insulators 613, 614, 680, 674, 681, 501, 503, 505, 507, and 509 may function as interlayer films and as planarizing films that cover the uneven shapes beneath them.

[0251] By configuring the display device 100 as shown in Figure 19, the display device 100 can be made smaller and have a narrower bezel, while all of its transistors can be OS transistors. This allows, for example, the transistors provided in the first layer 20 and the transistors provided in the second layer 30 to be manufactured using the same equipment. Therefore, the manufacturing cost of the display device 100 can be reduced, making the display device 100 a low-cost product.

[0252] <Example of cross-sectional configuration of a display device 2> Figure 20 is a cross-sectional view showing an example configuration of the display device 100. It differs from the display device 100 shown in Figure 18 in that it has a layer with transistor 800 between the layer with transistor 750 and the layer with transistors 441 and 601. In Figure 20, a configuration is shown in which transistors 601, 750, and 800 each have overlapping regions, but the present invention is not limited to this. For example, transistors 601 and 750 may have overlapping regions, while transistor 800, transistors 601, and transistor 750 may not each have overlapping regions. Alternatively, transistors 601 and 800 may have overlapping regions, while transistor 750, transistors 601, and transistor 800 may not each have overlapping regions.

[0253] The first layer 20 shown in Figure 15A, etc., can be a stacked structure of a first circuit layer and a second circuit layer on the first circuit layer. For example, transistors 441 and 601 can be transistors provided on the first circuit layer. Transistor 800 can be a transistor provided on the second circuit layer. Transistor 750 can be a transistor provided on the second layer 30.

[0254] Insulators 821 and 814 are provided on the conductor 459 and the insulator 419, respectively. Conductor 853 is embedded in insulator 821 and insulator 814. Here, the height of the upper surface of conductor 853 and the height of the upper surface of insulator 814 can be made to be approximately the same.

[0255] An insulator 816 is provided on the conductor 853 and on the insulator 814. The conductor 855 is embedded in the insulator 816. Here, the height of the upper surface of the conductor 855 and the height of the upper surface of the insulator 816 can be made to be approximately the same.

[0256] Insulators 822, 824, 854, 844, 880, 874, and 881 are provided on the conductor 855 and on the insulator 816. Conductors 805 are embedded in insulators 822, 824, 854, 844, 880, 874, and 881. Here, the height of the upper surface of conductor 805 and the height of the upper surface of insulator 881 can be made to be approximately the same.

[0257] Insulators 421 and 214 are provided on the conductor 817 and on the insulator 881, respectively.

[0258] As shown in Figure 20, the low-resistance region 449b, which functions as either the source region or the drain region of transistor 441, is electrically connected to the FPC 716 via conductors 451, 457, 459, 853, 855, 805, 817, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780.

[0259] A transistor 800 is provided on the insulator 814. The transistor 800 can be a transistor provided on the first layer 20. For example, in the display device 100 shown in Figures 15A and 15B, the transistor 800 can be a transistor provided in the drive circuit section 140a or drive circuit section 140b. For example, in the display device 100 shown in Figures 16A and 16B, the transistor 800 can be a transistor provided in the drive circuit section 130, drive circuit section 140a or drive circuit section 140b. It is preferable that the transistor 800 is an OS transistor.

[0260] Conductors 801a and 801b are embedded in insulators 854, 844, 880, 874, and 881, respectively. Conductor 801a is electrically connected to either the source or drain of transistor 800, and conductor 801b is electrically connected to the other source or drain of transistor 800. Here, the height of the upper surfaces of conductors 801a and 801b can be made to be approximately the same as the height of the upper surface of insulator 881.

[0261] The transistor 750 can be a transistor provided in the second layer 30. For example, in the display device 100 shown in Figures 15A, 15B, 16A, and 16B, the transistor 750 can be a transistor provided in the pixel section 150. It is preferable that the transistor 750 is an OS transistor.

[0262] Furthermore, an OS transistor or the like may be provided between the layer on which transistors 441 and 601 are provided and the layer on which transistors 800 are provided. Also, an OS transistor or the like may be provided between the layer on which transistors 800 are provided and the layer on which transistors 750 are provided. Moreover, an OS transistor or the like may be provided in a layer above the layer on which transistors 750 are provided.

[0263] Insulators 405, 407, 409, 411, 413, 415, 417, 419, 821, 814, 880, 874, 881, 421, 214, 280, 274, 281, 361, and 363 may function as interlayer films and as flattening films that cover the uneven shapes beneath them.

[0264] Figure 20 shows an example in which conductors 801a, 801b, and 805 are formed in the same layer. It also shows an example in which conductors 811, 813, and 817 are formed in the same layer.

[0265] Figure 20 shows a configuration in which transistors 441 and 601 are provided inside the substrate 701 such that a channel formation region is formed, and transistors 800 and 750 are provided by stacking them on top of transistors 441 and 601. However, the present invention is not limited to this. A modified example of Figure 20 is shown in Figure 21. The display device 100 shown in Figure 21 differs from the display device 100 shown in Figure 20 in that it has OS transistors, transistors 602 and 603, instead of transistors 441 and 601. In other words, the display device 100 shown in Figure 21 has OS transistors stacked in three layers.

[0266] OS transistors may be provided between the layer on which transistors 602 and 603 are provided and the layer on which transistors 800 are provided. Furthermore, OS transistors may be provided between the layer on which transistors 800 are provided and the layer on which transistors 750 or 750 are provided. Additionally, OS transistors may be provided in a layer above the layer on which transistors 750 are provided.

[0267] For example, transistors 602 and 603 may be transistors provided in the first circuit layer of the first layer 20. Transistor 800 may be a transistor provided in the second circuit layer of the first layer 20. Transistor 750 may be a transistor provided in the second layer 30.

[0268] Insulators 821 and 814 are provided on the conductor 471 and the insulator 509, respectively. Conductors 853 are embedded in insulators 821 and 814. Here, the height of the upper surface of conductor 853 and the height of the upper surface of insulator 814 can be made to be approximately the same.

[0269] As shown in Figure 21, either the source or drain of transistor 602 is electrically connected to FPC 716 via conductors 461, 463, 465, 467, 469, 471, 853, 855, 805, 817, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780.

[0270] By configuring the display device 100 as shown in Figure 21, a narrow-bezel and compact display device 100 can be made. Furthermore, by making all the transistors in the display device 100 OS transistors, the need to manufacture different types of transistors is eliminated, thereby reducing the manufacturing cost of the display device 100 and making the display device 100 inexpensive.

[0271] <Example of light-emitting device configuration> As the light-emitting device 572, for example, an EL element utilizing electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (hereinafter also referred to as the EL layer) between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting material contained in the EL layer emits light.

[0272] EL elements are distinguished by whether the light-emitting material is an organic compound or an inorganic compound; generally, the former are called organic EL elements, and the latter are called inorganic EL elements.

[0273] In organic light-emitting diodes (ELs), applying a voltage injects electrons into the EL layer from one electrode and holes from the other. These carriers (electrons and holes) then recombine, causing the luminescent organic compound to form an excited state. Light is emitted when this excited state returns to the ground state. Because of this mechanism, such light-emitting devices are called current-excited light-emitting devices.

[0274] In this specification, the voltage supplied to a display element such as a light-emitting device or liquid crystal element refers to the difference between the potential applied to one electrode of the display element and the potential applied to the other electrode of the display element.

[0275] In addition to luminescent compounds, the EL layer may also contain substances with high hole injection properties, substances with high hole transport properties, hole blocking materials, substances with high electron transport properties, substances with high electron injection properties, or bipolar substances (substances with high electron transport and hole transport properties).

[0276] The EL layer can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0277] Inorganic electroluminescent (EL) devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their device configuration. Dispersed inorganic EL devices have an emissive layer in which particles of emissive material are dispersed in a binder, and the emissive mechanism is donor-acceptor recombination type emissive emission, which utilizes donor and acceptor levels. Thin-film inorganic EL devices have a structure in which the emissive layer is sandwiched between dielectric layers, and then sandwiched between electrodes, and the emissive mechanism is localized type emissive emission, which utilizes inner-shell electron transitions of metal ions.

[0278] A light-emitting device only requires that at least one of its pair of electrodes is transparent in order to extract light. The transistor and light-emitting device are formed on a substrate, and there are light-emitting devices with top emission structures that extract light from the side opposite the substrate, bottom emission structures that extract light from the side facing the substrate, and dual emission structures that extract light from both sides. Any of these emission structures can be applied to the light-emitting device.

[0279] Figures 22A to 22E show examples of the configuration of the light-emitting device 572. Figure 22A shows a structure (single structure) in which an EL layer 786 is sandwiched between a conductor 772 and a conductor 788. As mentioned above, the EL layer 786 contains a light-emitting material, for example, an organic compound light-emitting material.

[0280] Figure 22B shows the stacked structure of the EL layer 786. In the light-emitting device 572 with the structure shown in Figure 22B, the conductor 772 functions as the anode, and the conductor 788 functions as the cathode.

[0281] The EL layer 786 has a structure in which a hole injection layer 721, a hole transport layer 722, a light-emitting layer 723, an electron transport layer 724, and an electron injection layer 725 are sequentially stacked on top of a conductor 772. Note that if the conductor 772 functions as a cathode and the conductor 788 functions as an anode, the stacking order is reversed.

[0282] The light-emitting layer 723 comprises a combination of light-emitting materials or multiple materials as appropriate, and can be configured to produce fluorescence or phosphorescence that exhibits a desired emission color. Alternatively, the light-emitting layer 723 may have a laminated structure with different emission colors. In this case, the light-emitting material and other materials used in each laminated light-emitting layer may be different materials.

[0283] In the light-emitting device 572, for example, by using the conductor 772 shown in Figure 22B as a reflective electrode and the conductor 788 as a semi-transmissive / semi-reflective electrode, a microcavity structure can be formed. This allows the light emitted from the light-emitting layer 723 contained in the EL layer 786 to resonate between the two electrodes, thereby strengthening the light emitted through the conductor 788.

[0284] Furthermore, if the conductor 772 of the light-emitting device 572 is a reflective electrode consisting of a laminated structure of a reflective conductive material and a translucent conductive material (transparent conductive film), optical adjustment can be performed by controlling the thickness of the transparent conductive film. Specifically, it is preferable to adjust the electrode distance between the conductor 772 and the conductor 788 to be approximately mλ / 2 (where m is a natural number) with respect to the wavelength λ of the light obtained from the light-emitting layer 723.

[0285] In order to amplify the desired light (wavelength: λ) obtained from the light-emitting layer 723, it is preferable to adjust the optical distance from the conductor 772 to the region of the light-emitting layer from which the desired light is obtained (light-emitting region), and the optical distance from the conductor 788 to the region of the light-emitting layer 723 from which the desired light is obtained (light-emitting region), so that they are both near (2m'+1)λ / 4 (where m' is a natural number). The light-emitting region referred to here is the region in the light-emitting layer 723 where holes and electrons recombine.

[0286] By performing such optical adjustments, the spectrum of specific monochromatic light obtained from the light-emitting layer 723 can be narrowed, resulting in emission with good color purity.

[0287] However, in the above case, the optical distance between the conductor 772 and the conductor 788 can be precisely defined as the total thickness from the reflective region of the conductor 772 to the reflective region of the conductor 788. However, since it is difficult to precisely determine the reflective regions of the conductor 772 and the conductor 788, the above effects can be sufficiently obtained by assuming that any position on the conductor 772 and the conductor 788 is the reflective region. Furthermore, the optical distance between the conductor 772 and the light-emitting layer from which the desired light is obtained can be precisely defined as the optical distance between the reflective region of the conductor 772 and the light-emitting region on the light-emitting layer from which the desired light is obtained. However, since it is difficult to precisely determine the reflective region of the conductor 772 and the light-emitting region on the light-emitting layer from which the desired light is obtained, the above effects can be sufficiently obtained by assuming that any position on the conductor 772 is the reflective region and any position on the light-emitting layer from which the desired light is obtained is the light-emitting region.

[0288] The light-emitting device 572 shown in Figure 22B has a microcavity structure, which allows it to extract light of different wavelengths (monochromatic light) even with the same EL layer. Therefore, color separation (e.g., RGB) to obtain different emission colors is unnecessary. Consequently, high resolution can be easily achieved. It can also be combined with a colored layer. Furthermore, it is possible to strengthen the emission intensity in the front direction at a specific wavelength, thus enabling lower power consumption.

[0289] Note that the light-emitting device 572 shown in Figure 22B does not necessarily have a microcavity structure. In this case, the light-emitting layer 723 is structured to emit white light, and by providing a colored layer, light of a predetermined color (e.g., RGB) can be extracted. Alternatively, when forming the EL layer 786, if different colors are applied to obtain different light emission colors, light of a predetermined color can be extracted without providing a colored layer.

[0290] At least one of the conductors 772 and 788 can be a light-transmitting electrode (transparent electrode, semi-transparent / semi-reflective electrode, etc.). If the light-transmitting electrode is a transparent electrode, the visible light transmittance of the transparent electrode shall be 40% or more. If it is a semi-transparent / semi-reflective electrode, the visible light reflectance of the semi-transparent / semi-reflective electrode shall be 20% or more and 80% or less, preferably 40% or more and 70% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ -2 A value of Ωcm or less is preferable.

[0291] If the conductor 772 or conductor 788 is a reflective electrode (reflective electrode), the visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of this electrode shall be 1 × 10⁻⁶ -2 A value of Ωcm or less is preferable.

[0292] The configuration of the light-emitting device 572 may be as shown in Figure 22C. Figure 22C shows a light-emitting device 572 with a stacked structure (tandem structure) in which two EL layers (EL layer 786a and EL layer 786b) are provided between the conductor 772 and the conductor 788, and a charge generation layer 792 is provided between the EL layer 786a and the EL layer 786b. By making the light-emitting device 572 a tandem structure, the current efficiency and external quantum efficiency of the light-emitting device 572 can be increased. Therefore, a high-brightness image can be displayed on the display device 100. In addition, the power consumption of the display device 100 can be reduced. Here, the EL layers 786a and EL layers 786b can have the same configuration as the EL layer 786 shown in Figure 22B.

[0293] The charge generation layer 792 has the function of injecting electrons into one of the EL layers 786a and 786b, and holes into the other, when a voltage is supplied between the conductor 772 and the conductor 788. Therefore, when a voltage is supplied such that the potential of the conductor 772 is higher than the potential of the conductor 788, electrons are injected from the charge generation layer 792 into the EL layer 786a, and holes are injected from the charge generation layer 792 into the EL layer 786b.

[0294] Furthermore, from the viewpoint of light extraction efficiency, it is preferable that the charge generation layer 792 transmits visible light (specifically, the visible light transmittance of the charge generation layer 792 is 40% or more). Also, the conductivity of the charge generation layer 792 may be lower than the conductivity of the conductor 772 or the conductivity of the conductor 788.

[0295] The configuration of the light-emitting device 572 may be as shown in Figure 22D. Figure 22D shows a tandem structure light-emitting device 572 having three EL layers (EL layer 786a, EL layer 786b, and EL layer 786c) between the conductor 772 and the conductor 788, with charge generation layers 792 between EL layer 786a and EL layer 786b, and between EL layer 786b and EL layer 786c. Here, EL layers 786a, EL layer 786b, and EL layer 786c can have the same configuration as EL layer 786 shown in Figure 22B. By configuring the light-emitting device 572 as shown in Figure 22D, the current efficiency and external quantum efficiency of the light-emitting device 572 can be further increased. Therefore, the display device 100 can display images with even higher brightness. In addition, the power consumption of the display device 100 can be further reduced.

[0296] The configuration of the light-emitting device 572 may be as shown in Figure 22E. Figure 22E shows a tandem structure light-emitting device 572 having n layers of EL (EL layer 786(1) to EL layer 786(n)) between a conductor 772 and a conductor 788, and a charge generation layer 792 between each of the EL layers 786. Here, the EL layers 786(1) to EL layers 786(n) can have the same configuration as the EL layer 786 shown in Figure 22B. Note that Figure 22E shows EL layer 786(1), EL layer 786(m), EL layer 786(m+1), and EL layer 786(n) among the EL layers 786. Here, m is an integer between 2 and n, and n is an integer greater than or equal to m. The larger the value of n, the higher the current efficiency and external quantum efficiency of the light-emitting device 572 can be. Therefore, a high-brightness image can be displayed on the display device 100. In addition, the power consumption of the display device 100 can be reduced.

[0297] The constituent materials that can be used in the light-emitting device 572 will be described below.

[0298] [Conductors 772 and 788] Conductors 772 and 788 can be made from the following materials in appropriate combinations, provided that they satisfy the functions of an anode and a cathode. For example, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, these include In-Sn oxide (also known as ITO), In-Si-Sn oxide (also known as ITSO), In-Zn oxide, and In-W-Zn oxide. In addition, metals such as aluminum (Al), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), gallium (Ga), zinc (Zn), indium (In), tin (Sn), molybdenum (Mo), tantalum (Ta), tungsten (W), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), yttrium (Y), neodymium (Nd), and alloys containing these in appropriate combinations can also be used. In addition, elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (for example, lithium (Li), cesium (Cs), calcium (Ca), strontium (Sr)), rare earth metals such as europium (Eu) and ytterbium (Yb), and alloys containing these in appropriate combinations, as well as graphene and other materials can be used.

[0299] [Hole injection layer 721 and hole transport layer 722] The hole injection layer 721 is a layer that injects holes from the anode conductor 772 or the charge generation layer 792 into the EL layer 786, and is a layer containing a material with high hole injection properties. Here, the EL layer 786 includes EL layer 786a, EL layer 786b, EL layer 786c, and EL layer 786(1) to EL layer 786(n).

[0300] Examples of materials with high hole injection potential include transition metal oxides such as molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, and manganese oxide. In addition, phthalocyanine compounds, aromatic amine compounds, or polymers can be used.

[0301] As a material with high hole injection capabilities, a composite material containing a hole transport material and an acceptor material (electron-accepting material) can also be used. In this case, electrons are extracted from the hole transport material by the acceptor material, generating holes in the hole injection layer 721, and these holes are injected into the light-emitting layer 723 via the hole transport layer 722. The hole injection layer 721 may be formed as a single layer of a composite material containing a hole transport material and an acceptor material (electron-accepting material), or it may be formed by laminating the hole transport material and the acceptor material (electron-accepting material) as separate layers.

[0302] The hole transport layer 722 is a layer that transports holes injected from the conductor 772 by the hole injection layer 721 to the light-emitting layer 723. The hole transport layer 722 is a layer containing a hole-transporting material. It is particularly preferable to use a hole-transporting material for the hole transport layer 722 that has the same or a similar HOMO level as the hole injection layer 721.

[0303] As the acceptor material used in the hole injection layer 721, oxides of metals belonging to groups 4 through 8 of the periodic table can be used. Specifically, examples include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among these, molybdenum oxide is particularly preferred because it is stable in air, has low hygroscopicity, and is easy to handle. In addition, organic acceptors such as quinodimethane derivatives, chloranil derivatives, and hexaazatriphenylene derivatives can be used.

[0304] The hole transport material used in the hole injection layer 721 and the hole transport layer 722 is 10 -6 cm 2 A material having a hole mobility of / Vs or higher is preferred. However, any material that has higher hole transport than electron transport can be used.

[0305] The hole transport material is preferably a π-electron-rich heteroaromatic compound (e.g., carbazole derivatives or indole derivatives) or an aromatic amine compound.

[0306] However, the hole transport material is not limited to the above, and various known materials can be used as hole transport materials in the hole injection layer 721 and the hole transport layer 722 by combining one or more types of materials. Note that the hole transport layer 722 may be formed from multiple layers. That is, for example, a first hole transport layer and a second hole transport layer may be laminated together.

[0307] [Emitting layer 723] The light-emitting layer 723 is a layer containing a light-emitting material. The light-emitting material can be any material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. As shown in Figures 22C, 22D, and 22E, if the light-emitting device 572 has multiple EL layers, different light-emitting materials can be used in the light-emitting layers 723 provided in each EL layer to create a configuration that exhibits different light-emitting colors (for example, white light emission obtained by combining complementary light-emitting colors). For example, if the light-emitting device 572 has the configuration shown in Figure 22C, the light-emitting material used in the light-emitting layer 723 provided in EL layer 786a and the light-emitting layer 723 provided in EL layer 786b can be made to exhibit different light-emitting colors from EL layer 786a and EL layer 786b. A laminated structure in which one light-emitting layer has different light-emitting materials is also possible.

[0308] The light-emitting layer 723 may contain one or more types of organic compounds (host material, assist material) in addition to the light-emitting substance (guest material). Furthermore, one or more types of hole-transporting materials and / or electron-transporting materials can be used as one or more types of organic compounds.

[0309] The light-emitting material that can be used in the light-emitting layer 723 is not particularly limited, and any light-emitting material that converts singlet excitation energy into visible light emission, or a light-emitting material that converts triplet excitation energy into visible light emission, can be used. Examples of such light-emitting materials include the following.

[0310] Examples of luminescent materials that convert singlet excitation energy into light include fluorescent materials, such as pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives. Pyrene derivatives are particularly preferred because they have a high luminescence quantum yield.

[0311] Examples of light-emitting materials that convert triplet excitation energy into light include phosphorescent materials and thermally activated delayed fluorescence (TADF) materials.

[0312] Phosphorescent materials include organometallic complexes, metal complexes (platinum complexes), and rare earth metal complexes. Since each of these exhibits a different emission color (emission peak), they should be selected and used as appropriate.

[0313] For blue light-emitting materials, a material with a photoluminescence peak wavelength of 430 nm to 470 nm, more preferably 430 nm to 460 nm, may be used. For green light-emitting materials, a material with a photoluminescence peak wavelength of 500 nm to 540 nm, more preferably 500 nm to 530 nm, may be used. For red light-emitting materials, a material with a photoluminescence peak wavelength of 610 nm to 680 nm, more preferably 620 nm to 680 nm, may be used. Photoluminescence measurements may be performed in either a solution or a thin film.

[0314] By using such compounds in combination with the microcavity effect, the aforementioned chromaticity can be achieved more easily. In this case, the film thickness of the semi-transparent / semi-reflective electrode (metal thin film portion) required to obtain the microcavity effect is preferably 20 nm to 40 nm. More preferably, it is greater than 25 nm and 40 nm or less. Note that efficiency may decrease if it exceeds 40 nm.

[0315] The organic compounds (host material, assist material) used in the light-emitting layer 723 may be selected from one or more types of materials having an energy gap larger than the energy gap of the light-emitting material (guest material). The hole-transporting material mentioned above and the electron-transporting material described later can also be used as the host material or assist material, respectively.

[0316] When the luminescent material is a fluorescent material, it is preferable to use an organic compound as the host material that has a high energy level in the singlet excited state and a low energy level in the triplet excited state. For example, it is preferable to use anthracene derivatives or tetracene derivatives.

[0317] When the luminescent material is a phosphorescent material, an organic compound with a triplet excitation energy greater than the triplet excitation energy (energy difference between the ground state and the triplet excited state) of the luminescent material should be selected as the host material. In this case, in addition to zinc and aluminum-based metal complexes, oxadiazole derivatives, triazole derivatives, benzimidazole derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, pyrimidine derivatives, triazine derivatives, pyridine derivatives, bipyridine derivatives, phenanthroline derivatives, etc., as well as aromatic amines and carbazole derivatives can be used.

[0318] When multiple organic compounds are used in the light-emitting layer 723, it is preferable to use compounds that form excitation complexes mixed with the light-emitting material. In this case, various organic compounds can be used in appropriate combinations, but in order to efficiently form excitation complexes, it is particularly preferable to combine a compound that readily accepts holes (hole transport material) and a compound that readily accepts electrons (electron transport material). Specific examples of hole transport materials and electron transport materials can be found in the materials shown in this embodiment.

[0319] TADF materials are materials that can be upconverted from a triplet excited state to a singlet excited state (reverse intersystem crossing) with a small amount of thermal energy, and that efficiently exhibit emission (fluorescence) from the singlet excited state. Furthermore, conditions for efficiently obtaining thermally activated delayed fluorescence include an energy difference between the triplet excited state and the singlet excited state of 0 eV to 0.2 eV, preferably 0 eV to 0.1 eV. In addition, delayed fluorescence in TADF materials refers to emission that has a spectrum similar to normal fluorescence but with a remarkably long lifetime. Its lifetime is 10 -6 10 seconds or more, preferably 10 -3 It is more than a second.

[0320] Examples of TADF materials include fullerenes and their derivatives, acridine derivatives such as proflavin, and eosin. Also, metal-containing porphyrins containing magnesium (Mg), zinc (Zn), cadmium (Cd), tin (Sn), platinum (Pt), indium (In), or palladium (Pd) are also used.

[0321] In addition, heterocyclic compounds having π-electron-rich heteroaromatic rings and π-electron-deficient heteroaromatic rings can be used. Furthermore, substances in which a π-electron-rich heteroaromatic ring and a π-electron-deficient heteroaromatic ring are directly bonded are particularly preferred because both the donor properties of the π-electron-rich heteroaromatic ring and the acceptor properties of the π-electron-deficient heteroaromatic ring become stronger, resulting in a smaller energy difference between the singlet and triplet excited states.

[0322] In addition, when using a TADF material, it can also be used in combination with other organic compounds.

[0323] 〔Electron transport layer 724〕 The electron transport layer 724 is a layer that transports electrons injected from the conductor 788 to the light-emitting layer 723 by the electron injection layer 725. Note that the electron transport layer 724 is a layer containing an electron transport material. The electron transport material used for the electron transport layer 724 preferably has an electron mobility of 1×10 -6 cm 2 / Vs or more. Note that other materials can be used as long as they are substances with higher electron transportability than holes.

[0324] Examples of the electron transport material include metal complexes having a quinoline ligand, a benzoquinoline ligand, an oxazole ligand, or a thiazole ligand, oxadiazole derivatives, triazole derivatives, phenanthroline derivatives, pyridine derivatives, bipyridine derivatives, etc. In addition, π-electron-deficient heteroaromatic compounds such as nitrogen-containing heteroaromatic compounds can also be used.

[0325] The electron transport layer 724 may be not only a single layer but also a structure in which two or more layers composed of the above substances are laminated.

[0326] 〔Electron injection layer 725〕 The electron injection layer 725 is a layer containing a substance with high electron injection properties. For the electron injection layer 725, alkali metals, alkaline earth metals, or their compounds such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), lithium oxide (LiO x ) etc. can be used. In addition, rare earth metal compounds such as erbium fluoride (ErF3) can be used. Also, electrides may be used for the electron injection layer 725. Examples of electrides include substances obtained by adding electrons at a high concentration to a mixed oxide of calcium and aluminum. Note that the substances constituting the above-described electron transport layer 724 can also be used.

[0327] A composite material obtained by mixing an organic compound and an electron donor may be used in the electron injection layer 725. Such a composite material has excellent electron injection and electron transport properties because electrons are generated in the organic compound by the electron donor. In this case, the organic compound is preferably a material that has excellent electron transport properties, and specifically, for example, an electron transport material (metal complex or heteroaromatic compound, etc.) used in the electron transport layer 724 described above can be used. Any substance that exhibits electron-donating properties to the organic compound can be used as the electron donor. Specifically, alkali metals, alkaline earth metals, and rare earth metals are preferred, such as lithium, cesium, magnesium, calcium, erbium, and ytterbium. Alkali metal oxides and alkaline earth metal oxides are also preferred, such as lithium oxide, calcium oxide, and barium oxide. Lewis bases such as magnesium oxide can also be used. Organic compounds such as tetrathiafulvalene (abbreviated as TTF) can also be used.

[0328] [Charge generation layer 792] The charge generation layer 792 has the function of injecting electrons into the EL layer 786 closer to the conductor 772 and injecting holes into the EL layer 786 further away from the conductor 788, when a voltage is applied between the conductor 772 and the conductor 788. For example, in the light-emitting device 572 with the configuration shown in Figure 22C, the charge generation layer 792 has the function of injecting electrons into EL layer 786a and holes into EL layer 786b. The charge generation layer 792 may be configured with electron acceptors added to a hole transport material, or with electron donors added to an electron transport material. Furthermore, both of these configurations may be laminated. By forming the charge generation layer 792 using the materials described above, it is possible to suppress the increase in the driving voltage of the display device 100 when the EL layers are laminated.

[0329] In the charge generation layer 792, when an electron acceptor is added to the hole transport material, examples of electron acceptors include 7,7,8,8-tetracyano-2,3,5,6-tetrafluoroquinodimethane (abbreviated as F4-TCNQ) and chloranil. Alternatively, oxides of metals belonging to groups 4 through 8 of the periodic table can be used. Specifically, examples include vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide.

[0330] In the charge generation layer 792, when an electron donor is added to the electron transport material, alkali metals, alkaline earth metals, rare earth metals, or metals belonging to groups 2 and 13 of the periodic table, as well as their oxides and carbonates, can be used as the electron donor. Specifically, lithium (Li), cesium (Cs), magnesium (Mg), calcium (Ca), ytterbium (Yb), indium (In), lithium oxide, cesium carbonate, etc. are preferred. Organic compounds such as tetrathianaphthalene may also be used as electron donors.

[0331] Furthermore, vacuum processes such as vapor deposition and solution processes such as spin coating and inkjet can be used to fabricate the light-emitting device 572. When using vapor deposition, physical vapor deposition methods (PVD) such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, as well as chemical vapor deposition (CVD), can be used. In particular, the functional layers (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer) and charge generation layer included in the EL layer of the light-emitting device can be formed by methods such as vapor deposition (vacuum deposition, etc.), coating (dip coating, die coating, bar coating, spin coating, spray coating, etc.), and printing (inkjet, screen printing, offset printing, flexographic printing, gravure printing, microcontact printing, etc.).

[0332] In this embodiment, the functional layers (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer) and charge generation layer constituting the EL layer of the light-emitting device are not limited to the materials described above. Other materials can be used in combination as long as they can satisfy the function of each layer. For example, polymer compounds (oligomers, dendrimers, polymers, etc.), medium-molecular-weight compounds (compounds in the intermediate region between low-molecular-weight and high-molecular-weight compounds: molecular weight 400-4000), inorganic compounds (quantum dot materials, etc.) can be used. As quantum dot materials, colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. can be used.

[0333] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0334] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0335] (Embodiment 2) This embodiment describes a transistor that can be used in a display device according to one aspect of the present invention.

[0336] <Transistor Configuration Example 1> Figures 23A, 23B, and 23C are a top view and a cross-sectional view of transistor 200A and its surroundings, which can be used in a display device according to one embodiment of the present invention. Transistor 200A can be applied to a display device according to one embodiment of the present invention.

[0337] Figure 23A is a top view of transistor 200A. Figures 23B and 23C are cross-sectional views of transistor 200A. Here, Figure 23B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 23A, and is also a cross-sectional view of transistor 200A in the channel length direction. Similarly, Figure 23C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 23A, and is also a cross-sectional view of transistor 200A in the channel width direction. Note that in the top view of Figure 23A, some elements have been omitted for clarity.

[0338] As shown in Figure 23B, the transistor 200A includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, conductors 242a and 242b disposed on the metal oxide 230b at a distance from each other, an insulator 280 disposed on the conductors 242a and 242b with an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed between the metal oxide 230b, conductor 242a, conductor 242b, insulator 280, and conductor 260, and a metal oxide 230c disposed between the metal oxide 230b, conductor 242a, conductor 242b, insulator 280, and insulator 250. Here, as shown in Figures 23B and 23C, it is preferable that the upper surface of the conductor 260 substantially coincides with the upper surfaces of the insulators 250, 254, metal oxide 230c, and 280. In the following, metal oxides 230a, 230b, and 230c may be collectively referred to as metal oxide 230. Also, conductors 242a and 242b may be collectively referred to as conductor 242.

[0339] In the transistor 200A shown in Figure 23, the sides of conductors 242a and 242b facing conductor 260 have a generally vertical shape. However, the transistor 200A shown in Figure 23 is not limited to this, and the angle between the side and bottom surfaces of conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing sides of conductors 242a and 242b may have multiple surfaces.

[0340] As shown in Figure 23, it is preferable that an insulator 254 is placed between the insulator 224, metal oxide 230a, metal oxide 230b, conductor 242a, conductor 242b, and metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and metal oxide 230b, and the top surface of the insulator 224, as shown in Figures 23B and 23C.

[0341] In transistor 200A, a configuration is shown in which three layers of metal oxide 230a, metal oxide 230b, and metal oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a two-layer structure of metal oxide 230b and metal oxide 230c, or a stacked structure of four or more layers, may be provided. Also, in transistor 200A, the conductor 260 is shown as a two-layer stacked structure. However, the present invention is not limited to this. For example, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxides 230a, 230b, and 230c may have a stacked structure of two or more layers.

[0342] For example, if the metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has the same composition as metal oxide 230b and the second metal oxide has the same composition as metal oxide 230a.

[0343] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode or drain electrode, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. In other words, in transistor 200A, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing a positional margin, the occupied area of ​​transistor 200A can be reduced. This makes it possible to make the display device high-resolution. It also makes it possible to make the display device narrow-bezel.

[0344] As shown in Figure 23, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0345] The transistor 200A preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on top of the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on top of the insulator 216 and the conductor 205, and an insulator 224 disposed on top of the insulator 222. It is preferable that a metal oxide 230a is disposed on top of the insulator 224.

[0346] It is preferable that insulators 274 and 281, which function as interlayer films, be placed on top of the transistor 200A. Here, it is preferable that insulator 274 is placed in contact with the upper surfaces of the conductor 260, insulator 250, insulator 254, metal oxide 230c, and insulator 280.

[0347] It is preferable that insulators 222, 254, and 274 have a function to suppress the diffusion of at least one of the hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0348] Here, insulator 224, metal oxide 230, and insulator 250 are separated from insulators 280 and 281 by insulators 254 and 274. Therefore, it is possible to suppress the mixing of impurities such as hydrogen contained in insulators 280 and 281, as well as excess oxygen, into insulators 224, metal oxide 230a, metal oxide 230b, and insulator 250.

[0349] It is preferable that a conductor 240 (conductor 240a and conductor 240b) is provided that is electrically connected to the transistor 200A and functions as a plug. In addition, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulator 254, insulator 280, insulator 274, and insulator 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made to be approximately the same. Although the transistor 200A shows a configuration in which the first conductor and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0350] In transistor 200A, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c) that includes the channel formation region. For example, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that forms the channel formation region of metal oxide 230.

[0351] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition, it is preferable that it contains element M. As element M, one or more of the following can be used: aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that element M contains either Ga or Sn, or both.

[0352] As shown in Figure 23B, the thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the thickness of the metal oxide 230b in the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is deposited on the upper surface of the metal oxide 230b, a region with low resistance may be formed near the interface with the conductive film. Thus, by removing the region with low resistance located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent the formation of a channel in that region.

[0353] According to one aspect of the present invention, a display device with a small size transistor and high resolution can be provided. Alternatively, a display device with a large on-current transistor and high brightness can be provided. Alternatively, a display device with a fast-operating transistor and fast operation can be provided. Alternatively, a display device with a stable electrical characteristic transistor and high reliability can be provided. Alternatively, a display device with a small off-current transistor and low power consumption can be provided.

[0354] A detailed configuration of transistor 200A, which can be used in a display device according to one aspect of the present invention, will be described.

[0355] The conductor 205 is arranged so as to have an overlapping region with the metal oxide 230 and the conductor 260. Furthermore, it is preferable that the conductor 205 is embedded in the insulator 216.

[0356] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 216. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of the insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of the insulator 216. In other words, conductor 205b is enclosed by conductors 205a and 205c.

[0357] It is preferable that the conductors 205a and 205c use conductive materials that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0358] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to suppress the diffusion of impurities such as hydrogen contained in conductor 205b into the metal oxide 230 via the insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress the oxidation of conductor 205b and the resulting decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductor 205a may be made of the above conductive material in a single layer or a multilayer. For example, titanium nitride may be used for conductor 205a.

[0359] The conductor 205b is preferably a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten can be used for the conductor 205b.

[0360] Here, conductor 260 may function as the first gate (also called the top gate) electrode. Also, conductor 205 may function as the second gate (also called the bottom gate) electrode. In that case, by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, the V of transistor 200A can be controlled. th This can be controlled. In particular, by applying a negative potential to the conductor 205, the V of transistor 200A can be controlled. th By making the voltage greater than 0V, it becomes possible to reduce the off-current. Therefore, applying a negative potential to the conductor 205 reduces the drain current when the potential applied to the conductor 260 is 0V compared to not applying a negative potential.

[0361] The conductor 205 should be larger than the channel-forming region in the metal oxide 230. In particular, as shown in Figure 23C, it is preferable that the conductor 205 extends to the region outside the end that intersects with the channel width direction of the metal oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 230, with an insulator in between.

[0362] With the above configuration, the channel-forming region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode.

[0363] As shown in Figure 23C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205.

[0364] The insulator 214 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen from the substrate side into the transistor 200A. Therefore, it is preferable to use an insulating material for the insulator 214 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen is less permeable).

[0365] For example, it is preferable to use aluminum oxide or silicon nitride as the insulator 214. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200A side beyond the insulator 214. Alternatively, it suppresses the diffusion of oxygen contained in the insulator 224, etc., to the substrate side beyond the insulator 214.

[0366] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as insulators 216, 280, and 281.

[0367] Insulators 222 and 224 function as gate insulators.

[0368] Here, it is preferable that the insulator 224 in contact with the metal oxide 230 desorbs oxygen upon heating. In this specification, the oxygen that is desorbed upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be silicon oxide or silicon oxide nitride, etc., as appropriate. By providing an oxygen-containing insulator in contact with the metal oxide 230, the oxygen deficiency in the metal oxide 230 can be reduced, and the reliability of the transistor 200A can be improved.

[0369] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as the insulator 224. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 The above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0370] As shown in Figure 23C, the thickness of the insulator 224 in the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b may be thinner than the thickness of the other regions. In the insulator 224, it is preferable that the thickness of the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b is such that the above-mentioned oxygen can diffuse sufficiently.

[0371] The insulator 222 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 200A from the substrate side, similar to the insulator 214. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, and the insulator 250 with the insulator 222, the insulator 254, and the insulator 274, it is possible to suppress the ingress of impurities such as water or hydrogen into the transistor 200A from the outside.

[0372] Furthermore, it is preferable that the insulator 222 has a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen does not permeate easily). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 has a function to suppress the diffusion of oxygen and impurities, thereby reducing the diffusion of oxygen contained in the metal oxide 230 to the substrate side. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the metal oxide 230.

[0373] The insulator 222 may be an insulator containing an oxide of either or both aluminum and hafnium, which are insulating materials. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 230 and the incorporation of impurities such as hydrogen from the periphery of the transistor 200A into the metal oxide 230.

[0374] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0375] The insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0376] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0377] The metal oxide 230 comprises a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By having the metal oxide 230a below the metal oxide 230b, the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b can be suppressed. Furthermore, by having the metal oxide 230c on the metal oxide 230b, the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b can be suppressed.

[0378] Furthermore, it is preferable that the metal oxide 230 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 230 contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230a to the total number of atoms of all elements constituting metal oxide 230a is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230a to In is higher than the atomic ratio of element M contained in metal oxide 230b to In. Here, metal oxide 230c can be any metal oxide that can be used in metal oxide 230a or metal oxide 230b.

[0379] It is preferable that the energy at the lower end of the conduction band of metal oxide 230a and metal oxide 230c is higher than the energy at the lower end of the conduction band of metal oxide 230b. In other words, it is preferable that the electron affinity of metal oxide 230a and metal oxide 230c is smaller than the electron affinity of metal oxide 230b. In this case, it is preferable that metal oxide 230c is a metal oxide that can be used for metal oxide 230a. Specifically, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230c to the total number of atoms of all elements constituting metal oxide 230c is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230c to In is higher than the atomic ratio of element M contained in metal oxide 230b to In.

[0380] Here, at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c.

[0381] Specifically, a mixed layer with a low defect level density can be formed by having metal oxide 230a and metal oxide 230b, and metal oxide 230b and metal oxide 230c, all having a common element other than oxygen (which serves as the main component). For example, if metal oxide 230b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., may be used as metal oxide 230a and metal oxide 230c. Furthermore, metal oxide 230c may be in a layered structure. For example, a layered structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a layered structure of In-Ga-Zn oxide and an oxide that does not contain In may be used as metal oxide 230c.

[0382] Specifically, for metal oxide 230a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For metal oxide 230b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. For metal oxide 230c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures for metal oxide 230c include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0383] In this case, the main carrier pathway is metal oxide 230b. By configuring metal oxide 230a and metal oxide 230c as described above, the defect level density at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200A can obtain high on-current and high frequency characteristics. Furthermore, if metal oxide 230c is in a multilayer structure, in addition to the effect of reducing the defect level density at the interface between metal oxide 230b and metal oxide 230c as described above, it is expected that the diffusion of constituent elements of metal oxide 230c to the insulator 250 side will be suppressed. More specifically, by making metal oxide 230c in a multilayer structure and positioning an oxide that does not contain In on top of the multilayer structure, it is possible to suppress In that could diffuse to the insulator 250 side. Since insulator 250 functions as a gate insulator, if In diffuses, it will result in poor transistor characteristics. Therefore, by using a layered structure for the metal oxide 230c, it becomes possible to provide a highly reliable display device.

[0384] A conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode and a drain electrode is provided on the metal oxide 230b. It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as the conductor 242, or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0385] By providing the conductor 242 in contact with the metal oxide 230, the oxygen concentration in the vicinity of the conductor 242 in the metal oxide 230 may be reduced. In addition, a metal compound layer containing the metal in the conductor 242 and the components of the metal oxide 230 may be formed in the vicinity of the conductor 242 in the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 near the conductor 242, and this region becomes a low-resistance region.

[0386] Here, the region between the conductor 242a and the conductor 242b is formed by superimposing it on the opening of the insulator 280. This allows the conductor 260 to be positioned self-aligned between the conductor 242a and the conductor 242b.

[0387] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxide nitride are preferred because they are stable with respect to heat.

[0388] Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0389] A metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. This suppresses the oxidation of the conductor 260 by oxygen from the insulator 250.

[0390] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0391] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0392] Although the conductor 260 is shown as a two-layer structure in Figure 23, it may also be a single-layer structure or a laminated structure of three or more layers.

[0393] It is preferable to use a conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms as described above. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of at least one of oxygen (e.g., oxygen atoms, oxygen molecules, etc.).

[0394] The conductor 260a has the function of suppressing oxygen diffusion, thereby preventing the conductor 260b from oxidizing due to oxygen contained in the insulator 250 and reducing its conductivity. It is preferable to use a conductive material that has the function of suppressing oxygen diffusion, such as tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0395] The conductor 260b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0396] As shown in Figures 23A and 23C, in the region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel-forming region of the metal oxide 230, the side surface of the metal oxide 230 is covered by the conductor 260. This makes it easier to apply the electric field of the conductor 260, which functions as the first gate electrode, to the side surface of the metal oxide 230. Therefore, the on-current of transistor 200A can be increased and the frequency characteristics can be improved.

[0397] The insulator 254, like the insulator 214, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 200A from the insulator 280 side. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Furthermore, as shown in Figures 23B and 23C, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and metal oxide 230b, and the top surface of the insulator 224. With this configuration, it is possible to suppress the ingress of hydrogen contained in the insulator 280 into the metal oxide 230 from the top or side surfaces of the conductor 242a, conductor 242b, metal oxide 230a, metal oxide 230b, and the insulator 224.

[0398] Furthermore, it is preferable that the insulator 254 has the function of suppressing the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen does not easily permeate it). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0399] The insulator 254 is preferably deposited using a sputtering method. By depositing the insulator 254 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulator 224 that is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 via the insulator 224. Here, the insulator 254 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. In addition, the insulator 222 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen deficiency in the metal oxide 230 and suppresses normally-on formation of the transistor.

[0400] As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as a film. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator containing an oxide of one or both of aluminum and hafnium.

[0401] The insulator 224, insulator 250, and metal oxide 230 are covered by the hydrogen barrier insulator 254, so the insulator 280 is separated from the insulator 224, metal oxide 230, and insulator 250 by the insulator 254. This prevents impurities such as hydrogen from entering the transistor 200A from the outside, thus providing the transistor 200A with good electrical characteristics and reliability.

[0402] The insulator 280 is provided on the insulator 224, the metal oxide 230, and the conductor 242 via the insulator 254. For example, the insulator 280 is preferably silicon oxide, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0403] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Furthermore, the upper surface of the insulator 280 may be flattened.

[0404] The insulator 274 preferably functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen into the insulator 280 from above, similar to the insulator 214. For example, the insulator 274 can be an insulator that can be used for the insulator 214, insulator 254, etc.

[0405] It is preferable to provide an insulator 281, which functions as an interlayer film, on top of the insulator 274. It is preferable that the insulator 281, like the insulator 224, has a reduced concentration of impurities such as water or hydrogen in the film.

[0406] Conductors 240a and 240b are placed in the openings formed in insulators 281, 274, 280, and 254. Conductors 240a and 240b are provided facing each other with conductor 260 in between. The height of the upper surfaces of conductors 240a and 240b may be on the same plane as the upper surface of insulator 281.

[0407] Furthermore, an insulator 241a is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240a is formed in contact with its side surface. Conductor 242a is located in at least a portion of the bottom of the opening, and conductor 240a is in contact with conductor 242a. Similarly, an insulator 241b is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240b is formed in contact with its side surface. Conductor 242b is located in at least a portion of the bottom of the opening, and conductor 240b is in contact with conductor 242b.

[0408] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0409] When the conductor 240 has a laminated structure, it is preferable to use a conductor that has the function of suppressing the diffusion of impurities such as water or hydrogen, as described above, for the conductors that come into contact with the metal oxide 230a, metal oxide 230b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminate. By using this conductive material, it is possible to suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0410] For insulators 241a and 241b, any insulator that can be used for insulator 254, for example, may be used. Since insulators 241a and 241b are provided in contact with insulator 254, it is possible to suppress the mixing of impurities such as water or hydrogen from insulator 280, etc., into the metal oxide 230 through conductors 240a and 240b. Furthermore, it is possible to suppress the absorption of oxygen contained in insulator 280 into conductors 240a and 240b.

[0411] Although not shown in the figures, conductors that function as wiring may be placed in contact with the upper surfaces of conductor 240a and conductor 240b. It is preferable that the conductors functioning as wiring are made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors may have a laminated structure; for example, they may be laminates of titanium or titanium nitride with the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0412] <Example of transistor configuration 2> Figures 24A, 24B, and 24C are a top view and a cross-sectional view of transistor 200B and its surroundings, which can be used in a display device according to one embodiment of the present invention. Transistor 200B is a modified example of transistor 200A.

[0413] Figure 24A is a top view of transistor 200B. Figures 24B and 24C are cross-sectional views of transistor 200B. Here, Figure 24B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 24A, and is also a cross-sectional view of transistor 200B in the channel length direction. Similarly, Figure 24C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 24A, and is also a cross-sectional view of transistor 200B in the channel width direction. Note that in the top view of Figure 24A, some elements have been omitted for clarity.

[0414] Transistor 200B differs from transistor 200A in that it has insulators 212 and 283.

[0415] Transistor 200B has an insulator 212 provided on a substrate (not shown). In addition, an insulator 283 is provided on the insulator 212 and on the insulator 271.

[0416] In transistor 200B, insulator 214, insulator 216, insulator 222, insulator 224, insulator 244, insulator 280, and insulator 274 are covered by insulator 283. Insulator 283 is in contact with the top surface of insulator 274, the side surface of insulator 274, the side surface of insulator 280, the side surface of insulator 244, the side surface of insulator 224, the side surface of insulator 222, the side surface of insulator 216, the side surface of insulator 214, and the top surface of insulator 212, respectively. As a result, metal oxide 230 and the like are isolated from the outside by insulator 283 and insulator 212.

[0417] It is preferable that insulators 283 and 212 have a high ability to suppress the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule) or water molecules. For example, it is preferable to use silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, as insulators 281 and 212. This suppresses the diffusion of hydrogen and the like into the metal oxide 230, and thus suppresses the degradation of the characteristics of transistor 200B. Therefore, the reliability of a semiconductor device according to one embodiment of the present invention can be improved.

[0418] For example, silicon nitride can be used as the insulator 283. When silicon nitride is used for the insulator 283, a silicon nitride film with high density and less susceptibility to porosity can be formed by depositing it using the sputtering method. Alternatively, as the insulator 283, silicon nitride deposited by the ALD method may be laminated on top of silicon nitride deposited by the sputtering method. With such a structure, even if defects, such as voids, occur in the silicon nitride deposited by the sputtering method, these voids can be filled by the silicon nitride deposited by the ALD method, which has good coverage, thereby improving sealing performance. For the insulator 212, a material that can be used for the insulator 214 can be used. For example, silicon nitride can be used for the insulator 212 and aluminum oxide can be used for the insulator 214.

[0419] <Transistor Configuration Example 3> Figures 25A, 25B, and 25C are a top view and a cross-sectional view of transistor 200C and its surroundings, which can be used in a display device according to one embodiment of the present invention. Transistor 200C is a modified example of transistor 200A.

[0420] Figure 25A is a top view of transistor 200C. Figures 25B and 25C are cross-sectional views of transistor 200C. Here, Figure 25B is a cross-sectional view of the area indicated by the dashed line B1-B2 in Figure 25A, and is also a cross-sectional view of transistor 200C in the channel length direction. Similarly, Figure 25C is a cross-sectional view of the area indicated by the dashed line B3-B4 in Figure 25A, and is also a cross-sectional view of transistor 200C in the channel width direction. Note that in the top view of Figure 25A, some elements have been omitted for clarity.

[0421] In transistor 200C, conductors 242a and 242b have regions that overlap with the metal oxide 230c, insulator 250, and conductor 260. This allows transistor 200C to have a high on-current. Furthermore, transistor 200C can be made easier to control.

[0422] The conductor 260, which functions as a gate electrode, comprises a conductor 260a and a conductor 260b on the conductor 260a. It is preferable that the conductor 260a is made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0423] The conductor 260a has the function of suppressing oxygen diffusion, thereby improving the material selectivity of the conductor 260b. In other words, the presence of the conductor 260a suppresses the oxidation of the conductor 260b and prevents a decrease in conductivity.

[0424] It is preferable to provide the insulator 254 so as to cover the top and sides of the conductor 260, the sides of the insulator 250, and the sides of the metal oxide 230c. The insulator 254 should be made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen.

[0425] By providing the insulator 254, oxidation of the conductor 260 can be suppressed. Furthermore, the presence of the insulator 254 can suppress the diffusion of impurities such as water and hydrogen present in the insulator 280 to the transistor 200C.

[0426] <Transistor Configuration Example 4> Figures 26A, 26B, and 26C are a top view and a cross-sectional view of transistor 200D and its surroundings, which can be used in a display device according to one embodiment of the present invention. Transistor 200D is a modified example of transistor 200A.

[0427] Figure 26A is a top view of transistor 200D. Figures 26B and 26C are cross-sectional views of transistor 200D. Here, Figure 26B is a cross-sectional view of the area indicated by the dashed line C1-C2 in Figure 26A, and is also a cross-sectional view of transistor 200D in the channel length direction. Similarly, Figure 26C is a cross-sectional view of the area indicated by the dashed line C3-C4 in Figure 26A, and is also a cross-sectional view of transistor 200D in the channel width direction. Note that in the top view of Figure 26A, some elements have been omitted for clarity.

[0428] In transistor 200D, an insulator 250 is present on a metal oxide 230c, and a metal oxide 252 is present on the insulator 250. Furthermore, a conductor 260 is present on the metal oxide 252, and an insulator 270 is present on the conductor 260. Additionally, an insulator 271 is present on the insulator 270.

[0429] Preferably, the metal oxide 252 has the function of suppressing oxygen diffusion. By providing the metal oxide 252 that suppresses oxygen diffusion between the insulator 250 and the conductor 260, the diffusion of oxygen into the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the metal oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen can be suppressed.

[0430] Furthermore, the metal oxide 252 may function as part of the gate electrode. For example, an oxide semiconductor that can be used as the metal oxide 230 can be used as the metal oxide 252. In that case, the electrical resistance of the metal oxide 252 can be reduced by depositing the conductor 260 by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0431] The metal oxide 252 may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide 252 that is a high-k material with a high dielectric constant. This layered structure provides thermal stability and a high dielectric constant. As a result, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulating layer that functions as a gate insulator.

[0432] In transistor 200D, the metal oxide 252 is shown as a single layer, but it may also be a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a metal oxide that functions as part of the gate insulator may be stacked.

[0433] By having the metal oxide 252, when it functions as a gate electrode, the on-current of the transistor 200D can be improved without weakening the influence of the electric field from the conductor 260. Alternatively, when it functions as a gate insulator, the physical thickness of the insulator 250 and the metal oxide 252 maintains the distance between the conductor 260 and the metal oxide 230, thereby suppressing leakage current between the conductor 260 and the metal oxide 230. Therefore, by providing a laminated structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the metal oxide 230, and the electric field strength applied from the conductor 260 to the metal oxide 230 can be easily adjusted.

[0434] Specifically, as metal oxide 252, a low-resistance oxide semiconductor that can be used for metal oxide 230 can be used. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0435] In particular, it is preferable to use an insulating layer containing an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in subsequent processes. Note that metal oxide 252 is not an essential component. It can be designed as appropriate depending on the desired transistor characteristics.

[0436] The insulator 270 should be made of an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. This prevents the conductor 260 from being oxidized by oxygen from above the insulator 270. It also prevents impurities such as water or hydrogen from entering the metal oxide 230 via the conductor 260 and the insulator 250 from above the insulator 270.

[0437] The insulator 271 functions as a hard mask. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 can be made approximately perpendicular, specifically, the angle between the side surface of the conductor 260 and the substrate surface can be made 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less.

[0438] Furthermore, the insulator 271 may also function as a barrier layer by using an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. In that case, the insulator 270 does not need to be provided.

[0439] By using the insulator 271 as a hard mask and selectively removing a portion of the insulator 270, conductor 260, metal oxide 252, insulator 250, and metal oxide 230c, these surfaces can be made to substantially align, and a portion of the metal oxide 230b surface can be exposed.

[0440] Transistor 200D has regions 243a and 243b on a portion of the exposed metal oxide 230b surface. One of region 243a or region 243b functions as the source region, and the other of region 243a or region 243b functions as the drain region.

[0441] The formation of regions 243a and 243b can be achieved, for example, by introducing impurity elements such as phosphorus or boron to the exposed metal oxide 230b surface using ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. In this embodiment, "impurity element" refers to an element other than the main component element.

[0442] By exposing a portion of the surface of the metal oxide 230b, a metal film can be formed, and then heat-treated to diffuse elements contained in the metal film into the metal oxide 230b, thereby forming regions 243a and 243b.

[0443] In the region where impurity elements of metal oxide 230b are introduced, the electrical resistivity decreases. For this reason, regions 243a and 243b are sometimes referred to as the "impurity region" or "low-resistance region."

[0444] By using the insulator 271 and / or the conductor 260 as a mask, regions 243a and 243b can be formed in a self-aligned manner. Therefore, regions 243a and / or region 243b do not overlap with the conductor 260, and parasitic capacitance can be reduced. In addition, no offset region is formed between the channel formation region and the source-drain region (region 243a or region 243b). By forming regions 243a and 243b in a self-aligned manner, it is possible to achieve an increase in on-current, a reduction in threshold voltage, and an improvement in operating frequency.

[0445] Transistor 200D has an insulator 271, an insulator 270, a conductor 260, a metal oxide 252, an insulator 250, and an insulator 272 on the side surface of the metal oxide 230c. The insulator 272 is preferably an insulator with a low dielectric constant. For example, it is preferably silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. In particular, using silicon oxide, silicon oxynitride, silicon oxide nitride, or porous silicon oxide for the insulator 272 is preferable because it allows for easy formation of an excess oxygen region within the insulator 272 in a later process. Furthermore, silicon oxide and silicon oxynitride are preferred because they are thermally stable. Additionally, the insulator 272 preferably has the function of diffusing oxygen.

[0446] Furthermore, to further reduce the off-current, an offset region may be provided between the channel formation region and the source-drain region. The offset region is a region with high electrical resistivity where the aforementioned impurity elements are not introduced. The formation of the offset region can be achieved by introducing the aforementioned impurity elements after the formation of the insulator 272. In this case, the insulator 272 also functions as a mask, similar to the insulator 271. Therefore, impurity elements are not introduced into the region of the metal oxide 230b that overlaps with the insulator 272, and the electrical resistivity of that region can be kept high.

[0447] The transistor 200D has an insulator 272 and an insulator 254 on a metal oxide 230. The insulator 254 is preferably deposited using a sputtering method. By using the sputtering method, an insulator with fewer impurities such as water or hydrogen can be deposited.

[0448] Furthermore, oxide films formed by sputtering may extract hydrogen from the structure to which the film is deposited. Therefore, the hydrogen concentration in the metal oxide 230 and insulator 272 can be reduced by the insulator 254 absorbing hydrogen and water from the metal oxide 230 and insulator 272.

[0449] <Materials used in transistors> This section describes the constituent materials that can be used in transistors.

[0450] 〔substrate〕 As the substrate for forming transistors 200A, 200B, 200C, or 200D, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include silicon, germanium, and other semiconductor substrates, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting devices, memory elements, and the like.

[0451] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0452] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0453] Examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0454] Examples of insulators with low dielectric constant include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resins.

[0455] Transistors using oxide semiconductors can have their electrical characteristics stabilized by surrounding them with an insulator (insulator 214, insulator 222, insulator 254, and insulator 274, etc.) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxide nitride, or silicon nitride can be used.

[0456] The insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with the metal oxide 230, the oxygen deficiency of the metal oxide 230 can be compensated for.

[0457] 〔conductor〕 It is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0458] Multiple conductors formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0459] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0460] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0461] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0462] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0463] (Embodiment 3) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0464] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 27A. Figure 27A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0465] As shown in Figure 27A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0466] The structure within the thick frame shown in Figure 27A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0467] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 27B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 27B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 27B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 27B is 500 nm.

[0468] As shown in Figure 27B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. In Figure 27B, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in Figure 27B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0469] The crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed using nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 27C. Figure 27C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 27C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, in nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0470] As shown in Figure 27C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0471] [Structure of oxide semiconductors] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 27A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, etc.

[0472] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0473] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0474] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0475] In In-M-Zn oxide (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. The In layer may also contain element M. The In layer may also contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0476] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0477] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0478] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0479] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0480] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0481] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0482] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0483] [Oxide semiconductor composition] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0484] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0485] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0486] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0487] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0488] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0489] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0490] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0491] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0492] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0493] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0494] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0495] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, which may result in a low trap level density.

[0496] Charges trapped in the trap levels of oxide semiconductors can take a long time to disappear and sometimes behave like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high density of trap levels may exhibit unstable electrical properties.

[0497] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0498] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0499] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are compared by 2 × 10⁻¹⁰ 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0500] When alkali metals or alkaline earth metals are present in oxide semiconductors, they can form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0501] In oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻¹⁰. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0502] Hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these vacancies, electrons, which act as carriers, can be generated. Furthermore, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0503] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0504] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0505] (Embodiment 4) This embodiment describes an electronic device equipped with a display device, which is one aspect of the present invention.

[0506] Figure 28A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. The camera 8000 is equipped with an imaging device. The camera 8000 can be, for example, a digital camera. In Figure 28A, the camera 8000 and the viewfinder 8100 are shown as separate electronic devices and are detachable, but the viewfinder equipped with a display device may be built into the housing 8001 of the camera 8000.

[0507] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached.

[0508] Here, the camera 8000 is configured so that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing could also be integrated.

[0509] Camera 8000 can take an image by pressing the shutter button 8004. Additionally, the display unit 8002 functions as a touch panel, and images can also be taken by touching the display unit 8002.

[0510] The camera 8000's housing 8001 has a mount with electrodes, and can be used to connect the viewfinder 8100, as well as a strobe device and the like.

[0511] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. The viewfinder 8100 can be an electronic viewfinder.

[0512] The housing 8101 has a mount that engages with the mount of the camera 8000, allowing the viewfinder 8100 to be attached to the camera 8000. The mount also has electrodes, which allow images and other data received from the camera 8000 to be displayed on the display unit 8102.

[0513] Button 8103 functions as a power button. Button 8103 can be used to switch the display on and off of the display unit 8102.

[0514] A display device according to one aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Because the display device according to one aspect of the present invention has extremely high resolution, even if the distance between the display unit 8002 or the display unit 8102 and the user is close, the user will not be able to see the pixels, and a more realistic image can be displayed on the display unit 8002 or the display unit 8102. In particular, the image displayed on the display unit 8102 provided in the viewfinder 8100 is viewed by bringing the user's eye close to the eyepiece of the viewfinder 8100, so the distance between the user and the display unit 8102 becomes very close. Therefore, it is particularly preferable to apply the display device according to one aspect of the present invention to the display unit 8102. When the display device according to one aspect of the present invention is applied to the display unit 8102, the resolution of the image that can be displayed on the display unit 8102 can be 4K, 5K, or higher.

[0515] Furthermore, it is preferable that the resolution of the images that can be captured by the imaging device provided in camera 8000 is equal to or higher than the resolution of the images that can be displayed on display unit 8002 or display unit 8102. For example, if display unit 8102 can display an image with a resolution of 4K, it is preferable that camera 8000 be equipped with an imaging device capable of capturing images of 4K or higher. Also, for example, if display unit 8102 can display an image with a resolution of 5K, it is preferable that camera 8000 be equipped with an imaging device capable of capturing images of 5K or higher.

[0516] Figure 28B shows the external appearance of the head-mounted display 8200.

[0517] The head-mounted display 8200 includes a mounting section 8201, lenses 8202, a main unit 8203, a display unit 8204, a cable 8205, etc. The mounting section 8201 also has a built-in battery 8206.

[0518] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 8203 is equipped with a wireless receiver and can display images corresponding to received image data on display unit 8204. In addition, a camera provided on main unit 8203 captures the movement of the user's eyeballs and eyelids, and by calculating the coordinates of the user's gaze based on that information, the user's gaze can be used as an input means.

[0519] The attachment part 8201 may have multiple electrodes positioned to come into contact with the user. The main unit 8203 may have a function to recognize the user's gaze by detecting the current flowing through the electrodes in accordance with the user's eye movements. It may also have a function to monitor the user's pulse by detecting the current flowing through the electrodes. Furthermore, the attachment part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function to display the user's biometric information on the display unit 8204. It may also detect the user's head movements and change the image displayed on the display unit 8204 in accordance with those movements.

[0520] A display device according to one embodiment of the present invention can be applied to the display unit 8204. This allows the head-mounted display 8200 to have a narrower bezel, enabling the display unit 8204 to display high-quality images and provide a more immersive viewing experience.

[0521] Figures 28C, 28D, and 28E show the external appearance of the head-mounted display 8300. The head-mounted display 8300 comprises a housing 8301, a display unit 8302, a band-shaped fixing device 8304, and a pair of lenses 8305.

[0522] The user can view the display on the display unit 8302 through the lens 8305. It is preferable to position the display unit 8302 in a curved shape. By positioning the display unit 8302 in a curved shape, the user can experience a high degree of realism. In this embodiment, a configuration with one display unit 8302 has been illustrated, but the system is not limited to this, and for example, a configuration with two display units 8302 may be used. In this case, if one display unit is positioned for each eye of the user, it becomes possible to perform 3D display using parallax, etc.

[0523] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. Because the display device according to one embodiment of the present invention has extremely high resolution, even when magnified using the lens 8305 as shown in Figure 28E, the user cannot see the pixels, and a more realistic image can be displayed.

[0524] Next, Figures 29A to 29G show the electronic equipment shown in Figures 28A to 28E, as well as an example of a different electronic equipment.

[0525] The electronic equipment shown in Figures 29A to 29G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0526] The electronic devices shown in Figures 29A to 29G have a variety of functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing by various software (programs), a wireless communication function, a function to connect to various computer networks using the wireless communication function, a function to transmit or receive various data using the wireless communication function, a function to read programs or data recorded on a recording medium and display them on a display unit, etc. However, the functions that the electronic devices shown in Figures 29A to 29G may have are not limited to these, and they may have a variety of functions. In addition, although not shown in Figures 29A to 29G, the electronic devices may have a configuration that includes multiple display units. Furthermore, the electronic devices may be equipped with a camera, etc., and have functions to capture still images, capture videos, save captured images to a recording medium (external or built into the camera), and display captured images on a display unit, etc.

[0527] Details of the electronic equipment shown in Figures 29A to 29G will be explained below.

[0528] Figure 29A is a perspective view showing the television system 9100. The television system 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0529] A display device according to one aspect of the present invention can be applied to the display unit 9001 of the television device 9100. This allows the television device 9100 to have a narrower bezel, enabling the display of high-quality images on the display unit 9001 and displaying images with a high sense of realism.

[0530] Figure 29B is a perspective view showing a personal information terminal 9101. The personal information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, or an information viewing device. Specifically, it can be used as a smartphone. The personal information terminal 9101 may also be equipped with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Furthermore, the personal information terminal 9101 can display text and images on multiple surfaces. For example, three operation buttons 9050 (also called operation icons or simply icons) can be displayed on one surface of the display unit 9001. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS (Social Networking Service) messages, and phone calls, the subject of emails and SNS messages, the sender's name of emails and SNS messages, the date and time, the battery level, and the antenna signal strength. Alternatively, instead of displaying information 9051, an operation button 9050 or the like may be displayed at the same location where information 9051 is displayed.

[0531] A display device according to one aspect of the present invention can be applied to the display unit 9001 of the portable information terminal 9101. This allows the portable information terminal 9101 to be miniaturized, high-quality images to be displayed on the display unit 9001, and images with a high sense of realism to be displayed.

[0532] Figure 29C is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user of the PDA 9102 can check the display (in this case, information 9053) while the PDA 9102 is stored in the breast pocket of their clothing. Specifically, the phone number or name of the caller of an incoming call is displayed in a position that can be observed from above the PDA 9102. The user can check the display and decide whether or not to answer the call without taking the PDA 9102 out of their pocket.

[0533] A display device according to one aspect of the present invention can be applied to the display unit 9001 of the portable information terminal 9102. This allows for miniaturization of the portable information terminal 9101, the display of high-quality images on the display unit 9001, and the display of highly immersive images.

[0534] Figure 29D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can run various applications such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 is also capable of performing standardized short-range wireless communication. For example, it can make hands-free calls by communicating with a wireless communication-enabled headset. The personal information terminal 9200 also has a connection terminal 9006, which allows it to directly exchange data with other information terminals via a connector. It can also be charged via the connection terminal 9006. Note that charging may be performed by wireless power supply without using the connection terminal 9006.

[0535] A display device according to one aspect of the present invention can be applied to the display unit 9001 of the portable information terminal 9200. This allows the portable information terminal 9200 to have a narrower bezel, enabling the display of high-quality images on the display unit 9001 and displaying images with a high sense of realism.

[0536] Figures 29E, 29F, and 29G are perspective views showing a foldable personal information terminal (PAD) 9201. Figure 29E is a perspective view of the PAD 9201 in an unfolded state, Figure 29F is a perspective view of the PAD 9201 in an intermediate state between being unfolded or folded, and Figure 29G is a perspective view of the PAD 9201 in a folded state. The PAD 9201 offers excellent portability in its folded state and excellent readability due to its seamless, wide display area in its unfolded state. The display unit 9001 of the PAD 9201 is supported by three housings 9000 connected by hinges 9055. By bending the two housings 9000 via the hinges 9055, the PAD 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the personal digital information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0537] A display device according to one aspect of the present invention can be applied to the display unit 9001 of the portable information terminal 9201. This allows the portable information terminal 9201 to have a narrower bezel, enabling the display of high-quality images on the display unit 9001 and displaying images with a high sense of realism.

[0538] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0539] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0540] In this embodiment, the operation of a pixel that can be used in a display device according to one aspect of the present invention was confirmed using circuit simulation. The configuration of pixel 10 shown in Figure 1B and the timing chart shown in Figure 2 were used for the simulation.

[0541] In the simulation, transistors 101, 102, 103, and 104 were each OS transistors with a channel length of 200 nm and a channel width of 60 nm. Capacitor element 111 had a capacitance value of 17.0 fF, and capacitor element 112 had a capacitance value of 3.4 fF. The potentials applied to wiring 121 and 122 were set to 5V for High and 0V for Low. Wiring 131 had "Vdata" set to 4.0V, wiring 161 had "Vref" set to 0.5V, wiring 128 had "Vano" set to 11.0V, and wiring 129 had "Vcath" set to -5.0V for the simulation. SPICE was used as the circuit simulation software.

[0542] The simulation results are shown in Figure 30. In Figure 30, the horizontal axis shows the time (Time) according to the timing chart, and the vertical axis shows the potential V of node ND11. ND11 , and the potential V of node ND12 ND12 This indicates that.

[0543] As shown in Figure 30, the potential V ND11 and potential V ND12 The difference was 3.23V in period P21a, 0.92V in period P21b, and 0.00V in period P22a. In period P21, the potential V ND11 and potential V ND12 We were able to confirm that the difference was smaller than 4.0V of “Vdata”. Also, during period P22, the potential V ND11 and potential V ND12 We were able to confirm that the difference was 0V. [Examples]

[0544] In this embodiment, the display device shown in the embodiment was manufactured.

[0545] The fabricated display panel has a diagonal size of 0.66 inches, a pixel count of 1440 x 1440, a resolution (pixel density) of 3078 ppi, a pixel size of 2.75 μm x 8.25 μm (2.75 μm x RGB x 8.25 μm), an aperture ratio of 33.7%, and a frame frequency of 90 Hz. The gate driver and source driver are built-in, with the gate driver using an OS transistor and the source driver using a CMOS with a Si transistor.

[0546] A photograph of the fabricated display device is shown in Figure 31A. A magnified photograph of the pixel area is shown in Figure 31B. As shown in Figures 31A and 31B, it was confirmed that the entire pixel area could be displayed well.

[0547] The brightness was evaluated using the aforementioned display device with varying duty cycles. The correlation between duty cycle and brightness is shown in Figure 32A. In Figure 32A, the horizontal axis represents the duty cycle, and the vertical axis represents the brightness L. Note that Figure 32A shows the brightness when the entire pixel area is displayed in white.

[0548] At a duty cycle of 100%, the brightness is 5040 cd / m². 2 With a duty cycle of 50%, the brightness is 2520 cd / m². 2 At a duty cycle of 20%, the brightness is 1008 cd / m². 2 At a duty cycle of 0%, the brightness is 0 cd / m². 2 Thus, we were able to confirm that duty cycle and brightness are proportional. In Figure 32A, the straight line connecting the plot for 100% duty cycle and the plot for 0% duty cycle is shown as a dashed line.

[0549] Figure 32B shows the time variation of the displayed brightness. In Figure 32B, the horizontal axis represents time, and the vertical axis represents brightness L. Figure 32B shows data measured with a spectroluminometer when a white line with a width of one pixel is displayed with a duty cycle of 20%.

[0550] We confirmed that the brightness increased during the illumination period (P21) within a single frame period (FP), and that the display switched from black to white. [Explanation of Symbols]

[0551] ND11: Node, ND12: Node, 10a: Pixel, 10B: Sub-pixel, 10b: Pixel, 10c: Pixel, 10d: Pixel, 10e: Pixel, 10f: Pixel, 10G: Sub-pixel, 10R: Sub-pixel, 10: Pixel, 20: First layer, 30: Second layer, 51a: Display area, 51b: Display area, 51c: Display area, 53a: Pixel electrode, 53b: Pixel electrode, 53c: Pixel electrode, 53: Pixel electrode, 100: Display device, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 111: Capacitive element, 112: Capacitive element, 114: Light-emitting device S, 121: Wiring, 122: Wiring, 123: Wiring, 128: Wiring, 129: Wiring, 130: Drive circuit section, 131: Wiring, 140a: Drive circuit section, 140b: Drive circuit section, 150: Pixel section, 161: Wiring, 162: Wiring, 200A: Transistor, 200B: Transistor, 200C: Transistor, 200D: Transistor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 205: Conductor, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230a: Metal oxide, 230b: Metal oxide, 230c: Gold 230: Metal oxide, 240a: Conductor, 240b: Conductor, 240: Conductor, 241a: Insulator, 241b: Insulator, 241: Insulator, 242a: Conductor, 242b: Conductor, 242: Conductor, 243a: Region, 243b: Region, 244: Insulator, 250: Insulator, 252: Metal oxide, 254: Insulator, 260a: Conductor, 260b: Conductor, 260: Conductor, 270: Insulator, 271: Insulator, 272: Insulator, 274: Insulator, 280: Insulator, 281: Insulator, 283: Insulator, 301a: Conductor, 301b: Conductor, 305: Conductive Body, 311: Conductor, 313: Conductor, 317: Conductor, 321: Lower electrode, 323: Insulator, 325: Upper electrode, 331: Conductor, 333: Conductor, 335: Conductor, 337: Conductor, 341: Conductor, 343: Conductor, 347: Conductor, 351: Conductor, 353: Conductor, 355: Conductor, 357: Conductor, 361: Insulator, 363: Insulator, 403: Element isolation layer, 405: Insulator, 407: Insulator, 409: Insulator, 411: Insulator, 413: Insulator, 415: Insulator, 417: Insulator, 419: Insulator, 421: Insulator, 441: Transistor,443: Conductor, 445: Insulator, 447: Semiconductor region, 449a: Low resistance region, 449b: Low resistance region, 451: Conductor, 453: Conductor, 455: Conductor, 457: Conductor, 459: Conductor, 461: Conductor, 463: Conductor, 465: Conductor, 467: Conductor, 469: Conductor, 471: Conductor, 501: Insulator, 503: Insulator, 505: Insulator, 507: Insulator, 509: Insulator, 572: Light-emitting device, 601: Transistor, 602: Transistor, 603: Transistor, 613: Insulator, 614: Insulator, 616: Insulator, 622 :Insulator, 624:Insulator, 644:Insulator, 654:Insulator, 674:Insulator, 680:Insulator, 681:Insulator, 701:Substrate, 705:Substrate, 712:Sealing material, 716:FPC, 721:Hole injection layer, 722:Hole transport layer, 723:Light-emitting layer, 724:Electron transport layer, 725:Electron injection layer, 730:Insulator, 732:Sealing layer, 734:Insulator, 736:Coloring layer, 738:Light-shielding layer, 750:Transistor, 760:Connecting electrode, 772:Conductor, 778:Structure, 780:Anisotropic conductor, 782:Light-emitting device, 786a:EL layer, 786b:EL layer, 786c: EL layer, 786: EL layer, 788: conductor, 790: capacitive element, 792: charge generation layer, 800: transistor, 801a: conductor, 801b: conductor, 805: conductor, 811: conductor, 813: conductor, 814: insulator, 816: insulator, 817: conductor, 821: insulator, 822: insulator, 824: insulator, 844: insulator, 853: conductor, 854: insulator, 855: conductor, 874: insulator, 880: insulator, 881: insulator, 8000: camera, 8001: housing, 8002: display unit, 8003: operation buttons, 8004: shutter Buttons, 8006: Lens, 8100: Viewfinder, 8101: Housing, 8102: Display unit, 8103: Buttons, 8200: Head-mounted display, 8201: Mounting part, 8202: Lens, 8203: Main unit, 8204: Display unit, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302: Display unit, 8304: Fixing device, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone,9050: Operation button, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television equipment, 9101: Personal digital assistant, 9102: Personal digital assistant, 9200: Personal digital assistant, 9201: Personal digital assistant,

Claims

1. Having multiple pixels, Each of the aforementioned plurality of pixels has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a light-emitting device. The channel formation region of the first transistor, the channel formation region of the third transistor, and the channel formation region of the fourth transistor each have a metal oxide. The channel formation region of the second transistor has silicon, The first transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The second transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The third transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The fourth transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The first gate and the second gate of the first transistor are electrically connected. The first gate of the first transistor is electrically connected to the first wiring, Either the source or the drain of the first transistor is electrically connected to the sixth wiring. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The second gate of the second transistor is electrically connected to either the source or the drain of the second transistor. The first gate of the second transistor is electrically connected to either the source or the drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the pixel electrode of the light-emitting device. The source or drain of the second transistor, the other of which is electrically connected to the fifth wiring, The first gate and the second gate of the third transistor are electrically connected. The first gate of the third transistor is electrically connected to the second wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The first gate and the second gate of the fourth transistor are electrically connected. The first gate of the fourth transistor is electrically connected to the third wiring. Either the source or the drain of the fourth transistor is electrically connected to the sixth wiring. The source or drain of the fourth transistor is electrically connected to the source or drain of the third transistor. One electrode of the first capacitor is electrically connected to either the source or the drain of the second transistor. The other electrode of the first capacitor is electrically connected to the first gate of the second transistor. One electrode of the second capacitor is electrically connected to the first gate of the second transistor. The other electrode of the second capacitance is electrically connected to the other source or drain of the second transistor. The first wiring has the function of transmitting a potential that selects the conduction state or non-conduction state of the first transistor. The second wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the third transistor. The third wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the fourth transistor. The fourth wiring has the function of transmitting an electric potential corresponding to the image data, The fifth wiring has the function of transmitting the first potential, The first potential is the potential at which the second transistor operates in the saturation region when the brightness of the light-emitting device is at its maximum. The sixth wiring is a display device having the function of transmitting a second potential, In a plan view of the pixel, the first wiring, the second wiring, the third wiring, and the fifth wiring are arranged to extend along the first direction. In a plan view of the pixel, the fourth wiring and the sixth wiring are arranged to extend along a second direction intersecting the first direction. In a plan view of the pixel, the wiring width of the fifth wiring is greater than the wiring width of the first wiring, greater than the wiring width of the second wiring, and greater than the wiring width of the third wiring. A display device wherein, in a plan view of the pixel, the fourth wiring does not overlap with the conductive layer that functions as the pixel electrode.

2. Having multiple pixels, Each of the aforementioned plurality of pixels has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a light-emitting device. The channel formation region of the first transistor, the channel formation region of the third transistor, and the channel formation region of the fourth transistor each have a metal oxide. The channel formation region of the second transistor has silicon, The first transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The second transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The third transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The fourth transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The first gate and the second gate of the first transistor are electrically connected. The first gate of the first transistor is electrically connected to the first wiring, Either the source or the drain of the first transistor is electrically connected to the sixth wiring. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The second gate of the second transistor is electrically connected to either the source or the drain of the second transistor. The first gate of the second transistor is electrically connected to either the source or the drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the pixel electrode of the light-emitting device. The source or drain of the second transistor, the other of which is electrically connected to the fifth wiring, The first gate and the second gate of the third transistor are electrically connected. The first gate of the third transistor is electrically connected to the second wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The first gate and the second gate of the fourth transistor are electrically connected. The first gate of the fourth transistor is electrically connected to the third wiring. Either the source or the drain of the fourth transistor is electrically connected to the sixth wiring. The source or drain of the fourth transistor is electrically connected to the source or drain of the third transistor. One electrode of the first capacitor is electrically connected to either the source or the drain of the second transistor. The other electrode of the first capacitor is electrically connected to the first gate of the second transistor. One electrode of the second capacitor is electrically connected to the first gate of the second transistor. The other electrode of the second capacitance is electrically connected to the other source or drain of the second transistor. The first wiring has the function of transmitting a potential that selects the conduction state or non-conduction state of the first transistor. The second wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the third transistor. The third wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the fourth transistor. The fourth wiring has the function of transmitting an electric potential corresponding to the image data, The fifth wiring has the function of transmitting the first potential, The first potential is the potential at which the second transistor operates in the saturation region when the brightness of the light-emitting device is at its maximum. The sixth wiring has the function of transmitting a second potential, The display device wherein the second potential is 0V or GND potential, In a plan view of the pixel, the first wiring, the second wiring, the third wiring, and the fifth wiring are arranged to extend along the first direction. In a plan view of the pixel, the fourth wiring and the sixth wiring are arranged to extend along a second direction intersecting the first direction. In a plan view of the pixel, the wiring width of the fifth wiring is greater than the wiring width of the first wiring, greater than the wiring width of the second wiring, and greater than the wiring width of the third wiring. A display device wherein, in a plan view of the pixel, the fourth wiring does not overlap with the conductive layer that functions as the pixel electrode.

3. Having multiple pixels, Each of the aforementioned plurality of pixels has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a light-emitting device. The channel formation region of the first transistor, the channel formation region of the third transistor, and the channel formation region of the fourth transistor each have a metal oxide. The channel formation region of the second transistor has silicon, The first transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The second transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The third transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The fourth transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The first gate and the second gate of the first transistor are electrically connected. The first gate of the first transistor is electrically connected to the first wiring, Either the source or the drain of the first transistor is electrically connected to the sixth wiring. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The second gate of the second transistor is electrically connected to either the source or the drain of the second transistor. The first gate of the second transistor is electrically connected to either the source or the drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the pixel electrode of the light-emitting device. The source or drain of the second transistor, the other of which is electrically connected to the fifth wiring, The first gate and the second gate of the third transistor are electrically connected. The first gate of the third transistor is electrically connected to the second wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The first gate and the second gate of the fourth transistor are electrically connected. The first gate of the fourth transistor is electrically connected to the third wiring. Either the source or the drain of the fourth transistor is electrically connected to the sixth wiring. The source or drain of the fourth transistor is electrically connected to the source or drain of the third transistor. One electrode of the first capacitor is electrically connected to either the source or the drain of the second transistor. The other electrode of the first capacitor is electrically connected to the first gate of the second transistor. One electrode of the second capacitor is electrically connected to the first gate of the second transistor. The other electrode of the second capacitance is electrically connected to the other source or drain of the second transistor. The first wiring has the function of transmitting a potential that selects the conduction state or non-conduction state of the first transistor. The second wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the third transistor. The third wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the fourth transistor. The fourth wiring has the function of transmitting an electric potential corresponding to the image data, The fifth wiring has the function of transmitting the first potential, The first potential is the potential at which the second transistor operates in the saturation region when the brightness of the light-emitting device is at its maximum. The sixth wiring is a display device having the function of transmitting a second potential, In a plan view of the pixel, the channel length direction of the first transistor, the channel length direction of the third transistor, and the channel length direction of the fourth transistor are directions along the first direction. In a plan view of the pixel, the channel length direction of the second transistor is along a second direction that intersects with the first direction. In a plan view of the pixel, the first wiring, the second wiring, the third wiring, and the fifth wiring are arranged to extend along the first direction. In a plan view of the pixel, the fourth wiring and the sixth wiring are arranged to extend along the second direction. In a plan view of the pixel, the wiring width of the fifth wiring is greater than the wiring width of the first wiring, greater than the wiring width of the second wiring, and greater than the wiring width of the third wiring. A display device wherein, in a plan view of the pixel, the fourth wiring does not overlap with the conductive layer that functions as the pixel electrode.

4. Having multiple pixels, Each of the aforementioned plurality of pixels has a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a light-emitting device. The channel formation region of the first transistor, the channel formation region of the third transistor, and the channel formation region of the fourth transistor each have a metal oxide. The channel formation region of the second transistor has silicon, The first transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The second transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The third transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The fourth transistor has a first gate having a region above the channel formation region and a second gate having a region below the channel formation region. The first gate and the second gate of the first transistor are electrically connected. The first gate of the first transistor is electrically connected to the first wiring, Either the source or the drain of the first transistor is electrically connected to the sixth wiring. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The second gate of the second transistor is electrically connected to either the source or the drain of the second transistor. The first gate of the second transistor is electrically connected to either the source or the drain of the third transistor. Either the source or the drain of the second transistor is electrically connected to the pixel electrode of the light-emitting device. The source or drain of the second transistor, the other of which is electrically connected to the fifth wiring, The first gate and the second gate of the third transistor are electrically connected. The first gate of the third transistor is electrically connected to the second wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The first gate and the second gate of the fourth transistor are electrically connected. The first gate of the fourth transistor is electrically connected to the third wiring. Either the source or the drain of the fourth transistor is electrically connected to the sixth wiring. The source or drain of the fourth transistor is electrically connected to the source or drain of the third transistor. One electrode of the first capacitor is electrically connected to either the source or the drain of the second transistor. The other electrode of the first capacitor is electrically connected to the first gate of the second transistor. One electrode of the second capacitor is electrically connected to the first gate of the second transistor. The other electrode of the second capacitance is electrically connected to the other source or drain of the second transistor. The first wiring has the function of transmitting a potential that selects the conduction state or non-conduction state of the first transistor. The second wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the third transistor. The third wiring has the function of transmitting a potential that selects the conduction or non-conduction state of the fourth transistor. The fourth wiring has the function of transmitting an electric potential corresponding to the image data, The fifth wiring has the function of transmitting the first potential, The first potential is the potential at which the second transistor operates in the saturation region when the brightness of the light-emitting device is at its maximum. The sixth wiring has the function of transmitting a second potential, The display device wherein the second potential is 0V or GND potential, In a plan view of the pixel, the channel length direction of the first transistor, the channel length direction of the third transistor, and the channel length direction of the fourth transistor are directions along the first direction. In a plan view of the pixel, the channel length direction of the second transistor is along a second direction that intersects with the first direction. In a plan view of the pixel, the first wiring, the second wiring, the third wiring, and the fifth wiring are arranged to extend along the first direction. In a plan view of the pixel, the fourth wiring and the sixth wiring are arranged to extend along the second direction. In a plan view of the pixel, the wiring width of the fifth wiring is greater than the wiring width of the first wiring, greater than the wiring width of the second wiring, and greater than the wiring width of the third wiring. A display device wherein, in a plan view of the pixel, the fourth wiring does not overlap with the conductive layer that functions as the pixel electrode.

5. In any one of claims 1 to 4, The aforementioned metal oxide contains indium, and is used in display devices.

Images