Computer implementation method for updating metadata prediction tables, computer program product for updating metadata prediction tables, and system for updating metadata prediction tables (metadata prediction table update using a re-prediction pipeline).

Abstract

To provide a computer-implemented method for updating metadata prediction tables, and a computer program product and system for updating metadata prediction tables.SOLUTION: Aspects of the invention include a computer-implemented method for updating metadata prediction tables. The computer-implemented method includes establishing, in the metadata prediction tables, a prediction of how a set of instructions is resolved, and identifying that the set of instructions is completed. The computer-implemented method also includes determining, upon completion of the set of instructions, whether prediction update queues (PUQs) associated with the set of instructions indicate that the set of instructions is resolved in one of multiple proscribed manners relative to the prediction, and deciding that the metadata predictions tables are candidates to be updated based on the PUQs indicating that the set of instructions is resolved in one of the multiple proscribed manners.SELECTED DRAWING: Figure 7A

Description

Technical Field

[0001] The present invention generally relates to a prediction pipeline, and more specifically to a method for updating a metadata prediction table using a re-prediction pipeline.

Background Art

[0002] The instruction pipeline of a computer processor improves instruction execution throughput by processing instructions using multiple pipeline stages, and the multiple stages can act in parallel on different instructions of an instruction stream. A conditional branch instruction in an instruction stream can cause a pipeline stall if the processor waits until the conditional branch instruction is resolved in the execution stage of the pipeline before fetching the next instruction in the instruction fetch stage of the pipeline. A branch predictor can attempt to predict whether a conditional branch will branch or not, and can include branch target prediction that attempts to predict the target of a conditional or unconditional branch before it is calculated by decoding and executing the instruction itself. The branch target may be an address calculated based on an offset or an indirect reference or both via a register.

[0003] A branch target buffer (BTB) can be used to predict the target of a predicted branch instruction based on the address of the branch instruction. Predicting the target of a branch instruction can prevent pipeline stalls by not waiting for the branch instruction to reach the pipeline execution stage in order to calculate the branch target address. By performing branch target prediction, decoding of the branch target instruction can be performed in the same cycle or in a cycle after the branch instruction, instead of having multiple bubble / empty cycles between the branch instruction and the target of the predicted branch instruction. Other branch prediction components that may be included in the BTB or implemented separately include a branch history table (BHT) and a pattern history table (PHT). The branch history table can predict the direction of a branch (whether to branch or not) as a function of the branch address. The pattern history table can assist in predicting the direction of a branch as a function of the branch pattern leading up to the predicted branch. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] This invention provides a computer implementation method for updating metadata prediction tables, a computer program product for updating metadata prediction tables, and a system for doing so. [Means for solving the problem]

[0005] A non-restrictive example includes establishing a metadata prediction table for how a set of instructions will be resolved and identifying when the set of instructions is complete. A computer implementation may also include, upon completion of the set of instructions, a prediction update queue (PUQ) associated with the set of instructions, which indicates that the set of instructions has multiple predictions. prescribed To determine whether the issue was resolved using one of the formats, and whether the set of instructions is multiple prescribed This includes determining that the metadata prediction table is a candidate for update based on a PUQ indicating that it has been resolved in one of the formats.

[0006] Another embodiment of the present invention implements the features of the method described above into a computer system and a computer program product.

[0007] Additional technical features and advantages are realized by the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered to be part of the subject matter described in the claims. For a better understanding, refer to the detailed description and drawings.

[0008] Details of the exclusive rights described herein are specifically pointed out and explicitly asserted in the claims at the end of the specification. The above and other features and advantages of embodiments of the present invention will become apparent from the detailed description below in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows a system for performing a computer implementation method for chip designs according to one or more embodiments of the present invention. [Figure 2] Figure 2 is a schematic diagram of a branch prediction update system according to one or more embodiments of the present invention. [Figure 3] Figure 3 is a schematic diagram illustrating the operation of a weak predictive update queue (WeakPUQ) according to one or more embodiments of the present invention. [Figure 4] Figure 4 is a schematic diagram illustrating the operation of a mis-branched PUQ (BrWrgPUQ) according to one or more embodiments of the present invention. [Figure 5] Figure 5 is a flowchart showing the operation of WeakPUQ and BrWrgPUQ according to one or more embodiments of the present invention. [Figure 6] Figure 6 is a flowchart showing the operation of the re-prediction pipeline according to one or more embodiments of the present invention. [Figure 7A] Figure 7A is a flowchart showing a computer implementation method for updating a metadata prediction table according to one or more embodiments of the present invention. [Figure 7B] Figure 7B is a flowchart showing a computer implementation method for updating a metadata prediction table according to one or more further embodiments of the present invention. [Figure 8] Figure 8 is a schematic diagram of a computer system for performing a branch prediction update method according to one or more embodiments of the present invention. [Figure 9] Figure 9 is a flowchart of a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

[0010] The figures shown herein are illustrative. Many variations are possible in the figures or the operations described therein without departing from the spirit of the invention. For example, actions can be performed in a different order, or actions can be added, deleted, or modified. Furthermore, the term “combined” and its variations indicate that there is a communication path between two elements, and does not imply a direct connection between elements without an intervening element / connection. All these variations are considered part of the specification. [Modes for carrying out the invention]

[0011] One or more embodiments of the present invention provide an accurate and efficient method for determining whether any of the predictive structures combined to create a branch prediction need to be updated. A set of structures is created that helps determine whether a particular execution pipeline path of a branch needs to update the branch's predictive structures. By using these structures and a read-before-write model of completion time updates, much of the need for logic to track and apply speculative updates is eliminated, and latency in the critical predictive time pipeline controlling instruction fetch and decode streams is reduced.

[0012] For example, branch data such as direction and target address is crucial for the performance of general-purpose computers (such as mainframe machines). This is because predictive structures can prepare the machine for future needs ahead of the current instruction. When these predictive structures encounter a branch, they store the branch completion result in several different structures. This allows the machine to use the execution result of the previous branch to more accurately determine the future branch when another branch is predicted. In this way, by accurately updating the data in these structures, the machine can improve its performance in this area.

[0013] Furthermore, forking is a very common instruction in computers. Given the common nature of forking, the method for determining whether or not a fork needs to update its metadata is crucial. Traditionally, this was achieved by storing data from the time a fork is predicted until it is completed. However, this is costly in terms of silicon area and consumes a lot of power when this data is transferred, especially since the process from prediction to completion can involve many cycles. For example, the aging of speculative entries related to update mechanisms was tracked in attempts to predict whether a fork needed updating, based on the assumption that the prediction was correct and tracking fork information through the pipeline.

[0014] The drawback of the conventional solutions is that when one branch is executed continuously several times, there is often no way to convey from the dependent path of the branch that the previous branch has already updated the prediction structure. In the conventional solutions, the update mechanism was determined based on the prediction time information and how the branch would complete. In the conventional solutions, the updates that occurred between the time when the branch was predicted and the time when it completed were not considered, so these updates were excessive and potentially inaccurate. Examples of how inaccurate updates occur include multiple instances of updating the strength of a branch, which causes it to change from an initially weak state to a strong state, but then misbranch in the last instance. This misbranching will perform an incorrect update based on referring not to the updated strong state but instead to the old, incorrect weak state from the initial prediction.

[0015] Another drawback is that the method for determining whether an update is necessary for a branch is generally unclear. In such cases, extra power is consumed to write to an array or perform unnecessary updates or both, and the pipeline is delayed in performing the necessary updates.

[0016] Furthermore, the drawback of the previous solutions is that the branch data from the prediction time was saved and carried over until the completion time. This is to determine what should be updated using the information at the prediction time when the branch is resolved. Therefore, a lot of information needs to be retained for each branch, which is costly. In many cases, the tracking is meaningless because no update is necessary.

[0017] One or more embodiments of the present invention address one or more of the above-mentioned drawbacks of the prior art by providing a creation of a side structure or a set of prediction update queues (PUQs) that function as a funnel to determine whether a branch needs to pass through an update pipeline based on how the branch was predicted and how the branch was completed. The reasons for a branch to pass through the update logic upon completion are limited. Some of these reasons can be detected upon completion by performing minimal data tracking in conjunction with the execution result of the branch. These reasons always pass through to be updated because an update is always required for that branch. For the remaining reasons, the PUQ is split by reason, and when the branch is completed, each PUQ is checked. If there is a match in any of the PUQs, it indicates that the branch needs to go through the update pipeline. The update pipeline will predict the branch by reading data from the prediction structure upon completion and determining the correct state to update in conjunction with the result obtained from the completion of the branch through the same prediction mechanism. By going through the same process of how the branch is predicted and knowing how the branch was completed, the update pipeline can determine the correct update without carrying a lot of data throughout the entire pipeline from prediction to completion.

[0018] Thus, the present invention reduces the logical complexity in the prediction pipeline and the potential silicon area required to track extra information through the pipeline. Also, the PUQ structure reduces the amount of data required to be tracked through the execution pipeline. The PUQ structure can indicate that a branch needs to pass through the update pipeline as long as it matches the IA of a given branch, regardless of how the branch was completed. Further, in the PUQ, information about branches that are likely to require updates can be maintained.

[0019] Using a re-predictive pipeline eliminates the need to store all prediction time information in a side structure for tracking throughout the pipeline. The data goes through a process of re-predicting the branch upon completion and knowing how the branch completed, allowing the pipeline to know what updates are needed. This effectively eliminates almost all data tracking from prediction time to completion, potentially leading to an overall reduction in silicon area and power consumption by the core.

[0020] Figure 1 is a block diagram of a system 100 for performing a computer implementation method for updating branch prediction according to an embodiment of the present invention. System 100 includes a processing circuit 110 used to generate a design which will ultimately be manufactured into an integrated circuit 120. The steps involved in the manufacturing of the integrated circuit 120 are well known and will be briefly described herein. Once the physical layout is determined, according to an embodiment of the present invention, the determined physical layout is provided to the foundry to facilitate the optimization of the wiring plan. Based on the determined physical layout, masks are generated for each layer of the integrated circuit. The wafer is then processed in the order of the masks. Processing includes photolithography and etching, which will be further described with reference to Figure 9.

[0021] Referring to Figure 2, a system 200 for updating branch predictions is provided, which can be run or implemented in the computer system 800 of Figure 8. As shown in Figure 2, system 200 includes a branch target buffer (BTB) 201, a pattern history table (PHT) 202, a change target buffer (CTB) 203, and a perceptron 204. System 200 further includes prediction logic 210, completion logic 211, WeakPUQ 220, false branch PUQ (BrWrgPUQ) 230, completion write queue 214, and re-prediction pipeline 240. Prediction logic 210 can communicate with prediction bundle unit 212 and WeakPUQ 220. Completion logic 211 can communicate with WeakPUQ 220, BrWrgPUQ 230, completion group unit 213, and completion write queue 214. The re-prediction pipeline 240 is interposed in a communicative manner between the completed write queue 214 and the BTB201, PHT202, CTB203, and perceptron 204.

[0022] When a branch is predicted by BTB201 or any of the auxiliary structures that help determine the characteristics of the branch, particularly its direction and target address (i.e., PHT202, CTB203, and perceptron 204), the prediction logic 210, completion logic 211, WeakPUQ220, and BrWrgPUQ230 cooperate to determine whether the branch is a candidate for update when the branch is completed. In particular, WeakPUQ220 and BrWrgPUQ230 determine whether the branch needs to be sent for an update, and if it is determined that the branch needs to be sent for an update, they write representative data for that branch to the completion write queue 214.

[0023] Surprise branches and dynamic branches always need to go through the update pipeline if they take the wrong target or direction. A surprise branch is a branch that is neither predicted nor learned as part of the instruction decoding function. This type of branch can be identified upon completion by storing very small data such as the predicted direction or target. In addition, there are several other types of dynamic branches, which can also be identified upon completion and do not require extra information to perform the necessary updates. WeakPUQ220 tracks the information and determines when an update is needed upon completion.

[0024] Refer to Figure 3 to illustrate an exemplary scenario of WeakPUQ220 operation. As shown in Figure 3, branches A, B, and C are provided. Branch A is predicted to be weakly branched and is placed in WeakPUQ220 (point 1). Branch A is resolved as branched (point 4) and matched in WeakPUQ220, which means an update is needed, so branch A is updated from a weak branch to a strong branch (point 7). At point 4, the entry that matched branch A is invalidated in WeakPUQ220. For branches B and C, the prediction, resolution, and update are all for separate instances of the same branch, and since there are no matching entries in WeakPUQ220, they are invalidated at point 4 when branch A matches, and once these branches are completed (points 5 and 6 respectively), these branches are not sent to the update pipeline (points 8 and 9 are redundant and do not occur in the implementation of WeakPUQ220). Therefore, only the entry for branch A is sent to the update pipeline.

[0025] BrWrgPUQ230 behaves differently from WeakPUQ220 because BrWrgPUQ230 is designed to track a different set of branches. BrWrgPUQ230 is designed to track future instances of branches predicted in a strong state, SNT (strongly-not-taken), or ST (strongly-taken), which, upon completion, resolve in the wrong direction before the update for that branch is processed by the re-prediction pipeline 240 in the strong state. Because the branch resolves in the wrong direction, it is passed to the update pipeline, and simultaneously, this branch is installed in BrWrgPUQ230. BrWrgPUQ230 has the same IA and tracks branches that, after the initial branch, were predicted before completing the update and resolved with a prediction in the correct direction. For example, a future instance of the same branch that caused the installation to BrWrgPUQ230 might complete without mis-branching, be predicted to be in a strong state, match BrWrgPUQ230, and be sent to the re-prediction pipeline 240. In this case, those branches would have referenced an incorrect state at the time of prediction because the update to that state had not yet occurred since the completion of the first instance, and would miss this update because it resolved in a way that would cause the update if it were weakly predicted. However, BrWrgPUQ230 exists to catch this case and knows that the branch will go through the update pipeline. In other words, this PUQ has an entry that is created and invalidated upon completion, while WeakPUQ220 has an entry that is created at the time of prediction and invalidated upon completion.

[0026] Referring to Figure 4, an exemplary scenario of BrWrgPUQ230 operation is shown. As shown in Figure 4, branch A is expected to be in a strongly branched (ST) state. Because it is in a strongly branched state, it cannot be placed in WeakPUQ220 (point 1). Branch A resolves as not branching, which is the wrong direction (point 2), and branch A proceeds to the update pipeline to have its state updated. Branch A also creates an entry in BrWrgPUQ230. After a restart following the wrong branching direction, before the update of branch A is complete, branch A prime A strong state is predicted (point 3). Branch A prime This will result in the same instruction address as branch A when there is a loop and the same branch is predicted multiple times. The update process for branch A is completed (point 4). Branch A prime If the branch resolves correctly, it is predicted to be strong and resolved correctly, so it is not automatically known that an update is needed (point 5). Branch A prime The system checks and finds a match in BrWrgPUQ230. This leads to branch A. prime It is determined that the update pipeline needs to be passed through because there is extra information obtained from resolving Branch A. Branch A prime The data is updated by going through the update pipeline and returning from the WT state to the ST state (point 6).

[0027] Next, with reference to Figure 5, the operation of WeakPUQ220 and BrWrgPUQ230 will be described.

[0028] In the first instance, branch X completes at 501, and it is determined at 502 whether branch X resolved in the wrong direction or target. If branch X resolved in the wrong direction or target, an entry for branch X is written to BrWrgPUQ230 at 503, and an attempt is made to write the entry for branch X to the complete write queue at 504. If the complete write queue is full at 504 and cannot accept the write of branch X, this data is not installed in the complete write queue. This is followed by waiting for a completion event at 505 and completing branch X at 501. If the event branch did not resolve in the wrong direction or target, an entry for branch X is searched for in WeakPUQ220 at 506, and it is determined at 507 whether there is a hit in WeakPUQ220. If there is a hit, the entry for branch X is invalidated from WeakPUQ220 at 508, and control is advanced to 504. Conversely, if there is no hit, the program searches for the branch X entry in BrWrgPUQ230 at 509, and determines at 510 whether there is a hit. If there is a hit, the branch X entry in BrWrgPUQ230 is invalidated at 511, and control proceeds to 504. Conversely, if there is no hit, it is determined at 512 that updating branch X is unnecessary, and control proceeds to 505.

[0029] Referring back to Figure 2, the reprediction pipeline 240 is responsible for performing reprediction on the branch once the branch enters the update pipeline. That is, once it is determined that the branch should pass through the update pipeline, the final step before the process completes is to update the branch state. Since most of the data tracking is removed from the process, the branch reprediction is performed at completion. The logic of the reprediction pipeline 240 reads data from the array, where it picks up branch data, rather than from information tracked throughout the pipeline. The latest data makes it possible to determine the updates needed for the branch, and once an update is determined, the logic of the reprediction pipeline 240 writes the data back to update the array.

[0030] Next, we will explain the operation of the re-prediction pipeline, referring to Figure 6.

[0031] First, at 601, an entry for the next branch is searched for in the completed write queue 214, and at 602, it is determined whether the entry for the next branch is valid. If the entry is not valid, control is returned to 601. If the entry is valid, at 603, one or more metadata tables from BTB201, PHT202, CTB203, and perceptron204 are indexed, at 604, hit detection is performed, and at 605, it is determined whether a hit occurred. If no hit occurred, at 606 it is determined that it is a surprise branch, and at 607 it is determined whether a metadata state update is needed. If a metadata state update is needed, at 608 the updated state is written to the metadata table, and control is advanced to 601. If a hit occurred, at 609 it is determined whether a duplicate was found, and if a duplicate was found, at 610 all but one duplicate entry are invalidated, at 611 the re-predicted value is determined, at 612 the re-predicted value is compared with the existing result, and control is advanced to 607. If no duplicates are found, control immediately proceeds to 611.

[0032] Referring to Figure 7A, a computer implementation method for updating the metadata prediction table is provided, generally as described above. The computer implementation method includes establishing a prediction in the metadata prediction table about how a set of instructions will be resolved (701), and identifying that the set of instructions has been completed (702). The computer implementation method also includes, upon completion of the set of instructions, a prediction update queue (PUQ) associated with the set of instructions, which indicates that the set of instructions has multiple predictions. prescribed To determine whether to indicate that the issue was resolved in one of the forms (703), and whether the set of instructions is multiple prescribed The method includes determining that a metadata prediction table is a candidate for update based on a PUQ indicating that it has been resolved in one of the formats (704). Furthermore, the method may include updating the properties of the metadata prediction table that is a candidate for update (705).

[0033] In one or more embodiments of the present invention, determining that a metadata prediction table characteristic is a candidate for update in operation 704 may include determining that a set of instructions resolved with the wrong target, in the wrong direction, or as a surprise; determining that a metadata prediction table characteristic needs to be strengthened or weakened; or determining that a set of instructions resolved as an incorrect branch. However, it should be understood that other embodiments exist, and determining that a metadata prediction table characteristic is a candidate for update in operation 704 may include other determinations, conclusions, etc.

[0034] In any case, determining that a metadata prediction table property is a candidate for update in operation 704 is made possible by the ability of WeakPUQ220 to track a set of instructions that will need updating upon completion based on the assumed correctness of the prediction, and by the ability of BrWrgPUQ230 to track a set of instructions that will need updating based on how each multiple instance of the set of instructions completes. Thus, determining that a metadata prediction table property is a candidate for update in operation 704 may further include observing that the metadata prediction table property is a candidate for update (7041) and confirming that it is correct that the metadata prediction table property is a candidate for update (7042).

[0035] As an example, considering an update that includes strengthening / weakening updates, the following describes the observation of operation 7041 and the confirmation of operation 7042 when the characteristics of the metadata prediction table are in a predetermined state (i.e., an unsaturated state). Observation of operation 7041 occurs when a prediction is established in the metadata prediction table and includes assuming that an update is needed if the set of instructions is resolved as expected, and writing the data representing the set of instructions and the prediction as an entry to a PUQ such as WeakPUQ220. Confirmation of operation 7042 occurs when the set of instructions is completed and includes comparing the data of the completed instructions with the data representing the previous set of instructions that was written to the PUQ as a previous entry. Confirmation of operation 7042 further includes determining whether there is a match between the data representing the set of instructions and the data representing the previous set of instructions in the PUQ, invalidating the entry if there is a match, and confirming that the characteristics of the metadata prediction table should be updated.

[0036] As another example, the observation of operation 7041 and the confirmation of operation 7042 are described below for cases where the characteristics of the metadata prediction table should be modified to account for erroneous branch instances as an update. The observation of operation 7041 occurs upon completion of the first and second instances of the instruction set and includes writing the data representing the first instance of the instruction set and the prediction to a PUQ such as BrWrgPUQ230, respectively. The confirmation of operation 7042 occurs upon completion of the second instance of the instruction set and includes comparing the second data with the data representing the previous instruction set that was written to the PUQ as a previous entry, determining whether there is a match between the second data representing the second instruction set and the data representing the previous instruction set in the PUQ, invalidating the entry if there is a match, and confirming that the characteristics of the metadata prediction table should be modified to account for erroneous branch instances.

[0037] As used herein, the metadata prediction table may include one or more selected from the group consisting of BTB201, PHT202, CTB203, and perceptron 204.

[0038] Referring to Figure 7B, a computer implementation method for performing an update of the metadata prediction table characteristics, which is a candidate for update of operation 705, is provided as an additional set of operations to the method in Figure 7A. As shown in Figure 7B, the computer implementation method for performing an update of the metadata prediction table characteristics, which is a candidate for update of operation 705, includes reading characteristic data from the metadata prediction table upon completion of the set of instructions (704), comparing the characteristic data with knowledge of how the set of instructions resolved (705), and determining, based on the result of the comparison, whether to update the characteristics of the metadata prediction table (706).

[0039] Now, looking at Figure 8, a computer system 800 according to an embodiment is broadly shown. The computer system 800 may be an electronic computer framework that includes, employs, or both, any number and combination of computing devices and networks utilizing various communication technologies, as described herein. The computer system 800 may be easily extensible, expandable, and modular, and may have the ability to be changed to different services or to reconfigure some functions independently of others. The computer system 800 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, the computer system 800 may be a cloud computing node. The computer system 800 may be described in the general context that computer system executable instructions, such as program modules, are executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform a specific task or implement a specific abstract data type. The computer system 800 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked over a communication network. In a distributed cloud computing environment, program modules may reside on both local and remote computer system storage media, including memory storage devices.

[0040] As shown in Figure 8, the computer system 800 has one or more central processing units ((one or more) CPUs) 801a, 801b, 801c, etc. (collectively or generally referred to as (one or more) processors 801). The processors 801 can be single-core processors, multi-core processors, computing clusters, or any number of other configurations. The processors 801, also called processing circuits, are coupled to the system memory 803 and various other components via the system bus 802. The system memory 803 may include read-only memory (ROM) 804 and random-access memory (RAM) 805. The ROM 804 may be coupled to the system bus 802 and may include a basic input / output system (BIOS) that controls certain basic functions of the computer system 800. The RAM is read-write memory coupled to the system bus 802 for use by the processors 801. The system memory 803 provides temporary memory space for the operation of the instructions during operation. The system memory 803 may include random-access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0041] The computer system 800 includes an input / output (I / O) adapter 806 and a communication adapter 807 coupled to a system bus 802. The I / O adapter 806 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 808 or any other similar component or both. The I / O adapter 806 and the hard disk 808 are collectively referred to herein as mass storage device 810.

[0042] Software 811 for execution on the computer system 800 may be stored in a mass storage device 810. The mass storage device 810 is an example of a tangible storage medium readable by the processor 801, and the software 811 is stored as instructions to be executed by the processor 801 to operate the computer system 800, as described below with respect to various figures. Examples of computer program products and the execution of such instructions are described in more detail herein. A communication adapter 807 interconnects the system bus 802 with a network 812, which may be an external network, enabling the computer system 800 to communicate with other such systems. In one embodiment, part of the system memory 803 and the mass storage device 810 collectively store an operating system, which may be any suitable operating system, such as IBM Corporation's z / OS or AIX operating system, in order to coordinate the functions of the various components shown in Figure 8.

[0043] Additional input / output devices are shown connected to the system bus 802 via the display adapter 815 and the interface adapter 816. In one embodiment, adapters 806, 807, 815, and 816 may be connected to one or more I / O buses connected to the system bus 802 via an intermediate bus bridge (not shown). A display 819 (e.g., a screen or display monitor) is connected to the system bus 802 by the display adapter 815, which may include a graphics controller and a video controller to improve the performance of graphics-intensive applications. A keyboard 821, mouse 822, speaker 823, etc., can be interconnected to the system bus 802 via the interface adapter 816, which may include, for example, a super I / O chip integrating multiple device adapters into a single integrated circuit. A suitable I / O bus for connecting peripherals such as a hard disk controller, network adapter, and graphics adapter typically includes a common protocol such as PCI (Peripheral Component Interconnect). Therefore, as configured in Figure 8, the computer system 800 includes a processor 801, processing capabilities including system memory 803 and mass storage device 810, input means such as a keyboard 821 and mouse 822, and output capabilities including a speaker 823 and display 819.

[0044] In some embodiments, the communication adapter 807 can transmit data using any suitable interface or protocol, such as an Internet Small Computer System interface. The network 812 may be a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet. An external computing device may be connected to the computer system 800 via the network 812. In some examples, the external computing device may be an external web server or a cloud computing node.

[0045] It should be understood that the block diagram in Figure 8 is not intended to show that the computer system 800 includes all the components shown in Figure 8. Rather, the computer system 800 may include any suitable few or additional components not shown in Figure 8 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, embodiments of the computer system 800 described herein may be implemented with any suitable logic, which in various embodiments may include any suitable hardware (e.g., processors, embedded controllers, or application-specific integrated circuits, etc.), software (e.g., applications, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0046] Figure 9 is a flowchart of a method for fabricating an integrated circuit according to an exemplary embodiment of the present invention. Based in part on the computer implementation method of branch prediction updates described herein, once physical design data is obtained, the integrated circuit 120 can be fabricated according to a known process generally described with reference to Figure 9. Generally, a wafer having multiple copies of the final design is fabricated and cut (i.e., diced) so that each die is one copy of the integrated circuit 120. In block 910, the process includes fabricating a mask for lithography based on the finalized physical layout. In block 920, fabricating the wafer includes performing photolithography and etching using the mask. Once the wafer is diced, in block 930, each die is tested and sorted to filter out any defective dies.

[0047] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments of the present invention can be devised without departing from the scope of the invention. Various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are shown in the following description and drawings. These connections or positional relationships, or both, are direct or indirect unless otherwise specified, and the present invention is not intended to limit itself in this respect. Thus, the joining of entities can refer to either direct or indirect joining, and the positional relationships between entities can be direct or indirect positional relationships. Furthermore, the various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes by having additional steps or functions not described in detail herein.

[0048] One or more of the methods described herein can be implemented using any or a combination of the following technologies well known in the art: individual logic circuits having logic gates for implementing logic functions in data signals, application-specific integrated circuits (ASICs) having appropriate combinations of logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), and the like.

[0049] For the sake of brevity, prior art relating to creating and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are well known. Therefore, for the sake of brevity, many prior implementation details are either briefly mentioned herein or omitted entirely without providing details of well known systems or processes or both.

[0050] In some embodiments, various functions or operations can be performed at a given location, in connection with the operation of one or more devices or systems, or both. In some embodiments, a portion of a given function or operation can be performed at a first device or location, and the remainder of the function or operation can be performed at one or more additional devices or locations.

[0051] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit them. Where used herein, the singular forms "a," "an," and "the" are intended to include the plural form unless the context explicitly indicates otherwise. Where used herein, the terms "comprises" or "comprising" or both specify the presence of a described feature, integer, step, operation, element, or component or combination thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof.

[0052] All corresponding structures, materials, actions, and equivalent means or step-plus-function elements in the following claims are intended to include any structures, materials, or actions for performing a function in combination with other claimed elements, as specifically claimed. This disclosure is presented for illustrative and explanatory purposes, but is not intended to be exhaustive or to be limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The embodiments have been selected and described to best illustrate the principles and practical applications of this disclosure and to enable those skilled in the art to understand this disclosure in terms of various embodiments with various modifications suitable for the particular use to be intended.

[0053] The diagrams shown herein are illustrative. Many variations are possible in the diagrams or the steps (or operations) described therein without departing from the spirit of this disclosure. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term “combined” describes the presence of a signal path between two elements, and does not mean a direct connection between elements without an intervening element / connection. All such variations are considered part of this disclosure.

[0054] The following definitions and abbreviations are for use in interpreting the claims and specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” “containing,” or any other variation thereof, mean exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus containing a list of elements is not necessarily limited to those elements alone and may include other elements not expressly listed in such composition, mixture, process, method, article, or apparatus.

[0055] Furthermore, the term “exemplary” is used herein to mean “example, instance, or illustration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” are understood to include one or more, i.e., any integer such as 1, 2, 3, 4, etc. The term “multiple” is understood to include two or more, i.e., any integer such as 2, 3, 4, 5, etc. The term “connection” may include both indirect and direct “connections.”

[0056] The terms “approximately,” “substantially,” and “estimated,” and their variations, are intended to include the degree of error associated with measuring a particular quantity based on the equipment available at the time of filing. For example, “approximately” may include a range of ±8%, 5%, or 2% of a particular value.

[0057] The present invention may be a system, method, or computer program product or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium storing computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0058] A computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. Examples of computer-readable storage media may be electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or appropriate combinations thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROM, DVD, memory stick, floppy disk, punch cards, or grooved raised structures, and mechanically encoded devices on which instructions are recorded, and appropriate combinations thereof. Computer-readable storage devices as used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0059] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computer device / processor. Alternatively, they can be downloaded to an external computer or external storage device via a network (e.g., the Internet, LAN, WAN, or wireless network, or a combination thereof). The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers or edge servers, or a combination thereof. A network adapter card or network interface within each computer device / processor receives computer-readable program instructions from the network and transfers them for storage in a computer-readable storage medium in each computer device / processor.

[0060] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed as a standalone software package, either entirely on the user's computer or partially on the user's computer. Alternatively, they can be executed partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including LANs and WANs, or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), and programmable logic arrays (PLAs), can execute computer-readable program instructions by utilizing state information of computer-readable program instructions in order to customize the electronic circuits for the purpose of performing aspects of the present invention.

[0061] Each aspect of the present invention is described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. Each block in a flowchart or block diagram, or both, and combinations of multiple blocks in a flowchart or block diagram, or both, are executable by computer-readable program instructions.

[0062] The above computer-readable program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing device for the purpose of producing a machine. This creates a means for these instructions, executed via the processor of such computer or other programmable data processing device, to perform functions / operations identified in one or more blocks in a flowchart or block diagram, or both. The above computer-readable program instructions may further be stored in a computer-readable storage medium that can be instructed to function in a particular manner to a computer, a programmable data processing device, or other device, or a combination thereof. This constitutes a product in which the computer-readable storage medium containing the instructions includes instructions for performing functions / operations identified in one or more blocks in a flowchart or block diagram, or both.

[0063] Alternatively, a computer execution process may be generated by loading computer-readable program instructions into a computer, another programmable device, or other device, and having a series of operational steps executed on that computer, other programmable device, or other device. This ensures that the instructions executed on the computer, other programmable device, or other device perform functions / operations identified in one or more blocks in a flowchart, block diagram, or both.

[0064] The flowcharts and block diagrams in the figures illustrate the configuration, functions, and operations of executable modes of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which constitutes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions shown in the blocks may differ from the order shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or the blocks may be executed in reverse order depending on their function. It should also be noted that each block in a block diagram or flowchart or both, and any combination of blocks in a block diagram or flowchart or both, can be implemented by a special-purpose hardware-based system that performs a specified function or operation, or a combination of special-purpose hardware and computer instructions.

[0065] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and changes are possible without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to describe the principles of the embodiments, their practical application to market-based technologies or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer implementation method for updating a metadata prediction table, wherein the computer implementation method is The metadata prediction table establishes a prediction of how the set of instructions will be resolved, Identifying that the aforementioned set of instructions has been completed, Upon completion of the set of instructions, it is determined whether the set of instructions resolved the prediction in one of a plurality of predetermined forms, When it is determined that the set of instructions has been resolved in one of the plurality of predetermined formats, and it is assumed that an update to the metadata prediction table is necessary based on the prediction of the set of instructions, if the prediction update queue (PUQ), which stores data representing the set of instructions and the prediction, contains data representing the set of instructions resolved in one of the plurality of predetermined formats, then it is determined that the metadata prediction table is a candidate for update. Computer implementation methods, including those mentioned above.

2. Determining that the set of instructions resolved in one of the plurality of predetermined forms includes determining that the set of instructions resolved to the wrong target, in the wrong direction, or as a surprise. The computer implementation method according to claim 1.

3. The determination that the metadata prediction table is a candidate for update is, Observe that the aforementioned metadata prediction table is a candidate for update. Confirm that the aforementioned metadata prediction table is indeed a candidate for update, The computer implementation method according to claim 1, including the method described in claim 1.

4. When the metadata prediction table is in a predetermined state, The observation includes assuming that an update is needed when the prediction is established in the metadata prediction table and the set of instructions is resolved as expected, and writing data representing the set of instructions and the prediction as an entry to one of the PUQs, The confirmation occurs upon completion of the set of instructions and includes comparing the data of the completed instructions with data representing a set of previous instructions that was written as a previous entry to one of the PUQs; determining whether there is a match between the data representing the set of instructions and the data representing the set of previous instructions in one of the PUQs; invalidating the entry if a match is found; and confirming that the metadata prediction table should be updated. The computer implementation method according to claim 3.

5. When the metadata prediction table should be modified to account for erroneous instances, The observation occurs upon completion of the first and second instances of the set of instructions and includes writing the data representing the first instance of the set of instructions and the prediction to one of the PUQs, respectively. The verification occurs upon completion of a second instance of the set of instructions and includes comparing second data representing the second instance of the set of instructions with data representing a previous set of instructions written as a previous entry in one of the PUQs; determining whether there is a match between the second data and the data representing the previous set of instructions in one of the PUQs; invalidating the entry if there is a match; and confirming that the metadata prediction table should be modified to account for erroneous branch instances. The computer implementation method according to claim 3.

6. The aforementioned decision is, A weak predictive update queue (WeakPUQ) tracks a set of instructions that need to be updated upon completion based on the assumed correctness of the aforementioned prediction, A false branch PUQ (BrWrgPUQ) tracks a set of instructions that need updating based on how multiple instances of the aforementioned set of instructions complete, The computer implementation method according to claim 1, made possible by the above.

7. This further includes updating the metadata prediction table which is a candidate for update, and the update is: Upon completion of the aforementioned set of instructions, characteristic data is read from the metadata prediction table, This involves comparing the aforementioned characteristic data with knowledge of how the aforementioned set of instructions was resolved, Based on the results of the comparison, a decision is made as to whether or not to update the metadata prediction table. The computer implementation method according to claim 1, including the method described in claim 1.

8. A system for updating a metadata prediction table, wherein the system is Memory containing computer-readable instructions, The system includes one or more processors for executing the computer-readable instructions, and the computer-readable instructions control the one or more processors, The metadata prediction table establishes a prediction of how the set of instructions will be resolved, Identifying that the aforementioned set of instructions has been completed, Upon completion of the set of instructions, it is determined whether the set of instructions resolved the prediction in one of a plurality of predetermined forms, When it is determined that the set of instructions has been resolved in one of the plurality of predetermined formats, and it is assumed that an update to the metadata prediction table is necessary based on the prediction of the set of instructions, if the prediction update queue (PUQ), which stores data representing the set of instructions and the prediction, contains data representing the set of instructions resolved in one of the plurality of predetermined formats, then it is determined that the metadata prediction table is a candidate for update. Perform an action that includes system.

9. Determining that the set of instructions resolved in one of the plurality of predetermined forms includes determining that the set of instructions resolved to the wrong target, in the wrong direction, or as a surprise. The system according to claim 8.

10. The determination that the metadata prediction table is a candidate for update is, Observe that the aforementioned metadata prediction table is a candidate for update. This includes verifying that the metadata prediction table is indeed a candidate for update, When the metadata prediction table is in a predetermined state, The observation includes assuming that an update is needed when the prediction is established in the metadata prediction table and the set of instructions is resolved as expected, and writing data representing the set of instructions and the prediction as an entry to one of the PUQs, The confirmation occurs upon completion of the set of instructions and includes comparing the data of the completed instructions with data representing a set of previous instructions that was written as a previous entry to one of the PUQs; determining whether there is a match between the data representing the set of instructions and the data representing the set of previous instructions in one of the PUQs; invalidating the entry if a match is found; and confirming that the metadata prediction table should be updated. The system according to claim 8.

11. The determination that the metadata prediction table is a candidate for update is, Observe that the aforementioned metadata prediction table is a candidate for update. This includes verifying that the metadata prediction table is indeed a candidate for update, When the metadata prediction table should be modified to account for erroneous instances, The observation occurs upon completion of the first and second instances of the set of instructions and includes writing the data representing the first instance of the set of instructions and the prediction to one of the PUQs, respectively. The verification occurs upon completion of a second instance of the set of instructions and includes comparing second data representing the second instance of the set of instructions with data representing a previous set of instructions written as a previous entry in one of the PUQs; determining whether there is a match between the second data and the data representing the previous set of instructions in one of the PUQs; invalidating the entry if there is a match; and confirming that the metadata prediction table should be modified to account for erroneous branch instances. The system according to claim 8.

12. The aforementioned decision is, A weak predictive update queue (WeakPUQ) tracks a set of instructions that need to be updated upon completion based on the assumed correctness of the aforementioned prediction, A false branch PUQ (BrWrgPUQ) tracks a set of instructions that need updating based on how multiple instances of the aforementioned set of instructions complete, The system according to claim 8, made possible by the above.

13. This further includes updating the metadata prediction table which is a candidate for update, and the update is: Upon completion of the aforementioned set of instructions, characteristic data is read from the metadata prediction table, This involves comparing the aforementioned characteristic data with knowledge of how the aforementioned set of instructions was resolved, Based on the results of the comparison, a decision is made as to whether or not to update the metadata prediction table. The system according to claim 8, including the above.

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