Metacapacitors and power electronic converters for power electronic systems

Abstract

Disclosed are power electronic systems and components of power electronic systems, such as electrical energy storage devices / subsystems and power electronic devices / subsystems in the form of supercapacitors. The supercapacitor has a conductive or semiconductive first metasurface layer, a conductive or semiconductive second metasurface layer, and a dielectric layer sandwiched between the first and second metasurface layers to electrically insulate the first metasurface layer from the second metasurface layer. The power converter has first power conversion circuitry for converting a first portion of power received from a power source and outputting the converted power via an output. The power converter also has one or more direct power transfer (DPT) channels electrically coupled in parallel with the first power conversion circuitry for bypassing the first power conversion circuitry and directly transferring a second portion of the power received from the power source to the output.

Description

[Technical Field]

[0001] Cross-reference of related applications This application 、2 This claim asserts the benefits of U.S. Provisional Patent Application No. 62 / 914,237, filed on October 11, 2019.

[0002] Areas of disclosure This disclosure generally relates to power electronic systems and their components, and more particularly to high-density energy storage devices using supercapacitors for providing energy storage, and power electronic devices and methods using direct power transfer for converting power from one form to another. [Background technology]

[0003] background Power electronic devices and systems supply power to various power-consuming loads, such as electronic devices, and, if necessary, provide solutions for converting power from one form to another in order to supply power to the load. Almost all devices that use electricity utilize some form of power electronics technology. Power electronic devices and systems typically include power electronic circuit configurations, such as power converters.

[0004] Power sources typically include generators, energy storage devices and systems, and associated circuit configurations. Generators may be conventional thermal power plants that use fossil fuels (e.g., coal, natural gas, and / or oil) to generate electricity, and / or generators that use renewable energy such as wind and / or solar energy.

[0005] Renewable energy is a clean and practical way of generating electricity to provide power to end users. For example, rooftop solar panels have gained considerable attention to meet residential energy needs. Wind energy has been used to harness wind power to generate electricity. Solar and wind energy are among the fastest-growing renewable energy systems due to their significant advantages.

[0006] Renewable energy has the potential to become one of the mainstream energy generation technologies of the future, but many challenges still remain that hinder its widespread adoption. Some of these challenges include: Energy generation may be unreliable due to the intermittency of solar and wind conditions. • There is a wide range of variations in the operating points of solar / wind energy harvesting systems, which can significantly reduce the overall efficiency of the system, and • Energy harvesting systems typically require the power grid to provide resilience.

[0007] Due to the challenges mentioned above, existing solar / wind harvesting systems may not offer optimal solutions for many new applications. Considering the exponential growth of solar / wind energy systems and their impact on the landscape of harvesting systems, suboptimal operation has a significant detrimental effect on these systems.

[0008] Energy storage systems can provide solutions to overcome the aforementioned challenges of intermittent renewable energy sources and facilitate reliable renewable energy generation systems.

[0009] Energy storage systems often include one or more batteries for storing energy. For example, lithium-ion batteries have been used in many applications (e.g., electric vehicles, residential energy storage, laptops, smartphones, tablets, etc.). Other types of battery technologies, such as redox flow batteries, have also been used in some applications (e.g., grid-scale energy storage).

[0010] Most batteries rely on certain types of redox reactions. Therefore, they typically undergo volume changes and expansion of the active material (usually due to excessive redox reactions) during charge and discharge cycles. Generally, when there are electrochemical reactions, there is lifecycle degradation and a decrease in the number of batteries. While considerable research has been done to mitigate degradation to extend lifespan, the lifespan of existing batteries is still limited. In addition, high-performance batteries often require expensive and hazardous materials, which can be flammable and pose several safety risks.

[0011] Other disadvantages of batteries typically include their bulkiness and their generally low power density.

[0012] Supercapacitors have been presented as another candidate for the energy storage market. As those skilled in the art will understand, supercapacitors offer considerable energy storage capacity and can provide performance improvements compared to battery technology, particularly in terms of lifespan and dynamics. For example, electric double-layer capacitors (EDLCs) are based solely on the generation of an electric field, virtually without chemical reactions. Thus, EDLCs can offer very long lifespans (e.g., up to millions of charge / discharge cycles) and very high power densities.

[0013] While the power density of supercapacitors is typically hundreds of times (e.g., 100 to 1000 times) higher than that of batteries, the energy density of supercapacitors (volumetric energy density measured in Wh / liter or gravimetric energy density measured in Wh / kg) is relatively limited. For example, the energy density of batteries is typically tens of times (e.g., 3 to 30 times) higher than that of supercapacitors. In fact, the low energy density of supercapacitors may be the main reason why batteries are far more prevalent in mainstream energy storage, despite the significant advantages they offer.

[0014] Therefore, existing energy storage systems are typically bulky (for example, due to their low energy density), usually have a short lifespan, low capacity, and are expensive. Thus, there is a need for low-cost, high-density energy storage systems. Such high-density energy storage systems could not only revolutionize the future of energy systems but could also be used in many other applications such as biomedical (e.g., wearable devices and / or implants), robotics, and IoT (Internet-of-Things) devices.

[0015] Regarding the power electronic circuit configurations of power electronic devices and systems, power electronics technology and power electronic converters have been used in many applications such as renewable energy systems, energy storage systems, electric vehicles, electronic devices (e.g., smartphones, tablets, etc.), and LED lighting. Therefore, power electronic converters play a crucial role in energy systems and electronic devices. Power electronic converters and their applications have shown exponential growth.

[0016] The efficiency, power density, and reliability of power electronic converters are extremely important for a variety of applications. However, • Large switching losses due to hard switching of power semiconductors. • Large conduction losses in various components used in power circuit configurations, and • The difficulty of thermal management to remove the heat generated during the operation of power electronic converters while ensuring reliable operation of the power electronic converters. There are various challenges and difficulties related to power conversion technologies of prior art, such as those mentioned above.

[0017] These challenges may mean that existing power electronic converters may not provide sufficiently high or optimal efficiency. The widespread adoption and exponential growth of power electronic converters and their applications may lead to their suboptimal performance or inefficiency, resulting in significant energy waste and consequently, a major negative impact on the global environment.

[0018] Therefore, there is a need for highly efficient power electronic converters to solve the above problems and challenges. [Overview of the project] [Means for solving the problem]

[0019] overview According to certain aspects of this disclosure, ultra-high-density energy storage devices and systems are provided that have a long lifespan (e.g., within a range of hundreds of thousands of cycles) and very high energy / power density.

[0020] According to one aspect of the present disclosure, an electrical energy storage device is provided, comprising a first conductive or semiconductive metasurface layer, a second conductive or semiconductive metasurface layer, and a dielectric layer sandwiched between the first and second metasurface layers to electrically insulate the second metasurface layer from the first metasurface layer.

[0021] In some embodiments, the first metasurface layer comprises a plurality of nanoscale or microscale first structures, the second metasurface layer comprises a plurality of nanoscale or microscale second structures, and the first and second structures extend relative to each other without electrical contact.

[0022] In some embodiments, the first structure includes a plurality of recesses at its distal end, and at least a second set of the second structure is housed within the recesses of the first structure without electrical contact with the recesses.

[0023] In some embodiments, the first structure includes a plurality of first rods having recesses at their distal ends, and at least a portion of the second structure is housed within the recesses of the first rods without electrical contact with the recesses.

[0024] In some embodiments, the first structure includes a plurality of first rods, and the second structure includes a plurality of second rods arranged alternately with the first rods.

[0025] In some embodiments, at least a first set of the first and second structures has a circular, elliptical, or rectangular cross-section.

[0026] In some embodiments, one or more dimensions of the first structure and the second structure are within the nanometer range or the micrometer range.

[0027] In some embodiments, the thicknesses of the first and second structures are in the nanometer range or the micrometer range.

[0028] In some embodiments, an electrical energy storage device further includes at least one of a first electrode bonded to a first metasurface layer and a second electrode bonded to a second metasurface layer.

[0029] In some embodiments, at least one of the first metasurface layer and the second metasurface layer includes a conductive base that forms an electrode.

[0030] In some aspects and in some embodiments, a method for manufacturing an electrical energy storage device is provided, the method comprising: (i) depositing a first conductive layer on a substrate; (ii) spin-coating a photoresist layer on the conductive layer; (iii) applying a mask to the photoresist layer and exposing the masked photoresist layer under light, wherein the mask has a predefined pattern; (iv) removing unexposed portions of the photoresist layer by developing; (v) depositing a conductive material on the photoresist layer to allow the first conductive material to fill the removed portions of the photoresist layer; (vi) dissolving the photoresist layer to form a first conductive structure set; (vii) depositing a layer of dielectric material on the deposited first conductive material to form a dielectric layer on the deposited first conductive material; (viii) depositing a second conductive material on the dielectric layer to form a second structure set; and (ix) electroplating a third conductive material on the second structure set.

[0031] In some embodiments, the substrate is silicon (Si).

[0032] In some embodiments, the first conductive layer contains silver (Ag).

[0033] In some embodiments, the first conductive layer further comprises titanium (Ti).

[0034] In some embodiments, the photoresist layer includes SU-8.

[0035] In some embodiments, the light includes ultraviolet (UV) light.

[0036] In some embodiments, the first conductive material includes Ag.

[0037] In some embodiments, the dielectric material includes fused silica (SiO2).

[0038] In some embodiments, the second conductive material includes Ag.

[0039] In some embodiments, the third conductive material includes Ag.

[0040] In some aspects and in some embodiments, power-electronic conversion systems and power-electronic converters using direct power transmission (DPT) are provided. The power-electronic converters disclosed herein can provide highly efficient and reliable solutions for a variety of applications.

[0041] In some aspects and in some embodiments, a power converter is provided, comprising: a first power conversion circuit configuration for receiving an input current from a power source, converting a first portion of the power of the input current, and outputting the converted power via at least one output, wherein the first power conversion circuit configuration includes a first transformer having a primary side for coupling to a power source and a secondary side for coupling to at least one output; and at least one direct power transmission (DPT) channel electrically coupled in parallel with the first power conversion circuit configuration to bypass the first power conversion circuit configuration and to directly transmit a second portion of the power received from the power source for power output via at least one output to the secondary side of the first transformer.

[0042] In some embodiments, the first power conversion circuit configuration includes a current switching structure coupled to the primary side of the first transformer for switching current.

[0043] In some embodiments, at least one DPT channel is coupled to the primary side of the first transformer by a second transformer.

[0044] In some embodiments, the first transformer and the second transformer share a common core.

[0045] In some embodiments, the first power conversion circuit configuration includes at least a pair of power semiconductors S1 and S2 suitable for operation under zero-voltage switching (ZVS) conditions.

[0046] In some embodiments, at least the first and second power semiconductors include at least one pair of metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0047] In some embodiments, the device further includes multiple output diodes suitable for operation under zero-current switching (ZCS) conditions.

[0048] In some embodiments, the device further includes an input switch for coupling a power supply to a first power conversion circuit configuration and at least one DPT channel, and the plurality of output diodes include four diodes D1, D2, D3, and D4, wherein the first end of D1 is coupled to the first end of D2 which forms a first input terminal, the first end of D3 is coupled to the first end of D4 which forms a second input terminal, and the first and second input terminals are coupled to the secondary side of a first transformer and the output side of at least one DPT channel, the second end of D1 is coupled to the second end of D3 which forms a first output terminal, the second end of D2 is coupled to the second end of D4 which forms a second output terminal, and the first and second output terminals are coupled to at least one output, and the device, It is suitable for operating in multiple modes, including (i) a first mode in which D1 and D4 are on and S1 is switched from on to off under ZVS conditions; (ii) a second mode in which D1 and D4 are on and S2 is turned on under ZVS conditions; (iii) a third mode in which D1 and D4 are off, D2 and D3 are on under ZCS conditions and S2 is on; (iv) a fourth mode in which S2 is turned off under ZVS conditions; (v) a fifth mode in which S1 is on under ZVS conditions and D2 and D3 are on; (vi) a sixth mode in which D2 and D3 are off under ZCS conditions and D1 and D4 are turned on under ZCS conditions; and (vii) a seventh mode in which the input switches are turned off to make the input current zero.

[0049] In some embodiments, the input switch is a diode.

[0050] In some embodiments, the device is suitable for operating the input current in a pseudo-continuous conduction mode (pseudo-CCM) to reduce the peak value and / or root mean square (RMS) value of the input current.

[0051] In some embodiments, the first power conversion circuit configuration includes a first resonant tank.

[0052] In some embodiments, at least one DPT channel includes at least one second resonant tank.

[0053] In some embodiments, the input current is alternating current (AC) or direct current (DC).

[0054] In some embodiments, at least one output includes either an AC output or a DC output.

[0055] In some embodiments, at least one output includes multiple outputs, at least one DPT channel includes multiple DPT channels, and at least two of the multiple DPT channels are coupled to different outputs of the multiple outputs.

[0056] Brief explanation of the drawing Embodiments of the present disclosure will now be described with reference to the following drawings, in which the same reference numerals in different drawings indicate the same elements. [Brief explanation of the drawing]

[0057] [Figure 1] This is a schematic diagram illustrating the basic operation of a conventional capacitor. [Figure 2] This is a schematic diagram showing the basic structure of an electric double-layer capacitor (EDLC). [Figure 3A] This is a schematic diagram showing an EDLC based on carbon nanotubes (CNTs). [Figure 3B]This is a schematic diagram showing a graphene-based EDLC. [Figure 4] This is a schematic diagram of a supercapacitor according to some embodiments of the present disclosure. [Figure 5A] These are schematic diagrams of supercapacitors according to some further embodiments of the present disclosure. [Figure 5B] Figure 5A is a schematic diagram showing the cylindrical nano / microstructure of a supercapacitor. [Figure 5C] Figure 5A is a schematic diagram showing the cubic nano / micro structure of a supercapacitor. [Figure 6A] These are schematic diagrams of supercapacitors according to some further embodiments of the present disclosure. [Figure 6B] This is a schematic diagram of a supercapacitor according to some embodiments of the present disclosure. [Figure 7A-7C] Figure 7A is a perspective view of a supercapacitor according to several more embodiments of the present disclosure, Figure 7B is a perspective cross-sectional view of the supercapacitor shown in Figure 7A along section AA, and Figure 7C is an exploded perspective view of the supercapacitor shown in Figure 7A. [Figures 8A-8F] Figures 8A to 8F illustrate the manufacturing process of the supercapacitor shown in Figure 7A, according to several embodiments of the present disclosure. [Figure 8G-8L] Figures 8G to 8K illustrate the manufacturing process of the supercapacitor shown in Figure 7A according to some embodiments of the present disclosure, and Figure 8L shows the legend for Figures 8A to 8K. [Figure 9] This is a schematic diagram illustrating an exemplary configuration of a DC microgrid. [Figure 10A] This is a schematic diagram of a power-electronic conversion system according to several embodiments of the present disclosure, showing a power-electronic conversion system having an AC power source, a DC load, and an AC-DC (AC / DC) power converter between them. [Figure 10B]This is a schematic diagram of a power electronic conversion system according to several embodiments of the present disclosure, showing a power electronic conversion system having a DC power supply, a DC load, and a DC-DC (DC / DC) power converter between them. [Figure 10C] This is a schematic diagram of a power-electronic conversion system according to some embodiments of the present disclosure, showing a power-electronic conversion system having a DC power supply, an AC load, and a DC-AC (DC / AC) power converter between them. [Figure 10D] This is a schematic diagram of a power-electronic conversion system according to some embodiments of the present disclosure, showing a power-electronic conversion system having an AC power source, an AC load, and an AC-AC (AC / AC) power converter between them. [Figure 11] Figure 10B is a schematic diagram of the circuit configuration of a prior art resonant DC / DC converter for use in the power electronic conversion system shown. [Figure 12] Figure 10B is a schematic diagram of the circuit configuration of a prior art non-resonant DC / DC converter for use in the power electronic conversion system shown. [Figure 13] Figure 10A is a schematic diagram of the circuit configuration of an AC / DC converter for use in the power electronic conversion system shown. [Figure 14] Figure 12 is a schematic diagram of the circuit configuration of a prior art non-resonant DC / DC converter, where block arrows indicate the power flow to show that the power semiconductor processes all the input power. [Figure 15] This is a schematic diagram of a power-electronic conversion system using direct power transmission (DPT) according to some embodiments of the present disclosure, the power-electronic conversion system includes a power-electronic converter having a power conversion circuit configuration and a DPT channel electrically coupled in parallel with it. [Figure 16A] Figure 15 is a schematic diagram of the circuit configuration of a DC / DC converter shown in some embodiments of the present disclosure. [Figure 16B] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16C] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16D] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16E] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16F] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16G] Figure 16A shows different operating modes of the DC / DC converter. [Figure 16H] Figure 16A shows different operating modes of the DC / DC converter. [Figure 17] Figure 16A shows the main waveforms of the DC / DC converter. [Figure 18] Figure 16A is a schematic diagram showing a simplified circuit of the DC / DC converter. [Figure 19] Figure 16A shows a plot of the DC / DC converter parameters PDPT,n from the perspective of different values ​​of nφ and nf of the DC / DC converter shown in Figure 16A. [Figure 20] From the perspective of the coupling coefficient k, plots of the inductances L1, L2, and M of the DC / DC converter shown in Figure 16A are presented. [Figure 21A] Figure 16A shows the simulation results of the DC / DC converter at the nominal load, and the waveform of switch S1 is shown. [Figure 21B] Figure 16A shows the simulation results of the DC / DC converter at the nominal load, and the waveform of switch S2 is shown. [Figure 21C] Figure 16A shows the simulation results of the DC / DC converter at the nominal load, and the current waveform of the coupled inductor is shown. [Figure 21D] Figure 16A shows the simulation results of the DC / DC converter at nominal load, with the waveforms of vinv, vprim, and iLs displayed. [Figure 21E]Figure 16A shows the simulation results of the DC / DC converter at nominal load, with the waveforms for vsec and it displayed. [Figure 21F] Figure 16A shows the simulation results of the DC / DC converter at nominal load, and displays the current and voltage waveforms of output diodes D1 and D2. [Figure 22] Figure 16A is a photograph of the prototype DC / DC converter shown. [Figure 23A] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 23B] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 23C] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 23D] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 23E] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 23F] The experimental waveforms obtained from the prototype shown in Figure 22 are shown under full load conditions. [Figure 24A] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 24B] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 24C] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 24D] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 24E] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 24F] The experimental waveform obtained from the prototype shown in Figure 22 at 50% of the nominal power is shown. [Figure 25]Figure 22 shows the efficiency measured from the prototype at 20% to 100% of the rated power. [Figure 26] Figure 15 is a schematic diagram of the circuit configuration of an AC / DC power electronic converter according to some embodiments of the present disclosure. [Figure 27] Figure 15 is a schematic diagram of the circuit configuration of a DC / DC power electronic converter shown in some embodiments of the present disclosure, the power conversion circuit configuration of which includes a resonant tank. [Figure 28] Figure 15 is a schematic diagram of the circuit configuration of a DC / DC power electronic converter shown in some embodiments of the present disclosure, wherein its DPT channel includes a resonant tank. [Figure 29] Figure 15 is a schematic diagram of the circuit configuration of a DC / DC power electronic converter shown in several embodiments of the present disclosure, in which each of the power conversion circuit configurations and DPT channels includes a resonant tank. [Figure 30] Figure 15 is a schematic diagram of the circuit configuration of an AC / DC power electronic converter shown in several embodiments of the present disclosure, the power conversion circuit configuration of which includes a resonant tank. [Figure 31] Figure 15 is a schematic diagram of the circuit configuration of an AC / DC power electronic converter shown in some embodiments of the present disclosure, wherein its DPT channel includes a resonant tank. [Figure 32] Figure 15 is a schematic diagram of the circuit configuration of an AC / DC power electronic converter shown in several embodiments of the present disclosure, in which each of the power conversion circuit configurations and DPT channels includes a resonant tank. [Figure 33] Figure 15 is a schematic diagram of the circuit configuration of a DC / DC power electronic converter shown in some embodiments of the present disclosure, the power conversion circuit configuration and DPT channel including a transformer sharing a common magnetic element structure in which coils are separately wound around a common core. [Figure 34]Figure 15 is a schematic diagram of the circuit configuration of a DC / DC power electronic converter shown in several embodiments of the present disclosure, the power conversion circuit configuration and DPT channel including a transformer that shares a common magnetic element structure implemented as a center-tapped transformer. [Figure 35] This is a schematic diagram of a power-electronic conversion system using DPT according to some embodiments of the present disclosure, the power-electronic conversion system includes a power conversion circuit configuration and a power-electronic converter having a plurality of DPT channels electrically coupled together in parallel. [Figure 36] Figure 35 is a schematic diagram of the circuit configuration of an exemplary DC / DC converter shown in some embodiments of the present disclosure, the power electronic converter system including a power conversion circuit configuration and a power electronic converter having two DPT channels electrically coupled together in parallel. [Figure 37] This is a schematic diagram of a power-electronic conversion system using DPT according to some embodiments of the present disclosure, the power-electronic conversion system includes a multi-output power-electronic converter having a power conversion circuit configuration and a plurality of DPT channels electrically coupled together in parallel. [Figure 38] Figure 37 is a schematic diagram of the circuit configuration of an exemplary multi-output DC / DC converter shown in some embodiments of the present disclosure, the power electronic conversion system including a power electronic converter having a power conversion circuit configuration and two DPT channels electrically coupled together in parallel. [Modes for carrying out the invention]

[0058] Detailed explanation Embodiments of this specification relate to power electronic systems, as well as components of power electronic systems such as energy storage devices / subsystems and power electronic devices / subsystems in the form of supercapacitors.

[0059] Supercapacitor In some embodiments, and in some cases, a supercapacitor is provided having a greatly increased energy density that can exceed the energy density of a battery. The supercapacitor structures disclosed herein could lead supercapacitor technology to the forefront of the energy storage market.

[0060] Figure 1 shows the basic operation of a conventional capacitor 10, which includes a pair of electrodes 12 with a layer of dielectric material 14 sandwiched between them. Power is output from the electrodes 12 by a conductor 16 that supplies power to a load 18.

[0061] According to Figure 1, the capacitance of capacitor 10 is

number

[0062] The energy stored in capacitor 10 is

number

[0063] Energy equation (2) shows the parameters that affect the energy density of capacitor 10. These parameters are: • Overlap area A between the two electrodes 12, • Distance d between electrodes 12, • The field dielectric constant of dielectric material 14, and • Operating voltage of capacitor 10 V That is the case.

[0064] When using a simple structure similar to the one shown in Figure 1, the capacitance C and stored energy W are often too small to make the capacitor 10 a viable option for energy storage purposes. In the prior art, much effort has been made to optimize the above parameters and increase the energy density of the capacitor (in which case it may be referred to as a "supercapacitor").

[0065] Figure 2 shows the basic structure of an electric double-layer capacitor (EDLC) 20. In this structure, the electrodes (i.e., anode 22 and cathode 24) are separated by a separator 26 (such as a membrane), and the electrolyte 28 is sandwiched between the electrodes 22, 24 and the separator 26. The EDLC 20 stores energy by charge separation (the same mechanism as the conventional capacitor 10 shown in Figure 1). As can be seen, the structure of the EDLC 20 is symmetrical and can provide different polarities. The main energy is stored in the electrodes between the two electrodes 22 and 24. The stronger the electric field, the more energy is stored in the EDLC 20.

[0066] As shown in Figure 2, the EDLC20 includes two separate charge layers 30 at the interface between the electrolyte 28 and the positive / negative electrodes 22 and 24 (this is where the name electric double-layer capacitor comes from). This differs from conventional structures that only include single-layer charge isolation. In the EDLC20, the distance between the electric double layers 30 is much smaller than that of the conventional structure 10. Therefore, the capacitance, and consequently the stored energy, can be increased by several orders of magnitude compared to that of the conventional structure 10.

[0067] Area and distance are the main parameters that can be controlled to achieve high capacity and high energy density in EDLC20. Since a high specific surface area is generally desirable in EDLCs, high capacity and high energy density can be achieved by using materials with a high specific surface area and good conductivity, such as nanostructures. Examples of such nanostructures include carbon nanotubes (CNTs) and graphene, where CNTs are one-dimensional (1D) structures and graphene is a two-dimensional (2D) structure. Graphene has an even larger specific surface area compared to CNTs and has therefore been used in many EDLC structures. Figures 3A and 3B show the structures of an EDLC with CNTs 30 and an EDLC with graphene 40, respectively. As shown, the structures of the EDLC with CNTs 30 and the EDLC with graphene 40 are similar to the structure of EDLC20 shown in Figure 2, except that EDLCs 30 and 40 contain CNTs 30 and graphene 40, respectively, sandwiched between electrodes 22, 24 and separator 26.

[0068] While carbon nanostructures offer high specific surface area and a large number of charge / discharge cycles, there are several challenges to using them in EDLCs. These challenges primarily relate to the synthesis and fabrication of carbon nanostructures for EDLCs, as well as device consistency. Furthermore, despite the fact that carbon nanostructures have significantly improved the performance of EDLCs, their energy density may still be lower than that of batteries.

[0069] While CNT and graphene structures effectively increase specific surface area and, consequently, capacity, such increases are somewhat random and cannot achieve the theoretical full size of the specific surface area. For example, theoretically, graphene could have a specific surface area of ​​several thousand m³. 2 / g(2630m 2 A specific surface area of ​​( / g) should be achieved. However, the practically achievable specific surface area of ​​graphene is only a few tens, or at most a few hundred m². 2 The amount is approximately [number] grams. The main problem stems from the atomic and molecular structure of these nanostructures.

[0070] Referring here to Figure 4, supercapacitors according to several embodiments of the present disclosure are shown, generally identified using reference numeral 100. As shown, the supercapacitor 100 includes a pair of electrode layers 102A and 102B (collectively identified using reference numeral 102) and a dielectric layer 104 sandwiched between the electrode layers 102. In these embodiments, each electrode layer 102 includes a conductive or semiconducting metasurface coupled to the respective electrode layer 102 to increase the specific surface area, and a suitable dielectric material sandwiched between the metasurfaces to electrically insulate the metasurfaces from each other.

[0071] The academic paper titled "LIGHT PROPAGATION WITH PHASE DISCONTINUITIES: GENERALIZED LAWS OF REFLECTION AND REFRACTION" by Nanfang Yu, Patrice Genevet, Mikhail A. Kats, Francesco Aieta, Jean-Philippe Tetienne, Federico Capasso, and Zeno Gaburro (Science volume 334, issue 6054, pages 333-337 (2011)), whose contents are incorporated herein by reference in their entirety, describes metasurfaces from the perspective of their use in the field of optics.

[0072] The conductive or semiconducting metasurfaces used in the supercapacitor 100 disclosed herein may be similar to those described in the aforementioned academic papers, but they do not necessarily have to exhibit the optical characteristics described herein.

[0073] Specifically, the conductive or semiconducting metasurface used in the supercapacitor 100 is a structure having a two-dimensional (2D) surface with superimposed nanoscale structures (also referred to as "nanostructures") arranged with nanoscale spacing, and the nanoscale structures consist of one or more suitable conductive or semiconducting materials.

[0074] In some embodiments, the nanoscale structure may be a structure in which one or more of its dimensions are within the nanometer (nm) range (e.g., less than 1 micrometer (μm)), and “nanoscale spacing” means that the spacing between nanoscale structures is within the nanometer range. In some embodiments, the nanoscale structure may include a plurality of nanorods (also referred to as “antennas”). In some embodiments, the nanoscale structure 124 may include a plurality of V-shaped nanorods. The nanoscale structure may form a periodic or repeating pattern, and each pattern may include a plurality of nanoscale structures of different shapes and dimensions.

[0075] In some embodiments, the metasurface of each electrode layer 102 may include a plurality of microscale structures (i.e., one or more of which have dimensions within the micrometer range (e.g., less than 1 millimeter (mm)) and / or have microscale spacing between them).

[0076] The supercapacitors 100 disclosed herein may be referred to as "metasupercapacitors" or "metacapacitors." By using metasurfaces, the effective area is greatly increased because the nano / microstructure allows the size of these cylinders / cylinders to be in the nanometer or micrometer range.

[0077] In some embodiments, the nano / microstructures of the metasurfaces of the electrode layer 102 extend without electrical contact with one another and are electrically insulated by a dielectric layer 104 sandwiched between them. Because the nano / microstructures of the metasurfaces have nanoscale or microscale spacing, the distance between metasurfaces is significantly reduced as a result. Consequently, the supercapacitor 100 disclosed herein can provide ultra-high energy density and stable device performance.

[0078] For example, Figure 5A shows the structure of a supercapacitor 100 in one embodiment. As shown, the supercapacitor 100 includes a pair of electrode layers 102A and 102B and a dielectric layer 104 sandwiched between them.

[0079] Each electrode layer 102A, 102B includes metasurfaces 106A, 106B (collectively identified using reference number 106) in which the nanostructures are arranged in interlocked cylinders to increase the specific surface area and reduce the spacing between them. Specifically, electrode layer 102A includes a first metasurface 106A that extends from the 2D surface of the first electrode layer 102A and includes a plurality of first nanostructures (also identified by using reference number 106A) in the form of hollow rods having open distal ends (i.e., having recesses at their distal ends).

[0080] The electrode layer 102B includes a second metasurface 106B which contains a plurality of second nanostructures (also identified by using reference no. 106B) in the form of solid or hollow rods extending from the 2D surface of the second electrode layer 102B. In embodiments where the second nanostructures are hollow rods, such hollow rods may also include an open distal end to further increase the specific surface area.

[0081] In these embodiments, at least a portion of the second nanostructure 106B is housed within the recesses of each of the first nanostructures 106A without electrical contact, thereby forming an interlocking cylinder. The first and second nanostructures 106A and 106B are separated by a suitable dielectric material of a dielectric layer 104 that isolates the charge.

[0082] In some embodiments, the interlock cylinder 106 may include first and second microstructures 106A and 106B, with at least a portion of the second microstructure 106B housed within each of the first microstructures 106A.

[0083] In various embodiments, the first and second nano / microstructures 106A and 106B may have any suitable shape. For example, in some embodiments shown in Figure 5B, the first and second nano / microstructures 106A and 106B may be cylindrical in shape with a circular or elliptical cross-section. In some embodiments shown in Figure 5C, the first and second nano / microstructures 106A and 106B may be cubic in shape with a rectangular cross-section.

[0084] The supercapacitor 100 disclosed herein can greatly increase its stored energy by substantially increasing its specific surface area (i.e., effective overlap area) and significantly reducing the distance between the electrode layers 102. Compared to existing EDLCs, the supercapacitor 100 can make full use of its surface area so that its capacitance, and consequently the energy stored within it, can increase by several orders of magnitude.

[0085] In the above embodiment, first and second nanoscale or microscale structures 106A and 106B extend toward each other without electrical contact, by housing at least a portion of the second structure 106B within a recess of the corresponding first structure 106A.

[0086] In some embodiments, as shown in Figure 6A, the first metasurface 106A does not contain any nanoscale or microscale rods. More precisely, the first metasurface 106A includes a plurality of nanoscale or microscale recesses for housing nano / microstructures 106B without electrical contact.

[0087] In some embodiments, as shown in Figure 6B, the nanoscale or microscale structures of the first and second metasurfaces 106A and 106B are arranged alternately (i.e., adjacent to each other) without electrical contact.

[0088] In the embodiments described above, each metasurface is formed by depositing a nano / microstructure on a conductive base, which also functions as an electrode layer. Therefore, in these embodiments, further or separate electrode layers may not be necessary. In some embodiments, each metasurface may be bonded to another electrode layer, which is conductive with the other electrode layer.

[0089] As described above, the effective surface area of ​​the supercapacitor 100 is greatly increased by incorporating nanorods or nanopillars into the design of the electrodes 102. The nanopillars may have circular, elliptical, square, or other shapes suitable for fabrication. To maintain a small gap between the electrodes 102, the nanopillars of one electrode may have a complementary shape to those of the other electrode. The dielectric layer includes a suitable dielectric material such as SiO2, Al2O3, or other dielectric material with a high breakdown voltage to fill the gaps between the nanoscale structures of the electrodes 102 and to electrically insulate them from each other.

[0090] The supercapacitor 100 can greatly increase its stored energy by substantially increasing its specific surface area and significantly decreasing the distance between electrodes. Therefore, the effects of the structure of the supercapacitor 100 disclosed herein consist of three parts: • To increase the effective overlap area, • Reducing the distance between electrodes, and • To create high-energy storage in an ultra-thin, small form factor structure.

[0091] Compared to existing EDLCs, the supercapacitor 100 disclosed herein can make full use of its surface area to maximize capacitance, and as a result, its stored energy can be increased by several orders of magnitude.

[0092] Because the surface is essentially very thin, the supercapacitor 100 disclosed herein can be easily integrated with a photovoltaic panel. Alternatively, the supercapacitor 100 may be fabricated directly on one side of a silicon-based photovoltaic panel for direct storage of the charge generated by the panel, thereby eliminating the losses associated with transmitting the charge from the photovoltaic cell to the distant storage. As a secondary advantage, having both the photovoltaic panel and the storage device on both sides of a single silicon substrate can significantly reduce the overall size of the device and eliminate the electronic circuits that would otherwise be required to connect the charge generation site and the storage site.

[0093] Figure 7A shows a supercapacitor 100 in several embodiments, Figure 7B is a perspective cross-sectional view of the supercapacitor 100 shown in Figure 7A along section AA, and Figure 7C is an exploded perspective view thereof.

[0094] Figures 8A to 8K illustrate the manufacturing process of the supercapacitor 100 shown in Figure 7A according to several embodiments of the present disclosure. Figure 8L shows the legend for Figures 8A to 8K.

[0095] As shown in Figure 8A, a base material 202, such as a silicon (Si) substrate, is prepared (preparation step). As shown in Figure 8B, a conductive layer 204 of, for example, titanium (Ti) and silver (Ag) is deposited on the silicon substrate using an electron beam or a thermal evaporator (Ag deposition step). In these embodiments, the Ti layer is used as an adhesive layer. As shown in Figure 8C, a photoresist layer 206, such as a layer of SU-8, is spin-coated onto the conductive layer 204 (SU-8 spin coating step).

[0096] As shown in Figure 8D, ultraviolet (UV) light 208 is emitted toward the photoresist layer 206 using a suitable mask layer 210 to define the nanopillar pattern (UV exposure step). As shown in Figure 8E, the exposed portions of the photoresist layer are crosslinked. As shown in Figure 8F, the unexposed portions of the photoresist layer are removed by development (development step).

[0097] As shown in Figure 8G, the Ag layer 212 is deposited within the pattern formed by the removed portion of the photoresist layer. The deposited Ag layer 212 is integrated with the conductive layer 204. As shown in Figure 8H, SU-8 is dissolved to produce Ag nanopillars (formed by the Ag layer 212). Thus, the integrated Ag layer 212 and conductive layer 204 form the metasurface of electrode 102B.

[0098] As shown in Figure 8I, a layer 214 of a dielectric material such as fused silica (SiO2) is deposited on the Ag nanopillar 212 to form a thin dielectric layer 104 that covers and insulates the Ag nanopillar 212.

[0099] As shown in Figure 8J, an Ag layer 216 is deposited on the dielectric layer 104, filling the gaps between the Ag nanopillars 212. The dielectric layer 104 electrically insulates the Ag layer 216 from the Ag nanopillars 212. As shown in Figure 8K, another Ag layer 218 is applied by an electroplating process to cover the entire area. The Ag nanopillars 212 are integrated with the Ag layer 218 to form the electrode 102A.

[0100] Power electronic conversion system and power electronic converter using direct power transmission (DPT) In some aspects and in some embodiments, power-electronic conversion systems and power-electronic converters using direct power transmission (DPT) are provided. The power-electronic converters disclosed herein can provide highly efficient and reliable solutions for a variety of applications.

[0101] In some embodiments and in several other embodiments, an isolated DC-DC converter circuit topology is provided that can provide high performance over a wide range of operating conditions. The main features of the DC / DC converter circuit include its DPT capability, pseudo-continuous conduction mode (pseudo-CCM) operation, and soft-switching performance over a wide range of operating conditions. When DPT operation is used, the amount of power that needs to be handled by the power switch and transformer is reduced. In addition, pseudo-CCM operation reduces the peak and root mean square values ​​of the input current, which results in a reduction of conduction losses related to the windings and semiconductors.

[0102] In the DC / DC converter circuit structure, the power switch benefits from zero-voltage switching characteristics while its output diode operates under zero-current switching conditions. As a result, the reverse recovery problem of the output diode is eliminated. All of these features result in low conduction loss and low switching loss, thereby improving overall efficiency. The operating principle of the proposed converter and its theoretical analysis will be described in detail later. To verify the feasibility of the proposed DC / DC converter and demonstrate its superior performance, simulation and experimental results of a 450-watt (W) (190V / 48V) experimental prototype are provided.

[0103] As those skilled in the art will understand, growing energy demand, coupled with concerns about climate change, necessitates a significant paradigm shift toward renewable energy sources. A reliable and efficient architecture is needed to extract and deliver energy from renewable sources to the load. Microgrids represent a relatively new and compelling concept for efficiently integrating renewable energy sources into power systems.

[0104] Specifically, DC microgrids have attracted considerable attention in recent years due to their efficient operation ([1]-[3]). Many renewable energy sources, such as solar and wind power, generate DC power (wind turbines, along with generators, produce alternating current (AC) power, but AC power has variable frequency and amplitude, requiring conversion to DC). Also, many energy storage systems are based on batteries, which are necessarily DC. In addition, the load situation has changed in recent years, with the presence of many DC loads such as electronic devices (smartphones, tablets, etc.) and LED lighting ([4]). Therefore, DC systems seem to be a natural fit for future grids using many DC sources, DC loads, and DC energy storage. DC systems have better efficiency, do not require reactive power, and are not sensitive to harmonics. Therefore, they are generally superior to their AC counterparts ([5]). The introduction of DC-powered homes is evidence of the great potential of DC microgrids ([6], [7]).

[0105] Figure 9 shows an exemplary configuration of a DC microgrid that can be used in a DC-powered residential system. As shown, the DC microgrid includes a high-voltage bus (HV BUS, e.g., ±190V) and a low-voltage bus (LV BUS, e.g., 48V). Higher power components such as the main energy storage system, renewable energy sources, and high-power loads are connected to the high-voltage bus, while many low-power loads such as LED lighting and electronics are connected to the low-voltage bus ([8]~

[10] ). A DC / DC converter is used between the high-voltage and low-voltage buses to maintain the voltage of the low-voltage DC bus within a desired range. Desirable attributes for this DC / DC converter are high efficiency, high power density, galvanic isolation, and low output current / voltage ripple. While this converter requires bidirectional power flow capability for some applications, for this application, unidirectional power flow is sufficient due to the fact that the low-voltage bus is simply responsible for supplying power to the loads (LED lighting, electronics, etc.).

[0106] DC / DC converters have been extensively analyzed in references

[11] –

[24] . Traditionally, many products have been based on the well-known phase-shifted full-bridge power circuit topology. However, this topology has several performance issues, including output diode voltage spikes, unpredictable spacing, and hard switching under light loads. To mitigate these problems, resonant DC / DC converters have been introduced (

[25] –

[27] ). Specifically, LLC resonant converters have attracted considerable attention due to their attractive features. In fact, many current industrial products are based on this power circuit topology because they offer superior performance. While LLC resonant converters have many attractive features, they also have several drawbacks, such as performance degradation under a wide range of operating conditions, complex magnetic design, complex control, and bulky resonant tanks (

[28] –

[31] ).

[0107] To further improve performance, higher-order resonant transducers are also introduced. For example, CLLC type resonant transducers can achieve zero-voltage switching (ZVS) and zero-current switching (ZCS) on their primary and secondary sides over a wide operating range (

[27] ). In addition, in

[32] , CLTC type resonant transducers are introduced by combining LLC, SRC, and CLLC types. In this topology, auxiliary transformers and additional resonant capacitors are used to provide ZVS over a wide operating range. However, the gain curves of these resonant transducers have multiple peaks. Therefore, control and design can be quite complex.

[0108]

[33] describes a current-driven non-resonant transducer that can provide high performance similar to an LLC resonant transducer with reduced complexity. This structure is further improved in

[18] to extend the soft-switching range. To reduce the effects of parasitic components, a non-resonant hybrid current-driven topology is disclosed in

[34] . This topology can reduce the adverse effects of transformer winding capacitance and can provide a transducer with higher voltage gain. However, passive components are added to the transducer structure, which increases reactive current and consequently conduction losses. In

[35] , the non-resonant current-driven topology is extended to an AC-DC (AC / DC) transducer. The power circuit topology of this transducer is shown in Figure 13 (which will be discussed further later). This transducer offers a simple structure and provides ZVS over a wide operating range using a simple control system. While this power circuit topology offers many advantages, it has some disadvantages. The operation of the input inductor in discontinuous conduction mode (DCM) results in high peak current values. As a result, the root mean square (RMS) value of the current is high, leading to high conduction losses. Another drawback of this topology is that all the power must be handled by the power semiconductors. This increases conduction losses and requires more effective thermal management.

[0109] Therefore, to reduce switching losses, existing power circuit typologies typically provide soft switching. However, they do not improve conduction losses.

[0110] Figures 10A to 10D show a power-electronic conversion system 110 according to several embodiments of the present disclosure. The power-electronic conversion system 110 can be used to convert power from one form to another and includes a power supply 120 that supplies power to a load 124 via a power-electronic converter 122.

[0111] The power supply 120 may be an AC power supply 120A (see Figures 10A and 10D) or a DC power supply 120D (see Figures 10B and 10C). The load 124 may be a DC load 124D (see Figures 10A and 10B) or an AC load 124A (see Figures 10C and 10D). Correspondingly, the power electronic converter 122 may be an AC / DC converter 122AD (see Figure 10A), a DC / DC converter 122DD (see Figure 10B), a DC-AC (DC / AC) converter 122DA (see Figure 10C), or an AC-AC (AC / AC) converter 122AA (see Figure 10D).

[0112] In prior art power-electronic conversion systems, and in some embodiments of the power-electronic conversion system 110 disclosed herein, the power circuit configuration of the power-electronic converter 122 may include power semiconductors (such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and / or diodes), capacitors, and magnetic elements (such as inductors and / or transformers). In these systems, the power semiconductors are used for high-frequency switching (and therefore sometimes referred to as “switching converters”).

[0113] Typically, the use of power semiconductors with higher switching frequencies necessitates smaller passive components (such as capacitors and / or magnetic elements) and higher power density. However, increasing the switching frequency of power semiconductors increases switching losses, thereby reducing power conversion efficiency, as switching losses are a result of the overlap between the switching current waveform and the switching voltage waveform during the switching transition. Soft switching techniques have been used to reach higher switching frequencies while mitigating switching losses.

[0114] Another important factor affecting power conversion efficiency is usually conduction loss (also called resistance loss), which is caused by the current flowing through components that are considered to be ideally conductive (i.e., zero resistance) but actually have non-zero resistance values. For example, when a MOSFET is on, it is theoretically considered to be ideally conductive, but in reality, it functions as a resistor (denoted as R DS (ON)>0) with a non-zero resistance value (i.e., R DS (ON)). Therefore, the conduction loss of the on-state MOSFET is I 2 rms ·R DS (ON)>0, where I rms is the root mean square (rms) of the current flowing through the MOSFET.

[0115] Before describing the power electronic conversion system and power electronic converter using DPT, first, several prior art power circuit configurations for reducing the switching loss and conduction loss of the power electronic converter will be described below.

[0116] One of the power circuit configurations widely used in prior art power electronic converters is the resonant converter. FIG. 11 is a schematic diagram of the circuit configuration of an exemplary resonant DC / DC converter 122DD'.

[0117] As shown, the resonant DC / DC converter 122DD' receives a DC input V in from a DC power source (not shown), and uses a pair of MOSFETS1 and S2 that form a current switching structure for switching the current on the primary side 126, a transformer 128 for electrically coupling the primary side 126 to the secondary side 130, and a set of four diodes D1 - D4 on the secondary side 130 for generating a DC output V o . The capacitor C o is used on the secondary side to filter the AC component from the DC output V o .

[0118] In this example, the resonant DC / DC converter 122DD' includes a high-frequency filter or resonant tank 132 between a pair of MOSFETs S1 and S2 on the primary side 126 and the transformer 128 in order to provide a waveform close to a sine wave and to provide soft switching to the transformer 128.

[0119] Non-resonant power circuit configurations are also known. Figure 12 is a schematic diagram of the circuit configuration of an exemplary non-resonant DC / DC converter 122DD''. Similar to the resonant DC / DC converter 122DD' shown in Figure 11, the non-resonant DC / DC converter 122DD'' shown in Figure 12 comprises a pair of MOSFETs S1 and S2 on the primary side, a transformer 128 for electrically coupling the primary side 126 to the secondary side 130, and a DC output V o A set of four diodes D1-D4 and capacitor C on the secondary side 130 to generate o The non-resonant DC / DC converter 122DD'' also includes appropriate components for providing soft switching.

[0120] The power circuit configurations shown in Figures 11 and 12 for resonant and non-resonant DC / DC converters can be modified for use in AC / DC converters. Figure 13 shows the circuit configuration of an exemplary non-resonant AC / DC converter 122AD'. The non-resonant AC / DC converter 122AD' includes a power circuit configuration similar to the power circuit configuration of the non-resonant DC / DC converter 122DD'' shown in Figure 12, and further includes a pair of diodes D5 and D6 coupled to the AC power supply 120A on the primary side 126 to convert AC power to DC power for input to the downstream power circuit configuration.

[0121] In conventional power circuit configurations, all input power is handled by power semiconductors and passive components (e.g., transformers). Figure 14 is a schematic diagram of the circuit configuration of the non-resonant DC / DC converter 122DD'' shown in Figure 12, where block arrows 134 indicate power flow. Because all input power is handled by power semiconductors S1 and S2 and transformer 128, large conduction losses can occur due to power semiconductors S1 and S2 and transformer 128. Therefore, prior art power converters may not provide sufficiently high power conversion efficiency.

[0122] A power-electronic conversion system and a power-electronic converter using DPT will be described below.

[0123] In some embodiments, the power electronic converter may be a DC / DC converter capable of minimizing both conduction and switching losses. The power circuit topology disclosed herein is based on the basic structure proposed in

[35] . The main feature of this structure is its DPT capability, which effectively reduces the power handled by the power semiconductors. Thus, conduction losses can be reduced; that is, a portion of the power is directly transmitted to the output. Consequently, the power ratings of the components and their costs can be reduced. Another main advantage of the proposed structure is that the input current operates in a pseudo-continuous conduction mode (pseudo-CCM). The input current of the proposed converter has much lower peak and RMS values ​​compared to that of

[35] . Thus, the proposed structure can significantly reduce conduction losses. This converter also provides a ZVS condition for the power semiconductors on the input side and a ZCS condition for the diodes on the output side.

[0124] Figure 15 is a schematic diagram of a power-electronic conversion system 110 for converting power from one form to another, according to several embodiments of the present disclosure. As shown, the power-electronic conversion system 110 includes a power supply 120 that supplies power to a load 124 via a power-electronic converter 122. Similar to the systems shown in Figures 10A to 10C, the power supply 120 in these embodiments may be an AC power supply (corresponding to the AC power supply 120A shown in Figure 10A) or a DC power supply (corresponding to the DC power supply 120D shown in Figures 10B and 10C). The load 124 may be a DC load (corresponding to the DC load 124D shown in Figures 10A and 10B) or an AC load (corresponding to the AC load 124A shown in Figure 10C).

[0125] Accordingly, the power electronic converter 122 may be an AC / DC converter (similar to the AC / DC converter 122AD shown in Figure 10A), a DC / DC converter (similar to the DC / DC converter 122DD shown in Figure 10B), or a DC / AC converter (similar to the DC / AC converter 122DA shown in Figure 10C).

[0126] In these embodiments, the power electronic converter 122 includes a power conversion circuit configuration 142 such as a “general” prior art power circuit configuration having passive components such as power semiconductors and transformers (this may be similar to the prior art power electronic converters shown in Figures 11-13). However, in these embodiments, the power electronic converter 122 further includes a DPT channel 144 electrically coupled in parallel to the power conversion circuit configuration 142 to improve the performance of the power electronic converter 122.

[0127] During operation, the power electronic converter 122 uses a power conversion circuit configuration 142 to convert a first portion of the power received from the power supply 120, and uses a DPT channel 144 to transmit a second portion of the power received from the power supply 120 directly to the output (e.g., load 124) without being processed by power semiconductors and passive components in the power conversion circuit configuration 142.

[0128] Figure 16A shows the circuit configuration of a DC / DC power electronic converter 122DD in one embodiment. As shown, the power electronic converter 122DD uses a pair of MOSFETs S1 and S2, as well as a first transformer 128 for converting a first portion of the DC power received from the DC power supply 120D (indicated by arrow 152), and a general power conversion circuit configuration 142 (inductor L in Figure 12) similar to that shown in Figure 12, which uses a pair of MOSFETs S1 and S2, as well as a first transformer 128 for converting a first portion of the DC power received from the DC power supply 120D. g This includes (labeled L1 in Figure 16A). The power electronic converter 122 is coupled by a coupling inductor L2 to inductor L1 of a general power conversion circuit configuration 142 on the primary side 126, thereby directly transmitting a second portion of the received DC power (indicated by arrow 156) from the primary side 126 to the secondary side 130, thereby further including a DPT channel 144 that forms a second transformer 154 to bypass MOSFETs 1 and S2, as well as the first transformer 128.

[0129] The input power is transmitted to the output through two different paths. A portion of the power 152 is processed by power semiconductors, and the other portion 156 is transmitted directly to the secondary side of the transformer by a coupled inductor (i.e., DPT). In this power circuit, the amount of energy that needs to be processed by the power semiconductors and the transformer is reduced. Therefore, this configuration can provide very efficient power transmission. Another key feature of the transducer 122DD is that the input current operates in a pseudo-CCM, which effectively reduces the peak and RMS values ​​of the input current, thereby resulting in reduced conduction losses and improved efficiency. The transducer 122DD also provides galvanic isolation between the input and output, and soft switching over a wide range of operating conditions.

[0130] The converter 122DD has seven operating intervals (modes) within a single switching cycle. Figures 16B-16H show the equivalent circuits of circuit topology 122DD in different operating modes. The main waveforms of circuit topology 122DD are shown in Figure 17. To obtain the current flowing through the coupled inductor winding during each mode, the following set of equations is used to describe the relationship between the current and voltage of the coupled inductor.

number

number

number

[0131] The operating modes are described below. Before Mode 1, the input current may be zero, the power switch S1 is on, and the output diodes D1 and D4 are conducting (i.e., on).

[0132] Mode 1[t0;t1]: In t0, switch S1 is the snubber capacitor Cs1 and S s2 Due to its presence, it is turned off under ZVS conditions. Current i Ls is a capacitor C s1 Charge the capacitor C s2 The system is discharged. As a result, the voltage of S1 increases linearly, and the voltage of S2 decreases linearly to zero.

[0133] Mode 2 [t1, t2]: When the voltage of S2 becomes zero, its body diode begins to conduct. Then, under ZVS conditions, S2 turns on. As a result, v inv =-V dc / 2 and v L1 =V in Therefore, on the output side, the total current i flowing through the output bridge diode is... t (ni Ls and i L2 Since the sum of ( ) is positive, D1 and D4 are still conductive. As a result, v sec =V o and v L2 =-V o On the other hand, inductance L s The voltage is obtained as follows: vL s =v inv -nv sec (6) From equation (6), the current i in this mode is Ls The slope is,

number

[0134] According to the voltages applied to L1 and L2, i L1 as increases linearly from zero, i L2 It begins to decrease. Therefore, input diode D in It turns on under ZCS conditions. L1 and i L2 The slope can be obtained using equation (4) as follows:

number

[0135] Mode 3 [t2, t3]: The direction of the current i t reverses. When i t becomes negative, the output diodes D2 and D3 turn on under ZCS conditions. Therefore, the polarities of the voltages of the secondary winding of the transformer and the secondary winding of the coupling inductor reverse, that is, v sec =-V o and v L2 =V o . Since the switch S2 is still on, the inverter output voltage and the voltage of L1 remain the same as in the previous mode (v inv =-V dc / 2 and v L1 =V in ). Using Equation (6), the slope of i Ls during this mode is expressed as follows.

Equation

Equation

[0136] Mode 4 [t3; t4]: At t3, the switch S2 is turned off under ZVS conditions. The sum of the magnitudes of the currents i L1 and i Ls charges the capacitor C s2 and discharges the capacitor C s1 . As a result, the voltage of S2 increases linearly, and the voltage of S1 decreases linearly to zero.

[0137] Mode 5[t4;t5]: When the voltage of S1 becomes zero, its body diode begins to conduct. Then S1 turns on under ZVS conditions. As a result, v inv =V dc / 2 and v L1 =V in -V dc Therefore, on the output side, since the current it is negative, diodes D2 and D3 are still conducting. sec and v L2 This is the same as the previous mode. Similarly, the current i in this mode Ls i L1 , and i L2 The slope can be obtained as follows:

number

[0138] On the other hand, current i t The magnitude decreases linearly to zero. When the current becomes zero, D2 and D3 turn off under ZCS conditions, and this mode ends.

[0139] Mode 6[t5;t6]: When the direction of current it reverses and becomes positive, D1 and D4 turn on under ZCS conditions. As a result, v sec =V o and v L2 =-V o Therefore, v inv =V dc / 2 and v L1 =V in -V dc This is the current i in this mode. Ls i L1 , and i L2 The slope can be obtained as follows:

number

[0140] Mode 7 [t6; t7]: During this mode, the input current i L1 is zero. The voltages v inv , v sec , and v L2 are the same as in the previous mode. Also, the current i Ls continues to increase with the slope obtained from Equation (16). Since the input current is zero, Equation (4) suggests that the voltage of L1 is determined by v L2 (i.e., v L1 = (M / L2)v L2 ). The slope of i L2 is obtained as follows. m 25 = -V o / L2 (19) This mode continues until, at the beginning of the next cycle, switch S1 is turned off again.

[0141] Converter 122DD is analyzed in mathematical detail. The DC / DC conversion stage can be simplified as depicted in Figure 18. In this figure, the voltage source v inv represents a square wave where V dc / 2 and -V dc / 2 alternate when the switch is on and off (assuming a duty cycle equal to 50%). The polarity of the voltage applied to the secondary winding of the transformer depends on the direction of the total high-frequency current i t (the sum of ni Ls and i L2 ). When i t is positive, D1 and D4 conduct, and v sec = V o . Alternatively, when it is negative, v sec = -V o . Therefore, the output part is represented by a current-controlled voltage source.

[0142] As previously mentioned, in the proposed power circuit topology, the input power is transmitted to the output through two paths: 1) through the power switch and high-frequency transformer, and 2) through the coupled inductor (DPT). First, the amount of energy transmitted through the transformer is obtained. For this purpose, the current i Ls This needs to be formalized.

[0143] Since the durations of modes 1 and 4 are sufficiently short compared to the other modes, they are ignored in the analysis. According to Figure 17, and assuming t0=0, i Ls This can be expressed by four linear equations within each switching cycle, as follows:

number

number

number

[0144] The average power P transmitted to the secondary side of a high-frequency transformer tran To calculate this, the instantaneous power v over one switching cycle inv (t)·i Ls (t) is integrated.

number

Equation

Equation

[0145] Equation (33) shows that P tran reaches its maximum value at n φ = 0.25. Also, it is inversely proportional to the switching frequency. That is, the amount of power transmitted through the transformer decreases with the switching frequency.

[0146] In addition to the power transmitted through the power switch and the transformer, a part of the power is transmitted to the output through the coupling inductor. To calculate this power, the current i L2 flowing through the secondary winding of the coupling inductor needs to be obtained.

[0147] According to Figure 17, i L2 can be expressed by five linear elements within one switching cycle.

Equation

number

number

number

number

number

[0148] Equation (50) is P tran Similarly, P DPT However, this is shown to be inversely proportional to the switching frequency. As a result, as the switching frequency increases, the amount of power transmitted to the output through both paths (through the transformer and through the coupled inductor) decreases. tranand P DPT When both are determined, the total output power is, P o =P tran +P DPT (51) It can be expressed as follows, and in the formula, P tran and P DPT These are obtained in equations (33) and (50), respectively.

[0149] Another important parameter that needs to be calculated is the average input current I in Therefore, i L1 This is first formalized. According to Figure 17, i L1 This can be represented by five linear elements within a single switching cycle.

number

number

number

[0150] According to that definition, the average input current I in This can be obtained as follows:

number

number

number

[0151] Equation (66) shows that the average input current (i.e., input power) is inversely proportional to the switching frequency. This follows the fact that the output power decreases linearly with the switching frequency, as shown in equations (33) and (50).

[0152] In converter 122DD, the voltage level V dc P is the average input power. in output power P o It is determined to be equal to (transformer losses are ignored). In other words, the following equation must be satisfied. V in I in =P tran +P DPT (67) By substituting equations (33), (50), and (66) into equation (67), the voltage V is obtained as follows. dc You can obtain this.

number

[0153] According to Figure 17, t φ is a square voltage v inv and v sec This represents the phase difference between the two. Voltage v inv This depends on the switching state. However, the voltage v sec This is V as shown in Figure 18.o sgn(ni Ls +i L2 ) is equal to. According to Figure 17, at t=t2 and t=t5, i t = 0. Therefore, the following equation is valid.

number

number

number

[0154] According to Figure 17, t f is, i L1 This is the duration of mode 6, where t = T s / 2+t φ +t f This can be calculated by evaluating equation (63). That is, t f This can be obtained from the following equation.

number

[0155] From equation (72), n f However, the result is as follows.

number

[0156] The design procedure for the transducer 122DD will now be described in more detail. This procedure is based on the theoretical analysis described above. Figure 17 shows i L1 According to the waveform, (i L1 As the duration of mode 7 approaches zero (where = 0), i.e., n φ +n f As approaches 0.5, the peak value of the input current relative to a given average current decreases further, which results in a lower RMS value. In addition, transmitting the maximum possible power through a directly coupled inductor minimizes the amount of power handled by the power switch. Therefore, n φ +n f It is desirable to design the proposed converter so that the maximum possible direct power transmission is achieved when the value is close to 0.5.

[0157] To simplify the analysis, the new parameters are defined as follows: x = M / L²(74) Using this definition, equations (50), (73), and (66) can be rewritten as follows:

number

[0158] From equation (76), the parameter x is derived as follows:

number

[0159] Since x is the ratio of the two inductances (M / L2), it must be positive. According to (78), the denominator is positive. Therefore, the numerator must also be positive. This gives us the following equation:

number

[0160] This equation imposes an upper limit on the selection of the DC bus voltage. On the other hand, according to equations (75) and (77), the normalized direct power P transmitted through the coupled inductor is DPT,n This is derived as follows:

number

[0161] parameter n φ and n f The interval of variation is given by condition n φ +n f Below <0.5, 0 <n φ , n f Since it is limited to <0.5, we use equations (78) and (80) to get n φ and n f From the perspective of different values ​​of n, the normalized direct power to be transmitted may be obtained. φ , n f and P DPT,n Among all different combinations of n, φ +n f A desirable operating point can be selected that is close to 0.5 while simultaneously achieving maximum direct power transmission.

[0162]

number

number

number

number

number

[0163] parameter n φ , n f Once x and x are determined, the inductance L2 is designed using equation (85). Then, the inductances M and L1 are determined according to the values ​​of M / L2 and L1 / L2, respectively.

[0164] From equation (33), L s The ratio of / n can be written as follows:

number

number

[0165] In this section, the converter 122DD is first designed using the above guidelines for a specific application: charging a 48V battery from a 190V DC grid with a nominal power of 450W. Next, to verify the theoretical analysis, it is simulated in the OrCAD PSPICE environment provided by Cadence Design Systems in San Jose, California, USA. As mentioned above, the output power of the converter 122DD is inversely proportional to the switching frequency. Therefore, it is designed so that the minimum frequency (at nominal power) is 140kHz.

[0166] The first step in designing this converter is to select an appropriate DC bus voltage using equation (79). As mentioned above, n is close to 0.5. φ +n f It is desirable to achieve this. On the other hand, in order to ensure the DCM operation of the proposed converter, n φ +n f n should be sufficiently smaller than 0.5. φ +n f Considering this, equation (79) is, V dc This suggests that it should be less than 427.5V. Therefore, V dc The voltage is selected to be 400V.

[0167] The next step is to calculate n equal to 0.05, 0.10, 0.15, 0.20, 0.25, 0.30, and 0.35. φ For some values ​​of 0 <n f <0.5-n φ Different n within the range f From the perspective of P DPT,n As plotted in Figure 19, which shows the plot of n, equations (78) and (80) are used to express n φ and n f From the perspective of different values, the normalized direct power P transmitted DPT,n The task is to calculate n. Also, the dashed line represents n φ +n f Different n that satisfy = 0.4 φ and nf shows the curve of P from the perspective of DPT,n . According to FIG. 19, P DPT,n reaches a maximum value of 36% at n φ = 0.15 and n f = 0.25. However, when n φ = 0.1 and n f = 0.3, P DPT,n is 34%, which is close to the maximum value. This results in P DPT = 153 W and P tran = 297 W. That is, approximately 150 W is transmitted to the output through the direct - coupled inductor, and approximately 300 W is transmitted to the output through the transformer. When n φ and n f are determined, using equation (78), x equal to 2.29 is obtained.

[0168] According to equations (82) - (85), the design of inductances L1, L2, and M depends on the value of the coupling coefficient k. FIG. 20 demonstrates how this parameter affects the design of these inductances. As observed, as k approaches 1, all of the inductances L1, L2, and M tend towards large values. Therefore, when the coupling coefficient is sufficiently small, it is possible to use small inductances. According to FIG. 20, by having a coupling coefficient within the range of 0.9 < k < 0.95, appropriate values for the above - mentioned inductances are obtained. Also, achieving this range for the coupling coefficient does not complicate the implementation of the coupled inductor. Considering k = 0.93, equation (85) yields L2 = 107 μH. As a result, M and L1 are determined to be 244 μH and 647 μH respectively, based on the values of M / L2 and L1 / L2 obtained from equations (74) and (83). Using (86) and (87), the series inductance and the transformer turns ratio are obtained as L s = 43 μH and n = 2.4.

[0169] Converter 122DD is simulated using the parameters listed in Table I below.

[0170] [Table 1]

[0171] The waveforms of the converter 122DD are shown in Figures 21A to 21F. Figures 21A and 21B show the waveforms of power switches S1 and S2, respectively. As can be observed, when one switch is turned off, the body diode of the other switch turns on, thereby providing the ZVS turn-on condition. In addition, the current-voltage overlap at the turn-off moment is sufficiently small for both switches. It is also observed that the DC bus voltage is around 400V. Figure 21C shows the current i flowing through the primary and secondary windings of the coupled inductor. L1 and i L2 This demonstrates that the pseudo-CCM operation of the input current can be observed. Also, t f This is equal to 2.4 μs, which is 34% of the switching cycle. In other words, parameter n f This is slightly greater than the desired value of 0.3. The voltage waveforms of the inverter output and the primary winding of the transformer, as well as the current waveform of the series inductor, are shown in Figure 21D. As observed, the square voltage has a delay of 0.7 μs, which is approximately 10% of the switching cycle. That is, parameter n φ This is approximately equal to the desired value (0.1). Figure 21E shows the voltage waveform of the transformer secondary winding v sec and the current waveform i flowing through the output bridge diode t This shows that, as explained above, the direction of this current determines the polarity of the voltage applied to the transformer's secondary winding. According to Figure 21F, which shows the current and voltage waveforms of D1 and D2, the output diodes are turned on and off under ZCS conditions.

[0172] To actually investigate the performance of the 122DD converter, a 450W experimental prototype was implemented for the given application described above, and the experimental results are presented. The components used in the prototype are listed in Table II below, and their photographs are shown in Figure 22.

[0173] [Table 2]

[0174] Figures 23A–23F show experimental waveforms obtained from the implemented prototype under full load conditions. These experimental waveforms closely match the theoretical and simulated waveforms shown in Figures 17 and 21A–21F, respectively. To investigate the performance of the 122DD converter under different load conditions, waveforms obtained from the implemented prototype at 50% of the nominal power are also shown in Figures 24A–24F. The switching frequency was increased to 280 kHz to reduce the power delivered to the output to half of the rated power.

[0175] According to Figures 24A and 24B, which show the voltage waveforms of S1 and S2, the power switch operates with a ZVS characteristic. In addition, it is observed that the DC bus voltage is still the same as the rated power. In other words, the proposed converter benefits from a nearly constant DC bus voltage under different load conditions through pseudo-CCM operation. From Figures 24C and 24D, t f However, 1.5 μs(n) is slightly larger than that value at full load. f =0.4) and t φ However, 0.3μs(n) is equal to the desired value. φ It is observed that = 0.1). In this case, n φ +n f The duration of Mode 7 is sufficiently short, close to or equivalent to 0.5. This results in low peak and low RMS values ​​with respect to the input current. In other words, the proposed converter maintains a pseudo-CCM input current waveform under different load conditions.

[0176] Figure 25 shows the efficiency measured from the implementation prototype at 20% to 100% of the rated power. As observed, as the power decreases from full load to light load, the efficiency first increases to a peak value of 95.4% (at nominal power) to 96.7% (at 70% of nominal power), and then begins to decrease. As previously mentioned, the output power decreases with the switching frequency in the proposed converter. Consequently, the decrease in output power leads to a decrease in conduction loss but an increase in switching loss. It is worth mentioning that, due to the ZVS performance of the proposed converter, at low frequencies, the switching loss is negligible compared to the conduction loss. However, when the output power decreases to below 70% of the rated power, the switching loss becomes considerable, and as a result, the efficiency begins to decrease.

[0177] The isolated DC / DC circuit topology 122DD disclosed herein can demonstrate high performance under a wide range of operating conditions. This isolated DC / DC converter 122DD is well suited for DC microgrid applications where the converter 122DD can maintain the DC voltage level of the low-voltage bus within a desired range. The converter 122DD can minimize both conduction and switching losses. The primary-side power semiconductors of the converter 122DD operate with ZVS characteristics, and the output diodes operate with ZCS characteristics. One of the main features of the converter 122DD is DPT, which reduces the power handled by the power semiconductors and minimizes conduction losses. A portion of the power can be directly transmitted to the output, thereby reducing the power rating and cost of the components. Another advantage of this structure is the pseudo-CCM operation with respect to the input current. This feature reduces the peak and RMS values ​​of the input current. As a result, conduction losses in this structure can be significantly reduced. Simulation and experimental results of a 450W prototype support the excellent performance of the proposed structure.

[0178] Figure 26 shows the circuit configuration of the AC / DC power electronic converter 122AD in several other embodiments. As shown, the power electronic converter 122AD includes a pair of MOSFETs S1 and S2 and a first transformer 128 for converting a first portion of DC power received from the AC power supply 120A, similar to a general power conversion circuit configuration 142 (inductor L in Figure 13) shown in Figure 13. g This includes (denoted as L1 in Figure 26). The power electronic converter 122AD is coupled by a coupling inductor L2 to inductor L1 of a general power conversion circuit configuration 142 on the primary side 126, thereby directly transmitting a second portion of DC power from the primary side 126 to the secondary side 130, thereby including a DPT channel 144 that forms a second transformer 154 to bypass MOSFETs 1 and 2, as well as the first transformer 128.

[0179] Figure 27 shows the circuit configuration of the DC / DC power electronic converter 122DD in several other embodiments. As shown, the power electronic converter 122DD includes a general power conversion circuit configuration 142 which includes a pair of MOSFETs 1 and 2, a first transformer 128 for converting a first portion of DC power received from a DC power supply 120D, and a resonant tank 132 similar to that shown in Figure 11 for providing a near sinusoidal waveform and soft switching to the transformer 128 between the pair of MOSFETs 1 and 2 and the transformer 128 on the primary side. The power electronic converter 122DD includes a coupling inductor L a Therefore, the inductor L of the general power conversion circuit configuration 142 on the primary side 126 g It also includes a DPT channel 144 that is coupled to the MOSFETs 1 and 2, thereby directly transmitting a second portion of the DC power from the primary side 126 to the secondary side 130, and thereby forming a second transformer 154 for bypassing the first transformer 128.

[0180] Figure 28 shows the circuit configuration of the DC / DC power electronic converter 122DD in yet another embodiment. The DC / DC power electronic converter 122DD in this embodiment is similar to that shown in Figure 27, except that in this embodiment the general power conversion circuit configuration 142 does not include a resonant tank, while the DPT channel 144 includes a resonant tank 132.

[0181] Figure 29 shows the circuit configuration of the DC / DC power electronic converter 122DD in another example. The DC / DC power electronic converter 122DD in this embodiment is similar to that shown in Figure 27, except that in this embodiment, each of the DPT channel 144 and the general power conversion circuit configuration 142 includes a resonant tank 132.

[0182] The resonant tank 132 can also be used in other types of transducers that use DPT.

[0183] For example, Figure 30 shows the circuit configuration of an AC / DC power electronic converter 122AD in one embodiment. In this embodiment, the AC / DC power electronic converter 122AD is similar to that shown in Figure 26, except that the DPT channel 144 does not include a resonant tank, while the general power conversion circuit configuration 142 includes a resonant tank 132.

[0184] Figure 31 shows the circuit configuration of the AC / DC power electronic converter 122AD in another embodiment. In this embodiment, the AC / DC power electronic converter 122AD is similar to that shown in Figure 26, except that the general power conversion circuit configuration 142 does not include a resonant tank, while the DPT channel 144 includes a resonant tank 132.

[0185] Figure 32 shows the circuit configuration of the AC / DC power electronic converter 122AD in yet another embodiment. In this embodiment, the AC / DC power electronic converter 122AD is similar to that shown in Figure 26, except that each of the general power conversion circuit configurations 142 and DPT channels 144 includes a resonant tank 132.

[0186] The DPT channel can be implemented in any suitable manner. For example, Figure 33 shows a DC / DC power electronic converter 122DD having a DPT channel 144 according to several embodiments of the present disclosure. In these embodiments, the transformer 128 of a general power conversion circuit configuration 142 and the transformer 154 of the DPT channel 144 share a common and / or integrated magnetic element structure 162. Specifically, the coils of transformers 128 and 154 are wound separately on a common magnetic core or a ferromagnetic core, thereby resulting in high power density.

[0187] Figure 34 shows a DC / DC power electronic converter 122DD having a DPT channel 144 according to several embodiments of the present disclosure. In these embodiments, the transformer 128 of a general power conversion circuit configuration 142 and the transformer 154 of the DPT channel 144 share a common and / or integrated magnetic element structure 164. Specifically, the DC / DC power electronic converter 122DD uses a center-tapped transformer 164 to implement the transformers 128 and 154 such that the transformers 128 and 154 share the same coil wound around a magnetic or ferromagnetic core, and these coils have three contacts, including two end contacts at both ends of the coil and an intermediate contact at a suitable location in the coil midway between the ends of the coil. In the example shown in Figure 34, the end contacts 172 and 174 are used for power output, and the intermediate contact 176 is connected to ground.

[0188] In the above embodiment, the power electronic converter 122 includes one DPT channel 144 electrically coupled in parallel to a typical power conversion circuit configuration 142. In some alternative embodiments, such as those shown in Figure 35, the power electronic converter 122 may include multiple DPT channels 144 electrically coupled in parallel to the typical power conversion circuit configuration 142. In some embodiments, the multiple DPT channels 144 may have the same structure, topology, components, and / or parameters. In some other embodiments, the multiple DPT channels 144 may have different structures, topologies, components, and / or parameters.

[0189] For example, Figure 36 shows the circuit configuration of a DC / DC power electronic converter 122DD in one embodiment. As shown, the power electronic converter 122DD includes a general power conversion circuit configuration 142 similar to that shown in Figure 12, using a pair of MOSFETs 1 and 2, and a first transformer 128 for converting a first portion of the DC power received from a DC power supply 120D. The DC / DC power electronic converter 122DD also includes two DPT channels 144-1 and 144-2, respectively, which transmit a second and third portion of the received DC power directly from the primary side 126 to the secondary side 130, and thereby are coupled to the general power conversion circuit configuration 142 on the primary side 126 by second transformers 154-1 and 154-2 for bypassing the MOSFETs 1 and 2, and the first transformer 128.

[0190] In some embodiments, the first transformer 128 of a typical power conversion circuit configuration 142 and one or more second transformers 154 of the DPT channel 144 (e.g., the second transformers 154-1, 154-2 shown in Figure 36) may share a common and / or integrated magnetic element structure, such as sharing a common core, and each second transformer 154 includes a separate set of coils wound around the common core (e.g., separate wires wound around the common core form the coil set).

[0191] In some embodiments, the first transformer 128 of a typical power conversion circuit configuration 142 and one or more second transformers 154 of the DPT channel 144 (e.g., the second transformers 154-1, 154-2 shown in Figure 36) may be implemented using center-tapped transformers having a single coil set (e.g., one wire wound around a core forms a single coil set), and each second transformer 154 includes a coil set corresponding to each part of the single coil set (e.g., each part of the wire wound around the core).

[0192] In the above embodiment, the power electronic converter 122 has only one output. In some alternative embodiments, such as those shown in Figure 37, the power electronic converter 122 may be a multi-output power electronic converter having multiple outputs 160 for supplying power to multiple loads 124.

[0193] The multi-output power electronic converter 122 may include a general power circuit configuration 142 having multiple outputs 162 and multiple DPT channels 144 electrically coupled in parallel to the general power conversion circuit configuration 142. Specifically, at least one or more of the outputs 162 of the general power circuit configuration 142 are electrically coupled to one or more of the multiple DPT channels 144, thereby forming each output of the multi-output power electronic converter 122 for supplying power to each load 124.

[0194] In some embodiments, at least one output 162 of a typical power circuit configuration 142 is not electrically coupled to any DPT channel 144 and directly forms the output 160 of the multi-output power electronic converter 122.

[0195] In some embodiments, all outputs 162 of a typical power circuit configuration 142 are electrically coupled to a DPT channel 144 to form the output 160 of a multi-output power electronic converter 122.

[0196] In some embodiments, the multiple DPT channels 144 may have the same structure, topology, components, and / or parameters. In some other embodiments, the multiple DPT channels 144 may have different structures, topologies, components, and / or parameters.

[0197] For example, Figure 38 shows the circuit configuration of a multi-output DC / DC power electronic converter 122DD in one embodiment. As shown, the power electronic converter 122DD includes a general power conversion circuit configuration 142 using a pair of MOSFETs S1 and S2 and a first transformer 128 for converting a first portion of the DC power received from a DC power supply 120D. The first transformer 128 includes an input coil set 164 and two output coil sets 166 wound around a common core 168. Each of the output coil sets 166 forms an output 162 of the general power circuit configuration 142.

[0198] The multi-output DC / DC power electronic converter 122DD transmits the second and third portions of the DC power received directly from the primary side 126 to the secondary side 130, respectively, and also includes two DPT channels 144 coupled to the general power conversion circuit configuration 142 of the primary side 126 by MOSFETs 1 and

[0199] Specifically, the multi-output DC / DC power electronic converter 122DD includes a coupled transformer 170 having an input coil set 172 electrically connected to the primary side 126 of a typical power circuit configuration 142, and two output coil sets 174 all wound around a common core 176. Each output coil set 174 is electrically coupled to a DPT channel 144. Thus, each output coil set 174, the common core 176, and the input coil set 172 form each second transformer 154.

[0200] On the secondary side, each DPT channel 144 is electrically coupled in parallel with the output 162 of a typical power circuit configuration 142 to form each output 160 of the multi-output DC / DC power electronic converter 122DD.

[0201] In some embodiments, either or both of the coupling transformer 170 and the first transformer 128 may be center-tapped transformers.

[0202] While embodiments have been described above with reference to the attached drawings, those skilled in the art will understand that modifications and alterations can be made without departing from the scope defined by the attached claims.

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Claims

1. A first conductive or semiconductive metasurface layer, A second metasurface layer that is conductive or semiconductive, A dielectric layer is sandwiched between the first metasurface layer and the second metasurface layer to electrically insulate the first metasurface layer from the second metasurface layer, Includes, The first meta-surface layer comprises a plurality of nanoscale or microscale first structures, each of which comprises a plurality of first rods extending from a base portion, and each first rod having a first recess at its distal end. The distal end portion of each first rod is defined as the first portion, and the base end portion of each first rod is defined as the second portion. The second meta-surface layer comprises a plurality of nanoscale or microscale second structures, each of which comprises a plurality of second rods extending from the base portion, and each second rod having a second recess at its distal end. The distal end portion of each second rod is defined as the first portion, and the base end portion of each second rod is defined as the second portion. An electrical energy storage device for storing electrical energy for use as a power source, wherein at least the first portion of the second rod is housed in the first recess of the corresponding first portion of the first rod without electrical contact with the first recess.

2. The electrical energy storage device according to claim 1, wherein the second portion of the first rod is arranged alternately with the second portion of the second rod.

3. The electrical energy storage device according to claim 1 or 2, wherein at least a first set of the first structure and the second structure has a circular, elliptical, or rectangular cross-section.

4. The electrical energy storage device according to any one of claims 1 to 3, wherein one or more dimensions of the first structure and the second structure are within the nanometer range or the micrometer range.

5. The electrical energy storage device according to claim 4, wherein the thickness of the first structure and the second structure is within the nanometer range or the micrometer range.

6. A first electrode bonded to the first meta-surface layer, and The second electrode bonded to the second meta-surface layer The electrical energy according to any one of claims 1 to 5 further includes at least one of the above. Treasury device.

7. An electrical energy storage device according to any one of claims 1 to 5, wherein at least one of the first metasurface layer and the second metasurface layer includes a conductive base for forming electrodes.

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