Accelerator state control device, accelerator state control method, and program

Abstract

To achieve high power efficiency of various accelerators for varying amount of input data, while securing responsiveness.SOLUTION: An accelerator state control device 100 includes: an input amount acquisition / prediction unit 110 that predicts amount of processing to be offloaded to an accelerator 12 and outputs a prediction result as a traffic and a variation range of the traffic; a computing power setup recording unit 150 that maintains information on a type and a model of the accelerator and setup information tailored to performance, as list information, and retrieves information from the list information in response to an inquiry and responds to the inquiry; an ACC computing power / power consumption setup determination unit 120 that determines setup information on computing power and varying time of the accelerator, based on the traffic and the variation range as well as the list information; and an ACC computing power / power consumption setting unit 130 that applies the setup information to the accelerator 12, based on the setup information for the accelerator 12 determined by the ACC computing power / power consumption setup determination unit 120.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an accelerator state control device ,a an accelerator state control method and a program.

Background Art

[0002] Depending on the type of processor, the workload that the processor is good at (has high processing power) is different. For a highly versatile CPU (Central Processing Unit), there are accelerators such as FPGA (Field Programmable Gate Array) / (in the following description, " / " represents "or") GPU (Graphics Processing Unit) / ASIC (Application Specific Integrated Circuit) that can perform operations on a workload with a high degree of parallelism that the CPU is not good at (has low processing power) quickly and efficiently. By combining these different types of processors and offloading the workload that the CPU is not good at to the ACC for operation, the utilization of offloading technology to improve the overall operation time and operation efficiency has been progressing.

[0003] In vRAN (virtual Radio Access Network) and the like, when the performance of only the CPU is insufficient to meet the requirements, some processing is offloaded to a high-speed computing accelerator such as an FPGA or a GPU. Specific workloads for which ACC offloading is performed include, as representative examples, encoding / decoding processing (FEC: Forward Error Correction processing) in vRAN, media processing of audio and video, encryption / decryption processing, and the like.

[0004] In computer systems, a configuration is sometimes adopted in which a computer (hereinafter referred to as an accelerator-equipped server) is equipped with hardware (CPU) that supports general-purpose processing and hardware (accelerator) specialized for specific calculations, and some calculation processing is offloaded from the general-purpose processor on which the software runs to the accelerator.

[0005] Furthermore, with the advancement of cloud computing, it is becoming increasingly common to simplify the configuration of client machines by offloading some computationally intensive processing tasks from client machines deployed at user sites to servers at remote sites (such as data centers located near the user) via the network (NW).

[0006] Figure 17 is a diagram illustrating the computer system. As shown in Figure 17, the server 50 is equipped with a CPU 11, an accelerator 12 having an accelerator arithmetic circuit and program 12a, an input / output unit 13, and a cooling mechanism (fan, etc.) 14 on the hardware 10, and includes a software application (hereinafter referred to as APL) 1 of software 20 that runs on the CPU 11 on the server 50. Although the cooling mechanism (fan, etc.) 14 is shown as being mounted on the hardware 10 in Figure 17, it may be mounted on hardware other than the hardware 10.

[0007] Server 50 receives input data from an external source, performs calculations internally, and then outputs the data to the outside.

[0008] Application 1 calls a set of functions (APIs) defined as a standard, and offloads some of the processing to accelerator 12.

[0009] Accelerator 12 is a computing accelerator device such as an FPGA / GPU. Accelerator 12 has an accelerator arithmetic circuit and program 12a, and performs calculations using the accelerator arithmetic circuit and program 12a. Furthermore, accelerator 12 may fail with a certain probability due to cooling fan failure or other reasons. The input / output unit 13 receives and outputs input data.

[0010] Figure 18 illustrates the fluctuations in the amount of input data traffic to the input / output unit 13 of the server 50. As shown in Figure 18, the amount of input data traffic fluctuates over time. For example, urban traffic in a RAN (Radio Access Network) is high during the day and low at night.

[0011] The requirements for minimizing the power consumption of the accelerator 12 and its cooling while maintaining responsiveness to input data within a certain time frame in server 50 are as follows: Requirement 1: [Power efficiency] The power consumption required for the calculations and cooling of the accelerator 12 should be minimized in relation to the input data of the server 50.

[0012] Requirement 2: [Responsiveness] The input data must be processed by server 50 within a certain time period after input.

[0013] Requirement 3: [Support for various accelerators] It must be compatible with various accelerators such as FPGAs, ASICs, and GPUs.

[0014] Figure 19 shows the server's processing capacity and surplus under fluctuations in the input data traffic. The solid line in Figure 19 represents the input data traffic, and the dashed line represents the server's processing capacity (≒power consumption). As shown by the dashed line in Figure 19, the server's processing capacity and power consumption are constant. Therefore, as shown by the solid line in Figure 19, a surplus occurs in relation to the server's processing capacity due to traffic fluctuations. In particular, at night, the traffic volume is low, and the server's processing capacity (≒power consumption) becomes excessive, resulting in power inefficiency.

[0015] In accelerator-equipped servers, there are conventional technologies that achieve high responsiveness and power efficiency for a given processing load, depending on the type of accelerator.

[0016] Existing technology 1: Power-saving circuit design technology tailored to specific traffic levels. Non-patent document 1 describes a technique for minimizing ACC power consumption in FPGA / ASIC circuit design by optimizing the minimum necessary circuit size for each specific processing load and model.

[0017] Existing technology 2: Changing the balance between processing power and power consumption by changing the clock frequency. Non-patent document 2 describes a technique for changing the balance between processing performance and power consumption by changing the operating frequency (which remains constant after being set).

[0018] Existing Technology 3: Output settings of the cooling mechanism required for stable accelerator operation Non-patent document 3 describes a configuration in which the fan is always operated at maximum output in order to ensure stable operation regardless of the operating circuit information. [Prior art documents] [Non-patent literature]

[0019] [Non-Patent Document 1] “Power-aware FPGA Design White Paper”, [online], [Accessed July 6, 2022], Internet <URL: https: / / www.microsemi.com / document-portal / doc_download / 131579-power-aware-fpga-design-white-paper> [Non-Patent Document 2] "Guide to FPGA Frequency Setting Change Command (Intel OPAE Tool kit)", [online], [searched on July 6, 2022], Internet <URL:https: / / opae.github.io / latest / docs / fpga_tools / userclk / userclk.html>

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0020] The existing technologies described in Non-Patent Documents 1 to 3 can achieve a configuration with high responsiveness and high power efficiency by preparing and setting the configuration corresponding to a certain amount of processing capacity for each accelerator. However, when the input amount varies over time, surplus processing capacity and power consumption occur, and there is a problem that it is impossible to simultaneously satisfy Requirement 1: [Power Efficiency], Requirement 2: [Responsiveness], and Requirement 3: [Correspondence to Various Accelerators] for the fluctuating traffic.

[0021] In view of such a background, the present invention has been made, and an object of the present invention is to realize high power efficiency of various accelerators while ensuring responsiveness according to the fluctuating input data amount.

Means for Solving the Problems

[0022] In order to solve the above-described problems, the present invention is an accelerator state control device that controls the state of an accelerator when offloading specific processing of an application to the accelerator for arithmetic processing, predicts the amount of processing to be offloaded to the accelerator, and the prediction result It is assumed that... Variation range and predicted processing volume A prediction unit that outputs as, Refer to the list of information regarding the settings of the aforementioned accelerator. Processing capacity setting recording unit, The predicted processing volume and, Based on the above list information, the accelerator Whether or not a setting change is necessary. A determination unit that makes a determination, and the determination unit When it is determined that a change in the settings of the aforementioned accelerator is necessary Based on the setting information for the accelerator, the accelerator Configure the settings The accelerator state control device is characterized by comprising a setting input unit. [Effects of the Invention]

[0023] According to the present invention, it is possible to achieve high power efficiency for various accelerators while ensuring responsiveness in response to fluctuating input data volumes. [Brief explanation of the drawing]

[0024] [Figure 1] This is a schematic diagram of an accelerator state control system according to an embodiment of the present invention. [Figure 2] This is a schematic diagram showing variations in the arrangement of the accelerator state control device in the accelerator state control system according to an embodiment of the present invention. [Figure 3] This figure illustrates a list of power reduction methods for the accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 4] This figure shows an example of processing capacity-specific circuit information held by the processing capacity-specific ACC circuit information recording unit of the accelerator state control system according to an embodiment of the present invention. [Figure 5] This figure shows a processing performance calculation table based on the amount of traffic held by the ACC circuit information recording unit for each processing capacity of the accelerator state control system according to an embodiment of the present invention. [Figure 6] This figure shows the accelerator mounting relationship management table held by the processing capacity-based ACC circuit information recording unit of the accelerator state control system according to an embodiment of the present invention. [Figure 7]This figure shows the accelerator list management table held by the processing capacity-based ACC circuit information recording unit of the accelerator state control system according to an embodiment of the present invention. [Figure 8] This figure shows the accelerator type management table held by the processing capacity-based ACC circuit information recording unit of the accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 9] This flowchart shows the <operation sequence 1> when the power saving control of the accelerator state control device of the accelerator state control system according to an embodiment of the present invention starts with the prediction of the input amount of function 1. [Figure 10] This flowchart shows the operation sequence 2 when the power saving control of the accelerator state control device of the accelerator state control system according to an embodiment of the present invention starts with periodic execution. [Figure 11] This figure shows details of a list of power reduction methods for the accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 12A] This flowchart shows an example of a setting sequence for a power reduction method of the accelerator state control device of an accelerator state control system according to an embodiment of the present invention. [Figure 12B] This flowchart shows an example of a setting sequence for a power reduction method of the accelerator state control device of an accelerator state control system according to an embodiment of the present invention. [Figure 12C] This flowchart shows an example of a setting sequence for a power reduction method of the accelerator state control device of an accelerator state control system according to an embodiment of the present invention. [Figure 13] This flowchart shows the operation sequence 1 of the Look-Aside type accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 14] This flowchart shows the operation sequence 1 of the inline type accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 15] This figure illustrates the processing capacity, power consumption, and surplus realized by the accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 16] This is a hardware configuration diagram showing an example of a computer that implements the functions of the accelerator state control device of the accelerator state control system according to an embodiment of the present invention. [Figure 17] This is a diagram illustrating a computer system. [Figure 18] This diagram illustrates the fluctuations in the amount of input data traffic to the server's input / output section. [Figure 19] This figure shows the server's processing capacity and surplus in response to fluctuations in the input data traffic volume. [Modes for carrying out the invention]

[0025] The accelerator state control system and the like in an embodiment of the present invention (hereinafter referred to as "this embodiment") will be described below with reference to the drawings. (Embodiment) [overview] Figure 1 is a schematic diagram of the accelerator state control system according to an embodiment of the present invention. As shown in Figure 1, the accelerator state control system 1000 comprises a server 200, an antenna device 210, and a downstream processing unit 220. Furthermore, the accelerator state control system 1000 includes an accelerator state control device 100 that controls the state of the accelerator 12 when offloading specific processing of application 1 to the accelerator 12 for computation, and a cooling mechanism 14 that cools the computing unit including the accelerator 12.

[0026] [Server 200] Server 200 is a Distributed Unit in 5G signal processing. Server 200 comprises hardware (HW) 10 and software 20.

[0027] Hardware 10 The hardware 10 includes a CPU (Central Processing Unit) 11, an accelerator 12, an input / output unit 13, and a cooling mechanism (fan, etc.) 14.

[0028] <cpu11> CPU 11 executes the processing of application 1 and also runs the software for each functional unit on server 200.

[0029] <Accelerator 12> Accelerator 12 is a computing accelerator device such as an FPGA / GPU. Accelerator 12 is a computing unit installed in server 200 that is specialized for specific processing. It can be connected to CPU 11 via a bus in various forms, including ASIC-based accelerators, FPGA-based accelerators, and GPUs.

[0030] The data processed by the accelerator 12 may be in a Look-Aside format (Sequence 2-1: Figure 13) input from the CPU 11, or in an In-Line format (Sequence 2-2: Figure 14) input directly from an I / O unit 13 such as a NIC. The signal line indicated by the arrow from the CPU 11 to the accelerator 12 in Figure 1 exists in the Look-Aside type ACC offload configuration shown in (Sequence 2-1: Figure 13). Also, the bidirectional signal line connecting the I / O unit 13 and the accelerator 12 in Figure 1 exists in the In-Line type ACC offload configuration shown in (Sequence 2-2: Figure 14).

[0031] The accelerator 12 has an accelerator arithmetic circuit / program 12a. The accelerator arithmetic circuit / program 12a is the circuit or program loaded into the accelerator 12. If the accelerator 12 is an FPGA, the accelerator arithmetic circuit / program 12a refers to FPGA circuit information, and if the accelerator 12 is a GPU, it refers to a program for the GPU. Furthermore, the accelerator 12 may fail with a certain probability due to a malfunction of the cooling mechanism (fan, etc.) 14.

[0032] <Input / output section 13> The input / output unit 13 is an input / output mechanism such as a NIC (Network Interface Card) and performs data input / output with external devices (antenna device 210 and downstream processing unit 220). The input / output unit 13 also has an interface that notifies application 1 of the current amount of data input.

[0033] <Cooling mechanism 14> The cooling mechanism 14 is a mechanism that cools all of the server 200's computing units (CPU 11 and accelerator 12). The cooling performance of the cooling mechanism 14 can be changed, and the power consumption changes accordingly. The cooling mechanism 14 accepts a setting for the cooling performance as input.

[0034] The cooling mechanism 14 is a mechanism that cools the entire server, including the CPU and accelerator, as a whole, but it may also be an independent cooling mechanism that cools only the CPU or only the accelerator.

[0035] Software 20 The software 20 includes an application 1 and an accelerator state control device 100 that controls the state of the accelerator.

[0036] <Application 1> Application 1 is a program that performs signal processing and runs on CPU 11. Specialized processing that is not suitable for the CPU, such as some parallel processing, is offloaded to accelerator 12. For example, Application 1 calls a set of standardized functions (APIs) to offload some processing to accelerator 12. In this case, if the accelerator becomes temporarily unavailable when the accelerator settings are changed, the ACC switching processing continuation unit 160 is offloaded.

[0037] Application 1 receives data to be processed from the input / output unit 13 as input. It passes the calculated data to the input / output unit 13 as output.

[0038] [Accelerator state control device 100] The accelerator state control device 100 includes an input quantity acquisition / prediction unit 110 (prediction unit, prediction procedure), an ACC processing capacity / power consumption setting determination unit 120 (determination unit, determination procedure), an ACC processing capacity / power consumption setting input unit 130 (setting input unit, setting input procedure), an ACC circuit information recording unit 140 by processing capacity, an ACC information / processing capacity setting recording unit 150 (processing capacity setting recording unit, processing capacity setting recording procedure), and an ACC switching processing continuation unit 160 (processing continuation unit).

[0039] <Input quantity acquisition / prediction unit 110> The input volume acquisition and prediction unit 110 predicts the amount of processing to be offloaded to the accelerator and outputs the prediction result as traffic volume and its fluctuation range. In this embodiment, one method for predicting (estimating) the amount of processing to be offloaded to the accelerator is to predict fluctuations in the amount of input data. Any method that can predict (estimate) the amount of processing to be offloaded to the accelerator is acceptable.

[0040] The input quantity acquisition and prediction unit 110 predicts fluctuations in the input data quantity based on the acquired input data quantity and outputs the prediction result as traffic quantity and its fluctuation range. Specifically, the input quantity acquisition and prediction unit 110 acquires the input data quantity from the server and predicts subsequent fluctuations in the input data quantity. The input quantity acquisition and prediction unit 110 accepts the input data quantity from the server as input and outputs, as a prediction result of future data quantity, the traffic quantity after a certain period of time has elapsed and the unit of fluctuation time.

[0041] • Example of a predictive function 1 It is conceivable to predict future changes based on past changes in traffic volume. For example, based on the last five traffic volumes obtained at regular intervals, it is possible to determine whether the traffic volume is on an increasing trend. The five traffic volumes are linearly approximated, and if the resulting slope is above a certain level, it is considered an increase; if it is below a certain level, it is considered a decrease, and the traffic volume after a certain period of time is predicted. Furthermore, the unit of time of variation is output based on the variance of each traffic volume. Specifically, if the variance is large, it is assumed that the traffic fluctuation is on the order of "seconds," and if the variance is small, it is output that it is on the order of "minutes."

[0042] • Example 2 of the predictive function Alternatively, the traffic volume of the device in question for each day of the week and time of day may be recorded, and traffic predictions may be made based on this data. For example, in the case of mobile phone wireless access networks, the temporal changes in traffic volume differ from location to location. For example, urban areas have high traffic volume during the day but low traffic volume at night. Also, areas along railway lines have extremely low traffic volume outside of train operating hours. These results may be used to predict hourly traffic volume. Note that when using the method in Example 2 of this prediction function, the unit of time for traffic volume fluctuations is long, in units of "minutes or hours".

[0043] In predicting traffic volume, other factors that determine the traffic volume of the server device in question may be used. For example, in a mobile phone wireless access network, the traffic volume of a device connected to an antenna device near a densely populated outdoor area fluctuates depending on the weather, as the number of people in the area changes accordingly. In such use cases, the fluctuation in traffic volume may be predicted based on weather forecasts. However, when using this method, the unit of time for the fluctuation in traffic volume will be long, in the order of minutes or hours.

[0044] • About the input data size prediction function In addition to the form of estimating from the time zone, the input data size prediction function may also be configured to estimate from other factors. For example, it may use, as an information source, the fluctuations in traffic volume due to weather or events, which are available in the RIC (RAN Intelligent Controller) in the RAN (Radio Access Network).

[0045] · Example of fluctuations in the input data volume over time In vRAN, the amount of input data to the server depends on the number of mobile phone terminals and the traffic volume in the area served by that server. The number of mobile phone terminals and the traffic volume depend on human movement. The time zones and areas where people gather have an increased traffic volume, while the time zones and areas where people do not gather have a decreased traffic volume. For example, in the office streets in the city center, the traffic volume during weekdays is large, while the traffic volume at night and on holidays is small. Also, in the residential areas in the suburbs, the traffic volume on holidays is larger than that during weekdays.

[0046] <ACC processing capacity and power consumption setting determination unit 120> Based on the traffic volume and the fluctuation range output from the input volume acquisition and prediction unit 110, and the list information (Figure 3) read from the ACC information and processing capacity setting recording unit 150, the ACC processing capacity and power consumption setting determination unit 120 determines the setting of the accelerator's processing capacity and the fluctuation time.

[0047] Specifically, the ACC processing capacity and power consumption setting determination unit 120 determines the setting of the accelerator's processing capacity and the fluctuation time according to the prediction result of the traffic volume output from the input volume acquisition and prediction unit 110 and the assumed fluctuation range. The ACC processing capacity and power consumption setting determination unit 120 inputs the traffic volume into the ACC information and processing capacity setting recording unit 150 and obtains the list information (Figure 3) of applicable accelerators and settings. From this list information of settings, it selects the settings of the accelerator and the settings of the cooling mechanism 14 that match the processing capacity and the fluctuation time, and notifies the ACC processing capacity and power consumption setting input unit 130. The ACC processing capacity and power consumption setting determination unit 120 receives, as input, the prediction and variation range of the traffic volume from the input amount acquisition and prediction unit 110. The ACC processing capacity and power consumption setting determination unit 120 passes the ACC setting information to the ACC processing capacity and power consumption setting input unit 130 as output.

[0048] <ACC processing capacity and power consumption setting input unit 130> The ACC processing capacity and power consumption setting input unit 130 reflects the setting information on the accelerator 12 based on the setting information on the accelerator 12 determined by the ACC processing capacity and power consumption setting determination unit 120. Specifically, the ACC processing capacity and power consumption setting input unit 130 reflects the input setting to the accelerator 12 and the setting to the cooling mechanism 14 on the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity and power consumption setting input unit 130 receives, as input, the setting to the accelerator 12 and the setting information to the cooling mechanism 14 from the ACC processing capacity and power consumption setting determination unit 120. The ACC processing capacity and power consumption setting input unit 130 reflects the setting information on the accelerator 12 and the cooling mechanism 14, respectively, as output.

[0049] Also, the ACC processing capacity and power consumption setting input unit 130 reflects the setting information in a common manner for the accelerators by changing the frequency and / or turning off the power supply. In the case of an FPGA, the setting information is reflected by rewriting the circuit, and in the case of a GPU, the setting information is reflected by going to sleep.

[0050] <ACC circuit information recording unit 140 by processing capacity> The ACC circuit information recording unit 140 by processing capacity holds the FPGA circuit information and the information on the FPGA type corresponding to the processing performance for each FPGA type, and responds with the FPGA circuit information and the information on the FPGA type in response to an inquiry. In this case, the ACC circuit information recording unit 140 by processing capacity responds to the ACC processing capacity and power consumption setting determination unit 120 via the ACC information and processing capacity setting recording unit 150 or directly.

[0051] The ACC circuit information recording unit 140 by processing capacity holds a plurality of FPGA circuit information corresponding to the processing performance for each FPGA type, and pays out the FPGA circuit information in response to an inquiry. This inquiry includes information on the FPGA type (Fig. 4). The ACC circuit information recording unit 140 by processing capacity receives information on the FPGA model from the ACC information and processing capacity setting recording unit 150 as an input. The ACC circuit information recording unit 140 by processing capacity responds with a plurality of FPGA circuit information to the ACC information and processing capacity setting recording unit 150 as an output.

[0052] The ACC circuit information recording unit 140 by processing capacity may also be configured to include "required processing performance" in the above inquiry and respond with only one optimal FPGA circuit information based on this information. Regarding the response of the FPGA circuit information, instead of the actual data of the FPGA circuit information itself, it may be an identifier that can uniquely identify circuit information such as a file path pointer required for access.

[0053] <ACC information and processing capacity setting recording unit 150> The ACC information and processing capacity setting recording unit 150 holds information on the accelerator type and model and setting information corresponding to the processing performance as list information 170 (Fig. 3), and extracts and responds from the list information 170 in response to an inquiry. Here, the above accelerator type and model information is information on the accelerator held by the host on which the accelerator can be mounted for use.

[0054] The ACC information and processing capacity setting recording unit 150 receives the accelerator type, model, and application name from the ACC processing capacity and power consumption setting judgment unit 120 as an input. The ACC information and processing capacity setting recording unit 150 responds with a list of applicable setting means for the corresponding accelerator to the ACC processing capacity and power consumption setting judgment unit 120 as an output. Also, when the input accelerator type is FPGA, the ACC information and processing capacity setting recording unit 150 makes an inquiry to the ACC circuit information recording unit 140 by processing capacity based on the model information and obtains a list of the corresponding compatible FPGA circuit information.

[0055] <ACC Switching Processing Continuance Unit 160> When the ACC switching processing continuance unit 160 temporarily stops the arithmetic function of the accelerator 12 in accordance with the input of setting information by the ACC processing capability and power consumption setting input unit 130, in order to continue the service, the CPU 11 or another accelerator temporarily continues the processing. It is activated when the arithmetic operation in the corresponding accelerator 12 temporarily stops during the setting change of the accelerator 12. When the ACC switching processing continuance unit 160 is activated, the arithmetic offloading from the application 1 is received by this functional unit and calculated using the arithmetic resources other than the setting change target.

[0056] In addition to the continued arithmetic operation by the CPU, it may also be in a form where another accelerator is temporarily used to continue the arithmetic operation.

[0057] [Antenna Device 210] The antenna device 210 is an antenna and a transceiver for wireless communication with a terminal (UE: User Equipment) (hereinafter, the "antenna device" is collectively referred to as the antenna, the transceiver, and its power supply unit). The transmitted and received data is connected to the signal processing device (server 200) of the base station (BBU: Base Band Unit) by, for example, a dedicated cable.

[0058] The antenna device 210 includes an antenna device data input / output unit 211. The antenna device data input / output unit 211 is a functional unit that sends the signal generated by the antenna device 210 to the server 200 and is realized in the form of a NIC or the like.

[0059] [Subsequent Processing Device 220] The subsequent processing device 220 is a Centralized Unit in 5G signal processing. The subsequent processing device 220 includes a subsequent processing device data input / output unit 221. The subsequent processing device data input / output unit 221 is a functional unit that receives the signal processing result processed by the server 200 and is realized in the form of a NIC or the like.

[0060] <Other Embodiments> In this embodiment, the input / output unit 13, CPU 11, and accelerator 12 are configured as separate hardware components, but the CPU 11, accelerator 12, and accelerator arithmetic circuit / program 12a may also be integrated into a single dedicated hardware component. In other words, as shown in Figure 1, in addition to the so-called Look-Aside type accelerator application, in which "data obtained via the input / output unit 13 such as a NIC is explicitly offloaded from the CPU 11 to the accelerator 12," the so-called In-line type accelerator application is also acceptable, in which "the NIC, accelerator, and CPU are integrated into a single piece of hardware, and processing is completed within the same hardware after data is received by the NIC." Furthermore, the CPU 11 and accelerator 12 may be mounted on a single chip, such as in a System on Chip (SoC) configuration.

[0061] [Placement of accelerator state control device] This section describes variations in the arrangement of the accelerator state control device in the accelerator state control system. The accelerator state control system 1000 in Figure 1 is an example in which the accelerator state control device 100 is located in the software 20 of the server 200. The accelerator state control device 100 can also have some of its functions installed in a separate enclosure outside the server 200, as illustrated below.

[0062] Figure 2 is a schematic diagram showing variations in the arrangement of the accelerator state control device in the accelerator state control system. In the following figures, the same reference numerals are used for components identical to those in Figure 1, and the explanation of the duplicated parts is omitted. The variation shown in Figure 2 is an example where the controller function unit, consisting of the input quantity acquisition / prediction unit 110, the ACC processing capacity / power consumption setting determination unit 120, the processing capacity-specific ACC circuit information recording unit 140, and the ACC information / processing capacity setting recording unit 150, is housed in a separate enclosure. As shown in Figure 2, the accelerator state control system 1000A includes an accelerator state control device 100A installed in a separate enclosure outside the server 200. The software 20 of the server 200 includes application 1, ACC processing capacity / power consumption setting input unit 130, and ACC switching processing continuation unit 160. The accelerator state control device 100A has the controller function unit installed outside the server 200 and has the same functions as the accelerator state control device 100 in Figure 1.

[0063] As shown in Figure 2, by deploying some or all of the functions of the accelerator state control device independently in a separate enclosure outside the server 200, it is possible to support the deployment of functions to the RIC (RAN Intelligent Controller) in the RAN (Radio Access Network).

[0064] Furthermore, by placing the controller function unit externally, it is possible to predict the input volume based on the input volume acquisition from multiple server machines (function 1), which has the advantage of improving the accuracy of traffic prediction for function 1. For example, in a mobile phone wireless system, if the traffic volume in a processing area handled by a certain server machine increases, it is assumed that the input volume in nearby processing areas will also fluctuate with a delay.

[0065] Furthermore, it becomes possible to operate multiple servers 200 with a single accelerator state control device. This reduces costs and improves the maintainability of the accelerator state control device. In addition, modifications to the server side can be eliminated or reduced, making it applicable to a wide range of applications.

[0066] [Accelerator data structure] This section describes a list of power reduction methods and their characteristics. Figure 3 is a diagram illustrating a list of power reduction methods. As shown in Figure 3, power reduction methods are classified into 1. circuit size modification, 2. clock control, 3. power supply control, and 4. others. For each of these four classifications, the power reduction method, ACC processing capacity, power consumption reduction amount (difference from maximum configuration), transition / recovery time, applicability by ACC, and remarks are defined. Applicability by ACC is divided into FPGA, GPU, and ASIC.

[0067] The above four categories represent methods for controlling the processing power and power consumption of accelerators. Each of the four power reduction methods differs in the range of variation in ACC processing power, the amount of power consumption reduction, the time required for transitions and recovery, and the applicability to different ACCs. In accelerator state control methods, these are used and set appropriately based on the load prediction results and the accelerator being controlled.

[0068] For example, in "Classification" 1. Circuit Scale Change, under "Power Reduction Methods," specifically "Partial Reconfiguration," the ACC processing capability is "Small to Large (Degenerate)," the power consumption reduction (difference from the maximum configuration) is "~60W," the transition / recovery time is "on the order of seconds," and the applicability for each ACC is "FPGA." Furthermore, it has the characteristic of "preparing optimal circuit information for each performance level and rewriting it as appropriate according to the load."

[0069] Furthermore, under "Classification" 4. Other "Power Reduction Methods," 4-2. "ACC Switching" has ACC processing capability ranging from "small to large (degraded)," power consumption reduction (difference from maximum configuration) of "~60W," transition and recovery time on the order of "seconds," and applicability by ACC type is "FPGA, GPU, ASIC." It also has the characteristic of "preparing multiple optimal circuits / ACCs for each performance level and switching between them as needed according to the load."

[0070] [Circuit information by processing power] The processing capacity-based circuit information of the ACC circuit information recording unit 140 will be explained below. Figure 4 shows an example of a database of circuit information categorized by processing capacity, which is held by the ACC circuit information recording unit 140. As shown in Figure 4, the circuit information by processing capability includes FPGA function type, application name, performance, and circuit information file name. The processing capability-based ACC circuit information recording unit 140 stores multiple FPGA circuit information (processing capability-based circuit information shown in Figure 4) according to the processing performance for each FPGA type, and dispenses FPGA circuit information in response to inquiries (hereinafter, "dispatch" means retrieving information and responding).

[0071] [Processing volume estimation table] This section describes the processing performance calculation table (processing volume estimation table) based on the traffic volume held by the ACC circuit information recording unit 140 according to processing capacity. Figure 5 shows a processing performance calculation table (processing volume estimation table) based on the traffic volume held by the ACC circuit information recording unit 140 according to processing capacity. As shown in Figure 5, the processing load estimation table specifies the required processing performance based on the traffic volume. For example, if the traffic volume is "0 bps or more but less than 10 Mbps", the required processing performance is "low".

[0072] [Accelerator-related management table] The accelerator-related management table held by the ACC circuit information recording unit 140, categorized by processing capacity, will now be described. Figure 6 shows the accelerator mounting relationship management table held by the ACC circuit information recording unit 140, categorized by processing capacity. As shown in Figure 6, the accelerator installation relationship management table stores the correspondence between the host ID and the accelerator ID. In the example in Figure 6, host Host-1 is equipped with accelerators with IDs "1", "2", and "3".

[0073] [Accelerator List Management Table] The accelerator list management table maintained by the ACC circuit information recording unit 140, categorized by processing capacity, will now be described. Figure 7 shows the accelerator list management table held by the ACC circuit information recording unit 140, categorized by processing capacity. As shown in Figure 7, the accelerator list management table stores the correspondence between accelerator IDs and accelerator type IDs. In the example in Figure 7, accelerator ID "1" specifies accelerator type ID "A", accelerator ID "2" specifies accelerator type ID "B", accelerator ID "3" specifies accelerator type ID "C", and accelerator ID "4" specifies accelerator type ID "D". Accelerator type IDs "A" to "D" are specifically shown in the accelerator type management table in Figure 8 below.

[0074] [Accelerator Type Management Table] The accelerator type management table maintained by the ACC circuit information recording unit 140, categorized by processing capacity, will now be described. Figure 8 shows the accelerator type management table held by the ACC circuit information recording unit 140, categorized by processing capacity. As shown in Figure 8, the accelerator type management table stores the accelerator type (remarks), performance, and power consumption for each accelerator type ID. For example, accelerator type ID "A" is an accelerator type "FPGA - low performance", performance "low to high", and power consumption "75W". Accelerator type ID "B" is an accelerator type "FPGA - high performance", performance "low to high", and power consumption "200W". Therefore, if performance is the priority with accelerator type "FPGA", accelerator type ID "B" is selected. Also, if the required performance is "medium to high", in addition to accelerator type "FPGA", accelerator type "GPU" with accelerator type ID "C" or accelerator type "ASIC" with accelerator type ID "D" can be selected. Note that items other than performance and power consumption (for example, application type) may also be managed. For example, if the application performs parallel processing, accelerator type "GPU" may be selected even if the power consumption is the same.

[0075] The operation of the accelerator state control system 1000, configured as described above, will be explained below. The operation sequence of this embodiment is a power saving control sequence, and there are two types: <Operation Sequence 1>, in which the power saving control begins with the prediction of the input amount of function 1, and <Operation Sequence 2>, in which the power saving control begins with periodic execution. These will be explained in order below. [Operation Sequence 1] Figure 9 is a flowchart of <Operation Sequence 1> when power saving control starts with predicting the input amount of function 1.

[0076] In step S11, the input quantity acquisition and prediction unit 110 receives the amount of input data from the server as input, and outputs the traffic quantity after a certain period of time and the unit of change time as prediction results for future data quantities.

[0077] In step S12, the ACC processing capacity / power consumption setting determination unit 120 determines the accelerator's processing capacity and fluctuation time settings based on the traffic amount and fluctuation range output from the input amount acquisition / prediction unit 110 and the list information (Figure 3) read from the ACC information / processing capacity setting recording unit 150.

[0078] In step S13, the installed ACC information / processing capacity setting record unit 150 stores information on the accelerator type and model installed in each host, as well as a list of setting information corresponding to the processing performance, and issues it upon inquiry. The ACC information / processing capacity setting record unit 150 receives the accelerator type, model, and application name from the ACC processing capacity / power consumption setting determination unit 120 as input. The ACC information / processing capacity setting record unit 150 responds to the ACC processing capacity / power consumption setting determination unit as output, with a list of setting means applicable to the relevant accelerator 12. Furthermore, if the input accelerator type is FPGA, the ACC information / processing capacity setting record unit 150 queries the processing capacity-specific ACC circuit information record unit 140 based on the model information and obtains a list of the corresponding suitable FPGA circuit information.

[0079] In step S14, the ACC processing capacity / power consumption setting determination unit 120 determines whether the installed accelerator 12 is an FPGA or not. If the installed accelerator 12 is not an FPGA (S14: No), the process proceeds to step S16.

[0080] If the installed accelerator 12 is an FPGA (S14: Yes), in step S15, the ACC circuit information recording unit 140 for each FPGA type stores FPGA circuit information and FPGA type information according to the processing performance, and responds with FPGA circuit information and FPGA type information in response to an inquiry. In this case, the ACC circuit information recording unit 140 responds to the ACC processing capacity / power consumption setting determination unit 120 either via the ACC information / processing capacity setting recording unit 150 or directly.

[0081] In step S16, the ACC processing capacity / power consumption setting input unit 130 reflects the input settings for the accelerator 12 and the cooling mechanism 14 to the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity / power consumption setting input unit 130 receives setting information for the accelerator 12 and the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120 as input. The ACC processing capacity / power consumption setting input unit 130 reflects the setting information to the accelerator 12 and the cooling mechanism 14, respectively, as output.

[0082] In step S17, accelerator 12 performs calculations specialized for a specific process. In step S18, the accelerator arithmetic circuit / program 12a loads the accelerator circuit or program and terminates the processing of this flowchart. If accelerator 12 is an FPGA, FPGA circuit information is loaded; if accelerator 12 is a GPU, the GPU is loaded.

[0083] Meanwhile, in step S19, the cooling mechanism 14 cools all of the server's computing units [CPU 11 and accelerator 12] and completes the processing of this flowchart.

[0084] [Operation Sequence 2] Figure 10 is a flowchart of the <Operation Sequence 2> when power saving control starts with periodic execution. Steps that perform the same processing as in the flowchart of <Operation Sequence 1> in Figure 9 are denoted by the same reference numerals and their explanations are omitted. In step S21, the ACC processing capacity / power consumption setting determination unit 120 is activated at regular intervals and determines the accelerator settings corresponding to the processing capacity and fluctuation time of the accelerator 12, based on the predicted traffic amount input from the input amount acquisition / prediction unit 110 and the expected fluctuation range.

[0085] After step S15, in step S22, the ACC switching processing continuation unit 160 temporarily continues processing on the CPU 11 or other accelerators in order to continue the service if the calculation function of accelerator 12 is temporarily stopped due to the input of setting information. This is activated when the calculation on accelerator 12 is temporarily suspended when the settings of accelerator 12 are changed.

[0086] After step S18, in step S23, the ACC switching processing continuation unit 160 temporarily suspends the calculation of the accelerator in question when the accelerator setting is changed, and terminates the processing of this flowchart. The above describes <Operation Sequence 1> when power saving control begins with predicting the input amount of function 1, and <Operation Sequence 2> when power saving control begins with periodic execution.

[0087] [Setting sequence for power reduction methods] The accelerator state control device 100 selects the power reduction method to apply based on the amount of traffic and the time range of its fluctuations. Examples of power reduction methods and examples of load patterns suitable for these methods are described below.

[0088] Figure 11 shows a detailed list of power reduction methods. As shown in Figure 11, the power reduction method, ACC processing capacity, power consumption reduction amount (difference from the maximum configuration), transition / recovery time, and suitable load pattern are divided into four categories. The four categories are: 1. Circuit scale change, 2. Clock control, 3. Power supply control, and 4. Other. The power consumption reduction amount is a calculated value based on a specific configuration (for example, Dell R740 2 socket + FPGA N3000). For example, if the classification is "1. Circuit size change" and the power reduction method is "1-1. Writing an empty design," the appropriate load pattern is "a case where load fluctuations occur on the order of minutes under a small load." In other words, when "a small load and load fluctuations on the order of minutes" are tolerable, it is appropriate to adopt "1-1. Writing an empty design." In particular, if the classification is "4. Other" and the power reduction method is "4-2. ACC switching," the appropriate load pattern is to "set according to the ACC processing capacity in all cases."

[0089] [Example of a power reduction method setup sequence] The settings for the accelerator 12 and the cooling mechanism 14 (fan, etc.), and an example of the decision logic for them, will be explained with reference to a flowchart. Each setting amount is an example, and the transition will vary depending on the specific setting item.

[0090] Figures 12A-12C are flowcharts illustrating an example of a power reduction method setup sequence. Although Figures 12A-12C represent a single flow, for illustrative purposes, [A], [B], and [C] are linked together. The dashed lines surrounding each step in the flow represent the functional units that execute that step.

[0091] As shown in Figure 12A, in step S31, the ACC processing capacity / power consumption setting determination unit 120 acquires the traffic amount. In step S32, the ACC processing capacity / power consumption setting determination unit 120 determines whether the traffic volume has increased or decreased for a certain number of consecutive times or more. If the traffic volume has not increased or decreased for a certain number of consecutive times or more (S32: No), the process returns to step S31.

[0092] If the traffic volume increases or decreases for a certain number of consecutive times or more (S32: Yes), the ACC processing capacity / power consumption setting determination unit 120 is bypassed and the process proceeds to step S33. In step S33, the ACC information / processing capacity setting recording unit 150 calculates the processing performance from the traffic volume by referring to the processing performance calculation table shown in Figure 5. In step S34, the ACC information / processing capacity setting recording unit 150 refers to the accelerator installation relationship management table shown in Figure 6 to obtain a list of installed ACCs and their performance.

[0093] Each step enclosed by the dashed line in Figure 12B is a process performed by the ACC processing capacity / power consumption setting determination unit 120. In step S35, the ACC processing capacity / power consumption setting determination unit 120 determines which type of ACC satisfies the processing performance requirements. If the ACC that meets the processing performance requirements is an FPGA, step S36 determines which of the following the processing performance requirements it matches.

[0094] If the processing performance is set to "Very Low", in step S37 select "3. Power Control 3-1. ACC Card Power OFF" (Figure 11), and in step S38 select "4. Other 4-1. Fan Control Fan Setting [Very Low]" (Figure 11) and proceed to step S48.

[0095] If the processing performance is "low", in step S39 select "1. Circuit size change 1-2. Select small-scale circuit with partial reconstruction" (Figure 11), in step S40 select "2. Clock control 2-1. Frequency [low] with arithmetic unit clock control" (Figure 11), in step S41 select "4. Other 4-1. Fan setting [low] with fan control" (Figure 11), and proceed to step S48.

[0096] If the processing performance is set to "medium", in step S42 select "1. Circuit scale change 1-2. Partial reconstruction and selection of medium-scale circuit" (Figure 3), in step S43 select "2. Clock control 2-1. Aptitude unit clock control frequency [medium]" (Figure 11), in step S44 select "4. Other 4-1. Fan control fan setting [medium]" (Figure 11) and proceed to step S48.

[0097] If the processing performance is "high", in step S45 select "1. Circuit scale change 1-2. Select large-scale circuit in partial reconstruction" (Figure 3), in step S46 select "2. Clock control 2-1. Frequency [high] in arithmetic unit clock control" (Figure 11), in step S47 select "4. Other 4-1. Fan setting [high] in fan control" (Figure 11) and proceed to step S48.

[0098] In step S48, the ACC switching processing continuation unit 160, if the calculation function of accelerator 12 is temporarily stopped due to the input of setting information, temporarily continues processing (activates) on CPU 11 or other accelerators in order to continue the service and proceeds to step S58. This activates when calculations on the accelerator are temporarily suspended when the accelerator settings are changed.

[0099] In step S35, if the ACC processing capacity / power consumption setting determination unit 120 determines that the ACC that meets the processing performance requirements is a GPU or ASIC, in step S49 it determines which of the following the processing performance requirements it matches.

[0100] If the processing performance is set to "Very Low", in step S50 select "3. Power Control 3-1. ACC Card Power OFF" (Figure 11), and in step S51 select "4. Other 4-1. Fan Control Fan Setting [Very Low]" (Figure 11) and proceed to step S58.

[0101] If the processing performance is "low", in step S52 select "2. Clock control 2-1. Frequency [low] in arithmetic unit clock control" (Figure 11), and in step S53 select "4. Other 4-1. Fan setting [low] in fan control" (Figure 11) and proceed to step S58.

[0102] If the processing performance is set to "medium", in step S54 select "2. Clock control 2-1. Frequency [medium] in arithmetic unit clock control" (Figure 11), and in step S55 select "4. Other 4-1. Fan control Fan setting [medium]" (Figure 3) and proceed to step S58.

[0103] If the processing performance is set to "High", in step S56 select "2. Clock control 2-1. Frequency [High] in arithmetic unit clock control" (Figure 3), and in step S57 select "4. Other 4-1. Fan control Fan setting [High]" (Figure 3) and proceed to step S58.

[0104] In step S58 shown in Figure 12C, the ACC processing capacity / power consumption setting input unit 130 sets the ACC / Fan.

[0105] In step S59, the ACC switching processing continuation unit 160 determines whether or not the ACC switching processing continuation function is being executed. If the ACC switching processing continuation function is not being executed (S59: No), the processing of this flow is terminated. If the ACC switching processing continuation function is being executed (S59: Yes), in step S60, the ACC switching processing continuation unit 160 disables the calculation of the accelerator in question when the accelerator setting is changed, thereby terminating the processing of this flow. The power reduction method setup sequence has been explained above with reference to Figures 11 and 12A-12C.

[0106] [Data processing sequence for operation sequence 1] The data processing sequence for operation sequence 1 will be explained. The data processing sequence for operation sequence 2 is similar. The data processing sequence for operation sequence 1 has two types: "Look-Aside type (the CPU actively offloads ACC processing data to ACC)" and "In-line type (the CPU actively offloads ACC processing data to ACC)". These will be explained in order below.

[0107] Figure 13 is a flowchart showing the data processing sequence for Look-Aside operation sequence 1. In step S61, the antenna device data input / output unit 211 sends the signal generated by the antenna device 210 to the server 200.

[0108] In step S62, the input / output unit 13 performs data input / output with external devices [antenna device 210 and downstream processing unit 220].

[0109] In step S63, Application 1 runs on CPU 11 and performs signal processing. For specialized processing that is not suitable for CPU 11, such as some parallel processing, Application 1 offloads it to accelerator 12.

[0110] In step S64, the accelerator 12 performs calculations specialized for a specific process. In step S65, application 1 receives data to be processed from the input / output unit 13 and passes the calculated data back to the input / output unit 13. When the settings of accelerator 12 are changed, if the accelerator 12 becomes temporarily unavailable, application 1 offloads the process to the ACC switching processing continuation unit 160.

[0111] In step S66, the input / output unit 13 performs data input / output with external devices [antenna device 210 and downstream processing unit 220].

[0112] In step S67, the downstream processing unit data input / output unit 221 receives the signal processing result processed by the server 200 and terminates the processing in this flowchart.

[0113] Figure 14 is a flowchart of the data processing sequence for In-Line operation sequence 1. In step S71, the antenna device data input / output unit 211 sends the signal generated by the antenna device 210 to the server 200.

[0114] In step S72, the input / output unit 13 performs data input / output with external devices [antenna device 210 and downstream processing unit 220].

[0115] In step S73, the accelerator 12 performs calculations specialized for a specific process. In step S74, application 1 receives data to be processed from the input / output unit 13 and passes the calculated data back to the input / output unit 13. When the settings of accelerator 12 are changed, if the accelerator 12 becomes temporarily unavailable, application 1 offloads the process to the ACC switching processing continuation unit 160.

[0116] In step S75, the input / output unit 13 performs data input / output with external devices [antenna device 210 and downstream processing unit 220].

[0117] In step S76, the downstream processing unit data input / output unit 221 receives the signal processing results processed by the server 200 and terminates the processing in this flowchart.

[0118] [Processing capacity, power consumption, and surplus] This section will explain the processing power, power consumption, and surplus realized by the accelerator state control device 100. The ACC processing capacity / power consumption setting determination unit 120 determines the accelerator settings according to the accelerator's processing capacity and fluctuation time, based on the predicted traffic amount input from the input amount acquisition / prediction unit 110 and the expected fluctuation range. The ACC processing capacity / power consumption setting input unit 130 receives setting information for the accelerator 12 and the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120, and reflects the setting information in the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity / power consumption setting input unit 130 dynamically changes the processing capacity and power consumption by automatically performing appropriate accelerator settings (circuit information, frequency, fan output, etc.) for each amount of input data.

[0119] Figure 15 illustrates the processing capacity, power consumption, and surplus realized by the accelerator state control device 100. The solid line in Figure 15 represents the amount of input data, and the dashed line in Figure 15 represents the server processing capacity (≒ power consumption). The ACC processing capacity / power consumption setting determination unit 120 and the ACC processing capacity / power consumption setting input unit 130 set the appropriate accelerator settings for each amount of input data, and the processing capacity and power consumption are dynamically changed. As shown by the arrows in Figure 15, the amount that the server 200 can process changes with the setting changes, improving power efficiency.

[0120] [Hardware configuration] The accelerator state control device 100 (Figure 1) of the accelerator state control systems 1000 and 1000A (Figures 1 and 2) according to the above embodiment is implemented by a computer 900 having a configuration such as that shown in Figure 16. Figure 16 is a hardware configuration diagram showing an example of a computer 900 that implements the functions of the accelerator state control device 100. The accelerator state control device 100 includes a CPU 901, RAM 902, ROM 903, HDD 904, accelerator 905, input / output interface (I / F) 906, media interface (I / F) 907, and communication interface (I / F) 908. Accelerator 905 corresponds to accelerator 12 in Figures 1 and 2.

[0121] Accelerator 905 is an accelerator (device) 12 (Figures 1 and 2) that processes at high speed data from either the communication interface 908 or the RAM 902. Note that accelerator 905 may be of a type that returns the execution result to the CPU 901 or RAM 902 after processing from the CPU 901 or RAM 902 (Look-Aside type). Alternatively, accelerator 905 may be of an in-line type that performs processing between the communication interface 908 and the CPU 901 or RAM 902.

[0122] The accelerator 905 is connected to the external device 915 via the communication interface 908. The input / output interface 906 is connected to the input / output device 916. The media interface 907 reads and writes data to the recording medium 917.

[0123] The CPU 901 operates based on a program stored in the ROM 903 or HDD 904, and controls the various parts of the accelerator state control devices 100 and 100A shown in Figures 1 and 2 by executing the program (also called an application or app) loaded into the RAM 902. This program can also be distributed via a communication line or by recording it on a recording medium 917 such as a CD-ROM. ROM903 stores boot programs executed by CPU901 when the computer 900 starts up, as well as programs that depend on the computer 900's hardware.

[0124] The CPU 901 controls the input / output device 916, which consists of an input unit such as a mouse or keyboard, and an output unit such as a display or printer, via the input / output interface 906. The CPU 901 acquires data from the input / output device 916 via the input / output interface 906 and outputs generated data to the input / output device 916. In addition to the CPU 901, a GPU (Graphics Processing Unit) or the like may also be used as a processor.

[0125] HDD904 stores programs executed by CPU901 and data used by those programs. Communication I / F908 receives data from other devices via a communication network (e.g., NW (Network)) and outputs it to CPU901, and also transmits data generated by CPU901 to other devices via the communication network.

[0126] The media interface 907 reads a program or data stored in the recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads the program related to the desired processing from the recording medium 917 onto the RAM 902 via the media interface 907 and executes the loaded program. The recording medium 917 can be an optical recording medium such as a DVD (Digital Versatile Disc) or PD (Phase Change Rewritable Disk), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a magnetic recording medium, a conductive memory tape medium, or a semiconductor memory.

[0127] For example, if computer 900 functions as an accelerator state control device 100 (Figure 1) configured as one of the devices according to this embodiment, the CPU 901 of computer 900 realizes the functions of the accelerator state control device 100 by executing a program loaded on RAM 902. The HDD 904 stores the data in RAM 902. The CPU 901 reads and executes a program related to the desired processing from the recording medium 917. Alternatively, the CPU 901 may read a program related to the desired processing from another device via a communication network. Furthermore, if the controller function unit shown in Figure 2 is installed outside the server 200, the accelerator state control device 100A is similarly implemented by a computer 900 with the configuration shown in Figure 16.

[0128] [effect] As described above, when offloading a specific process of Application 1 to the accelerator 12 for computation, the accelerator state control device 100 controls the state of the accelerator, and includes: an input quantity acquisition / prediction unit 110 that predicts the amount of processing to be offloaded to the accelerator 12 and outputs the prediction result as traffic quantity and its fluctuation range; a processing capacity setting record unit 150 that holds information on the accelerator type and model, and setting information according to processing performance as list information, and retrieves it from the list information in response to an inquiry; an ACC processing capacity / power consumption setting determination unit 120 that determines the setting information for the accelerator's processing capacity and fluctuation time based on the traffic quantity and fluctuation range output from the input quantity acquisition / prediction unit 110 and the list information read from the processing capacity setting record unit 150; and an ACC processing capacity / power consumption setting input unit 130 that reflects the setting information to the accelerator 12 based on the setting information for the accelerator 12 determined by the ACC processing capacity / power consumption setting determination unit 120.

[0129] By doing so, the system automatically sets the appropriate accelerator settings (circuit information, frequency, fan output, etc.) for each amount of input data, dynamically changing processing power and power consumption. This ensures responsiveness while achieving high power efficiency for various accelerators in response to fluctuating input data volumes. This allows for a balance between <Requirement 1: Power Efficiency> and <Requirement 2: Responsiveness>.

[0130] The accelerator state control devices 100 and 100A (Figures 1 and 2) include an ACC switching processing continuation unit 160 that temporarily continues processing in the CPU 11 or other accelerator when the calculation function of the accelerator 12 is temporarily stopped due to the input of setting information by the ACC processing capacity / power consumption setting input unit 130.

[0131] By doing this, if computation stops when an accelerator is brought into operation, the CPU 11 or other accelerators can continue the computation, thus maintaining availability.

[0132] In the accelerator state control devices 100 and 100A (Figures 1 and 2), the accelerator 12 has an FPGA and is equipped with an ACC circuit information recording unit 140 that stores FPGA circuit information and FPGA type information according to the processing performance for each FPGA type and responds with FPGA circuit information and FPGA type information in response to inquiries. The ACC circuit information recording unit 140 responds to the ACC processing capacity / power consumption setting determination unit 120 either via the ACC information / processing capacity setting recording unit 150 or directly. The ACC processing capacity / power consumption setting determination unit 120 determines accelerator setting information according to the accelerator's processing capacity and fluctuation time based on the FPGA circuit information and FPGA type information from the ACC circuit information recording unit 140.

[0133] In this way, the ACC circuit information recording unit 140 for each processing capacity records and manages power saving settings for each accelerator type. The ACC processing capacity / power consumption setting determination unit 120 selects a processing method for each piece of mounted ACC information, thereby enabling support for multiple accelerators (<Requirement 3: Support for multiple accelerators>). For example, in the case of an FPGA, it is circuit selection + frequency setting, and in the case of an ASIC, it is frequency setting, etc.

[0134] In the accelerator state control devices 100 and 100A (Figures 1 and 2), the accelerator 12 has an FPGA and a GPU, and the ACC processing capacity / power consumption setting input unit 130 is common to all accelerators and reflects the setting information by changing the frequency and / or turning off the power, and in the case of FPGAs it reflects the setting information by rewriting the circuit, and in the case of GPUs it reflects the setting information by sleeping.

[0135] By doing this, when determining power saving settings, it is possible to determine the parameters that can be set for each installed accelerator, thereby enabling support for multiple types of accelerators (<Requirement 3: Support for multiple accelerators>). For example, in the case of FPGAs, this would be circuit rewriting; in the case of GPUs, it would be sleep; and as a common method, it would be frequency change and power off.

[0136] An accelerator state control system 1000,1000A (Figures 1, 2) is provided, which includes an accelerator state control device 100,100A (Figures 1, 2) for controlling the state of the accelerator when offloading specific processing of Application 1 to the accelerator 12 for computation, and a cooling mechanism 14 for cooling the computation unit including the accelerator. The system includes an input quantity acquisition and prediction unit 110 that predicts the amount of processing to be offloaded to the accelerator 12 and outputs the prediction result as traffic quantity and its fluctuation range, and stores information on the accelerator type and model, and setting information according to processing performance as list information. The system includes a processing capacity setting recording unit 150 that retrieves information from a list in response to an inquiry and provides a response, an ACC processing capacity / power consumption setting determination unit 120 that determines the setting information for the accelerator's processing capacity and fluctuation time based on the traffic amount and fluctuation range output from the input amount acquisition / prediction unit 110 and the list information read from the processing capacity setting recording unit 150, and an ACC processing capacity / power consumption setting input unit 130 that reflects the setting information for the accelerator 12 and cooling mechanism 14 based on the setting information for the accelerator 12 and cooling mechanism 14 determined by the ACC processing capacity / power consumption setting determination unit 120.

[0137] By doing so, it is possible to ensure responsiveness (Requirement 2: Responsiveness) in response to fluctuating input data volumes while achieving high power efficiency (Requirement 1: Power Efficiency) for various accelerators. Furthermore, by determining the parameters that can be set for each installed accelerator when determining power saving settings, it is possible to support multiple types of accelerators (Requirement 3: Support for Multiple Accelerators). For example, this could involve circuit rewriting for FPGAs, sleep for GPUs, and frequency changes and power off as common methods. In addition, the cooling mechanism 14 is configured to output according to each accelerator and traffic volume.

[0138] Furthermore, among the processes described in the above embodiments and modifications, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings can be arbitrarily changed unless otherwise specified. Furthermore, the components of each illustrated device are functionally conceptual and do not necessarily need to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0139] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software that allows the processor to interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disc. [Explanation of Symbols]

[0140] 1. Application (APL) 10 Hardware 11 CPU 12 Accelerators 12a Accelerator arithmetic circuit and program 13 Input / output section 14 Cooling mechanism 20 Software 100,100A Accelerator Status Control Device 110 Input quantity acquisition and prediction unit (prediction unit, prediction procedure) 120 ACC Processing Capacity / Power Consumption Setting Determination Unit (Determination Unit, Determination Procedure) 130 ACC Processing Capacity / Power Consumption Setting Input Unit (Setting Input Unit, Setting Input Procedure) 140 ACC circuit information recording unit by processing capacity 150 ACC Information / Processing Capacity Setting Recording Unit (Processing Capacity Setting Recording Unit, Processing Capacity Setting Recording Procedure) 160 ACC Switching Processing Continuation Unit (Processing Continuation Unit) 170 List Information 200 servers (servers equipped with accelerators) 210 Antenna equipment 220 Downstream processing unit 1000, 1000A Accelerator State Control System

Claims

1. An accelerator state control device that controls the state of an accelerator when offloading specific processing of an application to an accelerator for computational processing, A prediction unit predicts the amount of processing to be offloaded to the accelerator and outputs the prediction result and the expected range of variation as the predicted processing amount. A processing capacity setting recording unit that refers to a list of information regarding the settings of the aforementioned accelerator, A determination unit that determines whether or not it is necessary to change the settings of the accelerator based on the predicted processing volume and the list information, The system includes a setting input unit that, when the determination unit determines that a change in the accelerator's settings is necessary, sets the accelerator based on the setting information for the accelerator. An accelerator state control device characterized by the following:

2. The list information holds setting information corresponding to processing performance based on traffic volume, The unit that makes the determination said, The predicted processing load is evaluated to determine whether to change the accelerator settings. The accelerator state control device according to feature 1.

3. An accelerator state control method for an accelerator state control device that controls the state of an accelerator when offloading specific processing of an application to an accelerator for computation processing, The accelerator state control device is The steps include predicting the amount of processing to be offloaded to the accelerator, and outputting the prediction result and the expected range of variation as the predicted processing amount, The steps include referring to a list of information regarding the settings of the aforementioned accelerator, A step of determining whether or not it is necessary to change the settings of the accelerator based on the predicted processing volume and the list information, If it is determined that a change in the accelerator settings is necessary, the following steps are performed:

1. Set the accelerator based on the setting information for the accelerator. An accelerator state control method characterized by the following.

4. When offloading specific processing of an application to an accelerator for computational processing, a computer is used as an accelerator state control device to control the state of the accelerator, Prediction means that predicts the amount of processing to be offloaded to the accelerator, and outputs the prediction result and the expected range of variation as the predicted processing amount. A processing capacity setting recording means that references a list of information relating to the settings of the accelerator, A determination means that determines whether or not it is necessary to change the settings of the accelerator based on the predicted processing volume and the list information. When the determination means determines that a change in the accelerator settings is necessary, a setting input means performs a setting on the accelerator based on the setting information for the accelerator. A program designed to function as such.

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