Training method, chip layout screening method, apparatus, and program used for chip layout encoders

Abstract

The present invention relates to a method and apparatus for training a chip layout encoder and screening a chip layout, which belongs to the technical field of integrated circuits. The method includes the steps of: obtaining a sample chip layout and an initial encoder (201); performing a geometric transformation on the sample chip layout to obtain at least one reference chip layout (202); extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder (203); and training the initial encoder based on the sample layout features and the reference layout features to obtain a trained encoder (204). By adopting the above method and apparatus, the chip layout encoder can output similar layout features for the chip layouts before and after the geometric transformation, and thus the chip layout encoder is advantageous in that it can focus on extracting layout features that can distinguish chip layout types, and then improve the accuracy of the clustering result when clustering chip layouts based on the layout features.

Description

[Technical Field]

[0001] The embodiments of this application relate to the technology of integrated circuits, and more particularly to training, chip layout screening methods, and apparatus used in chip layout encoders.

[0002] This application claims priority to a Chinese patent application filed on September 26, 2022, with application number 202211176018.8, and the title of the invention is "Method for training a chip layout encoder, method for screening a chip layout, and apparatus," the entire contents of which are incorporated into this application by reference. [Background technology]

[0003] With the continuous development of integrated circuit (IC) technology, the characteristic dimensions of IC layouts (also called chip layouts) are also continuously shrinking. Here, characteristic dimensions of a chip layout refer to the minimum dimensions of a semiconductor device. Currently, characteristic dimensions of chip layouts have already reached the nanometer level.

[0004] Normally, it is necessary to first operate a photolithography apparatus and use a light source to expose the chip layout onto a photoresist to obtain a mask layout, and then operate the photolithography apparatus again and use a light source to expose the mask layout onto a wafer to obtain an image layout. Because the characteristic dimensions of the chip layout are lower than the wavelength of the light source used in the photolithography process, interference and diffraction effects are amplified, resulting in distortion and blurring of the image layout obtained by exposing the mask layout onto the wafer, further reducing chip performance and yield. In this case, it is necessary to optimize the light source mask for the chip layout and obtain an optimized mask layout, thereby improving chip performance and yield.

[0005] When optimizing a light source mask for a chip layout, it is necessary to extract the layout features of the chip layout. Therefore, how to train a chip layout encoder that can extract the layout features of the chip layout is an urgent issue that needs to be resolved. [Overview of the project] [Problems that the invention aims to solve]

[0006] This application provides a training method, a chip layout screening method, and an apparatus for use in a chip layout encoder, and is a technical means for extracting layout features of a chip layout and screening a chip layout, the technical means including the following: [Means for solving the problem]

[0007] In one embodiment, a training method for use in a chip layout encoder is provided, the method being performed by an electronic device, and the method is Steps include obtaining a sample chip layout and an initial encoder, The steps include performing a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, The steps include: extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder; The process includes the steps of: training the initial encoder based on the layout features of the sample chip layout and the layout features of each of the reference chip layouts to obtain a chip layout encoder, wherein the chip layout encoder is used to extract the layout features of a target chip layout; or training the initial encoder based on the sample layout features and the reference layout features to obtain a trained encoder.

[0008] In another embodiment, a method for screening chip layouts is provided, the method being performed by an electronic device, and the method is A step of obtaining multiple target chip layouts and chip layout encoders (i.e., trained encoders), wherein the chip layout encoders (i.e., trained encoders) are obtained by training them using a training method used for the chip layout encoders. The steps include: extracting target layout features of each target chip layout using the aforementioned chip layout encoder (i.e., the trained encoder); A step of performing clustering on the plurality of target chip layouts based on the characteristics of each target layout to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups. The method includes the step of screening for a key chip layout from among the target chip layouts included in any one of the target clustering groups.

[0009] In another embodiment, a training device used for a chip layout encoder is provided, the device is A sample chip layout and an acquisition module used to obtain the initial encoder, A conversion module used to perform a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, An extraction module used to extract sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder, A training module used to train the initial encoder and obtain a chip layout encoder based on the layout features of the sample chip layout and the layout features of each of the reference chip layouts, wherein the chip layout encoder is used to extract the layout features of a target chip layout. Alternatively, the training module is used to train the initial encoder and obtain a trained encoder based on the sample layout features and the reference layout features.

[0010] In another embodiment, a chip layout screening apparatus is provided, the apparatus is An acquisition module used to acquire multiple target chip layouts and chip layout encoders (i.e., trained encoders), wherein the chip layout encoders (i.e., trained encoders) are obtained by training the acquisition module according to a training method used for the chip layout encoders, An extraction module used to extract target layout features of each target chip layout using the aforementioned chip layout encoder (i.e., the trained encoder), A clustering module used to perform clustering processing on a plurality of target chip layouts based on the characteristics of each target layout, and to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups, The system includes a screening module used to screen for a key chip layout from among the target chip layouts included in any one of the target clustering groups.

[0011] In another embodiment, an electronic device is provided, the electronic device comprising a processor and a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor, thereby enabling the electronic device to implement a training method used for the chip layout encoder or a screening method for the chip layout.

[0012] In another embodiment, a non-volatile computer-readable storage medium is provided, wherein at least one computer program is stored in the non-volatile computer-readable storage medium, and the at least one computer program is loaded and executed by a processor, thereby enabling an electronic device to implement a training method used for the chip layout encoder or a screening method for the chip layout.

[0013] In another embodiment, a computer program is further provided, the computer program being at least one, and the at least one computer program being loaded and executed by a processor, the electronic device implementing a training method used for the chip layout encoder or a screening method for the chip layout.

[0014] In yet another embodiment, a computer program product is provided, wherein at least one computer program is stored in the computer program product, and the at least one computer program is loaded and executed by a processor, thereby enabling the electronic device to implement a training method used for the chip layout encoder or a screening method for the chip layout. [Effects of the Invention]

[0015] The technical means provided by the present application performs a geometric transformation on the sample chip layout to obtain a reference chip layout, and uses the layout features of the sample chip layout and the layout features of the reference chip layout to train an initial encoder to obtain a chip layout encoder, so that the chip layout encoder can output similar layout features for the chip layouts before and after the geometric transformation. Since the chip layouts before and after the geometric transformation belong to the same type of chip layout type, the chip layout encoder focuses on extracting layout features that can distinguish the chip layout type, and then when performing clustering processing and screening processing on the chip layout based on the layout features, it is advantageous in improving the accuracy of the clustering result and reducing the redundancy of the screening result.

Brief Description of the Drawings

[0016] [Figure 1] It is a schematic diagram of the implementation environment of the training method used in the chip layout encoder provided by the embodiment of the present application, or the screening method of the chip layout. [Figure 2] It is a flowchart of the training method used in the chip layout encoder provided by the embodiment of the present application. [Figure 3] It is a schematic diagram of performing a geometric transformation on the sample chip layout provided by the embodiment of the present application. [Figure 4] It is a schematic diagram of the Unet framework provided by the embodiment of the present application. [Figure 5] It is a flowchart of the screening method of the chip layout provided by the embodiment of the present application. [Figure 6] It is a schematic diagram of the chip layout encoder provided by the embodiment of the present application, and clustering and screening are performed based on the chip layout encoder. [Figure 7] It is a structural schematic diagram of the training device used in the chip layout encoder provided by the embodiment of the present application. [Figure 8]This is a schematic diagram of the structure of a chip layout screening device provided by an embodiment of the present invention. [Figure 9] This is a schematic diagram of the structure of a terminal device provided by an embodiment of the present invention. [Figure 10] This is a schematic diagram of the structure of the server provided in the embodiment of the present invention. [Modes for carrying out the invention]

[0017] To further clarify the purpose, technical means, and advantages of this application, embodiments of this application will be described in more detail below, along with the drawings.

[0018] Figure 1 is a schematic diagram of the implementation environment for a training method or chip layout screening method used for a chip layout encoder provided in an embodiment of the present application. As shown in Figure 1, the implementation environment includes a terminal device 101 and a server 102. Here, the training method or chip layout screening method used for a chip layout encoder in an embodiment of the present application may be executed by the terminal device 101, by the server 102, or jointly by the terminal device 101 and the server 102.

[0019] The terminal device 101 may be a smartphone, game host, desktop computer, tablet computer, portable laptop computer, smart TV, smart in-car device, smart voice interaction device, smart home appliance, etc. The server 102 may be a single server, a server cluster consisting of multiple servers, or any one of a cloud computing platform and a virtualization center, and the embodiments of this application are not limited thereto. The server 102 may be connected to the terminal device 101 by a wired network or a wireless network. The server 102 may have functions such as data processing, data storage, and data transmission and reception, and the embodiments of this application are not limited thereto. There is no limit to the number of terminal devices 101 and servers 102; there may be one or more.

[0020] The training method or chip layout screening method used in the chip layout encoder provided in the embodiment of the present application can be realized based on artificial intelligence technology. Artificial intelligence (AI) is a theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and augment human intelligence, sense the environment, acquire knowledge, and use that knowledge to obtain optimal results. In other words, artificial intelligence is a comprehensive technology in computer science that aims to create a kind of new smart machine that can grasp the essence of intelligence and respond in a manner similar to human intelligence. Artificial intelligence studies the design principles and implementation methods of various smart machines, enabling machines to have sensing, reasoning, and decision-making functions.

[0021] Artificial intelligence technology is a comprehensive discipline encompassing both hardware and software technologies across a wide range of fields. Fundamental AI technologies generally include, for example, sensors, dedicated AI chips, cloud computing, distributed memory, big data processing technologies, operation / interaction systems, and mechatronics. Artificial intelligence software technologies primarily encompass several major areas, such as computer vision technology, speech processing technology, natural language processing technology, machine learning / deep learning, autonomous driving, and smart transportation.

[0022] In the field of integrated circuit technology, integrated circuit layouts are a type of standard layout, also known as chip layouts. Generally, it is necessary to optimize the light source mask for the chip layout to obtain an optimized mask layout. By operating a photolithography apparatus to expose the optimized mask layout onto a wafer and reducing the error between the resulting image layout and the chip layout, chip performance is improved and chip yield is increased.

[0023] When optimizing a light source mask for a chip layout, it is necessary to extract the layout features of the chip layout. Therefore, how to train a chip layout encoder and how to use that encoder to extract the layout features of the chip layout is one of the urgent issues that needs to be resolved.

[0024] The embodiment of the present invention provides a training method for use in a chip layout encoder, which can be applied in the above-described implementation environment and can solve the problem of obtaining a chip layout encoder through training. In the example flowchart of the training method for use in a chip layout encoder provided by the embodiment of the present invention shown in Figure 2, for convenience of description, the terminal device 101 or server 102 that executes the training method for use in a chip layout encoder in the embodiment of the present invention will be referred to as an electronic device, and the method may be executed by an electronic device. As shown in Figure 2, the method includes the following steps.

[0025] Step 201: Obtain the sample chip layout and initial encoder.

[0026] A sample chip layout is an integrated circuit (IC) layout, or a sub-region within an IC layout. Typically, there are multiple sample chip layouts, and the processing method for each sample chip layout is the same.

[0027] In the embodiments of this application, an arbitrary IC layout can be obtained and used as a sample chip layout. Alternatively, the IC layout can be uniformly divided into multiple sub-regions, each sub-region can be obtained, and any sub-region can be used as a sample chip layout. Selectively, some sub-regions can be manually screened from each sub-region (for example, screening for sub-regions that do not have defect points, which are parts of the IC layout that do not satisfy the process window requirement), and these sub-regions can be used as sample chip layouts. Alternatively, each sub-region can be classified, a chip layout type corresponding to each sub-region can be obtained, and sample chip layouts can be obtained by uniformly sampling and screening from the sub-regions corresponding to each chip layout type. Here, the chip layout type includes, but is not limited to, contact hole type, logic layout type, and dense line type.

[0028] To understand this, when uniformly dividing an IC layout, there is a possibility that a defect point may be located exactly along the dividing line. In this case, when dividing the IC layout, one defect point will be divided into at least two parts, and the different parts will be in different sub-regions. Because the sub-region contains part of the defect point, and this is an incomplete defect point, it becomes difficult to identify the defect point from the sub-region, making it easy to use the sub-region containing the defect point as the sample chip layout, which leads to a decrease in the quality of the sample chip layout.

[0029] In one possible implementation, each defect point in the IC layout can first be identified. The embodiments of this application do not limit the method of identifying defect points; for example, each defect point in the IC layout can be identified by a manual identification method, or by a photolithography simulation method. Subsequently, smart partitioning is performed on the IC layout using an image partitioning model to obtain each sub-region. By distributing the defect points as close to the center of the sub-region as possible, rather than at the edges of the sub-regions, defect points can be identified quickly and accurately from each sub-region when screening sample chip layouts from each sub-region, thereby avoiding sub-regions containing defect points in the screened sample chip layout and improving the quality of the sample chip layout. This improves the training effect of the chip layout encoder when it is subsequently trained using the sample chip layout.

[0030] In the embodiments of this application, the sample chip layout is image data and belongs to a representation method using pixels. By dividing the IC layout and screening the sample chip layout, various chip layout types such as contact hole type, logic layout type, and dense line type can all be represented using pixels. Here, the pixel dimensions of the sample chip layout must be greater than or equal to the wavelength of the light source / (4 × numerical aperture), that is, the pixel dimensions of the sample chip layout must satisfy the minimum resolution of the photolithography apparatus.

[0031] A sample chip layout is used to train an initial encoder to obtain a chip layout encoder. The embodiments of this application do not limit the structure and size of the initial encoder, and exemplary the initial encoder is an encoder in a deep learning framework based on a U network, and is abbreviated as the encoder in the Unet framework. The encoder in the Unet framework can effectively perform dimensionality reduction on high-dimensional data (e.g., image data), thereby extracting data features. The Unet framework is a type of convolutional self-encoder and is mainly composed of two parts. The first part is an encoder, which consists of at least two convolutional blocks, and this encoder can be the initial encoder in the embodiments of this application. The second part is a decoder, which consists of at least two deconvolutional blocks, and the number of convolutional blocks and the number of deconvolutional blocks are the same.

[0032] Step 202: Perform a geometric transformation on the sample chip layout to obtain at least one reference chip layout.

[0033] Geometric transformations include at least one type of transformation, such as inversion and rotation. A reference chip layout can be obtained by performing at least one type of transformation, such as inversion and rotation, on a sample chip layout. Here, inversion is the mirror inversion process mentioned below, and rotation is the rotation process mentioned below.

[0034] Exemplary, step 202 includes the step of performing a mirror inversion on the sample chip layout to obtain a symmetric chip layout, and making the symmetric chip layout at least one reference chip layout. To make it clear, the symmetric chip layout here may also be called the sample chip layout after the mirror inversion, and is abbreviated as the inverted chip layout. In other words, the sample chip layout is mirrored to obtain the inverted chip layout. At least one reference chip layout includes the inverted chip layout. The implementation of the mirror inversion process is described below, but will not be explained in detail here.

[0035] For example, step 202 includes the step of performing a rotation on the sample chip layout to obtain a rotated chip layout, and making the rotated chip layout at least one reference chip layout. To make it clear, the rotated chip layout here may also be called the sample chip layout after rotation, and is abbreviated as the rotated chip layout. In other words, the sample chip layout is rotated to obtain the rotated chip layout. At least one reference chip layout includes the rotated chip layout. The implementation of the rotation process is described below, but will not be explained in detail here.

[0036] In one possible implementation, step 202 includes the steps of: performing a mirror inversion on a sample chip layout to obtain a symmetric chip layout; performing a rotation on the sample chip layout and the symmetric chip layout to obtain a rotated chip layout; and making the symmetric chip layout and the rotated chip layout at least one reference chip layout. To make it clear, the symmetric chip layout here may also be called the sample chip layout after the mirror inversion, and is abbreviated as the inverted chip layout. The rotated chip layout here may also be called the sample chip layout after the rotation, and the symmetric chip layout after the rotation, and is abbreviated as the rotated chip layout. That is, a mirror inversion is performed on the sample chip layout to obtain the inverted chip layout, and a rotation is performed on the sample chip layout and the inverted chip layout to obtain the rotated chip layout. At least one reference chip layout includes the inverted chip layout and the rotated chip layout.

[0037] In the embodiment of the present invention, a mirror inversion process is performed on the sample chip layout according to the mirror surface information, thereby achieving a mirror transformation of the sample chip layout, obtaining a symmetrical chip layout, and allowing the symmetrical chip layout to be used as a reference chip layout. The mirror surface information can represent the position and orientation of the mirror surface, where the orientation of the mirror surface is the same as the normal direction of the mirror surface, and the position of the mirror surface is represented by the position of a reference point (e.g., the center point) on the mirror surface. When the mirror surface is oriented horizontally, it indicates that the normal direction of the mirror surface is horizontal, and in this case, a left or right mirror inversion process can be performed on the sample chip layout. When the mirror surface is oriented vertically, it indicates that the normal direction of the mirror surface is vertical, and in this case, an upward or downward mirror inversion process can be performed on the sample chip layout.

[0038] To make it understandable, there is at least one mirror image information. For any one of the mirror image information, a mirror inversion process is performed on the sample chip layout according to that mirror image information to obtain one symmetric chip layout, and this symmetric chip layout is used as the reference chip layout. This method makes it possible to determine different reference chip layouts according to different mirror image information, and to keep the number of reference chip layouts at least one.

[0039] By performing a rotation process on the sample chip layout at least once according to the rotation parameters, a rotational transformation of the sample chip layout can be achieved, and the rotated chip layout obtained after each rotation process can be obtained. In other words, first, the sample chip layout is rotated once according to the rotation parameters, and the sample chip layout obtained after the first rotation process is taken as the rotated chip layout obtained after the first rotation process. Next, according to the rotation parameters, the rotated chip layout obtained after the first rotation process is rotated a second time, and the rotated chip layout obtained after the second rotation process is taken. Subsequently, according to the rotation parameters, the rotated chip layout obtained after the second rotation process is rotated a third time, and the rotated chip layout obtained after the third rotation process is taken. This demonstrates how at least one rotation process can be performed on the sample chip layout.

[0040] Similarly, by performing a rotation process on a symmetric chip layout at least once according to the rotation parameter, a rotational transformation of the symmetric chip layout can be achieved, and a rotated chip layout can be obtained after each rotation process. Each rotated chip layout obtained after each rotation process can be used as a reference chip layout. It should be explained that the rotation parameter is used to specify the angle that needs to be rotated in each rotation process. For example, the rotation parameter is the target angle that needs to be rotated in each rotation process. In this case, one rotated chip layout can be obtained by rotating the sample chip layout once for each target angle, or one rotated chip layout can be obtained by rotating the symmetric chip layout once for each target angle.

[0041] As shown in Figure 3, Figure 3 is a schematic diagram illustrating the geometric transformation performed on a sample chip layout provided by an embodiment of the present invention. In the embodiment of the present invention, on the one hand, two rotated chip layouts can be obtained by rotating the sample chip layout once every 45 degrees, and on the other hand, a mirror inversion process to the right can be performed on the sample chip layout to obtain a symmetrical chip layout, and then two rotated chip layouts can be obtained by rotating the symmetrical chip layout once every 45 degrees.

[0042] In the embodiments of this application, a symmetrical chip layout and a rotated chip layout can be used as reference chip layouts. To make it clear, first, a rotation process is performed on a sample chip layout to obtain a rotated chip layout, and then a mirror inversion process is performed on the sample chip layout and the rotated chip layout to obtain a symmetrical chip layout. Subsequently, the symmetrical chip layout and the rotated chip layout can be used as reference chip layouts, and the number of reference chip layouts is at least one. To make it clear, the rotated chip layout here may also be called the sample chip layout after the rotation process, and is abbreviated as the rotated chip layout. The symmetrical chip layout here may also be called the sample chip layout after the mirror inversion process, and the rotated chip layout after the mirror inversion process, and is abbreviated as the rotated chip layout. That is, a rotation is performed on the sample chip layout to obtain the rotated chip layout, and then a mirror inversion is performed on the sample chip layout and the rotated chip layout to obtain the inverted chip layout. At least one reference chip layout includes the rotated chip layout and the inverted chip layout. The implementation forms of the rotation process and the mirror inversion process are described above and will not be explained in detail here.

[0043] In the embodiments of this application, performing a mirror inversion process on a chip layout (e.g., the previously mentioned sample chip layout, symmetric chip layout, and rotating chip layout, etc.) means adjusting the positional information of each pixel point in the chip layout according to the mirror information so that the adjusted positional information of any one pixel point and the positional information of that pixel point satisfy mirror symmetry. The symmetric chip layout obtained after the mirror inversion process includes the adjusted positional information of each pixel point.

[0044] Based on a similar principle, performing a rotation process on a chip layout means adjusting the positional information of each pixel point in the chip layout according to the rotation parameter, so that the adjusted positional information of any one pixel point and the positional information of that pixel point satisfy the rotation transformation. The rotated chip layout obtained after the rotation process includes the adjusted positional information of each pixel point.

[0045] As can be seen from this, performing a geometric transformation on the sample chip layout adjusts the positional information of each pixel point in the sample chip layout, and the reference chip layout contains the adjusted positional information of each pixel point. To understand this, the adjacency relationships between pixel points in the sample chip layout are the same as the adjacency relationships between pixel points in the reference chip layout, and the adjacency relationship between pixel points refers to whether or not two pixel points are adjacent to each other. In other words, if two pixel points are adjacent in the sample chip layout, then these two pixel points are also adjacent in the reference chip layout.

[0046] In the embodiments of this application, a reference chip layout can be obtained by performing mirror inversion and rotation on a sample chip layout, a reference chip layout can be obtained by performing rotation on a symmetric chip layout, and a reference chip layout can be obtained by performing mirror inversion on a rotated chip layout. By determining the reference chip layout using multiple methods, the diversity of reference chip layouts can be improved, a relatively strong generalization capability can be given to the chip layout encoder obtained by training with the reference chip layout, and the ability to represent layout features can be improved. As a result, the accuracy of the clustering results can be improved when performing clustering on the chip layout based on the layout features.

[0047] Step 203: Use the initial encoder to extract the sample layout features of the sample chip layout and the reference layout features of each reference chip layout.

[0048] Selectively, sample layout features may also be called layout features of the sample chip layout, and reference layout features may also be called layout features of the reference chip layout. Extracting layout features using an initial encoder is equivalent to extracting layout features by the initial encoder. In this case, step 203 may also be said to be extracting layout features of the sample chip layout and layout features of each reference chip layout by the initial encoder.

[0049] A sample chip layout can be input to an initial encoder, which then performs feature extraction on the sample chip layout to obtain its layout features. Similarly, any one reference chip layout can be input to the initial encoder, which then performs feature extraction on the reference chip layout to obtain its layout features. The following description will focus on the method by which the initial encoder performs feature extraction on the sample chip layout. However, the method by which the initial encoder performs feature extraction on the reference chip layout is similar to the method by which the initial encoder performs feature extraction on the sample chip layout, and therefore will not be explained in detail again below.

[0050] In one possible implementation, the step in step 203, "the step of extracting layout features of the sample chip layout using an initial encoder," includes the step of performing multiple downsampling operations on the sample chip layout using the initial encoder (i.e., using the initial encoder) to obtain each downsampling feature. Each downsampling feature is a downsampling feature obtained in each downsampling operation, and the layout features of the sample chip layout are sample layout features, which are downsampling features obtained in the last downsampling operation.

[0051] In the embodiment of the present invention, the initial encoder includes at least two convolutional blocks, where the input to the next convolutional block is the output of the previous convolutional block. Based on this, a sample chip layout is input to the initial encoder and subjected to multiple downsampling processes by at least two convolutional blocks, with the output of each convolutional block being one downsampled feature. Optionally, the output of each convolutional block has half the characteristic dimensions and double the number of channels compared to the input of the convolutional block. The final output of the initial encoder may be a one-dimensional feature vector, for example, with dimensions (1,1,1024). The one-dimensional feature vector is a layout feature of the sample chip layout.

[0052] In an exemplary embodiment, the step of "performing multiple downsampling operations on a sample chip layout using an initial encoder to obtain each downsampling feature" includes the steps of: performing a first downsampling operation on the sample chip layout using an initial encoder to obtain the first downsampling feature; and, using the initial encoder, performing a subsequent downsampling operation on one of the downsampling features obtained in any one downsampling operation to obtain the downsampling feature obtained in the subsequent downsampling operation.

[0053] In other words, after inputting the sample chip layout to the initial encoder, the initial encoder maps the sample chip layout as an initial feature and performs downsampling on the initial feature of the sample chip layout using the first of at least two convolutional blocks to obtain the first downsampled feature. Subsequently, the second of at least two convolutional blocks performs downsampling on the first downsampled feature to obtain the second downsampled feature, and so on. This process continues until the last downsampled feature is obtained, which is the layout feature of the sample chip layout.

[0054] In other words, after inputting the sample chip layout into the initial encoder, the first of at least two convolutional blocks performs downsampling on the initial features mapped from the sample chip layout to obtain the first downsampled feature. For the i-th convolutional block (where i is a positive integer greater than 1), the i-th convolutional block performs downsampling on the (i-1)th downsampled feature to obtain the i-th downsampled feature. Assuming there are a total of M convolutional blocks, the M-th downsampled feature obtained by the M-th convolutional block is the layout feature of the sample chip layout.

[0055] By performing multiple downsampling operations on the sample chip layout, the dimensionality of the downsampled features is continuously reduced, improving the expressive power of the downsampled features, i.e., improving the expressive power of the layout features of the sample chip layout.

[0056] Selectively, a convolutional block includes one convolutional layer, each convolutional layer consisting of at least one 3x3 filter, and the number of filters in the previous convolutional block is less than the number of filters in the next convolutional block. Here, the convolutional layer is used to perform a convolution on the initial features of the sample chip layout or downsampled features to obtain convolutional features. If a convolutional block includes only a convolutional layer, the convolution process corresponds to a downsampled process, and the convolutional features correspond to downsampled features.

[0057] Selectively, a convolutional block includes a series-connected convolutional layer and a batch normalization layer. The batch normalization layer is used to perform batch normalization on the convolutional features to obtain batch normalized features. If the convolutional block includes only a convolutional layer and a batch normalization layer, the downsampling process includes the convolution process and the batch normalization process, and the batch normalized features correspond to the downsampling features.

[0058] Selectively, a convolutional block includes a series-connected convolutional layer, a batch normalization layer, and an activation layer. The activation layer is used to perform an activation process on the batch normalization features to obtain activated features. If the convolutional block includes only a convolutional layer, a batch normalization layer, and an activation layer, then the downsampling process includes the convolution process, the batch normalization process, and the activation process, and the activated features correspond to the downsampling features. Here, the activation layer can employ a rectified linear unit (ReLU), also known as a modified linear unit.

[0059] As shown in Figure 4, Figure 4 is a schematic diagram of the Unet framework provided by an embodiment of the present application. The Unet framework includes an encoder, which is the initial encoder in an embodiment of the present application. The encoder includes eight convolutional blocks, each convolutional block including a series-connected convolutional layer, a batch normalization layer, and an activation layer, the activation layer employing a modified linear unit. These eight convolutional blocks include 8, 16, 32, 64, 128, 256, 512, and 1024 3×3 filters, respectively.

[0060] Figure 4 shows the sample chip layout, symmetrical chip layout, and rotational chip layout shown in Figure 3. All of these layouts are input into the Unet framework, and the encoders included in the Unet framework can extract the layout features of these layouts.

[0061] Taking the sample chip layout as an example, the sample chip layout is input into the Unet framework, and the encoder included in the Unet framework performs downsampling on the sample chip layout eight times to obtain eight downsampled features. Assuming the dimensions of the sample chip layout are (256,256,1), the dimensions of these eight downsampled features are (128,128,8), (64,64,16), (32,32,32), (16,16,64), (8,8,128), (4,4,256), and (1,1,1024), respectively. Here, the last downsampled feature is the layout feature of the sample chip layout, and therefore the dimensions of the layout feature of the sample chip layout are (1,1,1024), which is a single one-dimensional feature vector.

[0062] Step 204: Train the initial encoder based on the sample layout features and the reference layout features to obtain the trained encoder.

[0063] To make it easier to understand, the trained encoder may also be called a chip layout encoder. Based on this, step 204 may be said to train the initial encoder based on the layout features of the sample chip layout and the layout features of each reference chip layout to obtain a chip layout encoder.

[0064] Optionally, the trained encoder is used to generate a chip layout and / or to extract features of the chip layout.

[0065] In the embodiments of the present invention, the first loss can be determined based on the layout features of the sample chip layout and the layout features of each reference chip layout. Selectively, for any one of the reference chip layouts, the distance between the layout features of the reference chip layout and the layout features of the sample chip layout can be calculated and referred to as the distance corresponding to the reference chip layout. A weighted calculation (e.g., weighted addition and weighted averaging) can be performed on the distance corresponding to each reference chip layout, and the result of the weighted calculation can be taken as the first loss. Alternatively, an averaging calculation can be performed on the layout features of each reference chip layout to obtain an average layout feature, and the distance between the average layout feature and the layout features of the sample chip layout can be calculated and taken as the first loss.

[0066] For example, by employing equation (1) shown below, an average calculation can be performed on the layout features of each reference chip layout to obtain the average layout features.

[0067]

number

number

[0068] Furthermore, in equation (1), Encoder represents the feature extraction operation, and Σ represents the symbol for an additive function. Therefore, [Equation 3] represents the average layout features, and [Equation 4] represents the layout features of the reference chip layout obtained after performing the nth geometric transformation on the i-th sample chip layout.

[0069]

number

number

[0070] Based on equation (1), the distance between the average layout features and the layout features of the sample chip layout can be calculated by adopting equation (2) shown below, and the first loss can be obtained.

[0071]

number

[0072] Here, Loss rotation This represents the first loss. Encoder(x i ) represents the layout features of the i-th sample chip layout. The total number of sample chip layouts is N+1. Σ represents the notation for an addition function.

[0073] After calculating the first loss, the first loss is used as the loss of the initial encoder, and the initial encoder is trained using the loss of the initial encoder by gradient descent, thereby obtaining the trained initial encoder. Training the initial encoder involves reducing the loss of the initial encoder by adjusting the weights and biases of the neurons in the initial encoder. If the trained initial encoder satisfies the training termination condition, the trained initial encoder is used as the chip layout encoder (i.e., the trained encoder). If the trained initial encoder does not satisfy the training termination condition, the trained initial encoder is used as the initial encoder for the next training round, and the next training round is performed on the initial encoder according to the training method used for the chip layout encoder provided in the embodiment of this application, continuing until a chip layout encoder is obtained.

[0074] The embodiments of this application are not limited to satisfying the training termination condition. Exemplaryly, satisfying the training termination condition means that the number of training iterations reaches a target number (e.g., 500 iterations). Alternatively, when training an initial encoder using the loss of the initial encoder by gradient descent, it is necessary to determine the gradient of the loss of the initial encoder, and by adjusting the parameters of the initial encoder based on this gradient, the gradient of the loss of the initial encoder determined in the next training iteration is made smaller than the gradient of the loss of the initial encoder determined in the current training iteration. The training termination condition is determined to be satisfied when the gradient difference between the gradient of the loss of the initial encoder determined in the next training iteration and the gradient of the loss of the initial encoder determined in the current training iteration is smaller than the difference threshold. In other words, the gradient difference is obtained by subtracting the gradient of the loss of the initial encoder determined in the next training iteration from the gradient of the loss of the initial encoder determined in the current training iteration, and if the gradient difference is smaller than the difference threshold, the training termination condition is satisfied. In this case, satisfying the training termination condition corresponds to the descent range of the gradient of the loss of the initial encoder being within the range of the difference threshold. The embodiments of this application do not limit the method for determining the differential threshold. For example, the differential threshold may be determined based on human experience, or the data range may be artificially set, and the differential threshold may be randomly generated data within that data range.

[0075] One point that needs to be explained is that the first loss is determined based on the layout features of the sample chip layout and the layout features of each reference chip layout. Therefore, by using the first loss to train the initial encoder, the layout features of the sample chip layout extracted by the initial encoder and the layout features of the reference chip layout can be made closer to each other. Since the reference chip layout is obtained by performing a geometric transformation on the sample chip layout, the reference chip layout and the sample chip layout belong to the same type of chip layout. In the process of training the initial encoder, the layout features extracted by the initial encoder can continuously tend to represent the chip layout category, and the chip layout encoder obtained after final training will focus on extracting layout features that can represent the chip layout category. The layout features extracted by the chip layout encoder can represent the chip layout before and after the geometric transformation, and therefore the layout features extracted by the chip layout encoder have the characteristic of not changing before and after the geometric transformation. Thus, the first loss is a loss that can express that it does not change before and after the geometric transformation.

[0076] In one possible implementation, the training method used for a chip layout encoder further includes step 205, where step 205 is performed after step 203.

[0077] Step 205: Determine the reconstructed chip layout based on the layout characteristics of the sample chip layout. That is, the reconstructed chip layout is determined based on the characteristics of the sample layout, and the reconstructed chip layout is a chip layout reconstructed based on the layout characteristics of the sample chip layout.

[0078] In the embodiment of the present invention, the layout features of a sample chip layout are input to an initial decoder, and the initial decoder reconstructs a new chip layout based on the layout features of the sample chip layout, thereby obtaining the reconstructed chip layout. The embodiment of the present invention does not limit the structure and size of the initial decoder, and exemplarily, the initial decoder is a decoder in the Unet framework.

[0079] In one possible implementation, step 205 includes a step of performing multiple upsampling operations on the layout features of the sample chip layout to obtain each upsampling feature, where each upsampling feature is obtained in each upsampling operation. Alternatively, multiple upsampling operations are performed on the sample layout features to obtain each upsampling feature obtained in each upsampling operation. The reconstructed chip layout is the chip layout obtained based on the upsampling feature obtained in the last upsampling operation.

[0080] In the embodiment of the present invention, the initial decoder includes at least two deconvolution blocks, wherein the output of the previous deconvolution block is the input of the next deconvolution block. Selectively, the output of each deconvolution block has twice the characteristic dimensions and half the number of channels compared to the input of that deconvolution block. The characteristic dimensions ultimately output by the initial decoder match the dimensions of the sample chip layout input to the initial encoder.

[0081] In other words, after inputting the layout features of the sample chip layout into the initial decoder, the layout features of the sample chip layout are upsampled by the first of at least two deconvolution blocks to obtain the first upsampled feature. Subsequently, the first upsampled feature is upsampled by the second of at least two deconvolution blocks to obtain the second upsampled feature, and so on. This process continues until the last upsampled feature is obtained, and this last upsampled feature can be mapped as a single chip layout, which is the reconstructed chip layout.

[0082] In other words, after inputting the layout features of the sample chip layout into the initial decoder, the first of at least two deconvolution blocks upsamples the layout features of the sample chip layout to obtain the first upsampled feature. For the i-th deconvolution block (where i is a positive integer greater than 1), the i-th deconvolution block upsamples the (i-1)th upsampled feature to obtain the i-th upsampled feature. Assuming there are a total of M deconvolution blocks, the M-th upsampled feature obtained by the M-th deconvolution block can be mapped as the reconstructed chip layout.

[0083] Selectively, a deconvolution block includes one deconvolution layer, the deconvolution layer consists of at least one 3x3 filter, and the number of filters in the previous deconvolution block is greater than the number of filters in the next deconvolution block. Here, the deconvolution layer is used to deconvolve a layout feature of a sample chip layout or an upsampling feature to obtain a deconvolution feature. If a deconvolution block includes only a deconvolution layer, the deconvolution process corresponds to an upsampling process, and the deconvolution feature corresponds to an upsampling feature.

[0084] Selectively, a deconvolution block includes a series-connected deconvolution layer and a batch normalization layer. The batch normalization layer is used to perform batch normalization on the deconvolution features to obtain batch normalized features. If the deconvolution block includes only a deconvolution layer and a batch normalization layer, the upsampling process includes the deconvolution process and the batch normalization process, and the batch normalized features correspond to the upsampling features.

[0085] Selectively, a deconvolution block includes a series-connected deconvolution layer, a batch normalization layer, and an activation layer. The activation layer is used to perform an activation process on the batch normalization feature to obtain the activation feature. If the deconvolution block includes only the deconvolution layer, batch normalization layer, and activation layer, then the upsampling process includes the deconvolution process, batch normalization process, and activation process, and the activation feature corresponds to the upsampling feature. Here, the activation layer can employ either a Leaky-ReLU activation function or a sigmoid activation function.

[0086] The step of performing multiple upsampling operations on the layout features of a sample chip layout to obtain each upsampling feature, as selectable, includes steps A1 to A4 shown below.

[0087] Step A1: The first upsampling process is performed on the layout features of the sample chip layout (i.e., sample layout features) to obtain the first upsampling feature. The layout features of the sample chip layout (i.e., sample layout features) are obtained by performing multiple downsampling processes on the sample chip layout.

[0088] Step 203 mentioned that the layout features of the sample chip layout are obtained by performing multiple downsampling operations on the sample chip layout, so this will not be explained in detail again here. In the embodiment of the present invention, after the layout features of the sample chip layout are input to the initial decoder, the layout features of the sample chip layout are upsampled by the first of at least two deconvolution blocks to obtain the first upsampled features.

[0089] Step A2: For any one upsampling feature obtained in any one upsampling process, a downsampling feature corresponding to that upsampling feature is obtained, and when downsampling is performed on the sample chip layout to obtain a downsampling feature corresponding to any one upsampling feature, the number of downsampling processes is the first number, and when upsampling is performed on the layout features of the sample chip layout (i.e., sample layout features) to obtain any one upsampling feature, the number of upsampling processes is the second number, and the sum of the first number and the second number is the target number.

[0090] In the embodiment of the present invention, the number of convolutional blocks in the initial encoder is the same as the number of deconvolutional blocks in the initial decoder. Therefore, the total number of times the initial encoder performs downsampling is the same as the total number of times the initial decoder performs upsampling. The target count is the total number of times the initial encoder performs downsampling. For example, if the initial encoder performs downsampling a total of 8 times, the target count is 8.

[0091] For the i-th upsampling feature obtained in the i-th upsampling process (where i is a positive integer greater than or equal to 1), the second iteration is i. Since the sum of the first and second iterations is the target iteration, if the target iteration is M, then the first iteration is Mi. The downsampling feature corresponding to the i-th upsampling feature can be determined to be the Mi-th downsampling feature obtained by performing the Mi-th downsampling process on the sample chip layout.

[0092] For example, if the target number of iterations is 8, the downsampling feature corresponding to the first upsampling feature is the seventh downsampling feature, and the downsampling feature corresponding to the second upsampling feature is the sixth downsampling feature, and so on.

[0093] Step A3: Join any one upsampling feature with the downsampling feature corresponding to any one upsampling feature to obtain a joined feature corresponding to any one upsampling feature.

[0094] The i-th upsampling feature and the Mi-th downsampling feature can be joined together to obtain a joined feature corresponding to the i-th upsampling feature.

[0095] Step A4: Upsampling is performed on the spliced ​​feature corresponding to any one of the upsampling features to obtain the next upsampling feature of any one of the upsampling features.

[0096] Upsampling is performed on the spliced ​​feature corresponding to the i-th upsampling feature to obtain the (i+1)th upsampling feature.

[0097] One point that needs to be explained is that when obtaining the last upsampling feature, it is possible to map the last upsampling feature as the reconstructed chip layout. Alternatively, the last upsampling feature and the first downsampling feature can be joined together to obtain a joined feature corresponding to the last upsampling feature, and this joined feature corresponding to the last upsampling feature can be mapped as the reconstructed chip layout.

[0098] As shown in Figure 4, the Unet framework shown in Figure 4 includes a decoder, which is the initial decoder in the embodiment of the present invention. The decoder includes eight deconvolution blocks, each of which includes a series-connected deconvolution layer, a batch normalization layer, and an activation layer. These eight deconvolution blocks include, in order, 1024, 512, 256, 128, 64, 32, 16, and one 3x3 filter, where the activation layers in the first seven deconvolution blocks are all Leaky-ReLU activation functions, and the activation layer in the eighth deconvolution block is a sigmoid activation function. The encoder in the Unet framework has been described above and will not be described in detail again here.

[0099] In the embodiment of this application, the encoder in the Unet Framework performs downsampling on the sample chip layout eight times to obtain eight downsampling features. Upsampling is performed on the eighth downsampling feature to obtain the first upsampling feature. The second upsampling feature is obtained based on the first upsampling feature and the seventh downsampling feature. The third upsampling feature is obtained based on the second upsampling feature and the sixth downsampling feature, and so on. This process continues until the eighth upsampling feature is obtained based on the seventh upsampling feature and the first downsampling feature.

[0100] Here, when obtaining the second upsampling feature based on the first upsampling feature and the seventh downsampling feature, the first upsampling feature and the seventh downsampling feature are joined together to obtain a joined feature corresponding to the first upsampling feature. An upsampling process is then performed on the joined feature corresponding to the first upsampling feature to obtain the second upsampling feature. The method for determining the third to eighth upsampling features is similar to the method for determining the second upsampling feature, and will not be explained in detail again here.

[0101] Assuming the dimensions of the layout feature of the sample chip layout are (1,1,1024) and represent a single one-dimensional feature vector, the dimensions of the eight upsampling features are (2,2,1024), (4,4,512), (8,8,256), (16,16,128), (32,32,64), (64,64,32), (128,128,16), and (256,256,1). The dimensions of the reconstructed chip layout obtained based on the eighth upsampling feature are (256,256,1), which matches the dimensions of the sample chip layout.

[0102] In the embodiments of the present application, determining the next upsampling feature of an upsampling feature based on any one upsampling feature and the corresponding downsampling feature essentially involves jointly combining the output of the convolutional block in the initial encoder and the output of the deconvolutional block in the initial decoder to form the input of the next deconvolutional block. This improves the ability of the deconvolutional block to express the upsampling feature obtained after the upsampling process, thereby improving the accuracy of the reconstructed chip layout and bringing the reconstructed chip layout closer to the sample chip layout.

[0103] Selectively, the reconstructed chip layout output by the initial decoder is a binary mask layout. The binary mask layout contains multiple pixel points, and the value of each pixel point represents whether that pixel point is transparent or opaque. Selectively, if the value of a pixel point is a first value, that pixel point represents transparency, and if the value of a pixel point is a second value, that pixel point represents opaque. The first value is any number, for example, the first value is 0. The second value is any number different from the first value, for example, the second value is 1. That is, if the first value is 0 and the second value is 1, then when the value of a pixel point on the binary mask layout is 1, that pixel point represents opaque, and when the value of a pixel point on the binary mask layout is 0, that pixel point represents transparent.

[0104] If a reconstructed chip layout can be obtained, step 204 includes training an initial encoder based on the sample chip layout, the reconstructed chip layout, the layout features of the sample chip layout (i.e., sample layout features), and the layout features of each reference chip layout (i.e., reference layout features) to obtain a chip layout encoder (i.e., a trained encoder).

[0105] The loss of the initial encoder can be determined based on the sample chip layout, the reconstructed chip layout, the layout features of the sample chip layout, and the layout features of each reference chip layout. The loss of the initial encoder is used to train the initial encoder and obtain a chip layout encoder.

[0106] The steps of training an initial encoder and obtaining a chip layout encoder based on a selectable sample chip layout, a reconstructed chip layout, the layout features of the sample chip layout, and the layout features of each reference chip layout include steps B1 to B3 shown below.

[0107] Step B1: Determine the first loss based on the layout characteristics of the sample chip layout (i.e., sample layout characteristics) and the layout characteristics of each reference chip layout (i.e., reference layout characteristics). Here, since the process for determining the first loss has already been described in Step 204, it will not be explained in detail again here.

[0108] Step B2: Determine the second loss based on the sample chip layout and the reconstructed chip layout.

[0109] In the embodiment of the present invention, the sample chip layout and the reconstructed chip layout can be compared at the pixel level, the distance between the sample chip layout and the reconstructed chip layout can be obtained, and this distance can be used as the second loss.

[0110] The second loss is determined by using the following formula (3), which is optional.

[0111]

number

[0112] Here, Loss rebuild x represents the second loss. i This represents the i-th sample chip layout.i(pred) This represents the reconstructed chip layout corresponding to the i-th sample chip layout. The total number of sample chip layouts is N+1. Σ represents the symbol for an addition function.

[0113] Step B3: Train the initial encoder based on the first and second losses to obtain the chip layout encoder (i.e., the trained encoder).

[0114] In the embodiment of the present application, calculations such as addition, weighted addition, averaging, and weighted averaging can be performed on the first loss and the second loss, and the result of the calculation can be determined as the loss of the initial encoder. For example, the loss of the initial encoder is Loss = Loss. rebuild +Loss rotation Therefore, the initial encoder is trained using the loss of the initial encoder, and a chip-layout encoder is obtained.

[0115] Since the second loss is determined based on the sample chip layout and the reconstructed chip layout, the initial encoder can be trained using the second loss. This allows the initial encoder to extract the layout features of the sample chip layout, and then the initial decoder can reconstruct a reconstructed chip layout that is increasingly closer to the sample chip layout based on those layout features. This ensures that the layout features of the sample chip layout accurately represent the sample chip layout and improves the accuracy of the layout features of the sample chip layout.

[0116] One point that needs to be explained is that, in the process of training the initial encoder using the loss of the initial encoder, the initial decoder can be synchronously trained using the loss of the initial encoder, thereby improving the training effect. When applying this, the reconstructed chip layout can be determined based on the layout characteristics of the reference chip layout. The reconstructed chip layout is a chip layout reconfigured based on the layout characteristics of the reference chip layout. By determining the third loss using the reference chip layout and the reconstructed chip layout, and determining the loss of the initial encoder using at least one of the first, second, and third losses, the initial encoder is trained using the loss of the initial encoder, and a chip layout encoder is obtained. Here, the method for determining the reconstructed chip layout is similar to the method for determining the reconstructed chip layout, and the method for determining the third loss is similar to the method for determining the second loss, so it will not be explained in detail again here.

[0117] It is important to explain that the information relating to this application (including, but not limited to, user device information and user personal information), data (including, but not limited to, data used for analysis, stored data, and displayed data), and signals are all authorized by the user or fully authorized by each party, and the collection, use, and processing of the relevant data must comply with the relevant laws, regulations, and standards of the country or region. For example, the sample chip layouts relating to this application were all obtained with full authorization.

[0118] The above method involves performing a geometric transformation on a sample chip layout to obtain a reference chip layout, and then using the layout features of the sample chip layout and the reference chip layout to train an initial encoder and obtain a chip layout encoder. This allows the chip layout encoder to output layout features that are similar to those of the chip layout before and after the geometric transformation. Since the chip layouts before and after the geometric transformation belong to the same type of chip layout, the chip layout encoder is advantageous in that it can focus on extracting layout features that can distinguish chip layout types, and then improves the accuracy of clustering results and reduces redundancy in screening results when clustering and screening processes are performed on the chip layout based on the layout features.

[0119] Embodiments of the present application further provide a chip layout screening method that can be applied in the above-described implementation environment and can accurately screen key chip layouts from multiple target chip layouts. In the example flowchart of the chip layout screening method provided by Embodiments of the present application shown in Figure 5, for convenience of description, the terminal device 101 or server 102 that performs the chip layout screening method in Embodiments of the present application is referred to as an electronic device, and the method may be performed by an electronic device. As shown in Figure 5, the method includes the following steps.

[0120] Step 501: Obtain multiple target chip layouts and the trained encoders.

[0121] The trained encoder may also be called a chip layout encoder. Step 501 may also be described as acquiring multiple target chip layouts and chip layout encoders.

[0122] In the embodiments of this application, any one of the target chip layouts is an IC layout or a sub-region obtained by dividing an IC layout. The method for determining the target chip layout is the same as the method for determining the sample chip layout, and can be found in the description in step 201, so it will not be described in detail again here. The chip layout encoder is obtained by training according to the training method used for the chip layout encoder related to Figure 2, and can be found in the relevant descriptions in steps 201 to 205, so it will not be described in detail again here.

[0123] Step 502: Use the trained encoder to extract the target layout features for each target chip layout.

[0124] Target layout features may also be called layout features of the target chip layout. Step 502 can also be described as extracting the layout features of each target chip layout using a chip layout encoder.

[0125] One of the target chip layouts is input to the chip layout encoder, and the chip layout encoder performs feature extraction on the target chip layout to obtain the layout features of the target chip layout. Here, the method for determining the layout features of the target chip layout is similar to the method for determining the layout features of the sample chip layout, and can be found in the related description in step 203, so it will not be explained in detail again here.

[0126] Step 503: Clustering is performed on multiple target chip layouts based on the characteristics of each target layout to obtain multiple target clustering groups. At least one target chip layout is included in any one of the target clustering groups.

[0127] The layout features of a target chip layout can represent the target chip layout, and by calculating the layout features of each target chip layout, it is possible to concentrate multiple target chip layouts into multiple target clustering groups.

[0128] For example, for any two target chip layouts, the distance between their layout features can be calculated according to a distance formula. If the distance between the layout features of the two target chip layouts is less than a distance threshold, it means that the two target chip layouts are similar, and they are clustered in the same initial clustering group. If the distance between the layout features of the two target chip layouts is greater than or equal to the distance threshold, it means that the two target chip layouts are not similar, and they are clustered in different initial clustering groups. In this manner, multiple target chip layouts can be clustered in multiple initial clustering groups, each initial clustering group containing at least one target chip layout. Selectively, each initial clustering group can be designated as a target clustering group, thereby realizing the clustering of multiple target chip layouts in multiple target clustering groups. The embodiments of this application do not limit the distance formula; for example, the distance formula may be the Euclidean spatial distance formula or the cosine distance formula, etc. The numerical value of the distance threshold can be set empirically.

[0129] In one possible implementation, step 503 includes steps 5031 to 5034.

[0130] Step 5031: Multiple first layout features are obtained, and one first layout feature is used to represent the clustering center of one first clustering group.

[0131] The embodiments of this application do not limit the method by which an electronic device acquires a first layout feature. Exemplarily, multiple first layout features may be placed in the electronic device. Alternatively, a user may input multiple first layout features into the electronic device. Alternatively, the electronic device may concentrate multiple target chip layouts into multiple initial clustering groups, average the layout features of each target chip layout included in any one of the initial clustering groups, and use the resulting result as one first layout feature. In this case, the number of first layout features is the same as the number of initial clustering groups. Alternatively, multiple target chip layouts may be clustered multiple times according to the method of steps 5031 to 5038, and after the last clustering of the multiple clusterings, multiple clustering groups may be obtained, the layout features of each target chip layout included in each clustering group may be averaged, and the resulting results may be used as each first layout feature. One first layout feature is a desired clustering center of one first clustering group and can represent the clustering center of the first clustering group.

[0132] Step 5032: Calculate the distance between each target chip layout's layout feature (i.e., target layout feature) and each first layout feature. For example, the distance between any one target chip layout's layout feature and any one first layout feature can be calculated according to the Euclidean spatial distance formula or the cosine distance formula, etc.

[0133] Step 5033: For any one target chip layout, select the smallest first distance from the distance between the layout features of any one target chip layout (i.e., target layout features) and each first layout feature, and concentrate any one target chip layout to the first clustering group corresponding to the first layout feature corresponding to the first distance.

[0134] In the embodiments of this application, the smaller the distance between the layout features of the target chip layout and the first layout features, the more similar the layout features of the target chip layout are to the first layout features, and both can represent the same type of chip layout. Based on this principle, the smallest first distance can be selected from the distances between the layout features of any one target chip layout and each of the first layout features, and the first layout feature corresponding to this first distance is the first layout feature that is most similar to the layout features of the target chip layout among all the first layout features. The target chip layout can be concentrated in the first clustering group corresponding to the first layout feature corresponding to the first distance.

[0135] This method allows multiple target chip layouts to be concentrated into multiple first clustering groups. Since each target chip layout within the same first clustering group corresponds to the same type of chip layout, this method enables clustering of each target chip layout according to its type.

[0136] Step 5034: If each first clustering group satisfies the clustering termination conditions, then each first clustering group becomes the target clustering group.

[0137] The embodiments of this application do not limit the case to any one of the first clustering groups satisfying the clustering termination condition. Exemplarily, for any one of the first clustering groups to satisfy the clustering termination condition, it means that the number of clustering operations corresponding to that first clustering group reaches a set number. For example, if the number of clustering operations corresponding to one first clustering group is 50, then when the set number is reached, that first clustering group satisfies the clustering termination condition. It is important to note that other implementations in which any one of the first clustering groups satisfies the clustering termination condition are described below, but these will not be explained in detail here.

[0138] Optionally, for any one of the first clustering groups, the actual clustering center of the first clustering group can be determined based on the layout characteristics of each target chip layout in the first clustering group. Exemplarily, according to the formula (4) shown below, an averaging operation is performed on the layout characteristics of each target chip layout in the i-th first clustering group to obtain the actual clustering center of the first clustering group.

[0139]

Number

[0140] Here, μ i represents the actual clustering center of the i-th first clustering group. C i represents the quantity of target chip layouts included in the i-th first clustering group. x represents the layout characteristics of the target chip layout. Σ is the function symbol of the addition function.

[0141] In one possible implementation, a first clustering operation is performed on multiple target chip layouts a first time, and each first clustering group is obtained after the last clustering operation of the first clustering operation. At this time, the first clustering operation - 1 times has already been completed for multiple target chip layouts, and each clustering group can be obtained after the last clustering operation of the first clustering operation - 1 time. In other words, if M (where M is a positive integer) clustering operations are performed on multiple target chip layouts, and the last clustering operation of the M clustering operations is called the Mth clustering operation, then each first clustering group is obtained after the Mth clustering operation, and each clustering group is obtained after the M-1th clustering operation. In the embodiment of the present invention, the actual clustering center of each clustering group can be obtained. If the error between the actual clustering center of each clustering group and the actual clustering center of each first clustering group is within a set range, it is determined that each first clustering group satisfies the clustering completion condition.

[0142] In another possible implementation, the total clustering error can be obtained by determining the error of a first clustering group based on the layout characteristics of each target chip layout in any one of the first clustering groups and the actual clustering centers of the first clustering group, and then determining the sum of the errors of each first clustering group. Selectively, the sum of the squared differences between the layout characteristics of each target chip layout in any one of the first clustering groups and the actual clustering centers of the first clustering group is calculated according to equation (5) shown below to obtain the error of the first clustering group, and the sum of the errors of each first clustering group is taken as the total clustering error.

[0143]

number

[0144] Here, Error represents the total clustering error. N represents the number of the first clustering group. μ i This represents the actual clustering center of the i-th first clustering group. i x represents the number of target chip layouts included in the i-th first clustering group. x represents the layout features of the target chip layout. Σ is the function symbol for the addition function.

[0145] In one possible implementation, each first clustering group is determined to satisfy the clustering termination condition when the total clustering error of each first clustering group is smaller than the set total error. Alternatively, clustering is performed a first number of times on multiple target chip layouts to obtain each first clustering group. At this time, the total clustering error of each clustering group obtained after performing clustering a first number of times minus 1 times on the target chip layout can be obtained. If the difference between the total clustering error of each clustering group and the total clustering error of each first clustering group is within the set range, each first clustering group is determined to satisfy the clustering termination condition.

[0146] When each first clustering group satisfies the clustering termination conditions, each first clustering group becomes a target clustering group.

[0147] Optionally, after step 5033, steps 5035 to 5038 are further included.

[0148] Step 5035: If each first clustering group does not satisfy the clustering termination condition, a second layout feature is determined for any one of the first clustering groups based on the layout features of each target chip layout in that one first clustering group. The second layout feature is used to represent the clustering center of the second clustering group.

[0149] The fact that each first clustering group does not satisfy the clustering termination condition corresponds to the existence of multiple first clustering groups that do not satisfy the clustering termination condition. In this case, the actual clustering center of one of the first clustering groups can be determined based on the layout features of each target chip layout in that first clustering group (i.e., the target layout features), and the actual clustering center of that first clustering group can be made into a single second layout feature. This second layout feature is the desired clustering center of a single second clustering group and can represent the clustering center of that second clustering group.

[0150] Step 5036: Calculate the distance between the layout features of each target chip layout (i.e., the target layout features) and each second layout feature. For example, the distance between the layout features of any one target chip layout and any one second layout feature can be calculated according to the Euclidean spatial distance formula or the cosine distance formula, etc.

[0151] Step 5037: For any one target chip layout, select the smallest second distance from the distance between the layout features of any one target chip layout (i.e., target layout features) and each second layout feature, and concentrate any one target chip layout to the second layout feature corresponding to the second distance and the corresponding second clustering group.

[0152] The smaller the distance between the layout features of the target chip layout and the second layout features, the more similar the layout features of the target chip layout are to the second layout features, and the two can represent the same type of chip layout. Based on this principle, the smallest second distance can be selected from the distances between the layout features of any one target chip layout and each second layout feature. The second layout feature corresponding to this second distance is the second layout feature that is most similar to the layout features of the target chip layout among all the second layout features. The target chip layout can then be concentrated in the second clustering group corresponding to the second layout feature corresponding to the second distance.

[0153] This method allows multiple target chip layouts to be concentrated into multiple second clustering groups. Since each target chip layout within the same second clustering group corresponds to the same type of chip layout, this method enables clustering of each target chip layout according to its type.

[0154] Step 5038: If each second clustering group satisfies the clustering termination conditions, then each second clustering group becomes the target clustering group.

[0155] When each second clustering group satisfies the clustering termination condition, each second clustering group is designated as a target clustering group. If each second clustering group does not satisfy the clustering termination condition, the multiple target chip layouts can be clustered again according to the method in steps 5035 to 5038, and this process continues until a target clustering group is obtained.

[0156] The method described in steps 5031 to 5038 allows for the clustering of multiple target chip layouts multiple times, continuously changing the clustering center of each clustering group. Each target chip layout within the same clustering group becomes increasingly similar, while the target chip layouts in different clustering groups become increasingly different. This process continues until the clustering termination condition is met. Meeting the clustering termination condition corresponds to the convergence of the clustering group, and the clustering center of the clustering group ceases to fluctuate. Therefore, the error in the target clustering group obtained after clustering multiple target chip layouts multiple times using the method described in steps 5031 to 5038 is relatively small, and the accuracy is relatively high.

[0157] Step 504: For any one of the target clustering groups, screen for a key chip layout from among the target chip layouts included in that one of the target clustering groups.

[0158] In the embodiment of the present invention, each target chip layout included in a target clustering group belongs to the same type of chip layout. Therefore, a key chip layout can be obtained by randomly sampling from each target chip layout included in any one of the target clustering groups. The number of key chip layouts is at least one. By clustering each target chip layout to obtain each target clustering group, and then screening the key chip layout from the target chip layouts included in each target clustering group, it is possible to avoid manually selecting a key chip layout from all target chip layouts and prevent interference with the final result due to human experience and random selection.

[0159] In one possible implementation, step 504 includes the steps of: obtaining the distance between the layout features of each target chip layout in any one target clustering group and the clustering center of any one target clustering group; and uniformly sampling each target chip layout included in any one target clustering group based on the distance between the layout features of each target chip layout in any one target clustering group and the clustering center of any one target clustering group to obtain a plurality of key chip layouts.

[0160] In the embodiments of the present invention, the clustering center of any one target clustering group may be the desired clustering center of that target clustering group, or it may be the actual clustering center of that target clustering group. Here, the calculation method for the desired clustering center of the target clustering group can refer to the relevant content for determining the second layout feature, and the implementation principles of both are similar. The calculation method for the actual clustering center of the target clustering group can refer to the relevant content for determining the actual clustering center of the first clustering group, and the implementation principles of both are similar.

[0161] For any one target clustering group, the distance between the layout features of any one target chip layout included in the target clustering group and the clustering center of the target clustering group can be calculated according to the Euclidean spatial distance formula or the cosine distance formula, etc. This method allows us to obtain the distance between the layout features of each target chip layout in the target clustering group and the clustering center of the target clustering group.

[0162] Selectively, the maximum distance is determined from the distance between the layout features of each target chip layout in the target clustering group and the clustering center of the target clustering group, and the sampling interval is obtained by dividing the maximum distance by the number of samples. From the distance between the layout features of each target chip layout in the target clustering group and the clustering center of the target clustering group, sampling distances that satisfy an integer multiple of the sampling interval are screened. One key chip layout is sampled from the target chip layouts corresponding to the sampling distance.

[0163] As an example, assume there are M target clustering groups and the number of samples is L+1. For any one of the target clustering groups, the maximum distance is determined from the distance between the layout feature of each target chip layout in that target clustering group and the clustering center of that target clustering group, and the sampling interval is obtained by dividing the maximum distance by L+1. From the distance between the layout feature of each target chip layout in the target clustering group and the clustering center of that target clustering group, sampling distances of 0, 1*sampling interval, 2*sampling convolution, ..., and (L+1)*sampling interval are screened, and a total of L+2 target chip layouts are sampled from the target chip layouts corresponding to these sampling distances. Here, the layout feature of the target chip layout corresponding to sampling distance 0 is the clustering center of the target clustering group, and the distance between the layout feature of the target chip layout corresponding to sampling distance "(L+1)*sampling interval" and the clustering center of the target clustering group is the maximum distance. Since one target clustering group can sample L+2 target chip layouts, M target clustering groups can sample a total of M × (L+2) target chip layouts.

[0164] In one possible implementation, after step 504, the further steps include: performing light source mask optimization on a key chip layout to obtain a target light source and a mask layout corresponding to the key chip layout; and performing mask optimization on other chip layouts based on the target light source to obtain a mask layout corresponding to the other chip layouts, wherein the other chip layouts are target chip layouts other than the key chip layout among the target chip layouts.

[0165] In the embodiments of this invention, performing light source mask optimization on a key chip layout is equivalent to performing combined source and mask optimization (SMO) on the key chip layout, thereby obtaining a target light source and a mask layout corresponding to the key chip layout. Here, SMO is an important resolution improvement technique for realizing nanometer (e.g., 28 nanometers, and even smaller nanometers) integrated circuits. By screening key chip layouts from target chip layouts and performing SMO on the key chip layouts, the number of key chip layouts can be made smaller than the number of target chip layouts, thereby improving the speed of SMO. Furthermore, by clustering the target chip layouts and screening key chip layouts from the target chip layouts included in each clustering group, it is possible to ensure that the key chip layouts cover various chip layout types. In addition, because the redundancy phenomenon of key chip layouts is relatively small, the accuracy of the target light source obtained by performing SMO on the key chip layout is relatively high, improving the efficiency and effect of SMO.

[0166] SMO belongs to a type of Source Optimization (SO) technique. SMO technology can adjust the intensity and direction of incident light by changing the intensity distribution of the light source, thereby improving the quality of the imaged layout obtained by exposing a mask layout onto a wafer using the light source, and contributing to improved chip yield. When performing SMO on a key chip layout according to the method of the embodiment of this application, the speed and effect of SMO can be improved, so the embodiment of this application can improve photolithography resolution and increase the photolithography process window. Furthermore, the target chip layout in the embodiment of this application is a layout represented by pixels, and therefore has relatively high versatility and can be applied to chip layout types such as contact hole type, logic layout type, and dense line type.

[0167] When performing any one SMO, an arbitrary light source is used as the initial light source, the photolithography apparatus is operated, and the key chip layout is exposed onto the photoresist based on the initial light source to obtain an intermediate mask layout. The photolithography apparatus is then operated again, and the intermediate mask layout is exposed onto the wafer using the initial light source to obtain an image layout. By comparing the image layout with the key chip layout, the error between the image layout and the key chip layout is obtained.

[0168] Selectively, if the error between the imaging layout and the key chip layout satisfies the optimization conditions, the initial light source is set as the target light source and the intermediate mask layout is set as the mask layout corresponding to the key chip layout. The mask layout corresponding to the key chip layout is used to expose the mask layout corresponding to the key chip layout onto the wafer using the target light source by operating the photolithography apparatus, thereby obtaining the imaging layout corresponding to the key chip layout. If the error between the imaging layout and the key chip layout does not satisfy the optimization conditions, the initial light source is adjusted based on the error between the imaging layout and the key chip layout to obtain the adjusted initial light source. The adjusted initial light source is set as the initial light source for the next SMO, and at least one SMO as described above is performed based on this initial light source, continuing until the target light source and the mask layout corresponding to the key chip layout are obtained.

[0169] Selectively, the optimization condition is met if the error between the imaging layout and the key tip layout is within a set error range. Alternatively, the optimization condition is met if the gradient of the error between the imaging layout and the key tip layout is smaller than a set gradient threshold, in which case the initial light source can be adjusted based on the gradient of the error between the imaging layout and the key tip layout when adjusting the initial light source based on the error between the imaging layout and the key tip layout.

[0170] Subsequently, the photolithography apparatus is operated to expose the other chip layout onto the photoresist based on the target light source, thereby obtaining a mask layout corresponding to the other chip layout. The mask layout corresponding to the other chip layout is used to expose the mask layout corresponding to the other chip layout onto the wafer using the target light source by operating the photolithography apparatus, thereby obtaining an imaging layout corresponding to the other chip layout.

[0171] If, for selectable purposes, the key chip layout and other chip layouts are obtained by dividing a single chip layout, then, after optimizing the light source mask for the key chip layout to obtain a target light source, the photolithography apparatus is operated to expose this chip layout onto a photoresist based on the target light source, thereby obtaining a mask layout corresponding to this chip layout. This mask layout corresponding to the chip layout is used to expose the mask layout corresponding to this chip layout onto a wafer using the target light source by operating the photolithography apparatus, thereby obtaining an imaging layout corresponding to this chip layout.

[0172] It is important to explain that the information relating to this application (including, but not limited to, user device information and user personal information), data (including, but not limited to, data used for analysis, stored data, and displayed data), and signals are all authorized by the user or fully authorized by each party, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the country or region. For example, the target chip layouts relating to this application were all obtained with full authorization.

[0173] The chip layout encoder in the above method focuses on extracting layout features that can distinguish chip layout types. Therefore, when extracting layout features of each target chip layout using the chip layout encoder and performing clustering on multiple target chip layouts based on the layout features of each target chip layout, it is possible to accurately concentrate target chip layouts of the same chip layout type into the same target clustering group and concentrate target chip layouts of different chip layout types into different target clustering groups, thereby improving the accuracy of the clustering results. When screening key chip layouts from among the target chip layouts included in any one of the target clustering groups, it is possible to reduce the redundancy of key chip layouts and improve the screening quality.

[0174] The above describes the training method and chip layout screening method used for the chip layout encoder provided by the embodiment of the present application from the perspective of the steps of the method. Further details will be provided below in conjunction with Figure 6. Figure 6 is a schematic diagram of the chip layout encoder provided by the embodiment of the present application and the clustering and screening performed based on the chip layout encoder.

[0175] In the embodiment of the present invention, a sample dataset can be obtained, and an initial encoder can be trained using the sample dataset according to the training method used for the chip layout encoder related to Figure 2 to obtain a chip layout encoder. The sample dataset in the embodiment of the present invention includes two open-source datasets. One dataset contains 4877 chip layouts, and these 4877 chip layouts, or a selection of chip layouts extracted from these 4877 chip layouts, can be used as sample chip layouts. The other dataset contains 5394 chip layouts, and these 5394 chip layouts, or a selection of chip layouts extracted from these 5394 chip layouts, can be used as sample chip layouts. The sample chip layouts are used to train the initial encoder. Furthermore, the sample dataset in the embodiment of the present invention further includes several contact-hole type chip layouts, logic layout type chip layouts, and dense-line type chip layouts, etc.

[0176] After training and obtaining a chip layout encoder, it can be used to screen for a key chip layout from multiple target chip layouts. The structure of the chip layout encoder can be found in the relevant description in Figure 4 and will not be described in detail again here.

[0177] In the embodiment of the present invention, a chip layout encoder can be used to extract the layout features of each target chip layout. Subsequently, each target chip layout is clustered based on its layout features to obtain a plurality of target clustering groups. Each target clustering group contains at least one target chip layout. Subsequently, key chip layouts can be screened from each target clustering group. For example, for any one target clustering group, key chip layouts can be screened from each target chip layout included in that target clustering group.

[0178] The above-described chip layout encoder focuses on extracting layout features that can distinguish chip layout types. Therefore, when extracting layout features of each target chip layout using the chip layout encoder and performing clustering on multiple target chip layouts based on the layout features of each target chip layout, the accuracy of the clustering results can be improved. Furthermore, when screening key chip layouts from each target clustering group, the redundancy of key chip layouts can be reduced, improving the screening quality.

[0179] Figure 7 shows a schematic diagram of the structure of a training device used in a chip layout encoder provided in the embodiment of the present application. As shown in Figure 7, the device is An acquisition module 701 used to acquire a sample chip layout and an initial encoder, A conversion module 702 is used to perform geometric transformations on a sample chip layout to obtain at least one reference chip layout, An extraction module 703 used to extract layout features of a sample chip layout and layout features of each reference chip layout using an initial encoder, or an extraction module 703 used to extract sample layout features of a sample chip layout and reference layout features of each reference chip layout using an initial encoder, A training module 704 is used to train an initial encoder and obtain a chip layout encoder (i.e., a trained encoder) based on the layout features of a sample chip layout (i.e., sample layout features) and the layout features of each reference chip layout (i.e., reference layout features), the chip layout encoder includes a training module 704 used to extract the layout features of a target chip layout.

[0180] In one possible implementation, the conversion module 702 is used to perform a mirror inversion on a sample chip layout to obtain a symmetric chip layout, to perform a rotation on the sample chip layout and the symmetric chip layout to obtain a rotated chip layout, and to make the symmetric chip layout and the rotated chip layout into at least one reference chip layout. Alternatively, the conversion module 702 is used to perform a mirror inversion on a sample chip layout to obtain a reversed chip layout, to perform a rotation on the sample chip layout and the reversed chip layout to obtain a rotated chip layout, and at least one reference chip layout includes the reversed chip layout and the rotated chip layout.

[0181] In one possible implementation, the conversion module 702 is used to perform a mirror inversion on a sample chip layout to obtain a symmetric chip layout, and to make the symmetric chip layout at least one reference chip layout, or to perform a rotation on a sample chip layout to obtain a rotated chip layout, and to make the rotated chip layout at least one reference chip layout. Alternatively, the conversion module 702 is used to perform a mirror inversion on a sample chip layout to obtain a chip layout after inversion, wherein at least one reference chip layout includes the chip layout after inversion, or to perform a rotation on a sample chip layout to obtain a chip layout after rotation, wherein at least one reference chip layout includes the chip layout after rotation.

[0182] In one possible implementation, the conversion module 702 is used to perform a rotation on a sample chip layout to obtain a rotated chip layout, to perform a mirror inversion on the sample chip layout and the rotated chip layout to obtain a symmetrical chip layout, and to make the symmetrical chip layout and the rotated chip layout into at least one reference chip layout. Alternatively, the conversion module 702 is used to perform a rotation on a sample chip layout to obtain a rotated chip layout, to perform a mirror inversion on the sample chip layout and the rotated chip layout to obtain an inverted chip layout, and at least one reference chip layout includes the rotated chip layout and the inverted chip layout.

[0183] In one possible implementation, the extraction module 703 is used to perform multiple downsampling operations on the sample chip layout using the initial encoder (i.e., using ), and to obtain downsampling features obtained in each downsampling operation. The layout features of the sample chip layout are the downsampling features obtained in the final downsampling operation.

[0184] In one possible implementation, the device is A reconfiguration module used to determine a reconfigured chip layout based on the layout characteristics of a sample chip layout, wherein the reconfigured chip layout is a chip layout reconfigured based on the layout characteristics of the sample chip layout. The system further includes a training module 704 used to train an initial encoder and obtain a chip layout encoder based on a sample chip layout, a reconstructed chip layout, the layout features of the sample chip layout, and the layout features of each reference chip layout.

[0185] In one possible implementation, the reconstruction module is used to perform multiple upsampling operations on the layout features of the sample chip layout to obtain each upsampling feature, and the reconstructed chip layout is the chip layout obtained based on the upsampling feature obtained in the last upsampling operation.

[0186] In one possible implementation, the reconstruction module performs a first upsampling operation on the layout features of the sample chip layout to obtain the first upsampling feature, wherein the layout features of the sample chip layout are obtained by performing multiple downsampling operations on the sample chip layout, and for any one upsampling feature obtained in any one upsampling operation, a downsampling feature corresponding to any one upsampling feature is obtained when performing a downsampling operation on the sample chip layout to obtain a downsampling feature corresponding to any one upsampling feature. The number of ring processing steps is the first step, and the number of upsampling steps when performing upsampling on the layout features of the sample chip layout to obtain one upsampling feature is the second step, and the sum of the first and second steps is the target step. It is used to combine one upsampling feature with a downsampling feature corresponding to one upsampling feature to obtain a combined feature corresponding to one upsampling feature, and to perform upsampling on the combined feature corresponding to one upsampling feature to obtain the next upsampling feature of one upsampling feature.

[0187] In one possible implementation, the training module 704 is used to determine a first loss based on the layout features of a sample chip layout and the layout features of each reference chip layout, to determine a second loss based on the sample chip layout and the reconstructed chip layout, and to train an initial encoder based on the first and second losses to obtain a chip layout encoder.

[0188] The above device obtains a chip layout encoder by performing a geometric transformation on a sample chip layout to obtain a reference chip layout, and then training an initial encoder using the layout features of the sample chip layout and the reference chip layout to obtain a chip layout encoder. As a result, the chip layout encoder can output layout features that are similar to those of the chip layout before and after the geometric transformation. Since the chip layouts before and after the geometric transformation belong to the same type of chip layout, the chip layout encoder has an advantage in that it can focus on extracting layout features that can distinguish chip layout types, and then perform clustering and screening on the chip layout based on the layout features, thereby improving clustering accuracy and reducing redundancy in the screening results.

[0189] As should be understood, the device provided in Figure 7 above was explained by illustrating only the division of each functional module when realizing its function. However, in actual applications, the above functions can be completed by assigning them to different functional modules as needed. That is, all or some of the functions described above can be completed by dividing the internal structure of the device into different functional modules. Furthermore, the device provided in the above embodiment belongs to the same concept as the embodiment of the method, and the details of its specific implementation process can be found in the embodiment of the method, so it will not be explained in detail again here.

[0190] Figure 8 shows a schematic diagram of the structure of a chip layout screening apparatus provided by an embodiment of the present application, and as shown in Figure 8, the apparatus is An acquisition module 801 used to acquire multiple target chip layouts and chip layout encoders (i.e., trained encoders), wherein the chip layout encoders are obtained by training according to a training method used for the chip layout encoders, and the acquisition module 801 is used for acquiring multiple target chip layouts and chip layout encoders (i.e., trained encoders), An extraction module 802 is used to extract the layout features (i.e., target layout features) of each target chip layout using a chip layout encoder, A clustering module 803 used to perform clustering on multiple target chip layouts based on the layout characteristics of each target chip layout (i.e., the characteristics of each target layout) to obtain multiple target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups, The system includes a screening module 804 used to screen for a key chip layout from among the target chip layouts included in any one of the target clustering groups.

[0191] In one possible implementation, the clustering module 803 is used to acquire multiple first layout features, where one first layout feature is used to represent the clustering center of one first clustering group; to calculate the distance between the layout features of each target chip layout and each first layout feature; to select the smallest first distance from the distances between the layout features of any one target chip layout and each first layout feature for any one target chip layout, and to concentrate any one target chip layout into a first clustering group represented by the first layout feature corresponding to the first distance; and, if each first clustering group satisfies the clustering termination condition, to make each first clustering group a target clustering group.

[0192] In one possible implementation, the clustering module 803 is further used to determine a second layout feature for any one of the first clustering groups based on the layout features of each target chip layout in any one of the first clustering groups, if each first clustering group does not satisfy the clustering termination condition, the second layout feature is used to represent the clustering center of the second clustering group; calculate the distance between the layout features of each target chip layout and each second layout feature; select the smallest second distance for any one of the target chip layouts from the distance between the layout features of any one of the target chip layouts and each second layout feature, and concentrate any one of the target chip layouts into a second clustering group represented by the second layout feature corresponding to the second distance; and, if each second clustering group satisfies the clustering termination condition, make each second clustering group a target clustering group.

[0193] In one possible implementation, the screening module 804 is used to obtain the distance between the layout features of each target chip layout in any one target clustering group and the clustering center of any one target clustering group, and to uniformly sample each target chip layout included in any one target clustering group based on the distance between the layout features of each target chip layout in any one target clustering group and the clustering center of any one target clustering group, thereby obtaining a plurality of key chip layouts.

[0194] In one possible implementation, the device is The method further includes performing light source mask optimization on a key chip layout to obtain a target light source and a mask layout corresponding to the key chip layout, and performing mask optimization on other chip layouts based on the target light source to obtain a mask layout corresponding to the other chip layouts, wherein the other chip layouts are target chip layouts other than the key chip layout among the target chip layouts, and an optimization module used in this method.

[0195] The chip layout encoder in the above device focuses on extracting layout features that can distinguish chip layout types. Therefore, when extracting layout features of each target chip layout using the chip layout encoder and performing clustering processing on multiple target chip layouts based on the layout features of each target chip layout, it is possible to accurately concentrate target chip layouts of the same chip layout type into the same target clustering group and concentrate target chip layouts of different chip layout types into different target clustering groups, thereby improving the accuracy of the clustering results. When screening key chip layouts from among the target chip layouts included in any one of the target clustering groups, it is possible to reduce the redundancy of key chip layouts and improve the screening quality.

[0196] As should be understood, the device provided in Figure 8 above illustrates and explains only the division of each functional module when realizing its function. However, in actual applications, the above functions can be completed by assigning them to different functional modules as needed. That is, all or some of the functions described above can be completed by dividing the internal structure of the device into different functional modules. Furthermore, the device provided in the above embodiment belongs to the same concept as the embodiment of the method, and details of its specific implementation process can be found in the embodiment of the method, so it will not be explained in detail again here.

[0197] Figure 9 shows a structural block diagram of a terminal device 900 provided by one exemplary embodiment of the present application. The terminal device 900 includes a processor 901 and memory 902.

[0198] The processor 901 may include one or more processing cores, such as a 4-core processor and an 8-core processor. The processor 901 can be implemented using at least one hardware form from among DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 901 may include a main processor and a coprocessor, the main processor being a processor used to process data in a wake-up state and also called a CPU (Central Processing Unit), and the coprocessor being a low-power processor used to process data in a standby state. In some embodiments, the processor 901 may integrate a GPU (Graphics Processing Unit), which is used to render and draw content that needs to be displayed on a display screen. In some embodiments, the processor 901 may further include an AI (Artificial Intelligence) processor, which is used to process computational operations related to machine learning.

[0199] The memory 902 may include one or more computer-readable storage media, which may be non-temporary. The memory 902 may further include high-speed random-access memory, and non-volatile memory, such as one or more magnetic disk storage devices, and flash memory storage devices. In some embodiments, the non-temporary computer-readable storage media in the memory 902 are used to store at least one computer program, which is executed by the processor 901 to cause the terminal device 900 to implement a training method or a chip layout screening method used for a chip layout encoder provided by embodiments of the method of the present application.

[0200] In some embodiments, the terminal device 900 further optionally includes a display screen 905.

[0201] The display screen 905 is used to display a UI (User Interface). The UI may include shapes, text, icons, videos, and any combination thereof. When the display screen 905 is a touch display screen, the display screen 905 further has the ability to collect touch signals from or above the surface of the display screen 905. These touch signals can be input to the processor 901 as control signals for processing. In this case, the display screen 905 can further be used to provide virtual buttons, also called soft buttons and / or soft keyboards, and / or virtual keyboards. In some embodiments, the display screen 905 may be a single display screen mounted on the front panel of the terminal device 900, and in some other embodiments, the display screen 905 may be at least two display screens, each mounted on a different surface of the terminal device 900 or designed to be foldable. In some other embodiments, the display screen 905 may be a flexible display screen mounted on a curved surface or a foldable surface of the terminal device 900. Furthermore, the display screen 905 may be installed as a non-rectangular, irregular shape, i.e., an irregularly shaped screen. The display screen 905 may be manufactured using materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode). Exemplary examples include chip layouts such as sample chip layouts, rotational chip layouts, and symmetrical chip layouts, which are displayed on the display screen 905.

[0202] As those skilled in the art will understand, the structure shown in Figure 9 does not constitute a limitation on the terminal device 900, and may include more or fewer components than shown, or combine some components, or employ a different component arrangement.

[0203] Figure 10 is a schematic diagram of the structure of a server provided by an embodiment of the present application. The server 1000 may vary considerably due to differences in arrangement or performance, and may include one or more processors 1001 and one or more memories 1002. Here, at least one computer program is stored in the one or more memories 1002, and the at least one computer program is loaded and executed by the one or more processors 1001, thereby enabling the server 1000 to implement a training method or a chip layout screening method used for a chip layout encoder provided by the embodiments of the above methods. Exemplarily, the processor 1001 is a CPU. Of course, the server 1000 may further include components such as a wired or wireless network interface, a keyboard, and an input / output interface, thereby performing input and output, and the server 1000 may further include other components used to realize the functions of the device, which will not be described in detail here.

[0204] In an exemplary embodiment, a non-volatile computer-readable storage medium is further provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor, thereby enabling the electronic device to implement a training method or a chip layout screening method used for any one of the chip layout encoders described above.

[0205] The above-mentioned computer-readable storage medium may be, as selectable, read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices, etc.

[0206] In an exemplary embodiment, a computer program is further provided, which is at least one computer program, and when this at least one computer program is loaded and executed by a processor, the electronic device realizes a training method or a chip layout screening method used for any one of the chip layout encoders described above.

[0207] In an exemplary embodiment, a computer program product is further provided, in which at least one computer program is stored. When this at least one computer program is loaded and executed by a processor, the electronic device realizes a training method or a chip layout screening method used for any one of the chip layout encoders described above.

[0208] It should be understood that, as used herein, “plural” refers to two or more things. “And / or” describes the relationship between related objects and indicates that three types of relationships may exist; for example, A and / or B can indicate three cases: A existing alone, A and B existing together, and B existing alone. The letter “ / ” generally indicates that the preceding and succeeding related objects are in a kind of “or” relationship.

[0209] The numbering of the embodiments in the present application above is for descriptive purposes only and does not indicate any ranking of the embodiments.

[0210] The foregoing are merely illustrative examples of the present application and are not intended to limit it. Any modifications, substitutions with equivalents, and improvements made within the principles of the present application should all be included within the scope of protection.

Claims

1. A method for screening chip layouts, performed by an electronic device, wherein the method is A step of obtaining multiple target chip layouts and trained encoders, wherein the trained encoders are chip layout encoders, Steps include obtaining a sample chip layout and an initial encoder, The steps include performing a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, The steps include: extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder; The steps include determining a reconfigured chip layout based on the aforementioned sample layout characteristics, The steps include training the initial encoder based on the sample chip layout, the reconstructed chip layout, the sample layout features, and the reference layout features, and obtaining the trained encoder, The steps obtained by training using, The steps include: extracting target layout features of each target chip layout using the trained encoder; A step of performing clustering on the plurality of target chip layouts based on the characteristics of each target layout to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups. The steps include: screening key chip layouts from among the target chip layouts included in any one target clustering group; Includes, The step of screening key chip layouts from among the target chip layouts included in any one of the aforementioned target clustering groups is: A step of obtaining the distance between the layout features of each target chip layout in any one of the target clustering groups and the clustering center of any one of the target clustering groups, A chip layout screening method comprising the steps of: uniformly sampling each target chip layout included in the target clustering group based on the distance between the layout characteristics of each target chip layout in the target clustering group and the clustering center of the target clustering group, thereby obtaining a plurality of key chip layouts.

2. A method for screening chip layouts, performed by an electronic device, wherein the method is A step of obtaining multiple target chip layouts and trained encoders, wherein the trained encoders are chip layout encoders, Steps include obtaining a sample chip layout and an initial encoder, The steps include performing a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, The steps include: extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder; The steps include determining a reconfigured chip layout based on the aforementioned sample layout characteristics, The steps include training the initial encoder based on the sample chip layout, the reconstructed chip layout, the sample layout features, and the reference layout features, and obtaining the trained encoder, The steps obtained by training using, The steps include: extracting target layout features of each target chip layout using the trained encoder; A step of performing clustering on the plurality of target chip layouts based on the characteristics of each target layout to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups. The steps include: screening key chip layouts from among the target chip layouts included in any one target clustering group; Includes, After the step of screening key chip layouts from among the target chip layouts included in any one of the aforementioned target clustering groups, The steps include optimizing the light source mask for the aforementioned key chip layout to obtain a target light source and a mask layout corresponding to the aforementioned key chip layout, A chip layout screening method further comprising the steps of: performing mask optimization for other chip layouts based on the target light source to obtain a mask layout corresponding to the other chip layout, wherein the other chip layout is a target chip layout other than the key chip layout among the target chip layouts.

3. The step of performing clustering processing on the plurality of target chip layouts based on the characteristics of each target layout to obtain a plurality of target clustering groups is: A step of obtaining multiple first layout features, wherein one first layout feature is used to represent a clustering center of one first clustering group, A step of calculating the distance between each target layout feature and each first layout feature, For any one target chip layout, the minimum first distance is selected from the distance between the target layout feature of the any one target chip layout and each of the first layout features, and the any one target chip layout is concentrated in the first clustering group corresponding to the first layout feature corresponding to the first distance, The method according to claim 2, further comprising the step of setting each first clustering group as a target clustering group if each first clustering group satisfies the clustering termination condition.

4. The aforementioned method, If none of the first clustering groups satisfy the clustering termination condition, the step of determining a second layout feature for any one of the first clustering groups based on the target layout features in any one of the first clustering groups, wherein the second layout feature is used to represent the clustering center of the second clustering group. A step of calculating the distance between each of the aforementioned target layout features and each of the second layout features, For any one target chip layout, the minimum second distance is selected from the distance between the target layout feature of the any one target chip layout and each of the second layout features, and the any one target chip layout is concentrated in the second clustering group corresponding to the second layout feature corresponding to the second distance, The method according to claim 3, further comprising the step of making each second clustering group one of the target clustering groups if each second clustering group satisfies the clustering termination condition.

5. A chip layout screening apparatus, wherein the apparatus, An acquisition module used to acquire multiple target chip layouts and trained encoders, wherein the trained encoders are chip layout encoders, Steps include obtaining a sample chip layout and an initial encoder, The steps include performing a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, The steps include: extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder; The steps include determining a reconfigured chip layout based on the aforementioned sample layout characteristics, The steps include training the initial encoder based on the sample chip layout, the reconstructed chip layout, the sample layout features, and the reference layout features, and obtaining the trained encoder, The acquired module obtained by training using, An extraction module used to extract target layout features of each target chip layout using the trained encoder, A clustering module used to perform clustering processing on a plurality of target chip layouts based on the characteristics of each target layout, and to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups, A screening module used to screen for a key chip layout from among the target chip layouts included in any one target clustering group, Includes, The aforementioned screening module is The distance between the layout features of each target chip layout in any one of the aforementioned target clustering groups and the clustering center of any one of the aforementioned target clustering groups is obtained. A chip layout screening apparatus further configured to obtain a plurality of key chip layouts by uniformly sampling each target chip layout included in any one of the target clustering groups based on the distance between the layout characteristics of each target chip layout in any one of the target clustering groups and the clustering center of any one of the target clustering groups.

6. A chip layout screening apparatus, wherein the apparatus, An acquisition module used to acquire multiple target chip layouts and trained encoders, wherein the trained encoders are chip layout encoders, Steps include obtaining a sample chip layout and an initial encoder, The steps include performing a geometric transformation on the aforementioned sample chip layout to obtain at least one reference chip layout, The steps include: extracting sample layout features of the sample chip layout and reference layout features of each reference chip layout using the initial encoder; The steps include determining a reconfigured chip layout based on the aforementioned sample layout characteristics, The steps include training the initial encoder based on the sample chip layout, the reconstructed chip layout, the sample layout features, and the reference layout features, and obtaining the trained encoder, The acquired module obtained by training using, An extraction module used to extract target layout features of each target chip layout using the trained encoder, A clustering module used to perform clustering processing on a plurality of target chip layouts based on the characteristics of each target layout, and to obtain a plurality of target clustering groups, wherein at least one target chip layout is included in any one of the target clustering groups, A screening module used to screen for a key chip layout from among the target chip layouts included in any one target clustering group, The process involves performing light source mask optimization on the aforementioned key chip layout to obtain a target light source and a mask layout corresponding to the aforementioned key chip layout, and performing mask optimization on other chip layouts based on the aforementioned target light source to obtain a mask layout corresponding to the aforementioned other chip layouts, wherein the aforementioned other chip layouts are target chip layouts other than the aforementioned key chip layout among the respective target chip layouts, and the optimization module used for this process. A chip layout screening device, including [specific components / features].

7. An electronic device comprising a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor, thereby enabling the electronic device to implement the chip layout screening method described in any one of claims 1 to 4.

8. A computer program that, when loaded and executed by a processor, enables an electronic device to implement the chip layout screening method described in any one of claims 1 to 4.

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