MAC calculation circuit and method based on a hybrid ADC.

Abstract

To provide a hybrid ADC-based MAC computation circuit and method.SOLUTION: According to an embodiment, a MAC computation circuit comprises: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first ADC circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The following embodiments relate to a MAC arithmetic circuit and method, etc.

Background Art

[0002] The vector matrix multiplication operation, also known as MAC (multiply-accumulate) operation or product-sum operation, affects the performance of applications in various fields. For example, in the machine learning and authentication operations of a neural network including multiple layers, the MAC operation is executed. The input signal is regarded as forming an input vector and is data for an image, a byte stream or other data sets. The input signal is multiplied by a weight and an output vector is obtained from the result of the MAC operation, and this output vector can be provided as an input vector for the next layer. Since such MAC operations are repeated for multiple layers, the neural network processing performance greatly depends on the performance of the MAC operation.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The purpose of the following embodiments is to provide a MAC arithmetic circuit and method, etc. based on a hybrid ADC.

Means for Solving the Problems

[0004] According to one embodiment, a MAC arithmetic circuit includes a bit cell array that generates an analog output corresponding to the result of a MAC operation on an input signal, a first ADC (analog-to-digital conversion) circuit that determines the upper part of a digital output corresponding to the analog output, and a second ADC circuit that determines the lower part of the digital output based on a reference voltage corresponding to the upper part.

[0005] The first ADC circuit compares an approximate range based on a primary reference voltage with the analog output to determine the upper part, and determines a first range within the approximate range to which the analog output belongs, the first range which may correspond to the upper part of the digital output. The second ADC circuit compares a fine range of the first range based on a secondary reference voltage including the reference voltage with the analog output to determine a second range within the fine range to which the analog output belongs, the second range which may correspond to the lower part of the digital output. The primary reference voltage can be set based on the analog output.

[0006] The first ADC circuit may be a SAR ADC circuit, and the second ADC circuit may be a flash ADC circuit. The digital output may be 6 bits, with the upper part being 2 bits and the lower part being 4 bits.

[0007] The bit cell array includes a plurality of input lines and a plurality of output lines, wherein the first analog output of the first output line corresponds to the result of a first MAC calculation between the voltage value applied to the first output line by the input signal and the resistance value of the bit cell belonging to the first output line. The MAC calculation circuit may further include a capacitor array that converts the current value of the analog output into a voltage value.

[0008] The bit cell array includes a plurality of bit cell groups, each containing a plurality of output lines. Of the plurality of bit cell groups, the first output lines belonging to the first bit cell group may share a first capacitor array and a first ADC block assigned to the first bit cell group. The first capacitor array may include a first capacitor that samples the output of the output lines of a first subgroup of the first output lines, and a second capacitor that samples the output of the output lines of a second subgroup of the first output lines. The even-numbered output lines of the first output lines belong to the first subgroup, and the odd-numbered output lines belong to the second subgroup.

[0009] The first ADC block includes the first ADC circuit and the second ADC circuit, which can operate on a pipeline basis. The first ADC circuit determines the digital upper part of the output of the output lines of the first subgroup during a first time interval, the second ADC circuit determines the digital lower part of the output of the output lines of the first subgroup during a second time interval, and the first ADC circuit determines the digital upper part of the output of the output lines of the second subgroup during a third time interval, with at least a portion of the third time interval overlapping with the second time interval by the pipeline. The even-numbered output lines of the first output lines belong to the first subgroup, and the odd-numbered output lines belong to the second subgroup. The MAC arithmetic circuit may further include a plurality of capacitor arrays for sampling the analog output, a plurality of first ADC circuits including the first ADC circuit, and a plurality of second ADC circuits including the second ADC circuit.

[0010] According to another embodiment, the MAC arithmetic circuit includes a bit cell array that generates an analog output corresponding to the MAC arithmetic result of an input signal using a plurality of bit cell groups, each having a plurality of output lines; a plurality of capacitor arrays assigned to each of the plurality of bit cell groups and sampling the analog output; a plurality of first ADC circuits connected to the plurality of capacitor arrays and determining the upper part of the digital output corresponding to the analog output; and a plurality of second ADC circuits that determine the lower part of the digital output based on a reference voltage corresponding to the upper part.

[0011] The MAC calculation circuit may further include a reference generator that generates candidate reference voltages, and a reference selector that selects from the candidate reference voltages the reference voltage corresponding to the higher part of the digital output. The reference generator can determine at least some of the candidate reference voltages based on the analog output for generating the candidate reference voltages.

[0012] A first output line belonging to the first bit cell group among the plurality of bit cell groups can share the first capacitor array, the first ADC circuit, and the second ADC circuit assigned to the first bit cell group among the plurality of capacitor arrays, the plurality of first ADC circuits, and the plurality of second ADC circuits.

[0013] According to one embodiment, the MAC calculation method includes the steps of: generating an analog output corresponding to the MAC calculation result of an input signal using a bit cell array; determining the upper part of a digital output corresponding to the analog output using a first ADC circuit; setting a reference voltage for a second ADC circuit based on the upper part; and determining the lower part of the digital output using the second ADC circuit.

[0014] According to one embodiment, the electronic device includes a bit cell array that generates an analog output corresponding to the MAC calculation result of an input signal; a first ADC circuit that determines the upper bits of a digital output corresponding to the analog output by comparing the analog output with one or more primary reference values ​​determined based on the maximum value of the input signal value range; and a second ADC circuit that determines the lower bits of the digital output by comparing the analog output with one or more secondary reference values ​​determined based on the primary reference values.

[0015] The first ADC circuit can determine the most significant bit of the higher bits by comparing the analog output with one or more primary reference values, which are half the maximum value of the input signal value range. The value of the analog output and the secondary reference value are within the range of the first and second primary reference values ​​of the one or more primary reference values.

[0016] The electronic device may further include a processor that generates an input recognition result corresponding to the input signal based on the digital output. [Effects of the Invention]

[0017] According to the following embodiments, a MAC calculation circuit and method for a hybrid ADC substrate can be provided. [Brief explanation of the drawing]

[0018] [Figure 1] The schematic structure and operation of a MAC arithmetic circuit according to one embodiment are shown. [Figure 2] The structure of a bit cell array according to one embodiment is shown. [Figure 3] The structure of an ADC block according to one embodiment is shown. [Figure 4] This describes the operation of determining the upper and lower parts of a digital output according to one embodiment. [Figure 5] The structure of a MAC arithmetic circuit according to one embodiment is shown. [Figure 6]A bit cell group according to one embodiment is shown. [Figure 7] The structure of a MAC arithmetic circuit according to another embodiment is shown. [Figure 8] A hybrid ADC structure using two capacitors according to one embodiment is shown. [Figure 9] This describes a pipeline operation using two capacitors according to one embodiment. [Figure 10] A flash ADC circuit according to one embodiment is shown. [Figure 11] A reference generator according to one embodiment is shown. [Figure 12] A structure for generating a reference using an analog output according to one embodiment is shown. [Figure 13] This is an operation flowchart illustrating the computing operation according to one embodiment. [Figure 14] An example of a neural network operation that can be realized by a MAC arithmetic circuit according to one embodiment is shown. [Figure 15] This is a block diagram showing an electronic device according to one embodiment. [Modes for carrying out the invention]

[0019] The specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and can be modified in various ways. Therefore, the embodiments are not limited to the specific disclosure, and the scope of this specification includes modifications, equivalents, or substitutions that are part of the technical idea.

[0020] Terms such as "first" or "second" may be used to describe multiple components, but such terms should be interpreted solely for the purpose of distinguishing one component from others. For example, the first component may be named the second component, and similarly, the second component may also be named the first component.

[0021] When it is mentioned that one component is “linked” or “connected” to another component, it should be understood that it is directly linked to or connected to the other component, but that other components may be present in between.

[0022] A singular expression includes plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “includes” or “has” indicate the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood not to presuppose the existence or addition of one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0023] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally understood by a person of ordinary skill in the art to which this embodiment belongs. Commonly used, predefined terms should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as ideal or overly formal unless expressly defined herein.

[0024] Furthermore, when explaining with reference to the drawings, the same components will be assigned the same reference numerals regardless of the reference numerals used in the drawings, and redundant explanations will be omitted. In the description of embodiments, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of the present invention, such detailed explanation will be omitted.

[0025] Figure 1 shows a schematic structure and operation of a MAC arithmetic circuit according to one embodiment. Referring to Figure 1, the MAC arithmetic circuit 100 outputs a digital output 103 in response to the input signal 101. The MAC arithmetic circuit 100 includes a MAC arithmetic block 110 and an ADC block 120. The MAC arithmetic block 110 performs MAC calculations based on the input signal 101 and outputs an analog output 102 corresponding to the MAC calculation result. The ADC block 120 can convert the analog output 102 to a digital output 103 based on a hybrid ADC.

[0026] The MAC arithmetic block 110 includes a bit-cell array 111 and a capacitor array 112. The bit-cell array 111 may include multiple bit cells in array form. The bit-cell array 111 performs a memory function for storing weights and an arithmetic function for performing MAC operations between input values ​​and weight values. Bit cells include resistive elements and / or memory elements. For example, bit cells may be resistive memory elements.

[0027] Each row of the bit cell array 111 forms an input line, and each column forms an output line. The input value of any bit cell may be the voltage applied to that bit cell by the input signal 101, and the weight value of that bit cell may be the resistance value of that bit cell. The output value of the bit cell is the product of the input value and the resistance value, and corresponds to the current value. The currents of the output line to which the bit cell belongs can be summed to form the analog output 102 of that output line. The capacitor array 112 performs sampling operations based on the analog output 102. For example, the capacitor array 112 can convert the current value of the analog output 102 to a voltage value via sample and hold.

[0028] The ADC block 120 includes a first ADC circuit 121 and a second ADC circuit 122. The first ADC circuit 121 determines the upper part 104 of the digital output 103 corresponding to the analog output 102 based on the analog output 102. Once the reference voltage corresponding to the upper part 104 is determined, the second ADC circuit 122 can determine the lower part 105 of the digital output 103 based on the analog output 102 and the reference voltage. For example, the first ADC circuit 121 may be a successive approximation (SAR) ADC circuit, and the second ADC circuit 122 may be a flash ADC circuit. The upper part 104 is P bits from the MSB (most significant bit) of the digital output 103, and the lower part 105 is Q bits from the LSB (least significant bit) of the digital output 103. For example, P may be 2 and Q may be 4. The digital output 103 has a precision of P+Q bits.

[0029] The digital output 103 may be transmitted to a digital core (not shown). For example, the digital core may be a processor (not shown). The neural network may be executed via neural network operations, including MAC operations. The processor can perform MAC operations using the MAC operation circuit 100 and execute the neural network. For example, the bit cell array 111 stores a neural network model (e.g., network parameters, weights), and the processor may apply an input signal 101 corresponding to the input of the neural network to the MAC operation circuit 100. Once the MAC operation circuit 100 generates the analog output 102 and the digital output 103, the processor can use the digital output 103 as the MAC operation result.

[0030] Figure 2 shows the structure of a bit cell array according to one embodiment. Referring to Figure 2, the bit cell array 290 may include a plurality of input lines capable of individually receiving input signals and a plurality of output lines capable of individually outputting output signals. The input signals are input voltages V1 to V n The input is via and the output signal is output current I1~I m The output may be via a . The output signal is an analog output. Each of the multiple output lines may contain multiple bit cells. The bit cells perform a memory function to store weights and an arithmetic function to perform multiplication between the input value and the weight value. The bit cells may also contain resistive elements and / or memory elements, and the bit cell array 290 performs a memory function to store weights and an arithmetic function to perform MAC operations between the input value and the weight value. Each input line of the multiple input lines may intersect with multiple output lines. For example, the bit cell array 290 may contain m input lines and n output lines. For example, the i-th analog output I of the i-th output line 292 among the multiple output lines i This refers to the voltage values ​​V1~V applied to the i-th output line 292 by the input signal. n This corresponds to the MAC calculation result between the resistance values ​​of the bit cells belonging to the i-th output line 292. Although it has been shown that the input and output lines intersect perpendicularly to each other, this is not limited to this configuration.

[0031] Multiple bit cells can be arranged along multiple output lines and multiple input lines. For example, multiple bit cells may be arranged along an output line for each of the multiple input lines. Each of the multiple bit cells may be configured to receive a voltage through the input line on which it is located. For example, a bit cell arranged along the j-th input line 291 receives an input voltage V j The input signal may also be received. Input voltage V1~V nIt may have a voltage value that indicates a binary value. For example, an input voltage signal indicating a bit value of 1 indicates a determined voltage, and an input voltage signal indicating a bit value of 0 indicates a floating voltage. The bit cell array 290 is a memory array because it has memory functionality, and it is an accelerator because it performs specialized arithmetic functions.

[0032] The output signal is applied to multiple capacitors via the output line. These capacitors form an array. The capacitors may be individually positioned for each output line, or for each group of output lines. Each of the capacitors may be connected to a bit cell located along the output line on which it is positioned. Each of the capacitors can charge in response to the voltage received via the bit cell. For example, the capacitor located on the i-th output line 292 may be charged by the voltage applied to the bit cell located on the i-th output line 292. This allows each capacitor to sample a voltage value corresponding to the current output. For example, the capacitors may perform a sample-and-hold operation. The capacitors may have the same capacitance as each other.

[0033] FIG. 3 shows the structure of an ADC block according to an embodiment. Referring to FIG. 3, the ADC block 300 includes a SAR ADC circuit 310, a reference generator 320, and a flash ADC circuit 330. The SAR ADC circuit 310 corresponds to the first ADC circuit 121 shown in FIG. 1, and the flash ADC circuit 330 corresponds to the second ADC circuit 122. The SAR ADC circuit 310 can determine the upper part of the digital output 304 based on the analog output 301. The SAR ADC circuit 310 can compare a rough range based on a reference voltage with the analog output 301 and determine a first range to which the analog output 301 belongs within the rough range. Here, the first range corresponds to the upper part of the digital output 304. The reference generator 320 can determine a secondary reference voltage based on at least a part of the reference voltages that set the first range among the primary reference voltages. The secondary reference voltage may form a fine range of the first range. The flash ADC circuit 330 can compare the fine range with the analog output 301 and determine a second range to which the analog output 301 belongs within the fine range. Here, the second range corresponds to the lower part of the digital output 304.

[0034] FIG. 4 shows an operation of determining the upper and lower parts of a digital output according to an embodiment. Referring to FIG. 4, in the first box 410, a primary reference voltage is generated based on the maximum reference voltage V IN_MAX and the primary reference voltage forms rough ranges 401 to 404. FIG. 4 shows an example where the digital upper part is 2 bits and the digital lower part is 4 bits, but the number of bits of each part is not limited to this. In this case, the first rough range 401 indicates the digital upper part of "00", the second rough range 402 indicates the digital upper part of "01", the third rough range 403 indicates the digital upper part of "10", and the fourth rough range 404 indicates the digital upper part of "11".

[0035] The first output voltage V IN_COL0 corresponds to the first analog output of the first output line. The SAR ADC circuit is the first output voltage V IN_COL0Compare this with the primary reference voltage. First output voltage V IN_COL0 Since it belongs to the third schematic range 403, the SAR ADC circuit can determine "10", which corresponds to the third schematic range 403, as the upper part D[5:4] of the first digital output D[5:0] corresponding to the first analog output. The SAR ADC circuit determines the upper part of the digital output via binary search. The binary search may be performed as many times as there are bits in the upper part of the digital output. In the example in Figure 4, since the upper part is 2 bits, the upper part can be determined via two binary searches.

[0036] More specifically, the SAR ADC circuit has a first output voltage V IN_COL0 Maximum reference voltage V IN_MAX It may also be compared to the primary reference voltage, which is half of the first output voltage V as shown in box 410. IN_COL0 The maximum reference voltage V IN_MAX Since it is greater than half of, the SAR ADC circuit determines the first digital value (in other words, the MSB) of the first digital output D[5:0] to be 1. The SAR ADC circuit then determines the first output voltage V IN_COL0 Maximum reference voltage V IN_MAX It may also be compared to the primary reference voltage, which is 3 / 4 of the first output voltage V. IN_COL0 The maximum reference voltage V IN_MAX If it is less than half of the first output voltage V, the SAR ADC circuit will IN_COL0 Maximum reference voltage V IN_MAX It may also be compared to the primary reference voltage, which is 1 / 4 of the first output voltage V as shown in box 410. IN_COL0 The maximum reference voltage V IN_MAX Because it is less than 3 / 4 of the value, the SAR ADC circuit can determine the second digital value as 0.

[0037] Referring to the second box 420, the primary reference voltages forming the third schematic range 403 and / or the third schematic range 403 are the maximum voltage V of the secondary reference voltages. HIGH and minimum voltage V LOWIt constitutes the following. Also, as shown in the third box 430, the maximum voltage V HIGH and minimum voltage V LOW A secondary reference voltage may be generated based on this. The secondary reference voltage can form a fine range of a third approximate range 403. If the lower part is Q bits, then 2^Q fine ranges are formed through 2^Q-1 secondary reference voltages. For example, a 4-bit lower part may be determined through 16 fine ranges. As shown in the third box 430, the flash ADC circuit can determine the lower part D[3:0] to "1001". Based on the combination of the upper part D[5:4] and the lower part D[3:0], the first digital output D[5:0] may be determined to "101001".

[0038] Figure 5 shows the structure of a MAC arithmetic circuit according to one embodiment. Referring to Figure 5, the MAC arithmetic circuit 500 includes a bit cell array 510, multiple capacitor arrays 520, a sampling signal generator 530, multiple SAR ADC circuits 540, multiple reference selectors 550, multiple flash ADC circuits 560, a reference generator 570, digital flip-flops 580, and a digital core 590. The bit cell array 510, the multiple capacitor arrays 520, and the sampling signal generator 530 constitute the MAC arithmetic block, while the multiple SAR ADC circuits 540, the multiple reference selectors 550, the multiple flash ADC circuits 560, the reference generator 570, and the digital flip-flops 580 constitute the ADC block. The number of rows in the bit cell array 510, the number of capacitor arrays 520, and the digital output D are shown in Figure 5. COL The specific number of bits, such as [5:0], is just one example; various other implementations using different numbers are also possible.

[0039] The bit cell array 510 contains multiple output lines. Figure 5 shows an example where 64 columns form an output line. Multiple output lines constitute a bit cell group. For example, as shown in Figure 6, the bit cell array 600 contains bit cell groups 610 and 620, each containing 8 output lines. In this case, the first bit cell group 610 has a first output current I COL Outputting [0:7], the second bit cell group 620 outputs the second output current I COL You can output [8:15].

[0040] Referring again to Figure 5, the multiple capacitor arrays 520 and the multiple ADC blocks are assigned to each of the multiple bit cell groups. In other words, one capacitor array and one ADC block are assigned to one bit cell group, and multiple output lines belonging to the same bit cell group may share the capacitor array and ADC block assigned to that bit cell group. The multiple capacitor arrays 520 receive output current I from the bit cell group assigned to them. COL [0:63] is received. For example, the first capacitor array 521 receives the first output current I from the first bit cell group. COL Upon receiving [0:7], the second capacitor array receives the second output current I from the second bit cell group. COL [8:15] is received.

[0041] Multiple capacitor arrays 520 provide the output current I corresponding to the analog output. COL Output voltage I via sampling based on [0:63] COL [0:64] may be generated. More specifically, each capacitor array 520 may sequentially receive output current from each output line of the bit cell group relating to itself and sequentially convert the output current with an output voltage. For example, the first capacitor array 521 may generate output current I COL [0:7] Output voltage V COLThe ratio may be sequentially converted to [0:7]. Each capacitor array 520 of the multiple capacitor arrays 520 outputs an output current I based on the control signal of the sampling signal generator 530. COL [0:63] can be processed sequentially.

[0042] Multiple SAR ADC circuits 540 and multiple flash ADC circuits 560 are connected to multiple capacitor arrays 520. The multiple SAR ADC circuits 540 are referred to as the first ADC circuits, and the multiple flash ADC circuits 560 are referred to as the second ADC circuits. The multiple SAR ADC circuits 540 and the multiple flash ADC circuits 560 have output voltages V corresponding to analog outputs. COL [0:63] is output digitally by bitcell group D COL It can be converted to [5:0]. More specifically, the first SAR ADC circuit 541 and the first flash ADC circuit 561 output voltage V COL [0] Digital output D corresponding to [0] COL [5:0], Output voltage V COL [1] Digital output D corresponding to [1] COL [5:0] and output voltage V COL [2] Digital output D corresponding to [2] COL [5] is generated. The first SAR ADC circuit 541 and the first flash ADC circuit 561 generate the remaining output voltage V COL Digital output D corresponding to [3:7] COL [5:0] can also be generated. At this time, the first SAR ADC circuit 541 and the first flash ADC circuit 561 output voltage V COL Digital output D corresponding to [0:7] COL At least a portion of [5:0] can be generated using a pipeline. The pipeline operation will be explained in detail later.

[0043] The reference generator 570 generates a reference voltage, and the reference selector 550 selects the reference voltage. More specifically, the reference generator 570 may generate at least a portion of the primary reference voltage used by the multiple SAR ADC circuits 540 and the secondary reference voltage used by the multiple flash ADC circuits 560. Once the range is defined by the multiple SAR ADC circuits 540, the reference selector 550 can select at least a portion of the secondary reference voltages generated by the reference generator 570 and provide them to the multiple flash ADC circuits 560. For example, the reference generator 570 may generate candidate reference voltages for the secondary reference voltage, and the reference selector 550 may select at least a portion of the candidate reference voltages corresponding to the digital upper part as the secondary reference voltage.

[0044] Multiple SAR ADC circuits 540 output the output voltage V COL Based on [0:63], digital output D COL The upper part (e.g., 2 bits) of [5:0] is determined, and multiple flash ADC circuits 560 determine the output voltage V COL [0:63] and based on the secondary reference voltage, digital output D COL The lower part of [5:0] (for example, 4 bits) may be determined. Digital output D COL [5:0] is stored in the digital flip-flop 580, and then the digital output D ADC [47:0] can be integrated and provided to the digital core 590.

[0045] Figure 7 shows the structure of a MAC arithmetic circuit according to another embodiment. Referring to Figure 7, the MAC arithmetic circuit 700 includes a bit cell array 710, a plurality of capacitor arrays 720, a sampling signal generator 730, a plurality of SAR ADC circuits 740, a plurality of reference selectors 750, a plurality of flash ADC circuits 760, a reference generator 770, a digital flip-flop 780, and a digital core 790. Unlike the MAC arithmetic circuit 500 shown in Figure 5, any numerical value may be applied to the MAC arithmetic circuit 700 shown in Figure 7. More specifically, the bit cell array 710 is divided into K bit cell groups, and each bit cell group may include N output lines (in other words, columns). The plurality of SAR ADC circuits 740 have digital output D COL The upper P bit of [(P+Q)-1:0] is determined, and multiple flash ADC circuits 760 output digital output D COL The lower Q bit of [(P+Q)-1:0] is determined. In addition, the explanation shown in Figure 5 may be applied to the MAC arithmetic circuit 700.

[0046] Figure 8 shows a hybrid ADC structure using two capacitors according to one embodiment. Referring to Figure 8, when output signals COL0 to COL(N-1) are output from the bit cell array 801, capacitors 802 and 803 sequentially sample the output signals COL0 to COL(N-1). The output signals COL0 to COL(N-1) are the output currents of each output line of the bit cell array 801. The even capacitor 802 samples the even-numbered output signals COL0, COL2, ..., COL(N-2) corresponding to the output lines of the first subgroup, and the odd capacitor 803 samples the odd-numbered output signals COL1, COL3, ..., COL(N-1) corresponding to the output lines of the second subgroup.

[0047] The SAR ADC circuit 810 and the flash ADC circuit 860 may convert the sampling result (e.g., analog voltage value) into a digital output D. The SAR ADC circuit 810 determines the upper P bits of the digital output D, and the flash ADC circuit 860 determines the lower Q bits of the digital output D. The SAR ADC circuit 810 can determine the digital output D[P+Q-1:Q] corresponding to the sampling result by referring to a reference SAR_REF. For example, the SAR ADC circuit 810 determines the digital output D[P+Q-1:Q] based on P binary searches. The reference SAR_REF may include at least one primary reference voltage. For example, the reference SAR_REF may include the maximum reference voltage V shown in Figure 4. IN_MAX This may include or may include all primary reference voltages of box 410. Once the digital output D[P+Q-1:Q] is determined, the SAR ADC circuit 810 can output a completion signal SAR_DONE.

[0048] The first digital controller 820 transmits the digital output D[P+Q-1:Q] to the DAC circuits 831 and 832 in response to the completion signal SAR_DONE. The DAC circuits 831 and 832 and buffers 841 and 842 transmit the digital output D[P+Q-1:Q] to the analog voltage V HIGH , V LOW It may be converted to the first DAC circuit 831 and the first buffer 841 have a high analog voltage V HIGH The second DAC circuit 832 and the second buffer 842 are set to a low analog voltage V LOW Determines the analog voltage V. The reference voltage generator 850 determines the analog voltage V. HIGH , V LOW Based on the reference voltage V REF1 ,...,V REF_2^Q-1 It may generate a reference voltage V. The flash ADC circuit 860 uses a reference voltage V. REF1 ,...,V REF_2^Q-1The digital output D[Q-1:0] corresponding to the sampling result can be determined by referring to the data. The second digital controller 870 can output a digital output D[P+Q-1:0] by combining the digital output D[P+Q-1:Q] of the SAR ADC circuit 810 and the digital output D[Q-1:0] of the flash ADC circuit 860.

[0049] The SAR ADC circuit 810 and the flash ADC circuit 860 can operate on a pipelined board using capacitors 802 and 803. Pipeline operation will be described in detail with reference to Figure 9. Figure 9 shows pipeline operation using two capacitors according to one embodiment. In Figure 9, white blocks represent the sampling operation of the capacitors, horizontal striped blocks represent the conversion operation of the SAR ADC circuit, and vertical striped blocks represent the conversion operation of the flash ADC circuit. Referring to Figure 9, the even capacitor may sample the output of the first column Col#0 in the first clock, and the odd capacitor may sample the output of the second column Col#1 in the same clock (first clock). As this is the initial operation, both the even and odd capacitors operate, and thereafter the even and odd capacitors operate sequentially in accordance with the pipeline.

[0050] Between the next clock (second clock) and the P-clock, the SAR ADC circuit can determine the higher digital value of the sampling result, and between the next clock (P+2 clock) and one clock, the flash ADC circuit can determine the lower digital value of the sampling result. The SAR ADC circuit performs a binary search, requiring a P-clock to determine the digital value of P bits. The flash ADC circuit can determine the digital value of Q bits in one clock cycle using multiple reference voltages. While the flash ADC circuit performs the conversion operation for the first column Col#0, in other words, from the P+2 clock, the SAR ADC circuit can perform the conversion operation for the second column Col#1. Also, once the flash ADC circuit's conversion operation for the first column Col#0 is complete, the even capacitor can sample the output of the third column Col#2.

[0051] The capacitor and ADC circuits perform such conversion operations up to the Nth column Col#(N-1), and the conversion efficiency is improved by pipeline operation. The time intervals in which the operation of the capacitor and ADC circuits overlap affect the improvement in conversion efficiency. For example, the SAR ADC circuit can determine the digital upper part of the output of the output line of the first subgroup (e.g., the first column Col#0) during the first time interval (e.g., from the second clock to the P-clock), the flash ADC circuit can determine the digital lower part of the output of the output line of the first subgroup (e.g., the first column Col#0) during the second time interval (e.g., from the P+2 clock to the 1st clock), and the SAR ADC circuit can determine the digital upper part of the output of the output line of the second subgroup (e.g., the second column Col#1) during the third time interval (e.g., from the P+2 clock to the P-clock). Here, at least part of the third time interval overlaps with the second time interval due to pipeline, thereby improving the conversion efficiency. Furthermore, although embodiments in which capacitors are divided into even and odd numbers are described, capacitors may be divided according to different criteria, such as large and small numbers, and three or more capacitors may be used.

[0052] Figure 10 shows a flash ADC circuit according to one embodiment. Referring to Figure 10, the flash ADC circuit 1000 includes a plurality of comparators 1011-1013, a one-hot binary encoder 1020, and a digital flip-flop array 1030. The plurality of comparators 1011-1013 control the output voltage V COL and reference voltage V REF1 ~V REF15 The comparison can be performed and the comparison result can be output. If the number of bits of the digital value determined by the flash ADC circuit 1000 is Q, then 2^Q-1 comparators are used. The 15 comparators 1011 to 1013 shown in Figure 10 determine a 4-bit digital value. The one-hot binary encoder 1020 outputs a digital output D corresponding to the comparison result. COL Outputting [3:0], the digital flip-flop array 1030 has multiple output lines (e.g., 8) of digital output DCOL [3:0] is merged, and digital output D ADC [31:0] may be output. Since 2^Q-1 comparators are required for Q-bit conversion, adding comparators to the flash ADC circuit 1000 to improve bit precision would increase the number of comparators geometrically, and therefore the area and power consumption of the flash ADC circuit 1000 could also increase significantly. The hybrid ADC circuit according to the embodiment can improve bit precision while minimizing area and power consumption.

[0053] Figure 11 shows a reference generator according to one embodiment, and Figure 12 shows a structure that generates a reference using an analog output according to one embodiment. Referring to Figure 11, the reference generator 1100 includes amplifiers 1111, 1112 and a resistive DAC 1120. Amplifiers 1111, 1112 and resistive DAC 1120 generate a high reference voltage V HIGH and a low reference voltage V LOW Divide it equally, and the reference voltage V REF1 ~V REF15 Generates.

[0054] Referring to Figure 12, the MAC arithmetic circuit 1200 includes a CAP array 1221 and associated input / output lines instead of a reference generator 570. The bit cell array 510 outputs current I COL [0:63] In addition to the reference current I REF [0:M] is further output, and the reference current I REF [0:M] is provided to the capacitor array 1221. M-1 indicates the number of reference voltages required. For example, the maximum reference voltage V IN_MAX and maximum reference voltage V IN_MAX At least one of the voltage values ​​corresponding to 1 / 4, 2 / 4, and 3 / 4 of the approximate range is determined as the primary reference voltage, and at least one of the various voltage values ​​forming fine ranges of the approximate range is determined as the secondary reference voltage. The bit cell array 510 has an internal structure that can provide a reference current corresponding to at least a portion of such required reference voltages, thereby providing the reference current. The capacitor array 1221 provides the reference current I REFA reference voltage can be generated based on [0:M]. The reference voltage can be supplied to the SAR ADC circuit 540 and / or the flash ADC circuit 560.

[0055] Figure 13 is an operation flowchart showing the computing operation according to one embodiment. Referring to Figure 13, in step S1310, an analog output corresponding to the MAC calculation result of the input signal is generated using a bit cell array; in step S1320, the upper part of the digital output corresponding to the analog signal is determined using the first ADC circuit; in step S1330, the reference voltage of the second ADC circuit is set based on the upper part; and in step S1340, the lower part of the digital output is determined using the second ADC circuit. Steps S1310 to S1340 may be executed sequentially or not. For example, the order of steps S1310 to S1340 may be changed, and / or at least two of steps S1310 to S1340 may be executed in parallel. Steps S1310 to S1340 are executed by at least one component of the MAC calculation circuits 100, 500, 700, and 1200. In addition, the explanations shown in Figures 1 to 12, 14, and 15 may apply to computing operations.

[0056] Figure 14 shows an example of neural network computation realized by a MAC arithmetic circuit according to one embodiment. The neural network 1400 is an example of a deep neural network (DNN). A DNN may include a fully connected network, a deep convolutional network, and a recurrent neural network. The neural network 1400 can perform object classification, object recognition, speech recognition, and image recognition by mapping nonlinearly related input and output data to each other based on deep learning. Deep learning is a machine learning method for solving problems such as image or speech recognition from big datasets, and it can map input and output data to each other through supervised or unsupervised learning.

[0057] Figure 14 shows the hidden layer as containing two layers for illustrative purposes, but the hidden layer may contain any number of layers. Also, in Figure 14, the neural network 1400 is shown as containing a separate input layer 1410 for receiving input data, but the input data may be directly input to the hidden layer. In the neural network 1400, the artificial nodes or neurons of the layers excluding the output layer may be connected to the artificial nodes of the next layer via links for transmitting output signals. The number of links corresponds to the number of artificial nodes contained in the next layer.

[0058] Each artificial node in the hidden layer can be input in a weighted form of the outputs of the artificial nodes in the previous layer. This weighted form of input is called a weighted input, and it is obtained by multiplying the output of the artificial nodes in the previous layer by a weight value. The weight value is referred to as a parameter of the neural network 1400. An activation function may be applied to the sum of such weighted inputs and output from the next layer. The activation function may include a sigmoid, a hyperbolic tangent (tanh), and a rectified linear unit (ReLU), and the activation function may introduce nonlinearity into the neural network 1400. Each artificial node in the output layer can be input with a weighted input in the form of the outputs of the artificial nodes in the previous layer.

[0059] In memory computing for driving deep learning algorithms, the MAC arithmetic circuit described with reference to Figures 1 to 13 may be used. For example, the calculation of weighted inputs transmitted between nodes 1421 of the neural network 1400 is performed by MAC operations that repeatedly perform multiplication and addition. The output of any one node 1421 of the neural network 1400 is shown by the following formula.

[0060]

number

[0061] According to an embodiment, the bit cell of the MAC operation circuit may have a resistance corresponding to the connection weight value of the connection line connecting a plurality of nodes in the neural network 1400 including a layer including a plurality of nodes. The input voltage signal provided along the input line on which a plurality of bit cells are arranged represents a value corresponding to the node value x j . Therefore, the MAC operation circuit can perform at least a part of the operations required for the execution of the neural network 1400. In the MAC operation circuit, the resistance value of the bit cell is not fixed and may be changed to a resistance value corresponding to the weight value stored in the memory as described above.

[0062] However, without being limited to this, the application of the MAC operation circuit according to an embodiment can also be utilized for operation operations that must quickly process a plurality of input data using analog circuit characteristics with low power.

[0063] Figure 15 is a block diagram showing an electronic device according to one embodiment. Referring to Figure 15, the electronic device 1500 includes a processor 1510, a memory 1520, a camera 1530, a storage device 1540, an input device 1550, an output device 1560, and a network interface 1570, which can communicate via a communication bus 1580. For example, the electronic device 1500 can be implemented in at least part of a mobile device such as a mobile phone, smartphone, PDA, netbook, tablet computer, or laptop computer; a wearable device such as a smartwatch, smart band, or smart glasses; a computing device such as a desktop or server; a home appliance such as a television, smart TV, or refrigerator; a security device such as a door rack; or a vehicle such as an autonomous vehicle or smart vehicle. The electronic device 1500 may structurally and / or functionally include MAC arithmetic circuits 100, 500, 700, and 1200. For example, MAC arithmetic circuits 100, 500, 700, and 1200 may be implemented as part of the processor 1510 and / or memory 1520, or as part of the accelerator (not shown) of the electronic device 1500.

[0064] The processor 1510 executes functions and instructions for execution within the electronic device 1500. For example, the processor 1510 can process instructions stored in the memory 1520 or the storage device 1540. The processor 1510 may perform one or more operations as described with reference to Figures 1 to 15. The memory 1520 may include a computer-readable storage medium or a computer-readable storage device. The memory 1520 can store instructions for execution by the processor 1510 and related information while the software and / or application is executed by the electronic device 1500.

[0065] The camera 1530 takes photographs and / or videos. The storage device 1540 may include a computer-readable storage medium or a computer-readable storage device. The storage device 1540 can store a larger amount of information than the memory 1520 and can store information for a longer period of time. For example, the storage device 1540 may include a magnetic hard disk, an optical disk, flash memory, a floppy disk, or other forms of non-volatile memory known in the art.

[0066] The input device 1550 receives input from the user via traditional input methods such as a keyboard and mouse, and newer input methods such as touch input, voice input, and image input. For example, the input device 1550 may include a keyboard, mouse, touchscreen, microphone, or any other device that can detect input from the user and transmit the detected input to the electronic device 1500. The output device 1560 can provide the user with the output of the electronic device 1500 via a visual, auditory, or tactile channel. The output device 1560 may include, for example, a display, touchscreen, speaker, vibration generator, or any other device that can provide output to the user. The network interface 1570 can communicate with external devices via a wired or wireless network.

[0067] The embodiments described above are embodied in hardware components, software components, or combinations of hardware and software components. For example, the devices and components described in these embodiments are embodied using one or more general-purpose or special-purpose computers, such as a processor, controller, ALU (arithmetic logic unit), digital signal processor, microcomputer, FPA (field programmable array), PLU (programmable logic unit), microprocessor, or different devices that execute and respond to instructions. The processing device executes an operating system (OS) and one or more software applications that run on the OS. The processing device also accesses, stores, manipulates, processes, and generates data in response to the execution of the software. For convenience of understanding, the processing device may sometimes be described as being used as a single unit, but a person with ordinary skill in the art will understand that the processing device includes multiple processing elements and / or multiple types of processing elements. For example, the processing device includes multiple processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

[0068] Software includes computer programs, code, instructions, or a combination of one or more of these, which can configure a processing unit to operate as desired, or instruct the processing unit independently or in combination. Software and / or data can be permanently or temporarily embodied in any type of machine, component, physical device, virtual device, computer storage medium or device, or transmitted signal wave, for interpretation by a processing unit or for providing instructions or data to a processing unit. Software can be distributed across a network of computer systems and stored and executed in a distributed manner. Software and data can be stored on a recording medium readable by one or more computers.

[0069] The method according to this embodiment is embodied in the form of program instructions that are implemented via various computer means and recorded on a computer-readable recording medium. The recording medium includes program instructions, data files, data structures, etc., individually or in combination. The recording medium and program instructions may be specifically designed and configured for the purposes of the present invention, or they may be known and usable by those skilled in the art who have technology in the field of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floppy disks, and hardware devices specifically configured to store and execute program instructions, such as ROMs, RAMs, and flash memory. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code executed by a computer using an interpreter or the like.

[0070] The hardware device described above may be configured to operate as one or more software modules to perform the operations shown in the present invention, and vice versa.

[0071] As described above, although embodiments have been illustrated with limited drawings, a person with ordinary skill in the art can apply various technical modifications and variations based on the above description. For example, the described techniques may be performed in a different order than described, and / or the components of the described systems, structures, devices, circuits, etc. may be combined or assembled in a different manner than described, or replaced or substituted with other components or equivalents, and still achieve suitable results.

[0072] Therefore, other embodiments, other embodiments, and claims equivalent to those described below also fall within the scope of the claims.

Claims

1. MAC arithmetic circuit, A bit cell array that generates an analog output corresponding to the MAC calculation result of the input signal, A first ADC circuit that determines the higher-level part of the digital output corresponding to the analog output, A second ADC circuit that determines the lower part of the digital output based on the reference voltage corresponding to the upper part, The bit cell array includes a plurality of bit cell groups, each of which includes a plurality of output lines. Among the plurality of bit cell groups, the first output line belonging to the first bit cell group is a MAC arithmetic circuit that shares a first capacitor array and a first ADC block assigned to the first bit cell group.

2. The first ADC circuit is, To determine the aforementioned upper part, the approximate range based on the primary reference voltage is compared with the analog output, and the first range to which the analog output belongs is determined from the approximate range. The MAC arithmetic circuit according to claim 1, wherein the first range corresponds to the upper part of the digital output.

3. The second ADC circuit, in order to determine the lower part, compares the fine range of the first range, which includes the reference voltage, with the analog output, and determines the second range to which the analog output belongs within the fine range. The MAC arithmetic circuit according to claim 2, wherein the second range corresponds to the lower part of the digital output.

4. A MAC arithmetic circuit, A bit cell array that generates an analog output corresponding to the MAC calculation result of the input signal, A first ADC circuit that determines the higher-level part of the digital output corresponding to the analog output, A second ADC circuit that determines the lower part of the digital output based on the reference voltage corresponding to the upper part, The first ADC circuit includes, To determine the aforementioned upper part, the approximate range based on the primary reference voltage is compared with the analog output, and the first range to which the analog output belongs is determined from the approximate range. The first range corresponds to the upper part of the digital output, The primary reference voltage is set based on the analog output in the MAC calculation circuit.

5. The first ADC circuit is a SAR ADC circuit, The MAC arithmetic circuit according to claim 1, wherein the second ADC circuit is a flash ADC circuit.

6. The aforementioned digital output is 6 bits. The aforementioned upper part is 2 bits, The MAC arithmetic circuit according to claim 1, wherein the lower part is 4 bits.

7. The bit cell array includes a plurality of input lines and a plurality of output lines, The MAC arithmetic circuit according to claim 1, wherein the first analog output of the first output line among the plurality of output lines corresponds to the result of a first MAC calculation between the voltage value applied to the first output line by the input signal and the resistance value of the bit cell belonging to the first output line.

8. The MAC arithmetic circuit according to claim 1, further comprising a capacitor array that converts the current value of the analog output into a voltage value.

9. The MAC arithmetic circuit according to claim 1, wherein the first capacitor array includes a first capacitor for sampling the output of the output lines of a first subgroup of the first output lines, and a second capacitor for sampling the output of the output lines of a second subgroup of the first output lines.

10. The first ADC block includes the first ADC circuit and the second ADC circuit, The MAC arithmetic circuit according to claim 9, wherein the first ADC circuit and the second ADC circuit operate on a pipeline substrate.

11. The first ADC circuit determines the digital upper part of the output of the output line of the first subgroup during the first time interval. The second ADC circuit determines the digital lower part of the output of the output line of the first subgroup during the second time interval. The first ADC circuit determines the digital upper part of the output of the output line of the second subgroup during the third time interval. The MAC arithmetic circuit according to claim 10, wherein at least a portion of the third time interval overlaps with the second time interval due to the pipeline base.

12. The MAC arithmetic circuit according to claim 9, wherein the even-numbered output lines of the first output line belong to the first subgroup and the odd-numbered output lines belong to the second subgroup.

13. The MAC arithmetic circuit according to claim 1, further comprising a plurality of capacitor arrays for sampling the analog output, a plurality of first ADC circuits including the first ADC circuit, and a plurality of second ADC circuits including the second ADC circuit.

14. An electronic device comprising a MAC arithmetic circuit as described in claim 1 and a processor that generates an input recognition result corresponding to the input signal based on the digital output.

15. MAC arithmetic circuit, A bit cell array that generates analog outputs corresponding to the MAC calculation results of an input signal using multiple bit cell groups, each containing multiple output lines, A plurality of capacitor arrays, each assigned to one of the plurality of bit cell groups, which sample the analog output, Multiple first ADC circuits connected to the aforementioned multiple capacitor arrays, which determine the higher-level part of the digital output corresponding to the analog output, A plurality of second ADC circuits that determine the lower part of the digital output based on a reference voltage corresponding to the upper part, The MAC arithmetic circuit includes, A reference generator that generates candidate reference voltages, A reference selector that selects the reference voltage corresponding to the upper part of the digital output from among the candidate reference voltages, A MAC arithmetic circuit, which further includes this.

16. The MAC arithmetic circuit according to claim 15, wherein the reference generator determines at least a portion of the candidate reference voltages based on the analog output for generating the candidate reference voltages.

17. A MAC arithmetic circuit, A bit cell array that generates analog outputs corresponding to the MAC calculation results of an input signal using multiple bit cell groups, each containing multiple output lines, A plurality of capacitor arrays, each assigned to one of the plurality of bit cell groups, which sample the analog output, Multiple first ADC circuits connected to the aforementioned multiple capacitor arrays, which determine the higher-level part of the digital output corresponding to the analog output, A plurality of second ADC circuits that determine the lower part of the digital output based on a reference voltage corresponding to the upper part, A MAC arithmetic circuit including, wherein a first output line belonging to the first bit cell group among the plurality of bit cell groups shares the first capacitor array, the first ADC circuit, and the second ADC circuit assigned to the first bit cell group among the plurality of capacitor arrays, the plurality of first ADC circuits, and the plurality of second ADC circuits.

18. The first capacitor array includes a first capacitor that samples the output of the output lines of a first subgroup of the first output line, and a second capacitor that samples the output of the output lines of a second subgroup of the first output line. The MAC arithmetic circuit according to claim 17, wherein the first ADC circuit and the second ADC circuit operate on a pipeline substrate.

19. The first ADC circuit compares the approximate range determined by the primary reference voltage with the analog output to determine the upper part, and determines a first range to which the analog output belongs within the approximate range. The MAC arithmetic circuit according to claim 15, wherein the second ADC circuit compares the fine range of the first range, which includes the reference voltage, with the analog output in order to determine the lower part, and determines the second range to which the analog output belongs within the fine range.

20. A step of generating an analog output corresponding to the MAC calculation result of an input signal using a bit cell array, A step of determining the upper part of the digital output corresponding to the analog output using the first ADC circuit, The steps include setting the reference voltage of the second ADC circuit based on the aforementioned upper part, The steps include determining the lower part of the digital output using the second ADC circuit, In a MAC calculation method that includes, The bit cell array includes multiple bit cell groups, each containing multiple output lines. A MAC calculation method wherein, among the plurality of bit cell groups, the first output line belonging to the first bit cell group shares a first capacitor array and a first ADC block assigned to the first bit cell group.

21. An electronic device, A bit cell array that generates an analog output corresponding to the MAC calculation result of the input signal, A first ADC circuit that determines the upper bits of the digital output corresponding to the analog output by comparing the analog output with one or more primary reference values ​​determined based on the maximum value of the input signal value range, A second ADC circuit that determines the lower bits of the digital output by comparing the analog output with one or more secondary reference values ​​determined based on the primary reference value, Electronic devices, including those mentioned above.

22. The electronic device according to claim 21, wherein the first ADC circuit determines the most significant bit of the higher bits by comparing the analog output with one or more primary reference values ​​which is half the maximum value of the input signal value range.

23. The electronic device according to claim 21, wherein the value of the analog output and the secondary reference value are within the range of the first primary reference value and the second primary reference value of the one or more primary reference values.

24. The electronic device according to claim 21, further comprising a processor that generates an input recognition result corresponding to the input signal based on the digital output.

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