Low-power fractional analog PLL without feedback divider

Abstract

An integrated circuit device (200) is provided. In some examples, the integrated circuit device includes a first timing resetter (216) configured to receive a reference clock signal (201) and a voltage controlled oscillator (VCO) output signal (212), the first retimer configured to provide a first retimed clock signal (216A) in response to the reference clock signal and the VCO output signal. A first multiplexer (215) receives the first retimed clock signal and provides a feedback clock signal (215A). A phase frequency detector (202) receives a feedback clock signal and a reference clock signal and provides error signals (202A and 203A) in response to the feedback clock signal and the reference clock signal. A VCO (211) receives a voltage signal (220A) based on the error signal, the VCO configured to provide a VCO output signal (212) in response to the voltage signal.

Description

Background Art

[0001] In battery-powered devices, battery life depends on the power consumption by various systems within the device. A wireless device capable of transmitting and / or receiving may have, for example, a signal chain and a local oscillator (LO) system. The signal chain may include filters, amplifiers, analog-to-digital converters, and other components. Reducing the power consumed by these devices in the signal chain of a wireless device is one area for power savings, but since the various components of the LO system of a wireless device also consume power, if these are saved, it can thereby also extend the battery life.

[0002] One component of the LO can be a phase-locked loop (PLL). The PLL has a wide range of applications, from a simple clock clean-up circuit to an LO for high-frequency wireless communication links such as those used in wireless connections. The PLL compares the phase of a reference signal with the phase of an adjustable feedback signal. The comparison can be realized using a feedback loop, and when the comparison in the feedback loop is in a steady state, that is, when the output frequency and phase match the reference frequency and phase in the error detector, the PLL is locked.

[0003] To maintain a lock, a considerable amount of power is generally consumed by the PLL. One way to reduce the amount of power consumed by the PLL is to turn it off when it is not needed. In wireless devices such as mobile phones, the device spends a lot of time in sleep mode, and many of the wireless device's circuits are turned off. When in sleep mode, the wireless device may operate in listen mode or sniff mode with very low active power consumption. In listen mode or sniff mode, the wireless device listens for signals to come out of sleep mode and resume normal operation. However, since precise LO may be required during the listen or sniff function, power may still be consumed by the PLL during listen or sniff mode.

[0004] In high-frequency radio communications, fractional PLLs may be used to adjust the output to the required high-frequency channel. Fractional PLLs may include feedback divider circuits that consume a relatively large amount of power even when the radio device is in listen mode or sniffer mode. Some PLLs also include voltage-controlled oscillators (VCOs). Therefore, in some applications, the VCO of the PLL may be run in an open loop to avoid the power consumed in the feedback divider circuit. However, the usefulness of open-loop VCOs is limited by increased residual frequency error and phase noise, and for some radio communications, open-loop VCOs do not provide acceptable results even in listen or sniffer operation. [Overview of the Initiative]

[0005] In several examples, an integrated circuit is provided that includes a fractional PLL configured to operate in divider-disable mode. The fractional PLL may include a phase frequency detector (PFD), a charge pump, a loop filter, a VCO, a feedback divider, a sigma-delta modulator, a retimed clock signal based on the VCO output, and / or other appropriate components. The feedback divider of the fractional PLL may be disabled so that it does not consume power. The retimed clock signal may be multiplexed with sigma-delta modulation from the sigma-delta modulator. The retimed clock signal may include multiple retimed clock signals. The PFD may determine the error between the retimed clock signal and a reference clock and use the error between the retimed clock signal and the reference clock to adjust the VCO output to achieve locking of the PLL while the feedback divider is disabled.

[0006] In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage-controlled oscillator (VCO) output signal, the first re-timer configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. The integrated circuit device also includes a first multiplexer configured to receive the first re-timed clock signal and provide a feedback clock signal. The integrated circuit device also includes a phase-frequency detector (PFD) configured to receive a feedback clock signal and a reference clock signal and provide an error signal in response to the feedback clock signal and the reference clock signal. The integrated circuit device also includes a VCO configured to receive a voltage signal based on the error signal, the VCO configured to provide a VCO output signal in response to the voltage signal.

[0007] In some examples, the integrated circuit includes a first retimer, which includes a first input, a second input, and an output coupled to a reference clock. The integrated circuit also includes a first multiplexer, which includes a first input, a second input, and an output coupled to the output of the first retimer. The integrated circuit also includes a PFD, which includes a first input coupled to a reference clock, a second input, and an output coupled to the output of the first multiplexer. The integrated circuit also includes a charge pump, which includes an input and an output coupled to the output of the PFD. The integrated circuit also includes a filter, which includes an input and an output coupled to the output of the charge pump. The integrated circuit also includes a VCO, which includes an input coupled to the output of the filter and an output coupled to the second input of the first retimer. The integrated circuit also includes a feedback divider, which includes a first input coupled to the output of the VCO and an output coupled to the second output of the first multiplexer.

[0008] In some examples, a method includes receiving a reference clock signal and a voltage-controlled oscillator (VCO) output signal by a retimer. This method further includes retiming the reference clock signal according to the VCO output signal by the retimer to generate a retimed clock signal. This method further includes determining an error signal based on the retimed clock signal and the reference clock signal using a phase frequency detector (PFD). This method further includes modifying the VCO output signal based on the error signal. [Brief explanation of the drawing]

[0009] The features of this invention will be understood from the detailed description below and the accompanying drawings.

[0010] [Figure 1] This is a circuit diagram of the LO PLL circuit.

[0011] [Figure 2A] This is a schematic diagram of an LO PLL circuit according to some aspects of the present disclosure.

[0012] [Figure 2B] This is a timing diagram according to some aspects of this disclosure.

[0013] [Figure 3A] This is a schematic diagram of an LO PLL circuit according to some aspects of the present disclosure.

[0014] [Figure 3B] This is a timing diagram according to some aspects of this disclosure.

[0015] [Figure 4] This is a timing diagram according to some aspects of this disclosure.

[0016] [Figure 5] This is a flowchart of a method for performing local oscillation according to several aspects of this disclosure. [Modes for carrying out the invention]

[0017] Specific examples are described below with reference to the attached diagrams. These examples are not intended to be limiting, and unless otherwise noted, they do not necessarily represent features required for any particular example.

[0018] An example of a LO using a fractional PLL includes a PFD, charge pump, filter, VCO, and frequency divider circuit. The LO compares a reference clock signal with a feedback signal from a feedback divider and uses the result of this comparison to control the VCO until the PLL locks. The LO may include one or more filters and amplifiers for processing error signals. The feedback circuit may also include a modulator and one or more frequency divider buffers.

[0019] The frequency divider circuit may provide a feedback clock signal that is compared to a reference clock signal. In some cases, the frequency divider circuit is disabled. For example, when the frequency divider circuit is disabled, such as by disconnecting the VCO output from the frequency divider circuit, the feedback clock signal may be derived from the phase information of the VCO, and as a result, a retime clock signal is obtained. The phase information of the VCO is provided to the PFD at an accurate phase detection time by the edge of the retime clock signal.

[0020] In some cases, the retime clock signal may be extended for a plurality of subsequent clock edges to provide a group of retime clock signals. The group of retime clock signals may be used for fractional synthesis. In some cases, the frequency divider circuit may include a sigma-delta modulator, and the output of the sigma-delta modulator may be randomly selected from the group of retime clock signals and used to generate an error signal that drives the VCO output frequency to a value obtained by adding a fractional multiple of the reference frequency to an integer.

[0021] In these and other examples, when the frequency divider circuit is disabled, the power consumption of the LO is reduced, and the residual frequency error and phase noise are improved.

[0022] Of course, these advantages are merely examples, and no particular embodiment requires advantages.

[0023] Examples of integrated circuit devices including a disabled frequency divider circuit will be described hereinafter with reference to the drawings.

[0024] The frequency divider circuit may be associated with fractional synthesis. Fractional-N frequency synthesis provides a small step size (narrow channel) over a wide bandwidth without requiring a large division ratio. This solves problems associated with very large division ratios in the digital frequency divider of the LO phase-locked loop that can occur when very high frequencies, such as frequencies in wireless communication, are used. The radio frequency may be within the gigahertz range. For example, the frequency ranges used in wireless communication include the 900 MHz, 2.4 GHz, 3.6 GHz, 4.9 GHz, 5 GHz, 5.9 GHz, and 60 GHz bands. The channel spacing in these frequency bands can be just a few kilohertz (e.g., 200 KHz). Dividing such high frequencies by a reference clock signal such as 40 MHz or 80 MHz can require a very large division ratio, resulting in performance problems and requiring a large amount of power.

[0025] To achieve small steps between channels at high frequencies while providing a suitable operating frequency, a very large division ratio is required. For example, a PLL operating at 10 MHz and requiring a step size of 100 Hz needs a division ratio of 100,000. Such a large division ratio can affect the performance of the PLL because the PLL bandwidth can become about one-tenth of the reference comparison frequency. In the case of the above example, it means that the PLL bandwidth is only 10 Hz, which can slow down PLL frequency switching, increase the size of passive components, and increase phase noise at frequencies close to the carrier, resulting in degraded performance.

[0026] In fractional-N synthesis, large division ratios are avoided because the frequency divider uses fractional division ratios rather than integer division ratios. To achieve this, the frequency divider switches division ratios. For example, the ratio of various division ratios determined to give the required frequency can be changed between N, N+1, N-1, and N-2. The division ratios between N, N+1, N-1, and N-2 yield four frequencies between division ratios, which is considered second-order modulation. In another example, first-order modulation provides a division ratio range of N, and N+1 provides frequencies between two division ratios. Third-order modulation may provide division ratios between N, N+1, N+2, N+3, N-1, N-2, N-3, and N-4. Additional order modulations may also be used. The advantage of using fractional-n synthesis is that the step frequency can be reduced while high comparison frequency and loop bandwidth can be maintained to improve the overall performance of the synthesizer.

[0027] In this regard, Figure 1 is a circuit diagram of an LO PLL circuit 100 using a fractional PLL with sigma-delta modulation. A reference clock signal 101A is received by the PFD 102. The reference clock signal 101A from the reference clock 101 is a stable and accurate frequency reference, and the output is phase-locked to this reference clock signal 101A. The reference clock signal 101A can be derived, for example, from a crystal oscillator or a temperature-controlled crystal oscillator.

[0028] PFD102 compares the feedback clock signal 116 with the reference clock signal 101A and derives phase error signals 102A and 102B between the reference clock signal 101A and the feedback clock signal 116. PFD102 may include, for example, two flip-flops coupled to an AND gate.

[0029] Charge pumps 103 and 104 convert the phase error signals 102A and 102B into charge pump output signals containing positive or negative current pulse trains proportional to the phase error. Charge pump 103 may provide an up pulse, and charge pump 104 may provide a down pulse. The duration of the up pulse is proportional to the difference between the reference clock signal 101A and the feedback clock signal 116, if there is a difference. The duration of the down pulse can be predetermined by the PFD 102. For example, the delay of the down pulse may be defined by an internal circuit element of the PFD 102, such as an inverter delay. When the LO PLL circuit 100 using fractional synthesis is locked, the average duration of the up pulses becomes equal to the duration of the down pulses. By using integer N synthesis, locking is achieved when the duration of the up pulses is equal to the duration of the down pulses.

[0030] Charge pumps 103 and 104 respond to phase error signals 102A and 102B by pumping current to the loop filter 120 or pumping current from the loop filter 120 to ground. Charge pumps 103 and 104 can be equally weighted current sources.

[0031] The loop filter 120 includes an amplifier 108, a capacitor C1106, a resistor R1107, a capacitor C2105, a resistor R2109, and a capacitor C3110. The loop filter 120 integrates current pulses from charge pumps 103 and 104 to provide a clean voltage signal 120A to the VCO 111. Furthermore, the active loop filter topology using the operational amplifier 108 ensures a good bias margin for the charge pump current source, while allowing the loop filter 120 to reach even higher tuning voltages. The active filter includes an amplifier 108, a capacitor C1106, a resistor R1107, and a capacitor C2105, and the active filter controls the voltage signal 120A. Capacitor C2105 filters out high-frequency noise spurious signals caused by sampling. Resistor R1107 provides stability by isolating the phase correction component of the error signal from the frequency correction component. The passive low-pass filter includes a resistor R2109 and a capacitor C3110 to remove high-frequency jitter.

[0032] The voltage signal 120A from the loop filter 120 drives the VCO 111. The VCO 111 outputs a frequency based on the voltage signal 120A. For example, as the voltage signal 120A increases, the frequency of the VCO 111 may increase, and as the voltage signal 120A decreases, the frequency of the VCO 111 may decrease. The VCO output 112 is fed back to the LO PLL circuit 100.

[0033] In the feedback loop of the LO PLL circuit 100, the VCO output 112 is received by a frequency divider buffer 113. The output of the frequency divider buffer 113 is received by a feedback frequency divider 114. The feedback frequency divider 114 also receives a modulation signal 115A from a sigma-delta modulator 115. The feedback frequency divider 114 functions as an adjustable frequency divider, and control for the feedback frequency divider 114 is provided by the modulation signal 115A from the sigma-delta modulator 115. The sigma-delta modulator 115 provides a certain density of pulses, and the density of these pulses represents the average value of the signal over a specific period of time. The modulation signal 115A from the sigma-delta modulator 115 is the frequency divider coefficient of the feedback frequency divider 114, enabling fractional-N synthesis. The feedback clock signal 116 is provided to the sigma-delta modulator 115 and PFD 102, where the process is restarted.

[0034] The fractional synthesis in Figure 1 can be illustrated by the following example: In a PLL with a 19.68 MHz reference clock that can be tuned in 1 MHz steps from 2.402 GHz to 2.480 GHz, when the divider coefficient N is set to 122, the PLL outputs 2.40096 GHz, and when the divider coefficient N is set to 123, the PLL outputs 2.42064 GHz. If the desired output is 2.403 GHz, the divider coefficient N may need to be a non-integer value between 122 and 123. Since the divider coefficient must be an integer value, this cannot be implemented directly. However, since the divider coefficient can be updated for each reference period, the divider coefficient is switched between N=122 and N=123 so that the average coefficient over many reference periods converges to a desired N value between 122 and 123. Modulation from the sigma-delta modulator 115 provides the average coefficient for convergence to the desired N value.

[0035] Figure 1 shows an illustrative timing diagram for a reference clock signal 101A and a feedback clock signal 116. In this example, the modulation orders from the sigma-delta modulator 115 are N, N+1, N-1, and N-2, and the frequencies between the four division ratios are given. Figure 1 shows only N-2, N-1, and N+1. The timing diagram in Figure 1 discloses the difference between the reference clock signal 101A and the feedback clock signal 116 across the three division ratios.

[0036] In the LO PLL circuit 100 shown in Figure 1, the frequency divider circuit, including the feedback divider 114, the divider buffer 113, and the sigma-delta modulator 115, consumes the majority of the power in the PLL. For example, the LO PLL circuit 100 may consume approximately 7 mA of power, but the frequency divider circuit may consume approximately 4 mA of that 7 mA.

[0037] Figure 2A is a schematic diagram of an LO PLL circuit 200 according to some aspects of the present disclosure. A reference clock signal 201A is received by the PFD 202. The reference clock signal 201A from the reference clock 201 is a stable and accurate frequency reference, and the output is phase-locked to that reference clock signal 201A. The reference clock signal 201A may be derived, for example, from a crystal oscillator or a temperature-controlled crystal oscillator. The clock reference 201 is received by the retimer 216. The retimer 216 also receives the VCO output signal 212. The retimer 216 generates a retimed clock signal 216A that brings the phase information of the VCO 211 to the PFD 202 in an accurate phase detection time. For example, the retimer 216 latches when the reference clock 201 is high and the VCO output signal 212 is high. Similarly, the retimed clock signal 216A goes low, for example, when the reference clock signal 201A is low and the VCO output signal 212 is low. As a result, phase information from VCO 211 is captured and includes the retimed clock signal 216A, which can be used in a feedback loop to adjust the output of VCO 211. The function of the retimer 216 is further described below with reference to Figure 2B.

[0038] A retime clock signal 216A is provided to the multiplexer 215. The multiplexer 215 also receives a feedback divider signal 214A from the feedback divider 214. The multiplexer 215 selects either the retime clock signal 216A or the feedback divider signal 214A. In one example, when the feedback divider 214 is disabled, the multiplexer output 215A includes the retime clock signal 216A. In one example, when the feedback divider 214 is enabled, the multiplexer output 215A includes the feedback divider signal 214A.

[0039] PFD202 receives the reference clock signal 201A and the multiplexer output 215A. PFD202 compares the multiplexer output 215A with the reference clock signal 201A and derives a phase error signal between the multiplexer output 215A and the reference clock signal 201A. As described above with reference to Figure 1, charge pumps 203 and 204 convert the phase error signals 202A and 202B from PFD202 into positive or negative current pulse trains proportional to the phase error. The current pulses from charge pumps 203 and 204 are filtered by a loop filter 220 which includes an amplifier 208, a capacitor C1206, a resistor R1207, a capacitor C2205, a resistor R2209, and a capacitor C3210. The voltage signal 220A from the loop filter 220 is input to VCO211 to control the VCO output signal 212, as described with reference to Figure 1. In one example, the loop filter 220 may contain fewer components than those listed herein. For instance, the loop filter 220 may exclude a passive filter including resistor R2209 and capacitor C3210.

[0040] In one example, the LO PLL circuit 200 may include means for disabling the feedback divider 214 and operating the LO PLL circuit in divider-disable mode. The feedback divider 214 may be disabled to conserve power. For example, when a wireless device is in sleep mode, the wireless device may enter a low-power operation mode or sniffer / listen mode to conserve power. In the low-power operation mode or sleep mode, the LO PLL circuit 200 may disable the feedback divider 214. Then, in one example, a signal may be received indicating that the wireless device has "woke up" to receive a message, and the divider-disable mode is turned off or released so that the feedback divider 214 can resume normal operation. The feedback divider 214 may be disabled, for example, by a switch at node 217, and the VCO output signal 212 switches between the feedback divider 214 and the retimer 216. A signal received by the LO PLL circuit 200 or in a switch may indicate that the LO PLL circuit 200 operates in divider-disable mode, for example, by switching the VCO output signal 212 to the retimer 216. In another example, the feedback divider 214 may be disabled using a buffer or inverter (not shown) between the divider buffer 213 and the node 217. In one example, the buffer or inverter may include an output enable function that receives a signal to operate in divider-disable mode, which can be used to disable the reception of the VCO output signal 212 by the divider buffer 213 and the feedback divider 214. This effectively disables the feedback divider 214 and the divider buffer 213. In one example, a buffer or inverter may be placed between the retimer 216 and the node 217 to disable or enable the VCO output signal 212 to the retimer 216. These are illustrative means by which the feedback divider 214 may be disabled to save power, and are not limiting to the present disclosure. Any means of controlling the VCO output signal 212 to disable the feedback divider 214 is considered.Means for disabling the feedback divider 214 can be controlled by software, hardware, or a combination of hardware and software.

[0041] In one embodiment, when the LO PLL circuit 200 is in listen mode or sniffer mode, the feedback divider 214 may operate in a divider-disabled mode, disabled using one or more of the above means, thereby saving energy. The LO PLL circuit 200 is configured, for example, by the above means, so that when the feedback divider 214 is disabled, the VCO output signal 212 can be received by the retimer 216.

[0042] Figure 2B is a timing diagram 250 according to several aspects of the present disclosure. The timing diagram 250 discloses a reference clock signal 201A, a VCO output signal 212, a retimed clock signal 216A, an up-pulse signal 254, and a down-pulse signal 255. In one example, the reference clock signal 201A is slower than the VCO output signal 212.

[0043] The retimer 216 receives a reference clock signal 201A from the clock reference 201 and a VCO output signal 212 from the VCO 211. The retimer 216 outputs a retime clock signal 216A. The retimer 216 may include one or more latches. When the reference clock signal 201A is high and the VCO output signal 212 is high, the retimer 216 latches the VCO output signal 212 and the retime clock signal 216A from the retimer 216 becomes high. When the reference clock signal 201A is low and the VCO output signal 212 is low, the retime clock signal 216A from the retimer 216 becomes low.

[0044] Referring to the up-pulse signal 254, when the reference clock signal 201A goes high, an up-pulse is triggered, and when the retime clock signal 216A goes high, that up-pulse goes low. Therefore, the width of the up-pulse signal 254 is proportional to the phase difference between the reference clock signal 201A and the retime clock signal 216A.

[0045] Referring here to the down pulse signal 255, in one example, the PFD202 predefines the width of the down pulse signal. For example, a component of the PFD202 such as an inverter may define the down pulse signal 255, but is not limited to this component. In one example, the down pulse signal 255 may be defined by other hardware, software, or a combination of hardware and software.

[0046] In integer N synthesis, the LO PLL circuit 200 is locked when the width of the up pulse signal 254 is equal to the width of the down pulse signal 255.

[0047] Figure 3A is a schematic diagram of an LO PLL circuit 300 using fractional synthesis according to several aspects of the present disclosure. The LO PLL circuit 300 includes a retimer 316 which may provide one or more retime clock signals. In one example, the retimer 316 provides a first retime clock signal 321, a second retime clock signal 322, a third retime clock signal 323, and a fourth retime clock signal 324, each of which has a subsequent edge based on the VCO output signal 312. In one example, the second retime clock signal 322 may be delayed by one cycle of the VCO output signal 312, the third retime clock signal 323 may be delayed by two cycles of the VCO output signal 312, and the fourth retime clock signal 324 may be delayed by three cycles of the VCO output signal 312. One or more retime clock signals may be delayed by any amount, and the above examples are not limiting.

[0048] To generate retime clock signals 321, 322, 323, and 324, retimer 316 receives a reference clock signal 301A from a reference clock 301 and a VCO output signal 312 from a VCO 311. In this example, retimer 316 may represent four retimers. In other examples, retimer 316 may represent more or fewer retimers. Returning to Figure 3A, the reference clock signal 301A may be applied in series to the four retimers of retimer 316, so that each retimer receives the VCO output signal 312 in sequence. The delay caused by the series connection of the reference clock signal 301A passing through each retimer provides retimer 316 with subsequent delayed retime clock signals 321, 322, 323, and 324 (collectively, retime clock signal 316A). For example, in the series connection of Figure 3A, the reference clock signal 301A received by retimer 325 is disclosed. Next, the retime clock signal 321 from retimer 325 is provided to retimer 326. Retimer 326 outputs a retime clock signal 322, which is received by retimer 327, and retimer 327 outputs a retime clock signal 323. Retime clock signal 323 is received by retimer 328, and retimer 328 outputs a retime clock signal 324. Retime clock signal 324 is received by retimer 329. Each retimer 325-329 can have a different effect on the respective retime clock signals that it receives. Each retimer 325-329 can delay or advance the timing.

[0049] Each of the retime clock signals 316A is determined as described above with reference to Figures 2A and 2B. When the reference clock signal 301A is high and the VCO output signal 312 is high, the retime clock signal is high, and when the reference clock signal 301A is low and the VCO output signal 312 is low, the retime clock signal is low. As described above, since the reference clock signal 301A is received in series between one or more retimers of the retimer 316, the retime clock signal 316A of the retimer 316 may be delayed, resulting in multiple subsequent clock edges received by the multiplexer 315.

[0050] The multiplexer 315 receives the retimed clock signal 316A and the feedback frequency divider signal 314A. The multiplexer 315 also receives the modulation signal 318A from the sigma-delta modulator 318. In one example, the modulation signal 318A is a sigma-delta modulated signal. Although the example in Figure 3A discloses the sigma-delta modulator 318, this disclosure is not limited to sigma-delta modulation, and fractional synthesis can be achieved using other modulators, etc.

[0051] In an example where fractional synthesis uses quadratic modulation, there are four retimed clock signals, and the modulated signal 318A includes four sigma-delta modulated signals received by the multiplexer 315. In one example, the modulated signal 318A may include modulation based on a division ratio between N-1, N+1, N, and N-2. The disclosure may be used with modulation of different orders.

[0052] The multiplexer 319 receives the feedback divider signal 314A and the reference clock signal 301A. In one example, the multiplexer 319 outputs the modulator input signal 319A to the sigma-delta modulator 318. The modulator input signal 319A acts as the clock signal for the sigma-delta modulator 318. When the feedback divider 314 is disabled, the multiplexer 319 allows the sigma-delta modulator 318 to continue providing the modulation signal 318A to the multiplexer 315. For example, when the feedback divider 314 is enabled, the modulator input signal 319A includes the feedback divider signal 314A. When the feedback divider 314 is disabled, the modulator input signal 319A includes the reference clock signal 301A. Therefore, the LO PLL circuit 300 continues to function even when the feedback divider 314 is disabled.

[0053] The retime clock signal 316A is provided to the multiplexer 315. The multiplexer 315 also receives the feedback divider signal 314A from the feedback divider 314. The multiplexer 315 selects between the retime clock signal 316A and the feedback divider signal 314A. When the feedback divider 314 is disabled, the multiplexer 315 outputs one of the retime clock signals 321, 322, 323, and 324. As will be explained in more detail with reference to Figure 3B below, the multiplexer 315 outputs a retime clock signal (321, 322, 323, and 324) that matches the exact edge of the modulated signal 318A.

[0054] PFD302 receives the reference clock signal 301A and the multiplexer output 315A from the multiplexer 315. PFD302 compares the reference clock signal 301A with the multiplexer output 315A and derives a phase error signal between the reference clock signal 301A and the multiplexer output 315A. As described above with reference to Figure 1, charge pumps 303 and 304 convert the phase error signals 302A and 302B from PFD302 into positive or negative current pulse trains proportional to the phase error. The current pulses from charge pumps 303 and 304 are filtered by a loop filter 320 which includes an amplifier 308, a capacitor C1306, a resistor R1307, a capacitor C2305, a resistor R2309, and a capacitor C3310. The voltage signal 320A from the loop filter 320 is input to the VCO 311 to control the frequency and phase of the VCO output signal 312, as described with reference to Figure 1. In one example, the loop filter 320 may include fewer components than those listed herein. For example, the loop filter 320 may omit a passive filter including a resistor R2309 and a capacitor C3310.

[0055] In one example, the LO PLL circuit 300 may include means for disabling the feedback divider 314. For example, a switch on node 317 may be used to switch the VCO output signal 312 between the feedback divider 314 and the retimer 316. In another example, the feedback divider 314 may be disabled using a buffer or inverter (not shown) between the divider buffer 313 and node 317. In one example, the buffer or inverter may include an output enable function that can be used to disable the reception of the VCO output signal 312 by the divider buffer 313 and the feedback divider 314, thereby effectively disabling the feedback divider 314 and the divider buffer 313. In one example, a buffer or inverter may be placed between the retimer 316 and node 317 to disable or enable the VCO output signal 312 to the retimer 316. These are illustrative means by which the feedback divider 314 may be disabled to save power, and are not limiting to the present disclosure. Any means of controlling the VCO output signal 312 to disable the feedback divider 314 is contemplated. The means of disabling the feedback divider 314 may be controlled by software, hardware, or a combination of hardware and software.

[0056] In one embodiment, when the LO PLL circuit 300 is in listen mode or sniffer mode, the feedback divider 314 may be disabled using one or more of the above means, thereby saving energy. The LO PLL circuit 300 is configured, for example, by the above means, such that when the feedback divider 314 is disabled, the VCO output signal 312 is received by the retimer 316.

[0057] Figure 3B is a timing diagram 350 showing a reference clock signal 301A and a VCO output signal 312 according to several aspects of the present disclosure. In an example where the sigma-delta modulator 318 uses quadratic modulation, switching the N counter between four different numerical values, the VCO output signal 312 is delayed in the retimer 316 to generate retimed clock signals 321, 322, 323, and 324. As described above, each retimed clock signal may be subsequently delayed by the same amount or other amounts.

[0058] For each sigma-delta modulation value (N-1, N-2, N, N+1) in Figure 3B, when the feedback divider 314 is disabled, a retimed clock signal may be output to the PFD 302, where the edges of the retimed clock signal are matched with the corresponding sigma-delta modulation. Referring to Figure 3B, in one example, at N-1, the exact edge 358 is the edge of the retimed clock signal 323, and therefore the multiplexer output 315A includes the retimed clock signal 323. At N+1, the exact edge 359 is the edge of the retimed clock signal 322, and therefore the multiplexer output 315A includes the retimed clock signal 322. At N, the exact edge 360 ​​is also the edge of the retimed clock signal 323, and therefore the multiplexer output 315A includes the retimed clock signal 322. Throughout this process, the retime clock signals 321, 322, 323, and 324 maintain the phase information of the VCO output signal 312, so that fractional synthesis can be performed when the feedback divider 314 is disabled. In addition, the VCO output signal 312 to the retimer 316 can be disabled after the generation of the retime clock signal 324 and re-enabled when the reference clock signal 301A goes high, thereby saving power consumption in the retimer 316.

[0059] Figure 4 is a timing diagram 400 according to several aspects of this disclosure, illustrating the difference between fractional synthesis and integer synthesis described above with reference to Figures 3A and 3B. Figure 4 shows the reference clock signal 401, the VCO output signal 402, and the retime clock signal 403, as described above with reference to Figures 2B and 3B. In integer synthesis, locking is achieved by the PLL in LO when the width of the up pulse train 404 is equal to the width of the down pulse train 405. In fractional synthesis disclosed with reference to Figures 3A and 3B, locking is achieved by the PLL in LO when the average width of the up pulse train 406 is equal to the width of the down pulse train 407.

[0060] The operation of the receiver will be further described with reference to Figures 2A, 3A, and 5. Figure 5 is a flowchart of a method 500 for performing local oscillation according to several embodiments of this disclosure. Method 500 is suitable to be implemented by the LO PLL circuit 200 in Figure 2 and the LO PLL circuit 300 in Figure 3, or other suitable integrated circuits. The process of Method 500 may be carried out in an order other than that described, and the processes may be carried out simultaneously and in parallel. Also, in some examples of this disclosure, the process of Method 500 may be omitted or replaced.

[0061] Referring to block 502, Figures 2A and 3A, the feedback divider 314 of the LO PLL circuit 300 and the feedback divider 214 of the LO PLL circuit 200 can be disabled. The feedback dividers 314 and 214 can be disabled by one or more of the means described above with reference to Figures 2A and 3A, including using switches or other logic circuit elements to disconnect the feedback dividers 314 and 214 and the divider buffers 313 and 213 from the VCO output signals 312 and 212, respectively. Additional hardware, software, and / or a combination of hardware and software may be used to disable the feedback dividers 314 and 214 and the divider buffers 313 and 213 so that they do not consume power.

[0062] Referring to block 504, Figures 2A and 3A, the reference clock signal 201A is received by the retimer 216 in Figure 2A, and the reference clock signal 301A is received by the retimer 316 in Figure 3A.

[0063] Referring to block 506, retimers 316 and 216 receive VCO output signals 312 and 212, respectively.

[0064] Referring to block 508 and Figure 3A, the retimer 316 generates a retime clock signal 316A. As described above with reference to Figure 3A, the retime clock signal 316A may include retime clock signals 321, 322, 323, and 324, each having a subsequent edge based on the VCO output signal 312. When the reference clock signal 301A is high and the VCO output signal 312 is high, the retime signal is high, and when the reference clock signal 301A is low and the VCO output signal 312 is low, the retime signal is low. As described above, since the reference clock signal 301A is received in series between one or more retimers of the retimer 316, the output of the retimer 316 may be delayed, so that a number of subsequent VCO clock edges are generated which are used in the fractional synthesis process disclosed herein to determine the error between a selected clock edge of the VCO output signal 312 and the reference clock signal 301A.

[0065] Referring to block 508 and Figure 2A, the retimer 216 generates a retimed clock signal 216A that provides the PFD 202 with phase information from the VCO 211 at a precise phase detection time. For example, the retimer 216 latches when the reference clock signal 201A is high and the VCO output signal 212 is high. Similarly, the retimed clock signal 216A goes low when, for example, the reference clock signal 201A is low and the VCO output signal 212 is low. As a result, the retimed clock signal 216A generated by the retimer 216 based on the reference clock signal 201A and the VCO output signal 212 is obtained.

[0066] Referring to block 510 and Figures 3A and 3B, the multiplexer 315 receives a retime clock signal 316A from the retimer 316 and a modulated signal 318A from the sigma-delta modulator 318. The modulated signal 318A is multiplexed with the retime clock signal 316A from the retimer 316, and the multiplexer 315 generates a retime clock signal 321, 322, 323, or 324 that matches the precise edge of the modulated signal 318A, which is received by the PFD 302 as a multiplexer output 315A.

[0067] Referring to block 512, Figure 2A, and Figure 3A, the error signal is determined based on the retimed clock signal. In Figure 2A, PFD202 receives the reference clock signal 201A and the multiplexer output 215A. PFD202 compares the reference clock signal 201A with the multiplexer output 215A and derives the phase error signals 202A and 202B between the reference clock signal 201A and the multiplexer output 215A. In Figure 3A, PFD302 receives the reference clock signal 301A and the multiplexer output 315A. PFD302 compares the reference clock signal 301A with the multiplexer output 315A and derives the phase error signals 302A and 302B between the reference clock signal 301A and the multiplexer output 315A.

[0068] Referring to block 514, Figures 2A and 3A, a phase error signal between the reference clock signal and a retimed clock signal based on the VCO output signal is used to adjust the VCO, thereby adjusting the frequency and phase of the VCO output signal. In one example, the phase error signal from the PFD may be amplified and filtered as described above. Referring to Figure 2A, voltage signal 220A represents the phase error, and voltage signal 220A controls the VCO output signal 212 as described with reference to Figure 1. Referring to Figure 3A, voltage signal 320A represents the phase error, and voltage signal 320A controls the VCO output signal 312 as described with reference to Figure 1.

[0069] LO PLL circuits 200 and 300 or other integrated circuit devices can perform the process of method 500 using any combination of dedicated hardware and instructions stored in a non-temporary medium. Thus, elements of LO PLL circuits 200 and 300 may include processing resources coupled to a non-temporary computer-readable medium. Processing resources may include one or more microcontrollers, ASICs, CPUs, GPUs, and / or other processing resources configured to execute instructions stored on a non-temporary computer-readable medium. Examples of suitable non-temporary computer-readable media include one or more flash memory devices, battery-backed RAM, SSDs, HDDs, optical media, and / or other memory devices suitable for storing instructions for processing resources.

[0070] This disclosure provides numerous illustrative examples, and it will be understood that modifications are possible to these examples. Such modifications are clearly within the scope of this disclosure. Furthermore, applying these teachings to other environments, applications, and / or purposes is consistent with and contemplated by this disclosure.

[0071] The term “coupled” is used throughout this specification. This term may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain operation, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via intervening component C, such that device B is controlled by device A via a control signal generated by device A, provided that intervening component C does not substantially alter the functional relationship between device A and device B.

Claims

1. An integrated circuit device, A re-timer circuit is configured to receive a reference clock signal and a voltage-controlled oscillator (VCO) output signal, and to provide a re-timed clock signal in response to the reference clock signal and the VCO output signal, A first multiplexer configured to receive the retime clock signal and the feedback clock signal, and to selectively provide the feedback clock signal or the retime clock signal, A phase frequency detector (PFD) is configured to receive the output signal of the first multiplexer and the reference clock signal, and to provide an error signal in response to the output signal of the first multiplexer and the reference clock signal, A voltage-controlled oscillator (VCO) is configured to receive a voltage signal based on the error signal and to provide the VCO output signal in response to the voltage signal, and the VCO is configured to receive a voltage signal based on the error signal and to provide the VCO output signal in response to the voltage signal. A feedback frequency divider configured to provide the feedback clock signal based on the VCO output signal, Includes, An integrated circuit device in which the first multiplexer provides the retimed clock signal in frequency divider disabled mode.

2. An integrated circuit device according to claim 1, A charge pump configured to receive the error signal and provide a charge pump output signal, A filter configured to receive the charge pump output signal and provide the voltage signal, Integrated circuit devices, further including the following.

3. An integrated circuit device according to claim 2, An integrated circuit device in which the feedback frequency divider is configured to receive a modulation signal, and the first multiplexer is configured to receive the modulation signal.

4. An integrated circuit device according to claim 3, An integrated circuit device further comprising a sigma-delta modulator configured to provide the aforementioned modulated signal.

5. An integrated circuit device according to claim 4, An integrated circuit device further comprising a second multiplexer configured to receive the reference clock signal and the feedback clock signal, and to selectively provide the feedback clock signal or the reference clock signal to the sigma-delta modulator.

6. An integrated circuit device according to claim 1, The aforementioned retimer circuit A first retimer, configured to receive the reference clock signal and the VCO output signal, and to provide a first retime clock signal in response to the reference clock signal and the VCO output signal, A second retimer, configured to receive the first retime clock signal and the VCO output signal, and to provide a second retime clock signal in response to the first retime clock signal and the VCO output signal, A third retimer, configured to receive the second retime clock signal and the VCO output signal, and to provide a third retime clock signal in response to the second retime clock signal and the VCO output signal, A fourth retimer, configured to receive the third retime clock signal and the VCO output signal, and to provide a fourth retime clock signal in response to the third retime clock signal and the VCO output signal, Integrated circuit devices, including those mentioned above.

7. An integrated circuit device according to claim 6, An integrated circuit device wherein the first multiplexer is further configured to receive the first, second, third, and fourth retime clock signals as the retime clock signals.

8. An integrated circuit device according to claim 7, An integrated circuit device in which the first multiplexer is further configured to provide a feedback signal based on the first, second, third, and fourth retimed clock signals.

9. An integrated circuit device according to claim 1, An integrated circuit device in which the feedback frequency divider is further configured to be disabled in response to a low-power operating mode.

10. An integrated circuit device according to claim 2, An integrated circuit device further comprising a frequency divider buffer coupled between the VCO and the feedback frequency divider.

11. An integrated circuit device according to claim 2, An integrated circuit device in which the filter includes an active filter.

12. An integrated circuit device according to claim 1, An integrated circuit device in which the error signal includes an up pulse or a down pulse.

13. It is an integrated circuit, A retimer circuit including a first input for receiving a reference clock signal, a second input, and an output for providing a retime clock signal, A first multiplexer including a first input coupled to the output of the retimer circuit, a second input for receiving a feedback clock signal, and an output for selectively providing the feedback clock signal or the retimer clock signal, A phase frequency detector (PFD) includes a first input for receiving the reference clock signal, a second input coupled to the output of the first multiplexer, and an output for providing an error signal. A charge pump including an input and an output connected to the output of the PFD, A filter including an input and an output coupled to the output of the charge pump, A voltage-controlled oscillator (VCO) including an input coupled to the output of the filter and an output coupled to the second input of the retimer circuit, A feedback frequency divider including an input coupled to the output of the VCO and an output coupled to the second input of the first multiplexer, Includes, An integrated circuit in which the first multiplexer provides the retimed clock signal in frequency divider disabled mode.

14. The integrated circuit according to claim 13, An integrated circuit further comprising a modulator coupled to the feedback frequency divider.

15. The integrated circuit according to claim 14, An integrated circuit further comprising a second multiplexer having a first input for receiving the reference clock signal, a second input coupled to the output of the feedback divider, and an output coupled to the modulator.

16. The integrated circuit according to claim 15, The aforementioned retimer circuit A first retimer including an input for receiving the reference clock signal and an output coupled to the first multiplexer, A second retimer having an input coupled to the output of the first retimer and an output coupled to the first multiplexer, A third retimer having an input coupled to the output of the second retimer and an output coupled to the first multiplexer, A fourth retimer, including an input coupled to the output of the third retimer and an output coupled to the first multiplexer, An integrated circuit, including

17. It is a method, The retimer receives the reference clock signal and the voltage-controlled oscillator (VCO) output signal, The retimer generates a retimed clock signal by resetting the timing of the reference clock signal according to the VCO output signal, A frequency divider provides a feedback clock signal based on the VCO output signal, The multiplexer selectively provides the retimed clock signal or the feedback clock signal, An error signal is provided by a phase frequency detector (PFD) based on the retime clock signal or the feedback clock signal and the reference clock signal. The VCO output signal is modified based on the error signal, Includes, A method in which the retimed clock signal is provided from the multiplexer in frequency divider disabled mode.

18. The method according to claim 17, A method wherein the retime clock signal includes a first retime clock signal based on the reference clock signal and the VCO output signal, a second retime clock signal based on the first retime clock signal and the VCO output signal, a third retime clock signal based on the second retime clock signal and the VCO output signal, and a fourth retime clock signal based on the third retime clock signal and the VCO output signal.

19. The method according to claim 18, The retime clock signal is received by the multiplexer, The multiplexer receives the feedback clock signal, The multiplexer receives the modulated signal from the modulator, It further includes, A method wherein the multiplexer is configured to select one of the first, second, third, and fourth retime clock signals based on the modulated signal.

20. The method according to claim 17, Receiving a signal to operate the frequency divider in disabled mode, Disable the feedback clock signal in response to receiving a signal for operating in the frequency divider disabled mode, Methods that further include the above.

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