Semiconductor equipment
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- YAZAKI CORP
- Filing Date
- 2022-09-12
- Publication Date
- 2026-05-27
AI Technical Summary
The miniaturization of semiconductor devices leads to reduced pitch between lands, increasing the risk of solder bridges during soldering, while also reducing the durability of solder joints due to thermal stress.
A semiconductor device design with a solder resist layer that exposes the side surface of corner lands through a resist clearance, allowing for increased bonding area and contact angle, thereby enhancing durability and preventing solder bridges.
The design effectively suppresses solder bridges and improves solder durability against temperature changes by distributing stress and increasing the bonding area of corner lands.
Smart Images
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Figure 0007866462000003
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device.
Background Art
[0002] As this type of conventional technology, what is disclosed in Patent Document 1 has been proposed. Patent Document 1 discloses a semiconductor device formed by soldering a semiconductor package to a printed wiring board (mounting substrate).
[0003] In this Patent Document 1, a plurality of lands are formed on a printed wiring board (mounting substrate). Among the plurality of lands, the lands arranged at the corners are formed such that a part of the ends is exposed from the solder resist. By doing so, it is possible to prevent the thermal stress due to the thermal deformation of the semiconductor device from locally concentrating and occurring, and thus to prevent the solder joined to the land from peeling off.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] By the way, in recent years, with the miniaturization of semiconductor devices, there has been a tendency to reduce the pitch between a plurality of lands. When the pitch between a plurality of lands is reduced, there is a risk that solder bridges will occur during soldering.
[0006] Therefore, when attempting to reduce the pitch between a plurality of lands, it is preferable to be able to prevent the solder joined to the land from peeling off while suppressing the occurrence of solder bridges due to the reduced pitch.
[0007] This invention has been made in view of the problems of the prior art described above. The object of this invention is to provide a semiconductor device that can more reliably suppress the occurrence of solder bridges, even when a multi-pole and narrow-pitch design is implemented, while further improving the durability of the solder against temperature changes. [Means for solving the problem]
[0008] A semiconductor device according to one aspect of the present invention comprises a semiconductor package and a mounting substrate to which the semiconductor package is bonded, wherein the mounting substrate comprises a substrate body, a solder resist layer disposed on the surface of the substrate body, and a plurality of lands disposed on the surface of the substrate body in a state of being electrically insulated by the solder resist layer and bonded to the semiconductor package by solder, wherein the plurality of lands comprises a corner land disposed at a corner, a first land adjacent to the corner land in a first direction, and a second land adjacent to the corner land in a second direction intersecting the first direction, wherein the contour line of the corner land in a plan view is defined as the first shortest point located furthest out in the second direction among the parts with the shortest distance from the first land, and the second land When the corner land is divided into an inner contour line and an outer contour line by a second shortest point, which is the outermost point in the first direction among the parts that are closest to the land, and the peripheral edge of the corner land in a plan view of the solder resist layer is divided into an inner region defined by a first half-line extending outward from the first shortest point in the second direction, a second half-line extending outward from the second shortest point in the first direction, and the inner contour line, and an outer region defined by the first half-line, the second half-line, and the outer contour line, the solder resist layer has a resist clearance that exposes the side surface of the corner land, formed only in the outer region of the inner region and the outer region, and the corner land is joined with solder up to the side surface exposed by the resist clearance. [Effects of the Invention]
[0009] According to the present invention, even when a multi-pole and narrow-pitch design is implemented, it is possible to provide a semiconductor device that can more reliably suppress the occurrence of solder bridges while further improving the durability of the solder against temperature changes. [Brief explanation of the drawing]
[0010] [Figure 1] A plan view showing an example of a mounting substrate included in a semiconductor device according to one embodiment. [Figure 2] This is a partially enlarged cross-sectional view showing an example of a semiconductor device according to one embodiment. [Figure 3] This is a cross-sectional view showing a partially enlarged portion of the semiconductor device relating to the comparative example. [Figure 4] This is a plan view showing the mounting substrate of a semiconductor device according to the first modified example. [Figure 5] This is a cross-sectional view showing a partially enlarged portion of the semiconductor device according to the first modified example. [Figure 6] This is a plan view showing the mounting substrate of a semiconductor device according to the second modified example. [Modes for carrying out the invention]
[0011] The semiconductor device according to this embodiment will be described in detail below with reference to the drawings. Note that the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios.
[0012] As shown in Figure 1, the semiconductor device 1 according to this embodiment includes a mounting substrate 20 that is substantially rectangular in shape when viewed in plan (along the Z direction). Then, as shown in Figure 2, the semiconductor device 1 is formed by bonding a semiconductor package 10 to this mounting substrate 20 with solder 30. Thus, the semiconductor device 1 according to this embodiment includes a semiconductor package 10 and a mounting substrate 20 to which the semiconductor package 10 is bonded.
[0013] Such a semiconductor device 1 can be used, for example, as part of an imaging device using a semiconductor package 10 that has a camera function.
[0014] As shown in Figure 2, the semiconductor package 10 comprises a substrate body 11 and a solder resist layer 12 disposed on the surface 111 of the substrate body 11. Furthermore, the semiconductor package 10 includes a plurality of electrodes 13 disposed on the surface 111 of the substrate body 11 in a state of electrical insulation by the solder resist layer 12.
[0015] In this embodiment, the substrate body 11 is a rigid substrate formed in the shape of a substantially rectangular plate. This substrate body 11 can be formed from an electrically insulating material such as glass epoxy resin. The solder resist layer 12 is an insulating layer laminated on the surface 111 of the substrate body 11, and can be formed from a ceramic such as alumina. Multiple electrodes 13 made of a conductive material (for example, a metallic material such as copper) are arranged to be exposed on the surface side while being electrically insulated by the solder resist layer 12, which acts as an insulating layer. In this embodiment, a BGA (Ball Grid Array) type semiconductor package is used as such a semiconductor package 10, in which electrodes 13 that are substantially circular in plan view are arranged in a grid pattern.
[0016] Similarly, as shown in Figures 1 and 2, the mounting substrate 20 comprises a substrate body 21 and a solder resist layer 22 disposed on the surface 211 of the substrate body 21. Furthermore, the mounting substrate 20 comprises a plurality of lands 23 disposed on the surface 211 of the substrate body 21 while being electrically insulated by the solder resist layer 22.
[0017] The substrate body 21 is also a rigid substrate formed in a substantially rectangular plate shape in this embodiment. And this substrate body 21 can also be formed of a material having electrical insulation properties such as glass epoxy resin, for example. Also, the solder resist layer 22 is an insulating layer laminated on the surface 211 of the substrate body 21, and can be formed using a ceramic such as alumina, for example. And a plurality of lands 23 formed of a conductive material (for example, a metal material such as copper) are arranged so as to be exposed on the surface side in a state of being electrically insulated by the solder resist layer 22 as an insulating layer. In this embodiment, the same number of lands 23 as the electrodes 13 formed on the semiconductor package 10 are formed on the substrate body 21, and each land 23 is formed at a position corresponding to the electrode 13 in the substrate body 21. Specifically, on the substrate body 21, the lands 23 having a substantially circular shape in plan view are arranged in a lattice pattern. By doing so, the plurality of lands 23 include a corner land 231 arranged at a corner, a first land 232 adjacent to the corner land 231 in the first direction, and a second land 233 adjacent to the corner land 231 in the second direction intersecting the first direction. In this embodiment, for convenience, the X direction extending in the vertical direction of FIG. 1 is defined as the first direction, and the Y direction extending in the left-right direction of FIG. 1 is defined as the second direction. Also, in FIG. 1, only the land 23 arranged at the lower left corner is illustrated as the corner land 231, but it is preferable to regard all four corners of the lands 23 arranged in a lattice pattern as the corner lands 231.
[0018] And by joining the paired electrodes 13 and lands 23 with solder 30 respectively, the semiconductor package 10 is joined to the mounting substrate 20 with solder 30.
[0019] At this time, if all the lands 23 are joined to the corresponding electrodes 13 with solder in a state where the entire side surface is in contact with the solder resist layer 22, the joining force of the solder 30 can be made substantially equal regardless of the position of the lands 23.
[0020] However, when the semiconductor device 1 is formed such that the bonding forces of the solder 30 are substantially equal, when the substrate bodies 11 and 21 are warped due to the difference in the coefficients of thermal expansion between the semiconductor package 10 and the mounting substrate 20 when the temperature changes, stress concentrates on the lands 23 arranged at the four corners.
[0021] Therefore, when the semiconductor device 1 is formed such that the bonding forces of the solder 30 are substantially equal, the lands 23 arranged at the four corners are more affected by stress concentration due to the warping of the substrate, and there was a risk that the durability of the solder 30 would decrease.
[0022] Therefore, in the present embodiment, the durability of the solder 30 due to temperature changes can be further improved.
[0023] Specifically, a resist clearance 221 is provided around the corner land 231 arranged at the corner so that the side surface 2312 of the corner land 231 is exposed, and this exposed side surface 2312 is also joined with the solder 30.
[0024] By doing so, the bonding force of the solder 30 of the corner land 231 arranged at the corner is made larger than the bonding force of the solder 30 in the lands 23 arranged at other parts, and the concentration of stress on the lands 23 arranged at the four corners can be more reliably suppressed.
[0025] Furthermore, in the present embodiment, even when multi-polar and pitch reduction are achieved, the occurrence of solder bridges can be more reliably suppressed.
[0026] Specifically, when the contour line C1 of the corner land 231 in a plan view is divided into an inner contour line C11 and an outer contour line C12 by the first shortest point P1 and the second shortest point P2, and the peripheral edge R of the corner land 231 in a plan view of the solder resist layer 22 is divided into an inner region R1 and an outer region R2, the solder resist layer 22 is formed such that a resist clearance 221 that exposes the side surface 2312 of the corner land 231 is formed only in the outer region R2 of the inner region R1 and the outer region R2.
[0027] Here, the first shortest point P1 is the outermost point in the second direction (Y direction) among the parts that are closest to the first land 232. Similarly, the second shortest point P2 is the outermost point in the first direction (X direction) among the parts that are closest to the second land 233.
[0028] Furthermore, the inner region R1 is the region demarcated by the first half-line L1 extending outward in the second direction (Y direction) from the first shortest point P1, the second half-line L2 extending outward in the first direction (X direction) from the second shortest point P2, and the inner contour line C11. Similarly, the outer region R2 is the region demarcated by the first half-line L1, the second half-line L2, and the outer contour line C12.
[0029] Furthermore, the corner land 231 is joined with solder 30 up to the side surface 2312 exposed by the resist clearance 221.
[0030] Furthermore, in this embodiment, the resist clearance 221 is formed so that the entire surface of the side surface 23122 on the outer contour line C12 side of the corner land 231 is exposed.
[0031] This ensures that when the corner lands 231 located at the four corners are joined with solder 30, not only the top surface 2311 of the corner lands 231 but also the entire surface of the outer side 2312 is joined with solder 30. This makes it possible to make the contact angle θ1 of the solder 30 on the outside of the corner lands 231, which are prone to warping and stress concentration due to the difference in thermal expansion coefficients between the semiconductor package 10 and the mounting substrate 20 when temperature changes occur, larger than the contact angle θ2 shown in Figure 3. Note that Figure 3 shows a conventional semiconductor device 1A, and the contact angle θ2 shown in Figure 3 is the contact angle on the outside of the solder 30 when the corner lands 231 are joined with solder 30 without forming a resist clearance 221.
[0032] In this embodiment, by increasing the contact angle θ1 on the outside of the solder 30, it is possible to suppress warping and stress concentration on the outside of the corner land 231, thereby further improving the durability of the solder 30 against temperature changes.
[0033] Furthermore, the solder resist layer 22 is designed so that a resist clearance 221 is not formed in the inner region R1 of the peripheral edge R of the corner land 231, which is on the side of the first land 232 and the second land 233. In other words, the entire surface of the side surface 23121 on the inner contour line C11 side, which is on the side of the first land 232 and the second land 233, is in contact with the solder resist layer 22. This prevents the distance to the first land 232 and the second land 233 in the area where the solder resist layer 22 is present from becoming too short. This makes it possible to more reliably prevent solder bridges from forming between the corner land 231 and the first land 232, and between the corner land 231 and the second land 233.
[0034] Furthermore, the semiconductor package 10 and the mounting substrate 20 can also be configured as shown in Figures 4 and 5. In the semiconductor package 10 shown in Figures 4 and 5, an overresist portion is formed around the electrode 13. On the other hand, in the mounting substrate 20 shown in Figures 4 and 5, an overresist portion 222 is formed only on the inner contour line C11 side of the corner land 231.
[0035] Even with this configuration, it is possible to achieve almost the same functions and effects as the configuration shown in the above embodiment.
[0036] Furthermore, as shown in Figure 6, it is also possible to use a mounting substrate 20 that is compatible with LGA (Land Grid Array) type semiconductor packages. On the substrate body 21 of the mounting substrate 20 shown in Figure 6, lands 23 that are roughly rectangular in plan view are arranged in a grid pattern.
[0037] In this way, when the lands 23, which are roughly rectangular in plan view, are arranged in a grid, the edge S1 on the side of the first land 232 is the part that is closest to the first land 232. The point on edge S1 that is furthest out in the second direction (Y direction) (the upper left vertex in Figure 6) is the first shortest point P1. Similarly, the edge S2 on the side of the second land 233 is the part that is closest to the second land 233, and the point on edge S2 that is furthest out in the first direction (X direction) (the lower right vertex in Figure 6) is the second shortest point P2.
[0038] Even with this configuration, it is possible to achieve almost the same functions and effects as the configuration shown in the above embodiment.
[0039] [Effects / Effects] The following describes the characteristic configuration of the semiconductor device shown in the above embodiment and its modifications, and the effects obtained thereby.
[0040] The semiconductor device 1 shown in the above embodiment and its modifications comprises a semiconductor package 10 and a mounting substrate 20 to which the semiconductor package 10 is bonded.
[0041] Furthermore, the mounting substrate 20 comprises a substrate body 21 and a solder resist layer 22 disposed on the surface 211 of the substrate body 21. In addition, the mounting substrate 20 is disposed on the surface 211 of the substrate body 211 in a state of electrical insulation by the solder resist layer 22 and comprises a plurality of lands 23 that are joined to the semiconductor package 10 with solder 30.
[0042] Here, the multiple lands 23 include a corner land 231 positioned at the corner, a first land 232 adjacent to the corner land 231 in a first direction (X direction), and a second land 233 adjacent to the corner land 231 in a second direction (Y direction) that intersects the first direction (X direction).
[0043] Furthermore, when the contour line C1 of the corner land 231 in a plan view is divided into an inner contour line C11 and an outer contour line C12 by the first shortest point P1 and the second shortest point P2, and the peripheral edge R of the corner land 231 in a plan view of the solder resist layer 22 is divided into an inner region R1 and an outer region R2, the solder resist layer 22 is formed such that a resist clearance 221 that exposes the side surface 2312 of the corner land 231 is formed only in the outer region R2 of the inner region R1 and the outer region R2.
[0044] Here, the first shortest point P1 is the outermost point in the second direction (Y direction) among the parts that are closest to the first land 232. Similarly, the second shortest point P2 is the outermost point in the first direction (X direction) among the parts that are closest to the second land 233.
[0045] Furthermore, the inner region R1 is the region demarcated by the first half-line L1 extending outward in the second direction (Y direction) from the first shortest point P1, the second half-line L2 extending outward in the first direction (X direction) from the second shortest point P2, and the inner contour line C11. Similarly, the outer region R2 is the region demarcated by the first half-line L1, the second half-line L2, and the outer contour line C12.
[0046] The corner land 231 is then joined with solder 30 to the side surface 2312 exposed by the resist clearance 221.
[0047] As described above, in the semiconductor device 1 shown in the embodiment and its modified form, when joining the lands located at the four corners (corner lands 231) with solder 30, the solder 30 is extended to the side surface 2312 located outside the corner lands 231. This makes it possible to increase the contact angle θ1 of the solder 30 on the outside of the corner lands 231, where warping and stress concentration are likely to occur due to the difference in thermal expansion coefficients between the semiconductor package 10 and the mounting substrate 20 when temperature changes occur. As a result, warping and stress concentration on the outside of the corner lands 231 are suppressed, and the durability of the solder against temperature changes is further improved.
[0048] Furthermore, in the semiconductor device 1 shown in the above embodiment and its modified form, resist clearance 221 is not formed in the inner region R1 of the peripheral edge R of the corner land 231 in the solder resist layer 22, which is on the side of the first land 232 and the side of the second land 233. That is, the side surface 2312 of the corner land 231 is in contact with the solder resist layer 22 on the inner contour line C11 side, which is on the side of the first land 232 and the side of the second land 233. This makes it possible to suppress the shortening of the distance to the first land 232 and the second land 233 in the portion where the solder resist layer 22 is present. As a result, it becomes possible to more reliably suppress the formation of solder bridges between the corner land 231 and the first land 232, and between the corner land 231 and the second land 233.
[0049] Thus, with the semiconductor device 1 shown in the above embodiment and its modifications, even when multiple poles and a narrow pitch are implemented, it becomes possible to more reliably suppress the occurrence of solder bridges and further improve the durability of the solder against temperature changes.
[0050] Furthermore, the resist clearance 221 may be formed such that the entire surface of the side surface 23122 on the outer contour line C12 side of the corner land 231 is exposed.
[0051] This makes it possible to apply solder 30 to the entire surface of the side surface 23122 on the outer contour line C12 side, outside the corner land 231 where warping and stress concentration are likely to occur due to the difference in thermal expansion coefficients between the semiconductor package 10 and the mounting substrate 20 when temperature changes occur. As a result, it becomes possible to further improve the durability of the solder 30 against temperature changes.
[0052] [others] Although this embodiment has been described above, this embodiment is not limited to these, and various modifications are possible within the scope of the gist of this embodiment.
[0053] For example, it is possible to use a configuration that appropriately combines the configurations described in the above embodiment and its modified form.
[0054] Furthermore, while the above embodiments and their modifications illustrate lands 23 having a circular or square contour shape, the contour shape of the land 23 can be various shapes, such as polygonal shapes other than squares.
[0055] Furthermore, in the above embodiments and their modifications, BGA (Ball Grid Array) semiconductor packages and LGA (Land Grid Array) semiconductor packages were given as examples for the semiconductor package 10, but it is also possible to use a QFP (Quad Flat Package) semiconductor package.
[0056] Furthermore, in the above embodiment and its modifications, the resist clearance 221 is shown as being formed so that the entire surface of the side surface 23122 on the outer contour line C12 side of the corner land 231 is exposed. However, it is also possible to expose only a part of the side surface 23122.
[0057] Furthermore, while the above embodiments and their modifications illustrate the formation of multiple lands 23 at the corners of the mounting substrate 20, it is also possible to form multiple lands 23 at locations other than the corners, such as the central part of the mounting substrate 20. In this case, the region where the semiconductor package 10 and the mounting substrate 20 overlap in the thickness direction (mounting direction: Z direction) is designated as the land 23 mounting region, and the lands 23 positioned at the corners of this mounting region are designated as corner lands 231, thereby enabling the application of the present invention.
[0058] Furthermore, the specifications of the semiconductor package, mounting substrate, and other details (shape, size, layout, etc.) can be changed as needed. [Explanation of Symbols]
[0059] 1 Semiconductor device 10 Semiconductor Packages 20 Implemented circuit boards 21 Main board 211 Surface 22 Solder Resist Layers R peripheral area R1 medial region R2 outer area 221 Resist Clearance 23 Rand 231 Corner Land 2312 Side view 23122 Side view on the outer contour line side C1 Outline C11 Inner contour line C12 Outer contour P1 1st shortest point P2 2nd shortest point L1 1st half line L2 2nd half line 232 First Round 233 Second Round 30 solder X direction 1st direction Y direction, second direction
Claims
[Claim 1] Semiconductor packages and A mounting substrate on which the aforementioned semiconductor package is bonded, Equipped with, The aforementioned mounting board is The main circuit board and A solder resist layer disposed on the surface of the substrate body, A plurality of lands are arranged on the surface of the substrate body in a state of being electrically insulated by the solder resist layer and are joined to the semiconductor package by solder, Equipped with, The aforementioned multiple lands are Corner lands placed at the corners, The aforementioned corner land and the first land adjacent to it in the first direction, The aforementioned corner land and a second land adjacent to it in a second direction intersecting the first direction, It is equipped with, The contour line of the corner land in plan view is divided into an inner contour line and an outer contour line by a first shortest point located furthest out in the second direction among the parts that are closest to the first land, and a second shortest point located furthest out in the first direction among the parts that are closest to the second land. When the peripheral edge of the corner land in a plan view of the solder resist layer is divided into an inner region defined by a first half-line extending outward from the first shortest point in the second direction, a second half-line extending outward from the second shortest point in the first direction, and the inner contour line, and an outer region defined by the first half-line, the second half-line, and the outer contour line, The solder resist layer has a resist clearance that exposes the side surface of the corner land, formed only in the outer region of the inner region and the outer region. The corner land is joined with solder up to the side surface exposed by the resist clearance. The resist clearance is formed such that the entire surface of the side of the corner land on the outer contour line side is exposed. Semiconductor equipment.