Magnetic disk drive

Abstract

To detect fraud of a parity generated from truck-wise data.SOLUTION: A magnetic disc device includes an HDC and an RWC. The HDC receives a plurality of data pieces from a host, performs, for each of the data pieces, generation and addition of first codes and output of the data pieces added with the first codes. The HDC calculates an exclusive logic sum for a group of first codes and outputs obtained first information. The RWC performs data conversion and exclusive logic sum calculation for the plurality of data pieces added with the first codes, and outputs the plurality of data pieces already subjected to the data conversion and a truck parity obtained by the exclusive logic sum calculation. The RWC obtains the first codes from the plurality of data pieces. The RWC calculates an exclusive logic sum for a group of second codes as the obtained first codes to obtain second information. The RWC compares first information with the second information and outputs a result of the comparison.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] This embodiment relates to a magnetic disk drive.

Background Art

[0002] There is a magnetic disk drive having a function of protecting data written on each track in track units. Each track is provided with a sector for recording parity. A sector for recording parity is referred to as a parity sector. A sector for recording host data is referred to as a data sector. Parity generated from host data written to all data sectors in a track is written to the parity sector. By this mechanism, host data stored in all data sectors in a track is protected by the parity stored in the parity sector until the host data in any one of the data sectors is updated.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a magnetic disk drive capable of detecting falsification of parity generated from track unit data.

Means for Solving the Problems

[0005] A magnetic disk drive according to one embodiment is connectable to a host. The magnetic disk drive comprises a magnetic disk, a first circuit block, a second circuit block, and a magnetic head. The magnetic disk is provided with a track that includes a plurality of first sectors and a plurality of second sectors. The first circuit block receives a plurality of first data fragments written to the plurality of first sectors from the host, and performs the generation of a first code, the addition of the first code, and the output of the first data fragment with the first code added for each of the plurality of first data fragments. The first circuit block also calculates the exclusive OR of the group of first codes generated from each of the plurality of first data fragments, and outputs first information which is the information obtained by calculating the exclusive OR of the group of first codes. The second circuit block receives a plurality of second data fragments which are a plurality of first data fragments each with the first code added that were output from the first circuit block, and the first information output from the first circuit block. The second circuit block performs data conversion and outputs a third data piece, which is the second data piece after the data conversion, for each of the multiple second data pieces. The second circuit block calculates the exclusive OR of the multiple third data pieces generated by the data conversion for each of the multiple second data pieces, and outputs the parity, which is the information obtained from calculating the exclusive OR of the multiple third data pieces, following the output of the multiple third data pieces. The second circuit block obtains a first code from each of the multiple second data pieces and calculates the exclusive OR of the group of second codes, which are the first codes obtained from each of the multiple second data pieces. The second circuit block compares the second information, which is the information obtained from calculating the exclusive OR of the group of second codes, with the first information, and outputs the result of the comparison between the second information and the first information. The magnetic head writes the multiple third data pieces output from the second circuit block to multiple first sectors, and writes the parity output from the second circuit block to the second sector. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a magnetic disk drive according to an embodiment. [Figure 2] Figure 2 shows an example of the configuration of a magnetic disk in an embodiment. [Figure 3] Figure 3 is a diagram illustrating an example of data processing performed by the controller of the embodiment. [Figure 4] Figure 4 is a schematic diagram showing an example of the configuration of one track in the embodiment. [Figure 5] Figure 5 is a schematic diagram showing an example of the hardware configuration of the HDC in this embodiment. [Figure 6] Figure 6 shows an example of the hardware configuration of the RWC in this embodiment. [Figure 7] Figure 7 is a flowchart showing an example of the operation of calculating an exclusive OR using the XOR circuit of the embodiment (first XOR operation). [Figure 8] Figure 8 is a flowchart showing an example of the operation of the CRC XOR circuit in the embodiment for calculating the exclusive OR (second XOR operation). [Figure 9] Figure 9 is a flowchart showing an example of the operation of the selector in the embodiment. [Figure 10] Figure 10 is a flowchart showing an example of RWC operation when a track-by-track light operation is interrupted and resumed in the embodiment. [Figure 11] Figure 11 is a flowchart showing an example of the operation of the processor in the embodiment. [Figure 12] Figure 12 is a flowchart showing an example of the operation of a processor in a modified embodiment. [Modes for carrying out the invention]

[0007] The magnetic disk device according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (Embodiment) Figure 1 is a schematic diagram showing an example of the configuration of the magnetic disk device 1 of the embodiment.

[0009] The magnetic disk drive 1 is connectable to host 2. When connected to host 2, the magnetic disk drive 1 can receive access commands from host 2. Access commands include write commands and read commands.

[0010] The magnetic disk drive 1 includes a magnetic disk 11 on which a magnetic layer is formed on its surface. The magnetic disk drive 1 writes data to the magnetic disk 11 or reads data from the magnetic disk 11 in response to access commands.

[0011] Access commands include logical addresses. The magnetic disk drive 1 provides a logical address space to the host 2. A logical address indicates a location within that address space. The host 2 uses logical addresses to specify the location for writing or reading data. In other words, a logical address is location information specified by the host 2. Note that logical addresses are denoted as LBA (Logical Block Address).

[0012] Data is written and read via the magnetic head 22. In addition to the magnetic disk 11, the magnetic disk device 1 includes a spindle motor 12, a lamp 13, an actuator arm 15, a voice coil motor (VCM) 16, a motor driver IC (Integrated Circuit) 21, a magnetic head 22, a hard disk controller (HDC) 23, a head IC 24, a read / write channel (RWC) 25, a processor 26, RAM 27, and FROM (Flash Read Only Memory) 28.

[0013] HDC23 is an example of the first circuit block. RWC25 is an example of the second circuit block.

[0014] The magnetic disk 11 is rotated at a predetermined rotational speed by a spindle motor 12 mounted coaxially. The spindle motor 12 is driven by a motor driver IC 21.

[0015] The processor 26 controls the rotation of the spindle motor 12 and the rotation of the VCM 16 via the motor driver IC 21.

[0016] The magnetic head 22 writes and reads information to and from the magnetic disk 11 by means of the write core 22w and the read core 22r provided thereon. The magnetic head 22 is attached to the tip of the actuator arm 15. The magnetic head 22 is moved in the radial direction of the magnetic disk 11 by the VCM 16. Note that either one or both of the write core 22w and the read core 22r provided on the magnetic head 22 may be provided in plural for a single magnetic head 22.

[0017] When the rotation of the magnetic disk 11 is stopped, etc., the magnetic head 22 is moved onto the ramp 13. The ramp 13 is configured to hold the magnetic head 22 at a position separated from the magnetic disk 11.

[0018] The head IC 24 amplifies and outputs the signal read by the magnetic head 22 from the magnetic disk 11 during a read operation, and supplies it to the RWC 25. Also, during a write operation, the head IC 24 amplifies the signal corresponding to the data to be written supplied from the RWC 25, and supplies it to the magnetic head 22.

[0019] The HDC 23 controls the transmission and reception of data performed with the host 2 via the I / F bus.

[0020] The RAM 27 is used as a buffer for the data written to the magnetic disk 11 and the data read from the magnetic disk 11.

[0021] Also, the RAM 27 is used as an operation memory by the processor 26. The RAM 27 is used as an area where firmware is loaded and an area where various management data are temporarily stored.

[0022] RAM27 is composed of volatile memory capable of high-speed operation. The type of memory that makes up RAM27 is not limited to a specific type. RAM27 may be composed of, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof.

[0023] The RWC25 performs data conversions such as error correction coding and modulation coding on a sector-by-sector basis on the data to be written supplied from the HDC23, and supplies the converted data to the head IC24. The RWC25 also performs error correction and demodulation processing on a sector-by-sector basis on the signal read from the magnetic disk 11 and supplied from the head IC24, and outputs the processed signal as digital data to the HDC23.

[0024] The processor 26 is, for example, a CPU (Central Processing Unit). RAM 27 and FROM (Flash Read Only Memory) 28 are connected to the processor 26.

[0025] FROM28 is a non-volatile memory that stores firmware (program data) and various operating parameters.

[0026] The processor 26 performs overall control of the magnetic disk device 1 according to the firmware stored in FROM 28. For example, the processor 26 loads the firmware from FROM 28 into RAM 27 and then performs control of the motor driver IC 21, head IC 24, RWC 25, HDC 23, etc., according to the loaded firmware.

[0027] The firmware program may be stored on the magnetic disk 11. Furthermore, some or all of the functions of the processor 26 may be implemented by hardware circuits such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0028] The configuration including HDC23, RWC25, and processor26 can also be considered as a controller 30 that controls the operation of the magnetic disk drive 1. The controller 30 may also include other elements (e.g., RAM27 or FROM28).

[0029] Furthermore, the firmware program may be stored on the magnetic disk 11. In addition, some or all of the functions of the processor 26 may be implemented by hardware circuits such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0030] The number of magnetic disks 11 in the magnetic disk drive 1 is not limited to one. The magnetic disk drive 1 may also have a number of actuator arms 15 and magnetic heads 22 corresponding to the number of magnetic disks 11. Furthermore, if the magnetic disk drive 1 has multiple magnetic heads 22, these multiple magnetic heads 22 may be moved as a single unit, or they may constitute multiple groups that can move independently.

[0031] Figure 2 shows an example of the configuration of the magnetic disk 11 in the embodiment. Servo data used for positioning the magnetic head 22 is written to the magnetic layer formed on the surface of the magnetic disk 11, for example, by a servowriter or by a self-servo write (SSW).

[0032] Figure 2 shows a radially arranged servo region 41 as an example of the arrangement of servo regions to which servo data has been written. In the circumferential direction, the area between two servo regions 41 is designated as a data region 42 to which data can be written. Multiple concentric tracks 50 are provided in the radial direction of the magnetic disk 11. On the tracks 50, multiple sectors of data 42 are provided, each to which data of a predetermined size is written. The predetermined size is the sector size.

[0033] The servo data includes a servo mark, a Gray code, a burst pattern, and a postcode. The servo mark indicates the start of the servo data. The Gray code includes an ID, i.e., a track number, for identifying each track 50 on the magnetic disk 11, and an ID, i.e., a servo sector number, for identifying each servo sector (i.e., servo area 41) on track 50. The burst pattern is data used to detect the amount of deviation from the center of the track indicated by the track number included in the Gray code. The track number included in the Gray code is given as an integer value, for example, and by demodulating the burst pattern, it is possible to obtain a decimal offset amount relative to the position indicated by the track number. In other words, by demodulating the burst pattern, the current position of the magnetic head 22 in the radial direction can be obtained. The postcode is data for correcting the deviation of the shape of the track 50, as defined by the Gray code and burst pattern, from the ideal shape of the track 50.

[0034] When the controller 30 writes data to the magnetic disk 11 or reads data from the magnetic disk 11, it performs positioning of the magnetic head 22, i.e., seek control and tracking control, based on the servo data read by the magnetic head 22 from the servo area 41.

[0035] The controller 30 performs data processing on the data received from the host 2 (referred to as host data) for each data segment corresponding to the sector size, and then writes each processed data segment to the sector.

[0036] Figure 3 illustrates an example of data processing performed by the controller 30 of this embodiment. The data fragment of the host data before data processing is denoted as data fragment DSa.

[0037] HDC23 generates a CRC (Cyclic Redundancy Check) code from the data piece DSa and adds the CRC code to the data piece DSa (S101).

[0038] Hereafter, the CRC code generated by the processing in S101 will be referred to as the first code CRC1. A data piece DSa to which the first code CRC1 has been added will be referred to as a data piece DSb.

[0039] RWC25 performs scrambling (S102) on the data fragment DSb. RWC25 also performs run-length constraint coding (S103) on the data fragment DSb under conditions where the Maximum Transition Run (MTR) is constrained, as an example of modulation coding. Furthermore, RWC25 performs LDPC (Low Density Parity Check) coding (S104) on the data fragment DSb, as an example of error correction coding. Note that the execution order of steps S102 to S103 does not have to be as described.

[0040] Scrambling, run-length-constrained coding, and LDPC coding are just a few examples of data transformations performed in RWC25.

[0041] The data fragment DSb after scrambling will be denoted as data fragment DSc. The size of the data fragment does not change during scrambling. Therefore, the size of data fragment DSc is equal to the size of data fragment DSb.

[0042] The data fragment DSc after run-length constraint coding is denoted as data fragment DSd. In run-length constraint coding, the size of the data fragment may increase. Therefore, the size of data fragment DSd is greater than or equal to the size of data fragment DSc.

[0043] The data fragment DSd after LDPC encoding is denoted as data fragment DSe. LDPC encoding increases the size of the data fragment by the amount of the generated LDPC code. Therefore, the size of data fragment DSe is larger than that of data fragment DSd.

[0044] A data fragment DSe generated by RWC25 is written to a single sector. Therefore, the size of the data fragment DSe is equal to or less than the sector size.

[0045] Hereafter, data fragments DSa, DSB, DSC, DSD, and DSe may be collectively referred to as data fragment DS.

[0046] Figure 4 is a schematic diagram showing an example of the configuration of one track 50 in the embodiment. The servo region 41 is not shown in this figure. The write / read direction is also shown in this figure. The write / read direction is the direction in which the magnetic head 22 moves relative to the track 50 due to the rotation of the magnetic disk 11. The magnetic head 22 writes or reads data in the write / read direction for each track 50.

[0047] Each sector on track 50 is identified by its sector number. A sector with sector number x is denoted as sector #x. In the example shown in Figure 4, track 50 has 11 sectors, from sector #0 to sector #10. A data fragment DSe written to sector #x is denoted as data fragment DSe#x.

[0048] From now on, when referring to data fragments DSa, DSB, DSC, or DSD, in addition to DSe, the sector number of the sector to which the data will ultimately be written may be appended to the end.

[0049] Each data fragment DSe written to a sector contains an LDPC code generated by the process in S104 of Figure 3. Therefore, sector-level error correction using the LDPC code is possible for data fragment DSe read from a single sector.

[0050] When sector #0 is considered the beginning in the write / read direction, sector #10 can be considered the last sector. The last sector, #10, is designated as the sector where parity is stored. That is, a track-level write is performed, for example, as follows: First, data fragments DSe #0-#9 are written to sectors #0-#9 in the order of their sector numbers. Then, parity calculated based on the group of data fragments DSe written to sectors #0-#9 is written to sector #10. This parity is denoted as track parity TP.

[0051] Track parity TP is generated by calculating a bit-position-wise exclusive OR (in other words, XOR) for data fragments DSe#0-#9. The controller 30 can use the track parity TP to protect the data DSe#0-#9 written to sectors #0-#9 from errors. In other words, track parity TP protects data on a track-by-track basis.

[0052] For example, even if a data fragment DS stored in a particular sector (referred to as the target sector) among sectors #0-#9 contains an error that cannot be corrected by sector-level error correction, it is possible to obtain an error-free data fragment DS that was stored in the target sector by performing a calculation using the data fragments DS stored in all other sectors among sectors #0-#9, and the track parity TP.

[0053] Hereafter, error correction using track parity TP will be referred to as track-level error correction. The calculation of exclusive OR will mean the calculation of exclusive OR for each bit position. The sector to which data fragments DSe are written (for example, sectors #0-#9 in Figure 4) will be referred to as the data sector. The sector to which track parity TP is written (for example, sector #10 in Figure 4) will be referred to as the parity sector. The data sector is an example of the first sector. The parity sector is an example of the second sector.

[0054] When a data fragment DSe written to track 50 is protected by track parity TP, this is described as "track protection is enabled." Conversely, when a data fragment written to track 50 is not protected by track parity TP, this is described as "track protection is disabled."

[0055] For example, if data fragments DSe are written to all data sectors of a certain track 50, and a track parity TP calculated based on the group of data fragments DSe written to all data sectors is written to the parity sector of that track 50, then the group of data fragments DSe written to that track 50 corresponds to the track parity TP. Therefore, the group of data fragments DSe written to that track 50 is protected by the track parity TP. In other words, the track protection function is enabled for that track 50.

[0056] When a random write operation, specifically an overwrite of data fragment DSe for some data sectors, is performed on track 50 with track protection enabled, the group of data fragment DSe within track 50 will no longer correspond to the already written track parity TP and will no longer be protected by the track parity TP. In other words, track protection is disabled on track 50.

[0057] In track 50, where track protection is disabled, when a new track parity TP is recalculated and this new track parity TP is overwritten to the parity sector, the group of data fragments DSe within track 50 becomes protected by the new track parity TP. In other words, track protection is enabled for track 50.

[0058] Whether the track protection function is enabled or disabled affects various controls. One example of a control affected by whether the track protection function is enabled or disabled is the control related to adjacent track interference (ATI).

[0059] ATI (Attention-Through Interference) is the effect on adjacent tracks when writing to a magnetic disk. For example, when data is written to one track 50 (referred to as the first track 50), the adjacent track 50 (the second track 50) is affected by ATI. The ATI effect on the second track 50 accumulates with the number of writes to the first track 50. If the ATI effect on the second track 50 becomes too large, it becomes difficult to read the data stored on the second track 50.

[0060] The controller 30 performs a rewrite operation to rewrite all data fragments DSe on a track-by-track basis before data reading becomes difficult for each track 50 due to the effects of ATI. Specifically, the controller 30 estimates the degree of ATI influence on each track 50 from the number of writes to neighboring tracks 50, and when the estimated degree exceeds a predetermined threshold, it performs a rewrite operation on the track 50 where the estimated degree of ATI influence exceeds the threshold. The threshold that is compared with the estimated degree of ATI influence to determine whether or not to perform a rewrite operation is referred to as the ATI threshold.

[0061] Track 50 with the track protection function disabled is more vulnerable to the effects of ATI than track 50 with the track protection function enabled. Therefore, when the track protection function is disabled, the controller 30 uses a lower ATI threshold value than the one used when the track protection function is enabled. This prevents difficulty in reading data fragments DSe from track 50 with the track protection function disabled.

[0062] Another example of a control affected by whether the track protection function is enabled or disabled is the control that performs track-level error correction during a read operation. If sector-level error correction of the data fragment being read fails during a read operation, the controller 30 will perform track-level error correction if the track protection function is enabled. If the track protection function is disabled, it is clear that the error cannot be corrected by track-level error correction, so the controller 30 refrains from performing track-level error correction to save response time.

[0063] For the control based on whether the above-mentioned track protection function is enabled or disabled to achieve the expected effect, it is a prerequisite that a correct track parity TP is generated when writing or rewriting data fragments DSe on a track-by-track basis. If there is a malfunction in the circuit that generates the track parity TP, or if the generation of the track parity TP fails due to some processing error, an incorrect track parity TP is generated. In this case, the group of data fragments DSe written to track 50 and the track parity TP will not correspond, and error correction using the track parity TP will not function properly.

[0064] In other words, a mechanism is needed to verify that the correct track parity TP has been generated.

[0065] Therefore, in this embodiment, the controller 30 is configured to include hardware circuitry capable of detecting an invalid track parity TP during its generation. The configuration of the hardware circuitry for detecting an invalid track parity TP is described below.

[0066] Figure 5 is a schematic diagram showing an example of the hardware configuration of the HDC23 in the embodiment.

[0067] In Figures 5-7, the information generated based on the data fragment DS is represented by assigning it the same sector number as the data sector to which the data fragment DS is written. Also, in Figures 5-7, one track 50 is provided with multiple sectors, namely N+1 data sectors #0-#N (where N is an integer greater than or equal to 1) and a parity sector.

[0068] The HDC23 includes a CRC generation circuit 101, a selector 102 with two input terminals, and a CRC XOR circuit 103.

[0069] When writing data fragments DSa#0-#N, HDC23 executes the S101 process shown in Figure 3 for each data fragment DSa#0-#N in sector number order.

[0070] Specifically, data fragments DSa#0-#N are input to one of the two input terminals of selector 102 and to the CRC generation circuit 101 in sector number order. The CRC generation circuit 101 calculates a first code CRC1 from each input data fragment DSa and inputs the first code CRC1 generated by the calculation to the other of the two input terminals of selector. The first code CRC1 generated from data fragment DSa#x is denoted as first code CRC1#x. In other words, the CRC generation circuit 101 inputs the first codes CRC1#0-#N to selector 102 in the order of the data fragments DSa from which the calculation was performed, that is, in sector number order.

[0071] When the selector 102 receives data piece DSa#x and the first code CRC1#x as input, it outputs data piece DSa#x based on the selection signal, followed by the output of the first code CRC1#x. The selector 102 performs the output of data piece DSa#x and the output of the first code CRC1#x that follows the output of data piece DSa#x for each of the data pieces DSa#0-#N. As a result, the selector 102 outputs data pieces DSa#0-#N, i.e., data pieces DSb#0-#N, each with the corresponding first code CRC1 added.

[0072] The first codes CRC1#0-#N generated by the CRC generation circuit 101 are also input to the CRC XOR circuit 103. Each time a first code CRC1 is input to the CRC XOR circuit 103, it calculates the exclusive OR operation for all the first codes CRC1 that have been input so far from CRC#0-#N. The CRC XOR circuit 103 then sequentially outputs the values ​​generated by the calculation.

[0073] Specifically, the CRC XOR circuit 103 includes a register (not shown) capable of holding intermediate data. The first codes CRC1#0-#N are input to the CRC XOR circuit 103 in sector number order. Before the first code CRC1#0 is input to the CRC XOR circuit 103, the register of the CRC XOR circuit 103 is reset, and the intermediate data is set to all zeros. Each time one of the first codes CRC1 from CRC1#0-#N is newly input to the CRC XOR circuit 103, the CRC XOR circuit 103 calculates the exclusive OR of the intermediate data in the register and the newly input first code CRC1, and stores the value obtained from the calculation as intermediate data in an overwrite format in the register.

[0074] The CRC XOR circuit 103 performs the calculation of the exclusive OR operation and updates the intermediate data each time the first code CRC1 is input, and also outputs the updated intermediate data. The information output from the CRC XOR circuit 103 in response to the input of the first code CRC1#x, that is, the value obtained by the exclusive OR operation on the first codes CRC1#0-#x, is denoted as the operated first code CRC1op#x.

[0075] Note that CRC1op#N, one of the calculated first codes CRC1op#0-#N, is an example of the first information.

[0076] HDC23 synchronously inputs the data fragments DSb#0-#N and the calculated first codes CRC1op#0-#N to RWC25.

[0077] RWC25 generates data fragments DSe#0-#N and track parity TP from data fragments DSb#0-#N, and verifies whether a correct track parity TP has been generated based on the calculated first code CRC1op#N, etc.

[0078] Figure 6 shows an example of the hardware configuration of the RWC25 in this embodiment.

[0079] The RWC25 includes a scrambling circuit 111, a modulation coding circuit 112, an LDPC coding circuit 113, an XOR circuit 114, a selector 115, an error detection circuit 116, multiple buffers 120, a CRC XOR circuit 124, multiple buffers 130, and a comparison circuit 141. The XOR circuit 114 includes a restart processing circuit 117. The CRC XOR circuit 124 includes a restart processing circuit 127.

[0080] The scrambling circuit 111 scrambles the data fragment DSb and outputs the scrambled data fragment DSb, i.e., the data fragment DSc.

[0081] The modulation coding circuit 112 performs run-length constraint coding on the data fragment DSc output from the scrambling circuit 111 under conditions where the MTR is constrained, and outputs the data fragment DSc after run-length constraint coding, i.e., the data fragment DSd.

[0082] The LDPC encoding circuit 113 performs LDPC encoding on the data fragment DSd output from the modulation encoding circuit 112, and outputs the LDPC-encoded data fragment DSd, i.e., the data fragment DSe.

[0083] The data fragments DSb#0-#N output from HDC23 are sequentially input to the scrambling circuit 111. The scrambling circuit 111 then sequentially scrambles each of the data fragments DSb#0-#N to generate data fragments DSc#0-#N, and sequentially outputs the generated data fragments DSc#0-#N. The modulation coding circuit 112 then sequentially performs run-length constraint coding on each of the data fragments DSc#0-#N to generate data fragments DSd#0-#N, and sequentially outputs the generated data fragments DSd#0-#N. The LDPC coding circuit 113 then sequentially performs LDPC coding on each of the data fragments DSd#0-#N to generate data fragments DSe#0-#N, and sequentially outputs the generated data fragments DSe#0-#N.

[0084] The XOR circuit 114 generates track parity TP by calculating the exclusive OR of data pieces DSe#0-#N.

[0085] More specifically, data fragments DSe#0-#N are input to the XOR circuit 114 in sector number order. The XOR circuit 114 also includes a register (not shown) capable of holding intermediate data. Before data fragment DSe#0 is input to the XOR circuit 114, the contents of the register of the XOR circuit 114, i.e., the intermediate data, are reset to all zeros. Each time a new data fragment DSe from DSe#0-#N is input to the XOR circuit 114, it calculates the exclusive OR of the intermediate data and the newly input data fragment DSe, and stores the resulting data fragment as intermediate data in the register in an overwrite format.

[0086] Thus, each time a data fragment DSe is input to the XOR circuit 114, it proceeds with the calculation of the exclusive OR and the updating of the intermediate data. Therefore, when a data fragment DSe#x from among the data fragments DSe#0-#N is input to the XOR circuit 114, the XOR circuit 114's register is filled with the data fragment obtained by the exclusive OR of data fragments DSe#0-#x, through the calculation of the exclusive OR corresponding to the input of data fragment DSe#x and the updating of the intermediate data. Therefore, when the calculation of the exclusive OR corresponding to the input of data fragment DSe#N and the updating of the intermediate data are completed, the XOR circuit 114's register is filled with the data fragment obtained by the exclusive OR of data fragments DSe#0-#N, i.e., the track parity TP, as intermediate data.

[0087] The XOR circuit 114 outputs updated intermediate data, i.e., a data piece obtained by performing an exclusive OR operation on the data pieces DSe#0-#x, each time a data piece DSe#x is input to it. The data piece obtained by performing an exclusive OR operation on the data pieces DSe#0-#x output by the XOR circuit 114 is denoted as the processed data piece DSeop#x. The processed data piece DSeop#N corresponds to the track parity TP.

[0088] The selector 115 has two input terminals. Data fragments DSe#0-#N are input to one of these two input terminals, and processed data fragments DSeop#0-#N are input to the other of these two input terminals.

[0089] When data fragments DSe#0-#N are input to selector 115, it outputs data fragments DSe#0-#N to head IC24 based on the selection signal. Subsequently, when a calculated data fragment DSeop#N is input to selector 115, it outputs the input calculated data fragment DSeop#N, i.e., track parity TP, to head IC24 based on the selection signal.

[0090] The head IC 24 receives data fragments DSe#0-#N and track parity TP generated from data fragments DSe#0-#N from the selector 115. The head IC 24 sequentially supplies the data fragments DSe#0-#N and track parity TP to the magnetic head 22. Under position control, the magnetic head 22 performs writing of data fragments DSe#0-#N to data sectors #0-#N and writing of track parity TP to the parity sector.

[0091] The scrambling circuit 111, the modulation coding circuit 112, and the LDPC coding circuit 113 constitute a pipeline. Hereafter, in this specification, the pipeline composed of the scrambling circuit 111, the modulation coding circuit 112, and the LDPC coding circuit 113 will be simply referred to as the pipeline.

[0092] The number of buffers 120 in the RWC25 corresponds to the number of pipeline stages included in the pipeline. In this example, the number of pipeline stages is 3. Therefore, the RWC25 has three buffers 121-123, which are multiple buffers 120. These three buffers 121-123 are connected in series.

[0093] When a data fragment DSb#x is input to the scrambling circuit 111, the first code CRC1#x contained in the data fragment DSb#x is obtained from the data fragment DSb#x, and the obtained data fragment DSb#x is input to the buffer 121. The first code CRC1#x obtained from the data fragment DSb#x is denoted as the second code CRC2#x.

[0094] The second code CRC2#x input to buffer 121 is transferred from buffer 121 to buffer 123 in synchronization with the transfer of data fragments DS between circuits in the pipeline, and then input to CRC XOR circuit 124. Therefore, the second codes CRC2#0-#N are input to CRC XOR circuit 124 in synchronization with the input of data fragments DSe#0-#N to XOR circuit 114.

[0095] The CRC XOR circuit 124 has the same circuit configuration as the XOR circuit 114, except that the data subject to exclusive OR is the second code CRC2#0-#N instead of the data fragment DSe#0-#N.

[0096] Specifically, the CRC XOR circuit 124 includes a register (not shown) capable of holding intermediate data. Before the second code CRC2#0 is input to the CRC XOR circuit 124, the contents of the register of the CRC XOR circuit 124, i.e., the intermediate data, are reset to all zeros. Each time one of the second codes CRC2 from CRC2#0-#N is newly input to the CRC XOR circuit 124, it calculates the exclusive OR of the intermediate data and the newly input second code CRC2, and stores the data fragment obtained by the calculation as intermediate data in an overwrite format in the register.

[0097] Thus, each time a second code CRC2 is input to the CRC XOR circuit 124, it proceeds with the calculation of the exclusive OR and updating the intermediate data. Therefore, when a second code CRC2#x from among the second codes CRC2#0-#N is input to the CRC XOR circuit 124, the register of the CRC XOR circuit 124 is filled with the value obtained by the exclusive OR of the second codes CRC2#0-#x through the calculation of the exclusive OR and updating of the intermediate data. The value obtained by the exclusive OR of the second codes CRC2#0-#x stored in the register is denoted as the calculated second code CRC2op#x.

[0098] The CRC XOR circuit 124 outputs intermediate data in the register each time the second code CRC2 is input. In other words, the CRC XOR circuit 124 sequentially outputs the calculated second codes CRC2op#0-#N.

[0099] Note that CRC2op#N, one of the pre-calculated second codes CRC2op#0-#N, is an example of second information.

[0100] The comparator circuit 141 has two input terminals. The calculated second codes CRC2op#0-#N are sequentially input to one of these two input terminals. The calculated first codes CRC1op#0-#N are sequentially input to the other input terminal via a series of buffers 130.

[0101] The number of buffers 130 in the RWC25 corresponds to the number of pipeline stages included in the pipeline. Therefore, in this case, the RWC25 has three buffers 131-133 as multiple buffers 130. The three buffers 131-133 are connected in series.

[0102] Synchronized with the input of data fragment DSb#x to the scrambling circuit 111 (and the input of the second code CRC2#x to buffer 121), the calculated first code CRC1op#x is input to buffer 131. The calculated first code CRC1op#x input to buffer 131 is transferred from buffer 131 to buffer 133 in synchronization with the transfer of data fragment DS between circuits in the pipeline, and is then input to comparator circuit 141. Therefore, the calculated first codes CRC1op#0-#N are input to comparator circuit 141 in synchronization with the input of the calculated second codes CRC2op#0-#N.

[0103] The comparison circuit 141 compares the calculated second code CRC2op#N with the calculated first code CRC1op#N and transmits the comparison result to the processor 26.

[0104] If the CRC XOR circuit 124 correctly performs the exclusive OR calculation, the calculated second code CRC2op#N output from the CRC XOR circuit 124 should match the calculated first code CRC1op#N. If an error occurs during processing in the CRC XOR circuit 124, an invalid value will be output as the calculated first code CRC1op#N, and the output calculated second code CRC2op#N will not match the calculated first code CRC1op#N.

[0105] Furthermore, as mentioned above, the CRC XOR circuit 124 has the same circuit configuration as the XOR circuit 114, except that the data being subjected to the exclusive OR is different. The CRC XOR circuit 124 performs the exclusive OR calculation for the second code CRC2#0-#N in synchronization with the calculation of the exclusive OR for data pieces DSe#0-#N performed by the XOR circuit 114. Therefore, if the CRC XOR circuit 124 outputs an incorrect value as the calculated second code CRC2op#N, it can be inferred that an error has occurred in the processing of the XOR circuit 114.

[0106] For example, if there is a design flaw in the XOR circuit 114 (and CRC XOR circuit 124), an incorrect value may be output as the track parity TP. The manufacturer can detect the design flaw in the XOR circuit 114 (and CRC XOR circuit 124) using the mechanism described above. Specifically, the manufacturer has the magnetic disk device 1 perform track-by-track write operations during the manufacturing process and obtains the comparison result from the comparison circuit 141. If the comparison result is inconsistent, the manufacturer can infer that there is a design flaw in the XOR circuit 114 (and CRC XOR circuit 124).

[0107] Furthermore, one common cause of errors during the operation of the magnetic disk drive 1 is the failure of the restart process in the XOR circuit 114 (and the CRC XOR circuit 124). The restart process is described below.

[0108] In the magnetic disk drive 1, a write operation may be interrupted during the operation. For example, an off-track may occur when the position of the magnetic head 22 drifts radially beyond the allowable range from the target track 50 while a write operation is being performed on the target track 50. When the controller 30 detects an off-track, it immediately interrupts the write operation. Then, once the controller 30 confirms that the off-track has been resolved, it resumes the write operation from the sector where the write operation was interrupted.

[0109] Furthermore, if the controller 30 detects vibrations exceeding an acceptable level during light operation, it will interrupt the light operation. The controller 30 will then resume light operation when the vibration level falls below the acceptable level.

[0110] If the controller 30 interrupts track-based write operations, the XOR circuit 114 (and CRC XOR circuit 124) interrupts the calculation of the exclusive OR that it has been performing on the sequence of data (data fragment DSe or second code CRC2) input for each sector number. Then, when the controller 30 resumes track-based write operations, the XOR circuit 114 (and CRC XOR circuit 124) resumes the calculation of the exclusive OR.

[0111] In the XOR circuit 114 (and CRC XOR circuit 124), the exclusive OR calculation is resumed from the data input following the data that was last subjected to the exclusive OR calculation immediately before the interruption, from a series of data (data fragment DSe or second code CRC2). Therefore, the XOR circuit 114 (and CRC XOR circuit 124) needs to determine which data should be input to resume the exclusive OR calculation, that is, the timing of the exclusive OR calculation.

[0112] In this specification, the restart process is the process of determining the timing of the calculation of the exclusive OR. In the XOR circuit 114, the restart process circuit 117 executes the restart process. In the CRC XOR circuit 124, the restart process circuit 127 executes the restart process.

[0113] If the timing of the exclusive OR calculation determined in the XOR circuit 114 (more precisely, the restart processing circuit 117) is inappropriate, the resulting track parity TP will be incorrect. In that case, the CRC XOR circuit 124, which has a circuit configuration similar to the XOR circuit 114, will also restart the exclusive OR calculation based on the inappropriate timing, and the calculated second code CRC2op#N immediately after the restart process will have an incorrect value. As a result, the comparison circuit 141 outputs a determination result indicating a mismatch.

[0114] The processor 26 determines whether an invalid track parity TP value has been output based on the comparison result output by the comparison circuit 141.

[0115] Furthermore, in this embodiment, the RWC25 includes a mechanism to detect errors in the track parity TP caused by errors in the LDPC encoding circuit 113.

[0116] Specifically, the processed data fragments DSeop#0-#N output from the XOR circuit 114 are input to the error detection circuit 116. When the error detection circuit 116 receives the processed data fragment DSeop#N, i.e., the trap parity TP, it performs a hard judgment on the processed data fragment DSeop#N as an error correction corresponding to the LDPC code and attempts to detect an error. The error detection circuit 116 transmits the detection result to the processor 26.

[0117] Since all data fragments DSe#0-#N are LDPC encoded, it is possible to perform error correction corresponding to the LDPC encoding on the calculated data fragment DSeop#N generated from data fragments DSe#0-#N. Furthermore, since the calculated data fragment DSeop#N is generated based on data fragments DSe#0-#N that have not been LDPC encoded by the LDPC encoding circuit 113 for a short time, as long as the LDPC encoding circuit 113 is performing LDPC encoding correctly, no errors should be detected in the error correction of the calculated data fragment DSeop#N by the error detection circuit 116. Conversely, if an error is detected by the error detection circuit 116, it can be inferred that the LDPC encoding circuit 113 is not performing LDPC encoding correctly. If the LDPC encoding circuit 113 is not performing LDPC encoding correctly, the correct track parity TP cannot be obtained.

[0118] Therefore, if the error detection result from the error detection circuit 116 indicates the occurrence of an error, the processor 26 determines that an invalid track parity TP has been output. This mechanism makes it possible to detect invalid track parity TP caused by errors in processing in the LDPC encoding circuit 113.

[0119] Next, the operation of each component of the magnetic disk device 1 of this embodiment during track-by-track writing will be described.

[0120] First, using Figures 7-9, we will explain the operation of RWC25 when data fragments DSb#0-#N and pre-calculated first codes CRC1op#0-#N, synchronized with the input of data fragments DSb#0-#N, are input from HDC23 to RWC25.

[0121] Figure 7 is a flowchart showing an example of the operation of the XOR circuit 114 of the embodiment for calculating the exclusive OR (referred to as the first XOR operation).

[0122] First, the XOR circuit 114 resets the contents of its register, i.e., the intermediate data, to all zeros (S201), and initializes the loop processing index i to zero (S202).

[0123] Subsequently, the XOR circuit 114 executes the loop processing steps S203-S206 for each of the data fragments DSe#0-#N input from the LDPC coding circuit 113. The steps in the loop processing steps S203-S206 will be described in the order of execution.

[0124] In step S203, the XOR circuit 114 calculates the exclusive OR of the data piece DSe#i and the intermediate data in the register, and updates the intermediate data in the register with the calculation result.

[0125] In step S204, the XOR circuit 114 outputs the updated intermediate data, i.e., the processed data piece DSeop#i.

[0126] In step S205, the XOR circuit 114 determines whether i is equal to N. If i is not equal to N (S205: No), control proceeds to step S206. If i is equal to N (S205: Yes), the first XOR operation by the XOR circuit 114 is completed. The calculated data piece DSeop#N output by the XOR circuit 114 in step S203 of the final loop processing corresponds to the track parity TP calculated from data pieces DSe#0-#N.

[0127] In step S206, the XOR circuit 114 increments index i by 1. After step S206, control proceeds to step S203.

[0128] Figure 8 is a flowchart showing an example of the operation of the exclusive OR calculation by the CRC XOR circuit 124 of the embodiment (referred to as the second XOR operation).

[0129] First, the CRC XOR circuit 124 resets the contents of its register, i.e., the intermediate data, to all zeros (S301), and initializes the loop processing index j to zero (S302).

[0130] Subsequently, the CRC XOR circuit 124 executes the loop processing steps S303-S306 for each of the second codes CRC2#0-#N input from buffer 121. The steps in the loop processing steps S303-S306 will be described in the order of execution.

[0131] In step S303, the CRC XOR circuit 124 calculates the exclusive OR of the second code CRC2#j and the intermediate data in the register, and updates the intermediate data in the register with the calculation result.

[0132] In step S304, the CRC XOR circuit 124 outputs the updated intermediate data, i.e., the calculated second code CRC2op#j.

[0133] In step S305, the CRC XOR circuit 124 determines whether j is equal to N. If j is not equal to N (S305: No), control proceeds to step S306. If j is equal to N (S305: Yes), the second XOR operation by the CRC XOR circuit 124 is completed.

[0134] In step S306, the CRC XOR circuit 124 increments index j by 1. After step S306, control proceeds to step S303.

[0135] Figure 9 is a flowchart showing an example of the operation of the selector 115 in the embodiment.

[0136] The selector 115 outputs the data fragments DSe#0-#N input from the LDPC encoding circuit 113 directly to the head IC 24 (S401). Subsequently, the selection signal is switched (S402), and as a result, the selector 115 outputs the calculated data fragment DSeop#N, i.e., the track pitch TP, input from the XOR circuit 114 to the head IC 24 (S403). Then, the operation of the selector 115 ends.

[0137] Figure 10 is a flowchart showing an example of the operation of the RWC25 when a track-by-track light operation is interrupted and resumed in the embodiment.

[0138] When input of data fragments DSb#0-#N and pre-calculated first codes CRC1op#0-#N synchronized with the input of data fragments DSb#0-#N are initiated from HDC23 to RWC25 (S501), input of data fragments DSe#0-#N is initiated to XOR circuit 114, and input of second codes CRC2#0-#N is initiated to CRC XOR circuit 124. Then, XOR circuit 114 and CRC XOR circuit 124 begin XOR operations on the data input to them, respectively (S502).

[0139] Next, if a write operation is interrupted and the input of data fragments DSb#0-#N and the input of calculated first codes CRC1op#0-#N from HDC23 to RWC25 is interrupted (S503), the XOR circuit 114 and the CRC XOR circuit 124 stop their XOR operations (S504).

[0140] When the cause of the interruption in the write operation is resolved and the write operation resumes, the input of data fragments DSb#0-#N and the input of calculated first codes CRC1op#0-#N from HDC23 to RWC25 resumes (S505). At this time, the restart processing circuit 117 of the XOR circuit 114 and the restart processing circuit 127 of the CRC XOR circuit 124 determine the timing for resuming the XOR operation (S506). When the restart timing arrives, the XOR circuit 114 and the CRC XOR circuit 124 resume the XOR operation (S507).

[0141] Once the input of data fragments DSb#0-#N and the input of calculated first codes CRC1op#0-#N from HDC23 to RWC25 is complete (S508), the XOR operation in XOR circuit 114 and CRC XOR circuit 124 is completed after a delay (S509). Then the operation example ends.

[0142] Figure 11 is a flowchart showing an example of the operation of the processor 26 in the embodiment. The series of operations shown in this figure are, in one example, executed at any time after the track parity TP is calculated during a track-by-track write operation.

[0143] Based on the comparison results received from the comparison circuit 141, the processor 26 determines whether or not a mismatch has been detected between the calculated first code CRC1op#N and the calculated second code CRC2op#N in the comparison circuit 141 (S601).

[0144] If no mismatch is detected between the calculated first code CRC1op#N and the calculated second code CRC2op#N (S601: No), the processor 26 determines, based on the inspection results received from the error detection circuit 116, whether or not an error was detected in the calculated data piece DSeop#N (i.e., track parity TP) in the error detection circuit 116 (S602).

[0145] If the comparison circuit 141 detects a mismatch between the calculated first code CRC1op#N and the calculated second code CRC2op#N (S601: Yes), or if the error detection circuit 116 detects an error in the calculated data piece DSeop#N (S602: Yes), the processor 26 records in the management information stored in a predetermined location (e.g., RAM 27) that the track parity TP written to the destination track 50 is invalid (S603), and terminates its operation.

[0146] If no error is detected in the calculated data piece DSeop#N by the error detection circuit 116 (S602: No), the processor 26 skips the processing in step S603 and terminates its operation.

[0147] In the example shown in Figure 11, the determination of whether a mismatch was detected in the comparison circuit 141 and the determination of whether an error was detected in the error detection circuit 116 were performed in this order. The order in which these two determinations are performed may be reversed.

[0148] The processor 26 controls track 50 on which a track-specific write operation has been performed, depending on whether or not the track parity TP for track 50 is recorded as invalid in the management information.

[0149] For example, even if no random write operations have been performed on a track 50 since a track-specific write operation was performed on that track 50, if the management information records that the track parity TP for that track 50 is disabled, the processor 26 will consider the track protection function for that track 50 to be disabled. Specifically, the processor 26 may reduce the ATI threshold compared to when the track protection function is enabled, or refrain from performing track-specific error correction if sector-specific error correction fails.

[0150] Furthermore, if a track 50 has not been randomly written to since a track-level write operation was performed on that track 50, and the management information does not record that the track parity TP for that track 50 is invalid, the processor 26 considers the track protection function for that track 50 to be enabled. Specifically, the processor 26 uses the ATI threshold when the track protection function is enabled, or performs track-level error correction if sector-level error correction fails.

[0151] However, the methods for differentiating control based on management information are not limited to this.

[0152] As described above, according to the embodiment, the magnetic disk device 1 comprises a first circuit block HDC23 and a second circuit block RWC25. The HDC23 receives data fragments DSa#0-#N from the host 2. Data fragments DSa#0-#N are a plurality of data fragments DSa that are written to data sectors #0-#N. The HDC23 performs the generation and addition of a first code CRC1 and the output of a data fragment DSb, which is a data fragment DSa to which the first code CRC1 has been added, for each of the data fragments DSa#0-#N. The HDC23 also calculates the exclusive OR of the first CRC1#0-#N, which is the group of first code CRC1s generated from each of the data fragments DSa#0-#N, and outputs the calculated first code CRC1op#N, which is first information obtained by calculating the exclusive OR of the first code CRC1#0-#N. RWC25 receives multiple second data fragments, data fragments DSb#0-#N, output from HDC23, and the calculated first code CRC1op#N, also output from HDC23. RWC25 then performs data conversion on each of data fragments DSb#0-#N and outputs data fragment DSe, which is the data fragment DSb after data conversion. RWC25 also calculates the exclusive OR of multiple third data fragments, data fragments DSe#0-#N, generated by the data conversion on each of data fragments DSb#0-#N, and outputs the track parity TP, which is the information obtained from calculating the exclusive OR of data fragments DSe#0-#N, following the output of data fragments DSe#0-#N. Furthermore, RWC25 obtains the first code CRC1 as the second code CRC2 from each of the data pieces DSb#0-#N, and calculates the exclusive OR of the group of second codes CRC2#0-#N obtained from each of the data pieces DSb#0-#N. Then, RWC25 compares the calculated first code CRC1op#N with the calculated second code CRC2op#N, which is the second information obtained by calculating the exclusive OR of the second codes CRC2#0-#N, and outputs the result of the comparison between the calculated first code CRC1op#N and the calculated second code CRC2op#N.The magnetic head 22 writes data fragments DSe#0-#N, output from the RWC25 and supplied by the head IC24, to data sectors #0-#N, and writes track parity TP, output from the RWC25 and supplied by the head IC24, to the parity sector.

[0153] Therefore, the controller 30 can detect an error in the track parity TP by comparing the calculated first code CRC1op#N with the calculated second code CRC2op#N. More specifically, the controller 30 can detect an error in the track parity TP caused by a design flaw in the XOR circuit 114, or an error in the processing (e.g., restart processing) of the XOR circuit 114.

[0154] Furthermore, according to the embodiment, the RWC25 includes an XOR circuit 114 and a CRC XOR circuit 124 having the same circuit configuration as the XOR circuit 114. The XOR circuit 114 calculates the exclusive OR of data pieces DSe#0-#N. The second XOR circuit calculates the exclusive OR of second codes CRC2#0-#N.

[0155] The CRC XOR circuit 124 has the same circuit configuration as the XOR circuit 114, except that the data for which the exclusive OR is calculated is different. Therefore, by comparing the calculated first code CRC1op#N with the calculated second code CRC2op#N output by the CRC XOR circuit 124, it is possible to detect errors in the track parity TP caused by a design flaw in the XOR circuit 114 or errors in the processing (e.g., restart processing) of the XOR circuit 114.

[0156] In this embodiment, if the input of data fragments DSb#0-#N from HDC23 to RWC25 is interrupted, the XOR circuit 114 and the CRC XOR circuit 124 interrupt the calculation of the exclusive OR, and then, when the input of data fragments DSb#0-#N from HDC23 to RWC25 resumes, they perform a restart process. In the restart process, the XOR circuit 114 and the CRC XOR circuit 124 determine the timing for restarting the calculation of the exclusive OR. The XOR circuit 114 and the CRC XOR circuit 124 restart the calculation of the exclusive OR at the restart timing determined by the determination.

[0157] If an error occurs during the restart process, an invalid value will be output as the track parity TP. The controller 30 can detect the invalid track parity TP that occurs in such cases.

[0158] Furthermore, according to the embodiment, the data conversion in RWC25 includes LDPC coding, which is error correction coding. RWC25 performs error detection (hard judgment in the above example) corresponding to LDPC coding on the track parity TP and outputs the result of the error detection.

[0159] Therefore, it becomes possible to detect errors in the LDPC encoding circuit 113 that cause incorrect track parity TP.

[0160] (modified version) In the magnetic disk device 1 of this embodiment, if an error in the track parity TP is detected, this fact is recorded in the management information, and the contents recorded in the management information are used for subsequent control. The actions taken when an error in the track parity TP is detected are not limited to this.

[0161] This section describes a modified example of what happens when an error is detected in the track parity (TP). Note that details similar to those in the embodiment are omitted here.

[0162] Figure 12 is a flowchart showing an example of the operation of the processor 26 in a modified embodiment.

[0163] The processor 26 executes the process of step S601, as in the embodiment, and if it is determined to be No in the process of step S601, it executes the process of step S602.

[0164] If the comparison circuit 141 detects a mismatch between the calculated first code CRC1op and the calculated second code CRC2op (S601: Yes), or if the error detection circuit 116 detects an error (S602: Yes), the processor 26 retries the track-by-track write operation (S701) and terminates the operation. During the track-by-track write operation retry, the processor 26 re-executes the series of processes shown in Figure 12 as appropriate.

[0165] If no error is detected in the error detection circuit 116 (S602: No), the processor 26 skips the processing in step S603 and terminates its operation.

[0166] Thus, if the controller 30 detects an error in the track parity TP, it may retry the write operation on a track-by-track basis.

[0167] As described above, the operation when an error in the track parity TP is detected can be changed in various ways. The controller 30 can change the control to track 50 according to the result of the comparison between the calculated first code CRC1op and the calculated second code CRC2op, and the result of the error detection in the error detection circuit 116.

[0168] In addition, the error detection circuit 116 may be omitted from the controller 30, and the controller 30 may be configured to change the control to track 50 according to the result of comparing the calculated first code CRC1op and the calculated second code CRC2op.

[0169] Furthermore, in the embodiment and its modifications, the second code CRC2#x was obtained from the data fragment DSb#x before data conversion to the data fragment DSb#x. The timing of obtaining the second code CRC2#x is not limited to this.

[0170] For example, in RWC25, the scrambling (S102) and run-length-constrained coding (S103) of the data transformation (S102-S104) are performed on the portion of the data piece DSb excluding the first code CRC1. LDPC coding (S104) is performed on the entire data piece DS, including the first code CRC1. RWC25 may also obtain the LDPC-coded first code CRC1 from the data piece DS after LDPC coding (S104) as the second code CRC2.

[0171] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0172] 1 Magnetic disk drive, 2 Host, 11 Magnetic disk, 12 Spindle motor, 13 Ramp, 15 Actuator arm, 21 Motor driver IC, 22 Magnetic head, 22r Read core, 22w Write core, 23 HDC, 24 Head IC, 25 RWC, 26 Processor, 27 RAM, 28 FROM, 30 Controller, 41 Servo area, 42 Data area, 50 Track, 101 CRC generation circuit, 102 Selector, 103, 124 CRC XOR circuit, 111 Scramble circuit, 112 Modulation coding circuit, 113 LDPC coding circuit, 114 XOR circuit, 115 Selector, 116 Error detection circuit, 117, 127 Restart processing circuit, 120, 121-123, 130, 131-133 Buffer, 141 Comparator circuit.

Claims

1. A magnetic disk device that can be connected to a host, A magnetic disk having tracks including multiple first sectors and second sectors, A first circuit block receives a plurality of first data fragments to be written to the plurality of first sectors from the host, performs the generation of a first code, the addition of the first code, and the output of the first data fragment to which the first code has been added for each of the plurality of first data fragments, calculates the exclusive OR of the group of first codes generated from each of the plurality of first data fragments, and outputs first information which is information obtained by calculating the exclusive OR of the group of first codes, A second circuit block receives a plurality of second data pieces, each of which has the first code attached, output from the first circuit block, and the first information output from the first circuit block; performs data conversion and outputs a third data piece, which is the second data piece after the data conversion, for each of the plurality of second data pieces; calculates the exclusive OR of the plurality of third data pieces generated by the data conversion for each of the plurality of second data pieces; outputs parity, which is information obtained by calculating the exclusive OR of the plurality of third data pieces, following the output of the plurality of third data pieces; obtains the first code from each of the plurality of second data pieces; calculates the exclusive OR of the group of second codes obtained from each of the plurality of second data pieces; compares the second information, which is information obtained by calculating the exclusive OR of the group of second codes, with the first information; and outputs the result of the comparison between the second information and the first information. A magnetic head that writes the plurality of third data fragments output from the second circuit block to the plurality of first sectors, and writes the parity output from the second circuit block to the second sector, A magnetic disk drive equipped with the following features.

2. The second circuit block comprises a first XOR circuit and a second XOR circuit having the same circuit configuration as the first XOR circuit. The first XOR circuit calculates the exclusive OR of the plurality of third data pieces, The second XOR circuit calculates the exclusive OR of the second group of symbols. The magnetic disk device according to claim 1.

3. The first XOR circuit and the second XOR circuit are, If the input of the plurality of second data pieces from the first circuit block to the second circuit block is interrupted, the calculation of the exclusive OR is interrupted. When the input of the plurality of second data fragments from the first circuit block to the second circuit block resumes, the timing for resuming the exclusive OR calculation is determined, and the exclusive OR calculation is resumed at the resumption timing determined by the determination. The magnetic disk device according to claim 2.

4. The group of second codes is input to the second XOR circuit in synchronization with the input of the plurality of third data pieces to the first XOR circuit. The magnetic disk device according to claim 3.

5. The aforementioned data conversion includes error correction coding for the second data fragment, The second circuit block performs error detection corresponding to the error correction coding on the parity and outputs the result of the error detection. A magnetic disk device according to any one of claims 1 to 4.

6. The system further includes a controller that changes the control over the track according to the results of the comparison. A magnetic disk device according to any one of claims 1 to 4.

7. The controller further comprises a controller that changes the control over the track according to the results of the comparison and the results of the error detection. The magnetic disk device according to claim 5.

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