transistor

Abstract

This transistor includes: an amorphous substrate; a first buffer layer on the amorphous substrate; a first nitride semiconductor layer that is provided in an island shape on the first buffer layer; a second nitride semiconductor layer that is on the first nitride semiconductor layer and covers the first nitride semiconductor layer; and a gate electrode layer that is on the second nitride semiconductor layer and overlaps with the first nitride semiconductor layer.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a transistor utilizing a compound semiconductor, and more particularly to a high-electron-mobility transistor (HEMT). [Background technology]

[0002] Gallium nitride (GaN) is a direct bandgap semiconductor. Focusing on the properties of gallium nitride, it is characterized by high saturation electron mobility and high breakdown voltage. In recent years, these characteristics of gallium nitride have been utilized in the development of transistors for high-frequency power device applications, so-called HEMTs.

[0003] HEMTs have a heterojunction structure in which not only gallium nitride but also aluminum gallium nitride (AlGaN) is provided in contact with the gallium nitride. At the interface between gallium nitride and aluminum gallium nitride, charges are induced by the spontaneous polarization of the gallium nitride, which functions as a semiconductor layer, and the piezoelectric effect of the aluminum gallium nitride, which functions as a polarization layer, forming a high-density two-dimensional electron gas (2DEG). The high concentration of the two-dimensional electron gas in HEMTs, as well as the high saturation electron mobility, enables high-speed operation.

[0004] Gallium nitride (HEMT) is typically deposited on sapphire substrates, which are difficult to fabricate in large areas, at high temperatures of 800°C to 1000°C using MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2010-267658 [Patent Document 2] International Publication No. 2018 / 042792 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As mentioned above, gallium nitride is generally deposited on sapphire substrates at high temperatures, but sapphire substrates are difficult to process in large areas, making it difficult to reduce manufacturing costs. Therefore, development is underway to deposit gallium nitride at low temperatures by sputtering, using a buffer layer (orientation layer) to control the c-axis orientation of gallium nitride on amorphous substrates that can be processed in large areas, such as glass substrates. However, HEMTs generally have the problem of being prone to normally-on (depletion-type) properties.

[0007] One of the objectives of one embodiment of the present invention, in view of the above-mentioned problems, is to provide a transistor that suppresses normally-on activity and has a structure with a high degree of design flexibility. [Means for solving the problem]

[0008] A transistor according to one embodiment of the present invention includes an amorphous substrate, a first buffer layer on the amorphous substrate, a first nitride semiconductor layer provided in an island-like manner on the first buffer layer, a second nitride semiconductor layer covering the first nitride semiconductor layer on the first nitride semiconductor layer, and a gate electrode layer superimposed on the first nitride semiconductor layer on the second nitride semiconductor layer. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view showing the configuration of a transistor relating to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing the configuration of a transistor relating to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing the configuration of a transistor relating to one embodiment of the present invention. [Figure 4]This is a schematic cross-sectional view showing the configuration of a transistor relating to one embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing the configuration of a transistor relating to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] The embodiments of the present invention will be described below with reference to the drawings. Note that each embodiment is merely an example, and any embodiment that a person skilled in the art could easily conceive by modifying it appropriately while maintaining the spirit of the invention is naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may schematically represent the width, thickness, or shape of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention.

[0011] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] In this specification, for the sake of explanation, the terms "up" or "above" or "down" or "below" will be used. However, as a general rule, the substrate on which the structure is formed is used as the reference point, and the direction from the substrate toward the structure is defined as "up" or "above." Conversely, the direction from the structure toward the substrate is defined as "down" or "below." Therefore, in the expression "structure on a substrate," the surface of the structure facing the substrate is the bottom surface of the structure, and the opposite surface is the top surface of the structure. Furthermore, the expression "structure on a substrate" merely describes the hierarchical relationship between the substrate and the structure, and other components may be placed between the substrate and the structure. In addition, the terms "up" or "above" or "down" or "below" refer to the stacking order in a structure with multiple layers, and do not necessarily mean that the layers are in a superimposed positional relationship in a plan view.

[0013] In this specification, characters such as "first", "second", or "third" appended to each component are for convenience of identification to distinguish each component, and have no further meaning unless otherwise specified.

[0014] In this specification and the drawings, when collectively representing a plurality of identical or similar components, the same reference numerals are used, and when separately representing each of these plurality of components, it may be represented with appended lowercase or uppercase alphabets. Also, when separately representing a plurality of parts within one component, hyphens and natural numbers may be used.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] <First Embodiment> FIG. 1 is a schematic cross-sectional view showing the configuration of a transistor 10 according to an embodiment of the present invention.

[0017] As shown in FIG. 1, the transistor 10 includes an amorphous substrate 100, an underlying layer 110, a first buffer layer 120, a first nitride semiconductor layer 140, a second nitride semiconductor layer 150, a gate insulating layer 160, a gate electrode layer 170, a source electrode layer 180, and a drain electrode layer 190. The underlying layer 110 is provided on the amorphous substrate 100. The first buffer layer 120 is provided on the underlying layer 110. The first nitride semiconductor layer 140 has an island pattern and is provided on the first buffer layer 120. The second nitride semiconductor layer 150 covers the first nitride semiconductor layer 140 and is provided on the first nitride semiconductor layer 140. The gate insulating layer 160 overlaps with the first nitride semiconductor layer 140 and is provided on the second nitride semiconductor layer 150. The gate electrode layer 170 overlaps with the first nitride semiconductor layer 140 and is provided on the gate insulating layer 160. Each of the source electrode layer 180 and the drain electrode layer 190 is provided on the second nitride semiconductor layer 150 exposed from the gate insulating layer 160. Also, each of the source electrode layer 180 and the drain electrode layer 190 is in contact with the second nitride semiconductor layer 150.

[0018] The first nitride semiconductor layer 140 can be patterned using photolithography. The first nitride semiconductor layer 140 is located between the source electrode layer 180 and the drain electrode layer 190 and does not overlap with the source electrode layer 180 and the drain electrode layer 190.

[0019] The first nitride semiconductor layer 140 is in contact with the second nitride semiconductor layer 150. Furthermore, the first nitride semiconductor contained in the first nitride semiconductor layer 140 is different from the second nitride semiconductor contained in the second nitride semiconductor layer 150. Therefore, a heterojunction with a band discontinuity is formed at the interface between the first nitride semiconductor layer 140 and the second nitride semiconductor layer 150, and a high-concentration, high-mobility two-dimensional electron gas (2DEG) 145 is generated near the junction interface due to spontaneous polarization and the piezoelectric effect. In other words, the first nitride semiconductor layer 140 and the second nitride semiconductor layer 150 can function as a channel layer and a polarization layer, respectively. That is, the transistor 10 is a so-called HEMT.

[0020] The transistor 10 may also have a configuration in which the underlayer 110 or the gate insulating layer 160 is not provided. If the gate insulating layer 160 is not provided, the gate electrode layer 170 is in contact with the second nitride semiconductor layer 150 and functions as a so-called Schottky gate electrode.

[0021] The amorphous substrate 100 is a support substrate for the transistor 10. As will be described in detail later, the first nitride semiconductor layer 140 and the second nitride semiconductor layer 150 are deposited by sputtering, so the amorphous substrate 100 only needs to have heat resistance of, for example, about 600°C. For this reason, for example, an amorphous glass substrate can be used as the amorphous substrate 100. Alternatively, a resin substrate such as a polyimide substrate, acrylic substrate, siloxane substrate, or fluororesin substrate can also be used as the amorphous substrate 100. Such amorphous glass substrates or resin substrates are substrates that can be made in large areas.

[0022] The underlayer 110 can prevent the diffusion of impurities from the amorphous substrate 100 or from external sources (e.g., moisture or sodium (Na)). For example, silicon nitride (SiN) can be used as the underlayer 110. x A film or the like can be used as the base layer 110. x ) film and silicon nitride (SiN x) A laminated film with a film can also be used.

[0023] The first buffer layer 120 can control the crystal orientation of the first nitride semiconductor layer 140 deposited by sputtering, thereby improving the crystallinity of the first nitride semiconductor layer 140. Specifically, the first buffer layer 120 can control the crystallinity of the first nitride semiconductor layer 140 so that it has c-axis orientation. For example, if the first nitride semiconductor is gallium nitride, gallium nitride having a hexagonal close-packed structure grows in the c-axis direction to minimize surface energy, but by depositing gallium nitride on the first buffer layer 120, crystal growth of gallium nitride in the c-axis direction is promoted. As the first buffer layer 120, a material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto can be used. Here, a hexagonal close-packed structure or a structure similar to a face-centered cubic structure includes a crystal structure in which the c-axis is not 90° with respect to the a-axis and b-axis. A first buffer layer 120 made of a material having a hexagonal close-packed structure or a similar structure is oriented in the (0001) direction, i.e., in the c-axis direction, with respect to the amorphous substrate 100 (hereinafter referred to as the (0001) orientation of the hexagonal close-packed structure). Alternatively, a first buffer layer 120 made of a material having a face-centered cubic structure or a similar structure is oriented in the (111) direction with respect to the amorphous substrate 100 (hereinafter referred to as the (111) orientation of the face-centered cubic structure). The first buffer layer 120 having the (0001) orientation of the hexagonal close-packed structure or the (111) orientation of the face-centered cubic structure promotes the crystal growth of gallium nitride deposited on the first buffer layer 120 in the c-axis direction, and as a result, the first nitride semiconductor layer 140 has a highly crystalline c-axis orientation.

[0024] The crystallinity of the first nitride semiconductor layer 140 on the first buffer layer 120 is influenced by the surface state of the first buffer layer 120. Therefore, it is preferable that the first buffer layer 120 has a smooth surface with minimal irregularities. For example, the arithmetic mean roughness (Ra) of the surface of the first buffer layer 120 is preferably less than 2.3 nm. Also, the root mean square roughness (Rq) of the surface of the first buffer layer 120 is preferably less than 2.9 nm. When the surface roughness of the first buffer layer 120 meets the above conditions, the first nitride semiconductor layer 140 has a more crystallinity c-axis orientation. The film thickness of the first buffer layer 120 is preferably 50 nm or more.

[0025] The first buffer layer 120 may be made of a conductive material or an insulating material. The first buffer layer 120 can be formed using any method (apparatus) such as sputtering or CVD.

[0026] As the conductive material for the first buffer layer 120, titanium (Ti), magnesium (Mg), aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), or thorium (Th), or alloys thereof can be used. Alternatively, titanium nitride (TiN) can be used as the conductive material for the first buffer layer 120. x ), titanium dioxide (TiO x ), graphene, zinc oxide (ZnO), magnesium diboride (MgB2), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT can be used. In particular, it is preferable to use titanium, graphene, or zinc oxide as the first buffer layer 120.

[0027] Furthermore, silicon (Si), germanium (Ge), or alloys thereof can be used as the conductive material for the first buffer layer 120. Although silicon and germanium are semiconductor materials, they have higher conductivity than the insulating materials described later. Therefore, in this specification, semiconductor materials such as silicon and germanium are included in the category of conductive materials.

[0028] As the insulating material for the first buffer layer 120, aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), lithium niobate (LiNbO), BiLaTiO, SrFeO, SrFeO, BiFeO, BaFeO, ZnFeO, PMnN-PZT, or bioapatite (BAp) can be used. In particular, it is preferable to use aluminum nitride or silicon carbide as the first buffer layer 120.

[0029] As described above, the first nitride semiconductor layer 140 and the second nitride semiconductor layer 150 can function as the channel layer and polarization layer of the HEMT, respectively. The first nitride semiconductor layer 140 and the second nitride semiconductor layer 150 can be, but are not limited to, gallium nitride (GaN) and aluminum gallium nitride (AlGaN) compound semiconductors, respectively. For example, indium nitride (InN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN) can be used as the first nitride semiconductor layer 140 and the second nitride semiconductor layer 150, respectively.

[0030] Since the first nitride semiconductor layer 140 is formed on the first buffer layer 120, the first nitride semiconductor layer 140 has a highly crystalline c-axis orientation. Furthermore, since the second nitride semiconductor layer 150 is formed on the first nitride semiconductor layer 140 which has a highly crystalline c-axis orientation, the second nitride semiconductor layer 150 also has a highly crystalline c-axis orientation.

[0031] Here, as an example of forming the first nitride semiconductor layer 140, we will describe the deposition of gallium nitride using sputtering.

[0032] An amorphous substrate 100 is placed in a vacuum chamber facing a gallium nitride target. The composition ratio of gallium nitride in the gallium nitride target is preferably 0.7 to 2 gallium relative to nitrogen. In addition, nitrogen can be supplied to the vacuum chamber separately from the sputtering gas (such as argon (Ar) or krypton (Kr)). In this case, the composition ratio of gallium nitride in the gallium nitride target is preferably more gallium than nitrogen. For example, nitrogen can be supplied using a nitrogen radical source. The sputtering power supply may be a DC power supply, an RF power supply, or a pulsed DC power supply.

[0033] The amorphous substrate 100 in the vacuum chamber may be heated. For example, the amorphous substrate 100 can be heated to a temperature between room temperature and 600°C, preferably between 100°C and 400°C. This temperature range is applicable even to amorphous glass substrates with low heat resistance. Furthermore, this temperature is lower than the film deposition temperature in MOCVD or HVPE.

[0034] After thoroughly evacuating the vacuum chamber, sputtering gas is supplied. A voltage is then applied between the amorphous substrate 100 and the gallium nitride target at a predetermined pressure to generate plasma and deposit gallium nitride.

[0035] The above describes a method for depositing gallium nitride by sputtering, but the sputtering configuration or conditions can be modified as appropriate. Furthermore, if an aluminum gallium nitride target is used instead of a gallium nitride target, aluminum gallium nitride can be deposited.

[0036] As the gate insulating layer 160, silicon oxide (SiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x)、Lanthanum Oxide (LaO x )、Silicon Nitride (SiN x )、or Aluminum Nitride (AlN x ) etc. can be used. The gate insulating layer 160 may be a single layer or a laminated layer.

[0037] As the gate electrode layer 170, metals such as aluminum (Al), titanium (Ti), platinum (Pt), nickel (Ni), tantalum (Ta), or gold (Au), or alloys thereof can be used. The gate electrode layer 170 may be a single layer or a laminated layer.

[0038] As each of the source electrode layer 180 and the drain electrode layer 190, metals such as aluminum (Al), titanium (Ti), platinum (Pt), nickel (Ni), tantalum (Ta), or gold (Au), or alloys thereof can be used. Each of the source electrode layer 180 and the drain electrode layer 190 may be a single layer or a laminated layer.

[0039] In the transistor 10 according to this embodiment, the first nitride semiconductor layer 140 has an island - shaped pattern and does not overlap with the source electrode layer 180 and the drain electrode layer 190. Therefore, the 2DEG (two - dimensional electron gas) 145 generated by the hetero - junction also does not overlap with the source electrode layer 180 and the drain electrode layer 190. Thus, the leakage current between the 2DEG 145 formed in the first nitride semiconductor layer 140 and the source electrode layer 180 or the drain electrode layer 190 can be suppressed. Therefore, the transistor 10 has the property of being normally - off (enhancement type). Also, since the first nitride semiconductor layer 140 can be formed at an arbitrary position by patterning the first nitride semiconductor layer 140, the transistor 10 has a structure with a high degree of design freedom.

[0040] <Modification Example 1 of the First Embodiment> Referring to Figure 2, a modified example of transistor 10 will be described. Figure 2 is a schematic cross-sectional view showing the configuration of transistor 10A according to one embodiment of the present invention. In the following description, if the configuration of transistor 10A is the same as that of transistor 10, the description of the configuration of transistor 10A may be omitted.

[0041] As shown in Figure 2, the transistor 10A includes an amorphous substrate 100, a base layer 110, a first buffer layer 120A, a first nitride semiconductor layer 140, a second nitride semiconductor layer 150, a gate insulating layer 160, a gate electrode layer 170, a source electrode layer 180, and a drain electrode layer 190. The first buffer layer 120A is patterned such that the base layer 110 is exposed. The exposed base layer 110 is covered by the second nitride semiconductor layer 150. Specifically, the first buffer layer 120A includes a first region 121A-1 that overlaps with the first nitride semiconductor layer 140, and a second region 121A-2 that does not overlap with the first nitride semiconductor layer 140, with each end of the first region 121A-1 and the second region 121A-2 covered by the second nitride semiconductor layer 150. Furthermore, the first region 121A-1 and the second region 121A-2 are separated by the second nitride semiconductor layer 150 and are electrically insulated from each other by the second nitride semiconductor layer 150.

[0042] The first buffer layer 120A can be patterned using photolithography. The first region 121A-1 and the first nitride semiconductor layer 140 are located between the source electrode layer 180 and the drain electrode layer 190 and do not overlap with the source electrode layer 180 and the drain electrode layer 190.

[0043] If the first buffer layer 120A contains a conductive material, the second region 121A-2 can be used as a wiring channel. The transistor 10A may also have a configuration in which the second region 121A-2 is not provided.

[0044] In the transistor 10A according to this modified example 1, not only the first nitride semiconductor layer 140, but also the first region 121A-1 beneath the first nitride semiconductor layer 140 does not overlap with the source electrode layer 180 and the drain electrode layer 190. Furthermore, the first region 121A-1 and the second region 121A-2 are electrically insulated. Therefore, even if the first buffer layer 120A contains a conductive material, leakage current between the first buffer layer 120A (more specifically, the first region 121A-1) and the source electrode layer 180 or drain electrode layer 190 can be suppressed, so the transistor 10A has normally-off (enhancement) properties. Moreover, by patterning the first buffer layer 120A, the transistor 10A has normally-off (enhancement) properties regardless of the material of the first buffer layer 120A, so the transistor 10A has a structure with a high degree of design freedom.

[0045] <Modification 2 of the first embodiment> Referring to Figure 3, another modification of transistor 10 will be described. Figure 3 is a schematic cross-sectional view showing the configuration of transistor 10B according to one embodiment of the present invention. In the following description, if the configuration of transistor 10B is the same as that of transistor 10 or transistor 10A, the description of the configuration of transistor 10B may be omitted.

[0046] As shown in Figure 3, the transistor 10B includes an amorphous substrate 100, a base layer 110, a first buffer layer 120A, a second buffer layer 130B, a first nitride semiconductor layer 140, a second nitride semiconductor layer 150, a gate insulating layer 160, a gate electrode layer 170, a source electrode layer 180, and a drain electrode layer 190. The second buffer layer 130B is provided between the first buffer layer 120A and the first nitride semiconductor layer 140. The second buffer layer 130B is patterned to cover the first region 121A-1 and expose the second region 121A-2. The exposed second region 121A-2 is covered by the second nitride semiconductor layer 150. That is, each end of the first region 121A-1 and the second region 121A-2 is covered by the second buffer layer 130B.

[0047] The second buffer layer 130B has the same function as the first buffer layer 120A. That is, the second buffer layer 130B can also control the crystal orientation of the first nitride semiconductor layer 140 deposited by sputtering and improve the crystallinity of the first nitride semiconductor layer 140. However, an insulating material is used as the second buffer layer 130B. Because the second buffer layer 130B contains an insulating material, the first region 121A-1 and the second region 121A-2 are separated via the second buffer layer 130B and electrically isolated via the second buffer layer 130B.

[0048] The second buffer layer 130B can be patterned using photolithography. The second buffer layer 130B may or may not be superimposed on the source electrode layer 180 or the drain electrode layer 190. The transistor 10B may also have a configuration in which the second buffer layer 130B is not patterned.

[0049] In the modified transistor 10B, the second buffer layer 130B contains an insulating material, and the first region 121A-1 and the second region 121A-2 are electrically isolated via the second buffer layer 130B. Therefore, even if the first buffer layer 120A contains a conductive material, leakage current between the first buffer layer 120A (more specifically, the first region 121A-1) and the source electrode layer 180 or drain electrode layer 190 can be suppressed, and the transistor 10B has normally-off (enhancement) properties. Furthermore, by patterning the second buffer layer 130B to cover the first region 121A-1, the transistor 10B has normally-off (enhancement) properties regardless of the material of the first buffer layer 120A, and therefore the transistor 10B has a structure with a high degree of design freedom.

[0050] <Second Embodiment> Figure 4 is a schematic cross-sectional view showing the configuration of a transistor 20 according to one embodiment of the present invention. In the following description, when the configuration of transistor 20 is the same as that of transistor 10, the description of the configuration of transistor 20 may be omitted.

[0051] As shown in Figure 4, the transistor 20 includes an amorphous substrate 200, a base layer 210, a source electrode layer 280, a drain electrode layer 290, a first buffer layer 220, a first nitride semiconductor layer 240, a second nitride semiconductor layer 250, a gate insulating layer 260, and a gate electrode layer 270. The base layer 210 is provided on the amorphous substrate 200. The source electrode layer 280 and the drain electrode layer 290 are provided on the base layer 210. The first buffer layer 220 is located between the source electrode layer 280 and the drain electrode layer 290 and is provided on the base layer 210. The first nitride semiconductor layer 240 has an island-like pattern and is provided on the first buffer layer 120. The second nitride semiconductor layer 250 covers the source electrode layer 280, the drain electrode layer 290, and the first nitride semiconductor layer 240, and is provided on the source electrode layer 280, the drain electrode layer 290, and the first nitride semiconductor layer 240. Each of the source electrode layer 280 and the drain electrode layer 290 is in contact with the second nitride semiconductor layer 250. The edges of the first buffer layer 220 are covered by the second nitride semiconductor layer 250. The gate insulating layer 260 is superimposed on the first nitride semiconductor layer 240 and is provided on the second nitride semiconductor layer 250. The gate electrode layer 270 is superimposed on the first nitride semiconductor layer 240 and is provided on the gate insulating layer 260.

[0052] Transistor 20 is a so-called HEMT. That is, the first nitride semiconductor layer 240 and the second nitride semiconductor layer 250 function as a channel layer and a polarization layer, respectively, and a high-concentration, high-mobility two-dimensional electron gas (2DEG) 245 is generated near the junction interface between the first nitride semiconductor layer 240 and the second nitride semiconductor layer 250.

[0053] In transistor 20, the first buffer layer 220 has the same function as the first buffer layer 120 described above. However, a conductive material is used for the first buffer layer 220. The first buffer layer 220 is provided in the same layer as the source electrode layer 280 and the drain electrode layer 290. That is, the first buffer layer 220, the source electrode layer 280, and the drain electrode layer 290 are formed by patterning the same conductive material. The first buffer layer 220, the source electrode layer 280, and the drain electrode layer 290 can be patterned using photolithography. Thus, since the source electrode layer 280 and the drain electrode layer 290 are formed by patterning the conductive material of the first buffer layer 220, the first buffer layer 220 does not overlap with the source electrode layer 280 and the drain electrode layer 290.

[0054] In the transistor 20 according to this embodiment, the first buffer layer 220 and the first nitride semiconductor layer 240 do not overlap with the source electrode layer 280 and the drain electrode layer 290. Furthermore, the first buffer layer 220 is electrically insulated from the source electrode layer 280 and the drain electrode layer 290 via the second nitride semiconductor layer 250. Therefore, leakage current between the first buffer layer 220 and the source electrode layer 280 or the drain electrode layer 290 can be suppressed, and the transistor 20 has normally-off (enhancement) properties. In addition, since the source electrode layer 280 and the drain electrode layer 290 can be formed in the same process as the first buffer layer 220, the manufacturing cycle time of the transistor 20 can be shortened and manufacturing costs can be reduced. Moreover, in the transistor 20, the first buffer layer 220 does not overlap with the source electrode layer 280 and the drain electrode layer 290. Therefore, since the first nitride semiconductor layer 240 can be formed according to the pattern of the first buffer layer 220, the transistor 20 has a structure with a high degree of design flexibility.

[0055] <Modified form of the second embodiment> A modified example of transistor 20 will be described with reference to Figure 5. Figure 5 is a schematic cross-sectional view showing the configuration of transistor 20A according to one embodiment of the present invention. In the following description, when the configuration of transistor 20A is the same as that of transistor 20, the description of the configuration of transistor 20 may be omitted.

[0056] As shown in Figure 5, the transistor 20A includes an amorphous substrate 200, a base layer 210, a source electrode layer 280, a drain electrode layer 290, a first buffer layer 220, a second buffer layer 230A, a first nitride semiconductor layer 240, a second nitride semiconductor layer 250, a gate insulating layer 260, and a gate electrode layer 270. The second buffer layer 230A is provided between the first buffer layer 220 and the first nitride semiconductor layer 240. The second buffer layer 230A covers the first buffer layer 220 and is patterned so that the source electrode layer 280 and the drain electrode layer 290 are exposed. The exposed source electrode layer 280 and the drain electrode layer 290 are covered by the second nitride semiconductor layer 250. In other words, the ends of the first buffer layer 220, the source electrode layer 280, and the drain electrode layer 290 are each covered by the second buffer layer 230A.

[0057] The second buffer layer 230A has the same function as the first buffer layer 220A. However, an insulating material is used for the second buffer layer 230A. Because the second buffer layer 230A contains an insulating material, the first buffer layer 220 and the source electrode layer 280 or drain electrode layer 290 are separated via the second buffer layer 230A and electrically insulated via the second buffer layer 230A.

[0058] The second buffer layer 230A can be patterned using photolithography. The second buffer layer 230A may or may not be superimposed on the source electrode layer 280 or the drain electrode layer 290. The transistor 20A may also have a configuration in which the second buffer layer 230A is not patterned.

[0059] In the modified transistor 20A, the second buffer layer 230A contains an insulating material, and the first buffer layer 220 is electrically insulated from the source electrode layer 280 and the drain electrode layer 290 via the second buffer layer 230A. Therefore, leakage current between the first buffer layer 220 and the source electrode layer 280 or drain electrode layer 290 can be suppressed, and the transistor 20 has normally-off (enhancement) properties. Furthermore, since the source electrode layer 280 and the drain electrode layer 290 can be formed in the same process as the first buffer layer 220, the manufacturing cycle time of the transistor 20 can be shortened and manufacturing costs can be reduced. In addition, because the second buffer layer 230A is patterned to cover the first buffer layer 220, the transistor 20A has normally-off (enhancement) properties without depending on the conductive material of the first buffer layer 220A, and therefore the transistor 20A has a structure with a high degree of design freedom.

[0060] The embodiments described above as examples of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any modifications made by those skilled in the art to each embodiment, such as adding, deleting, or changing components, or adding, omitting, or changing processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0061] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0062] 10, 10A, 10B, 20, 20A: Transistors, 100, 200: Amorphous substrate, 110, 210: Base layer, 120, 120A, 220, 220A: First buffer layer, 121A-1: First area, 121A-2: Second area, 130B, 230A: Second buffer layer, 140, 240: First nitride semiconductor layer, 145, 245: Two-dimensional electron gas (2DEG), 150, 250: Second nitride semiconductor layer, 160, 260: Gate insulating layer, 170, 270: Guard electrode layer, 180, 280: Source electrode layer, 190, 290: Drain electrode layer,

Claims

1. Amorphous substrate and A first buffer layer on the amorphous substrate, On the first buffer layer, a first nitride semiconductor layer is provided in an island-like manner, On the first nitride semiconductor layer, a second nitride semiconductor layer covering the first nitride semiconductor layer, A transistor comprising a gate electrode layer superimposed on the first nitride semiconductor layer on the second nitride semiconductor layer.

2. The transistor according to claim 1, wherein the end of the first buffer layer is covered by the second nitride semiconductor layer.

3. Furthermore, it includes a second buffer layer between the first buffer layer and the first nitride semiconductor layer, The transistor according to claim 1, wherein the end of the first buffer layer is covered by the second buffer layer.

4. The first buffer layer comprises a conductive material, The transistor according to claim 3, wherein the second buffer layer comprises an insulating material.

5. Furthermore, the transistor according to claim 1, further comprising a source electrode layer and a drain electrode layer in contact with the second nitride semiconductor layer on the second nitride semiconductor layer.

6. The transistor according to claim 1, further comprising a source electrode layer and a drain electrode layer provided in the same layer as the first buffer layer.

7. Furthermore, the transistor according to claim 1, further comprising a gate insulating layer between the second nitride semiconductor layer and the gate electrode layer.

8. Furthermore, the transistor according to claim 1, further comprising an underlayer between the amorphous substrate and the first buffer layer.

9. The transistor according to claim 1, wherein the first buffer layer comprises at least one selected from titanium, graphene, and zinc oxide.

10. The transistor according to claim 1, wherein the first buffer layer comprises at least one selected from silicon, germanium, alloys thereof, and silicon carbide.

11. The transistor according to claim 1, wherein the amorphous substrate is an amorphous glass substrate.

12. The first nitride semiconductor layer is in contact with the second nitride semiconductor layer. The transistor according to claim 1, wherein a two-dimensional electron gas is generated near the interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

13. The transistor according to claim 1, wherein the first nitride semiconductor layer comprises gallium nitride.

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