Transceiver control antenna electron beam tilt

Abstract

A transceiver integrated circuit (IC) subarray, each transceiver IC subarray comprising at least a first transceiver IC and a second transceiver IC physically disposed within the subarray, the transceiver ICs configured to use one or more signal processing techniques to process a series of commonly processed aggregated signal port IQ data packets to achieve an electronic beam tilt selected from the group consisting of: (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via an NCO) according to the beam tilt information received in the control message packet and (ii) the subarray position of the transceiver IC; (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication); (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication); and (iv) imposing a time delay on the discrete time domain signal of the transmit baseband signal.

Description

Technical Field

[0001] The present disclosure relates to the field of telecommunication, and more specifically, to the distribution of signals for transmission via an antenna radiating element. It can find applications in the field of wireless communication such as 2G / 3G / 4G, LTE, LTE-Advanced, and 5G.

Background Art

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 357,579, filed on Jun. 30, 2022, entitled "Transceiver-Controlled Antenna Electronic Beam Tilt" with inventors Jongheon Kim and Yaniv Kaver, which is hereby incorporated by reference in its entirety for all purposes.

[0003] This section is intended to introduce the reader to various aspects of the technology that may be related to the various aspects of the present disclosure described and / or claimed below. This description is considered useful in providing the reader with background information that facilitates a better understanding of the various aspects of the systems and methods described herein. Accordingly, it should be understood that these descriptions are to be read from this perspective and should not be read as an admission of prior art.

Summary of the Invention

[0004] Described herein are methods and apparatus for implementing electron beam tilt in a subarray of individual transceivers, each transceiver being provided with the same frequency-domain IQ data (so-called “commonly processed IQ data”) for processing. When processing the frequency-domain IQ data, each transceiver implements one or more signal processing techniques to achieve electron beam tilt, including (i) applying an incremental phase rotation (e.g., via NCO) to each subcarrier frequency-domain IQ data point, (ii) applying a constant phase rotation (e.g., via complex multiplication) to each subcarrier frequency-domain IQ data point, (iii) applying a constant phase rotation (e.g., via complex multiplication) to each sample of the baseband time-domain signal, (iv) imposing a time delay on the discrete-time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. References to “one embodiment,” “embodiment,” “exemplary embodiment,” etc., herein indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments necessarily include those particular features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in relation to an embodiment, such feature, structure, or characteristic may be used in relation to other embodiments, whether or not it is explicitly described. [Brief explanation of the drawing]

[0005] [Figure 1] This document shows one embodiment of an active antenna array assembly or active antenna unit (AAU) according to several embodiments. [Figure 2] The following describes a radio unit architecture having multiple groups of serially connected transceivers used to process RF communication signals associated with corresponding groups of antenna radiating elements, according to several embodiments. [Figure 3]This describes a group of serially connected transceivers in which an incoming packet for transmission is received by a first transceiver and propagated through a serial data connection to other transceivers in the group, and the incoming RF signal is processed and packetized so as to be transferred along the serial transceiver chain. [Figure 4] This is an alternative embodiment of a wireless unit architecture having a hierarchical data distribution topology to each group of serially connected transceivers. [Figure 5] This document illustrates an embodiment of a synchronization and clock distribution circuit for use with transceivers distributed across an active antenna array assembly. [Figure 6] Several embodiments of providing a clock signal to a transceiver array and various clock distribution trees for reducing clock skew are shown. [Figure 7] This is a block diagram of a distributed unit connected to a wireless unit via a front-haul data interface, and a hierarchical beamformer architecture within the wireless unit, according to several embodiments. [Figure 8] This is a graphical representation of downlink transmit beamforming operation using a beamforming / precoding matrix operating on a user data layer to generate antenna-specific IQ data, according to several embodiments. [Figure 9] This figure shows the transformation of the user data layer into a beamforming downlink transmit data stream by a precoding operation followed by a beamforming operation, according to several embodiments. [Figure 10] This diagram illustrates the transformation of a user data layer into a beamforming data stream through generalized, combined precoding and beamforming operations, according to several embodiments. [Figure 11] This diagram shows a received uplink signal processing method, including received beamforming and layer decoding, according to several embodiments. [Figure 12A] A transceiver device architecture for forming a group of serially connected transceivers, according to several embodiments, is an example of a transceiver device architecture in which each transceiver includes an integrated digital signal processor for converting frequency-domain digital data to and from time-domain digital data, a plurality of integrated digital power amplifiers for converting digital baseband time-domain signals to amplified analog RF signals, an analog RF downconverter and an analog-to-digital converter. [Figure 12B] This is another example of a transceiver device architecture, excluding, in some embodiments, an integrated digital signal processor for converting frequency-domain digital data to and from time-domain digital data. [Figure 13A] Figures 12A and 12B are block diagrams of transceiver device transmitting circuits that generate multiple amplified multi-carrier RF signals, and transceiver device receiving circuits that generate multiple down-converted and sampled OFDM signals, respectively, according to several embodiments. [Figure 13B] Figures 12A and 12B are block diagrams of transceiver device transmitting circuits that generate multiple amplified multi-carrier RF signals, and transceiver device receiving circuits that generate multiple down-converted and sampled OFDM signals, respectively, according to several embodiments. [Figure 14] The signal processing flow through the transceiver devices of Figures 12A, 12B, 13A, and 13B for dual-carrier, dual-polarization communication signals according to several embodiments is shown. [Figure 15] Figures 12A, 12B, 13A, and 13B show a signal processing flow through two serially connected transceiver devices for generating a four-carrier dual-polarization communication signal according to several embodiments. [Figure 16] Several embodiments of multilayer beamforming are shown, illustrating various additional details. [Figure 17] The following describes the beamforming weight error in a subarray beamforming signal processing system according to several embodiments. [Modes for carrying out the invention]

[0006] Figure 1 shows an antenna array assembly 100 according to several embodiments. As shown, the antenna array assembly 100 has a grid of radiating elements (hereinafter also called antenna elements or antenna radiating elements) generally arranged in rows (e.g., row 104) and columns (e.g., column 100) on a panel 102 which may be a printed circuit board (PCB) or other suitable support structure for the radiating elements. Positions within the grid, such as position 116, have juxtaposed radiating elements such as elements 112 and 114, which can provide different radiating polarizations typically referred to as horizontal and vertical polarity, or equivalently, plus 45 degrees (+45°) and minus 45 degrees (-45°). The grid of radiating elements may be arranged in a regular array pattern as shown in Figure 1. In one embodiment, the radiating elements are spaced about half a wavelength (λ) apart, where the wavelength (λ) is associated with a desired frequency operating range of the antenna array, which can be associated with the system's carrier frequency, or more generally, the system's center frequency, particularly in embodiments using a frequency division duplexing system (FDD) that utilizes multiple carrier frequencies. Some embodiments may operate within multiple frequency bands, in one such embodiment, an array as shown in Figure 1 may be configured to operate in a first band using a first frequency of wavelength λ1 and in a second frequency band having wavelength λ2 = 2λ1. In such embodiments, operation in the first band (λ1) can utilize adjacent antenna radiating elements spaced 0.5λ1 apart as shown, but for operation in a second, lower frequency band (having wavelength λ2), two spaced elements (e.g., every other row or every other column) have a spacing of 0.5λ2 and can therefore be used for operation in the second frequency band.

[0007] The antenna array panel may consist of more antenna pairs (e.g., 128, 194, 256, 512, etc.) or fewer antennas (e.g., 32, 16, etc.), but the particular array in Figure 1 shows 64 horizontal radiating elements and 64 vertical radiating elements arranged in pairs in an 8x8 square configuration on a panel of approximately 35-40 cm x 35-40 cm, with the radiating elements spaced approximately 4.3 cm apart. The antenna array assembly 100 also includes a circuit board assembly 128 which includes a power module 130, a clock distribution circuit 132, a Global Positioning Satellite (GPS) receiver 134, a processor circuit 138 for performing packet protocol processing, among other things, beamforming in some embodiments, a network data interface 136, a power connector 140, and a GPS connector 142.

[0008] In the various embodiments described below in this specification, the radiating elements may be grouped into subarrays such as a column subarray 106 having eight vertical radiating elements and eight horizontal radiating elements, or into smaller subarrays such as groups 108 and 122, each having four horizontal elements and four vertical elements, or into groups 110, 120, 124, and 126, each having two vertical radiating elements and two horizontal radiating elements. In some embodiments, the antenna subarray may comprise a two-dimensional set of elements, such as four cross-polarized radiating elements arranged in a square configuration, or six cross-polarized pairs arranged in a 2x3 grid. Alternative forms include two or more adjacent sets of vertically polarized elements forming one antenna element subarray and a corresponding set of vertically polarized elements of cross-polarized pairs forming a separate subarray. In further embodiments, each cross-polarized pair of radiating elements may be an independently driven array element.

[0009] Each subarray of radiating elements may be driven by radio frequency (RF) signals generated by a set of transceivers located adjacent to the antenna. As used herein, the term “antenna subarray” refers to a group of radiating elements arranged in a corresponding array pattern that are functionally interconnected primarily in accordance with connections to a corresponding set of cooperative RF transceiver integrated circuits (ICs) used to process the RF signals associated with the radiating elements of the antenna subarray. In such a case, the transceiver circuit comprises a set or group of serially connected transceiver integrated circuit packages (hereinafter referred to as “transceiver ICs”) having a first transceiver IC connected to a beamformer processor via a serial data connection (or “link”) and a series of point-to-point serial data connections between the transceiver ICs, wherein in some embodiments, the data path terminates at the last transceiver IC in the group. In alternative embodiments, the transceiver ICs may be interconnected in a ring configuration, and the last transceiver IC in the chain may be connected back to the beamformer processor using additional serial data connections, or connected to the last transceiver IC in a separate subarray chain of serially connected transceiver ICs.

[0010] It should be noted that in some embodiments, a given group of transceiver ICs in a transceiver IC subarray associated with a corresponding antenna subarray (i.e., a set of serially connected transceiver ICs) may be capable of processing independent RF signals for each radiating element. Thus, as used herein, the term “antenna subarray” refers to a set of antenna elements (possibly of a larger antenna element array) associated with a given set of transceiver ICs. In some embodiments described herein, a group of radiating elements may work in a coordinated manner by transmitting identical or similar RF signals (or sets of RF signals for H and V polarization) with possible phase differences between them to achieve a desired radiation pattern for beamforming, antenna tilt, or similar directivity.

[0011] Figure 2 shows a radio unit architecture having multiple groups of serially connected transceivers used to process RF communication signals associated with corresponding groups of antenna radiating elements, according to several embodiments. As shown in Figure 2, each serially connected transceiver IC group includes at least two serially connected transceiver ICs physically arranged within a transceiver IC subarray. Specifically, transceiver IC 222, connected to a beamformer processor (referred to as "BFP" in some places herein) 202 via serial data link 206, is also serially connected to transceiver IC 232 via a full dual serial data link 228, thereby forming a transceiver IC subarray oriented vertically along a row of panel arrays, such as group 110. Similarly, transceiver IC 212 is connected to transceiver IC 230, forming another transceiver IC subarray.

[0012] Each serial data link between transceiver ICs (e.g., 228) establishes a point-to-point link using a Serdes (serializer / deserializer) transceiver or a set of Serdes transceivers. In one embodiment, each transceiver IC includes two such Serdes transceivers. Alternatively, a larger number of Serdes devices may be included to provide a higher level of interconnectivity between transceiver ICs. Serdes can utilize standard serial data signaling formats, such as two-level pulse amplitude modulation (PAM2) non-zero return (NRZ) differential signals transmitted over a pair of conductors. In one embodiment, a PAM2 data rate of 6 gigabits per second (Gbps) is sufficient to carry aggregated signal port IQ data packets (including headers) and to provide additional throughput capacity for transmitting control plane messaging to the transceiver ICs. The serial link data rate may be selected to accommodate data packets between individual transceiver IC subarrays, according to a desired deployment including a desired number of independent signal ports, a desired number of component carriers, multiband operation (thereby adding further carriers), FDD or TDD, and the number of transceiver ICs connected within the transceiver IC subarray.

[0013] Furthermore, as will be described in more detail below, in various embodiments, each serial data link between the beamformer processor 202 and a given transceiver IC subarray, as well as the serial data links that serially interconnect individual transceiver ICs within a given transceiver IC subarray, can have a data rate sufficient to accommodate data packets that carry IQ data in either the frequency domain or the time domain. In this regard, as will be described in more detail, each transceiver IC subarray may, for example, (i) receive / transmit aggregated frequency-domain IQ data packets to / from the beamformer processor when frequency-time domain conversion (transmission side) and time-frequency domain conversion (reception side) are performed in individual transceiver ICs (e.g., via respective iFFT (inverse fast Fourier transform) and FFT (fast Fourier transform) processes), or (ii) receive / transmit aggregated time-domain IQ data packets to / from the beamformer processor when frequency-time domain conversion (transmission side) and time-frequency domain conversion (reception side) are instead performed in the beamformer processor (e.g., via respective iFFT and FFT processes).

[0014] As an example of serial link data rates, one symbol of a 100MHz OFDM 5G carrier with a 30kHz subcarrier spacing is transmitted in a 33.33 microsecond (μs) time window. Having 3300 subcarriers, with 2 samples (I / Q) per subcarrier, and having, for example, 12 bits / sample, the data rate required for such transmission on two signal ports (e.g., separate signals for H and V polarization) yields 2 × 3,300 × 2 × 12 = 158.4kbps for each of the 14 OFDM symbol time slots, of which 14 are transmitted in a 0.5 millisecond transmit slot, resulting in a net required data rate of 158.4k × 14 bits / 0.5 milliseconds = 4.43Gbps. If 8b-10b encoding is used over the serial data link, and an additional 10% is added for packet headers and protocol overhead, then for a dual signal port, approximately 1.1 × 4.43 × 10 / 8 Gbps = 6.1 Gbps of throughput is required per carrier. In some embodiments, a serial data transmission capacity of 6.1 Gbps per transceiver IC subarray (i.e., a set of serially linked transceiver ICs) is sufficient. In other embodiments having independently controlled signal ports at each transceiver IC, a total throughput of 12 Gbps, or even up to 20 Gbps, is sufficient for most applications and configurations as described herein, although 30 Gbps may be achieved if desired for some other embodiments.

[0015] For lower-capacity deployments, a lower serial data rate is sufficient. For example, a dual-polarization 20 MHz 4G LTE data signal utilizing a size 2,048 FFT that occupies a transmission slot time window of 66.67 μs requires a data throughput of 2 ports × 1,200 subcarriers x 2 (I / Q samples / subcarrier) x 12 (bits / sample) / 66.67 μs window = 1,200 x 2 x 12 x / 66.67 μs = approximately 864 Mbps. If the data rate is increased by 10 / 8 to accommodate 8b-10b encoding and the overhead is 10%, the data rate is approximately 1.2 Gbps.

[0016] In a further embodiment of the transceiver IC serial data port, a 4-wire interface can be used to double the data rate. Alternatively, so-called ensemble NRZ (ENRZ) signaling, which uses a correlation signal in the form of a vector signal code, may be transmitted over 4 wires to carry 3 bits per baud (i.e., per signaling interval), resulting in a three-fold increase in the data rate rather than just doubling (at the same baud rate). Thus, using a signaling rate of 7.5 G baud / second, a data throughput of 22.5 Gbps can be reliably achieved over the distance from the beamformer to the transceiver IC subarray. As a further alternative, PAM4 signaling (in combination with NRZ or ENRZ signaling), or other vector signal formats (e.g., correlated NRZ (so-called CNRZ-5) that uses a correlation signal to carry 5 bits over 6 wires), can increase the data throughput without significantly increasing the signaling baud rate.

[0017] Overall, Figure 2 shows a total of eight columns of transceiver ICs, each column having eight transceiver ICs for a total of 64 transceiver ICs, and each transceiver IC is configured to handle two separate transmit signals (e.g., different RF signals on the H and V signal ports) and two separate receive signals (H / V signal ports). However, in the embodiment of Figure 2, the first two rows of eight transceiver ICs are connected in pairs, so these 16 transceiver ICs form a single “row” 238a of eight transceiver IC groups, also referred to herein as transceiver IC subarrays. Similarly, the other transceiver ICs are grouped into three further “rows” (238b, 238c, 238d) of eight transceiver subarrays, each resulting in a total of 8 columns × 4 rows of transceiver IC groups (32 transceiver IC subarrays). In terms of physical dimensions, each column is the width associated with a single, juxtaposed cross-polarized antenna, while each "row" in a transceiver IC group encompasses two rows of cross-polarized antenna elements.

[0018] Figure 4, further described below, also shows 32 transceiver IC subarrays within an 8x4 transceiver IC subarray configuration. However, each transceiver IC subarray contains three serially connected transceiver ICs. Note that the transceiver IC subarrays are positioned element-wise adjacent to the corresponding radiating antenna elements located in the corresponding antenna subarrays. In some embodiments, the transceiver IC subarrays are located on the back side of the antenna array panel 102, but are still adjacent (i.e., in close proximity) to each radiating element used to transmit and / or receive RF communication signals associated with a given transceiver IC. In some embodiments, the transceiver ICs may be coupled to the radiating elements through vias, intermediate structures, and / or circuits, such as transmit and receive filters, mounted on the panel or on a subpanel located behind the structure supporting the array of antenna radiating elements.

[0019] Element-to-element adjacency refers to the relative arrangement in which a transceiver IC subarray and a corresponding antenna subarray are superimposed on each other, such that each individual transceiver IC in a given transceiver IC subarray is located within the area of ​​panel 102 associated with the corresponding antenna radiating element of the antenna array or subarray used to transmit and receive signals associated with that individual transceiver IC.

[0020] As a further example of element-wise adjacency, in some embodiments such as frequency division duplexing (FDD) systems, two transceiver ICs (one dedicated to generating two transmit (H / V) signals at the transmit frequency and the other to processing two receive (H / V) signals at the receive frequency) can form a transceiver IC subarray associated with an antenna subarray consisting of a single juxtaposed cross-polarized antenna. In a dual-band FDD configuration, four transceiver ICs may be linked as a transceiver subarray and positioned adjacent to an antenna subarray consisting of a single juxtaposed cross-polarized antenna.

[0021] The element-wise adjacent characteristics provide a distributed transceiver IC architecture that allows the amplified transmit RF signal generated by each given transceiver IC to suffer very little power loss or noise degradation as it traverses the very short physical connection from the transceiver IC to the radiating element. Different ratios of transceiver ICs to radiating elements can be adjacent in pairs, such that two transceiver ICs may be placed adjacent to each set of three cross-polarized elements.

[0022] Throughout this description, many embodiments are described using a transceiver IC (e.g., 212, 222, 230, 232, etc.) which includes two independent full dual transceivers comprising two transmitters / amplifiers and two independent receivers, with each transceiver associated with an RF signal port (e.g., 214 or 216) interconnected to its respective antenna radiating element (e.g., 218, 220, respectively). Thus, in one embodiment, a single transceiver IC comprises an integrated circuit having two full transceivers that transmit and receive two independent RF signals, configured such that one RF signal port (tx / rx) is associated with an H-polarized signal port (e.g., 214) and the other RF signal port (tx / rx) is associated with a V-polarized signal port (e.g., 216). In such embodiments, each transceiver IC may be referred to as a 2T2R transceiver IC and may be associated with a pair of juxtaposed cross-polarized radiating elements. As an illustrative example, each cross-polarization pair of radiating elements (218, 220), (224, 226), and (234, 236) is associated with a single transceiver integrated circuit, such as transceiver IC212 associated with cross-polarization radiating element (218, 220), transceiver IC222 associated with element (224, 226), and transceiver IC232 associated with element (234, 236).

[0023] In other embodiments, each transceiver IC may be configured to provide four separate analog RF transmit and receive paths through, for example, four independent signaling ports (4T4R). Such embodiments may include a dual PLL for generating carrier frequencies for both the transmit and receive carriers for full utilization of the transceiver IC when operating in FDD signaling mode. The specific number of transceivers included in a given transceiver IC may depend on factors such as the desired total output power of the panel, the use of additional external power amplifiers, FDD or TDD operation, the data carrier capacity of the serial data link providing interconnection between the transceiver ICs, and many other factors.

[0024] More generally, referring to Figure 2, the circuitry of the radio unit 200 may all be located within a single active antenna panel assembly and include a high-throughput packet-based interface 252 to a base station or distributed unit (DU) (not shown). Interface 252 may comprise several separate physical network interfaces, such as four separate 25 Gigabit Ethernet links provided over fiber optic cable using small form factor pluggable (SFP) modules 242 or quad SFP (QSFP) modules. Data can be carried over interface 240 using the Ethernet protocol, CPRI / eCPRI protocol, or a similar protocol. The beamformer processor (BFP) 202 performs precoding and beamforming operations for downlink transmit data, as further described below with reference to Figures 8, 9, and 10, and in response generates aggregated signal port IQ data packets for transmission to the respective transceiver IC subarrays. As described above, in some embodiments, the IQ data packet may include frequency domain IQ values ​​for subcarriers in an OFDM (Orthogonal Frequency Division Multiplexing) communication system, such as an LTE or 5G communication system. In other embodiments, the IQ data packet may instead include time domain IQ values ​​for subcarriers in an OFDM communication system, or for other carriers, such as 2G GSM signals. In the uplink direction, the BFP202 performs beamformer coupling to acquire virtual beamforming antenna port signals, as further described below with respect to Figure 11, and performs further coupling to restore the user data layer.

[0025] In the embodiment shown in Figure 2, the beamformer processor 202 is connected to each transceiver IC subarray via serial data links such as link 206. Depending on the length of the data links, shown as four sets of eight links each 204a, 204b, 204c, and 204d, each data link can utilize Serdes repeaters / rettimers 208, 210 to extend the range of the serial data link from the BFP 202 to the area of ​​panel 102 where a given transceiver IC subarray (and corresponding antenna subarray elements) are located. In an alternative embodiment shown in Figure 4, the BFP 400 is connected to a set of transceiver IC subarrays via a high-speed Serdes link 402, and then Serdes multiplexer (MUX) 404 (and its respective high-speed links to Serdes MUX 422, 424, and 426) demultiplex (i.e., separate) the high-speed serial data stream into slower serial data streams 406 directed to each individual transceiver IC subarray. Serdes MUX devices 404, 422, 424, and 426 perform demultiplexing operations on the uplink data being transported from the transceiver IC subarray to the BFP202.

[0026] Referring to Figure 2, one exemplary transceiver IC subarray comprises transceiver ICs 222 and 232 coupled via serial data link 228. These two transceiver ICs are located adjacent to their respective antenna radiating elements 224, 226 and 234, 236. In some embodiments, they are located on one side of the printed circuit board in close proximity to the antenna elements and are electrically connected using through vias or by intermediate circuit elements such as filters, biplexers, quadriplexers, and SPDT (single-pole double-throw) TDM switches. As shown in Figure 2, each transceiver IC generates two separate RF transmit downlink (DL) signals for H and V polarities and receives and processes two separate RF uplink (UL) signals. Also shown is an observation transceiver 246 connected to the BFP 202 via serial data link 244, and an RF signal connection 248 interconnects each transceiver via a calibration network.

[0027] Figure 3 shows one such group of serially connected transceivers positioned in a transceiver IC subarray location adjacent to each antenna radiating element of a corresponding antenna subarray located within the antenna panel array 102. Incoming packets for DL ​​transmission are received from 300BFP via serial data link 308 in the first transceiver IC 312, and at least some of the packets are propagated through serial data connections 348, 364 to other transceiver circuits in transceiver ICs 350, 366 within the transceiver group. Similarly, incoming RF signals on UL are processed and packetized for transmission along the serial data transceiver IC chain 362, 346, 310. In this embodiment, each transceiver IC is configured to handle two separate transmit signal paths and two separate receive signal paths via two separate signal ports typically associated with two corresponding antenna radiating elements. In the transceiver subarray shown in Figure 3, operating in TDD mode, transceiver IC 312 is configured to transmit and receive RF signals on the first signal port 328 and on the second signal port 344. Similarly, transceiver IC 350 is associated with signal ports 356 and 360, and transceiver IC 366 is associated with signal ports 370 and 378.

[0028] As mentioned above, the two transceiver signal ports of the transceiver IC may be interconnected to a single set of cross-polarized antenna elements. In TDD operation, this provides 2T2R (two transmit and two receive) signal processing capability. In an alternative embodiment, each of the two signal ports can be connected to the corresponding radiating elements in two different cross-polarized antenna pairs, for example, a first transceiver in the transceiver IC process transmits and receives signals relating to the vertically polarized elements of the first cross-polarized radiating element pair, and a second transceiver in the same transceiver IC process transmits and receives signals relating to the vertically polarized elements of the second cross-polarized radiating element pair. The second transceiver IC can then be used to process signals relating to the two horizontally polarized elements of the two cross-polarized pairs.

[0029] In further alternative embodiments, the output of each signal port may be split and connected in parallel to multiple radiating elements, such that one signal port is connected in parallel to two (or three, etc.) vertically polarized radiating elements and the other signal port is connected in parallel to the same two (or three, etc.) cross-polarized pairs of horizontally polarized radiating elements. In further embodiments described below herein, the amplified RF signal generated by the transceiver IC, or by multiple transceiver ICs, may be supplied to and / or combined with an additional amplifier stage outside the transceiver IC before being supplied to the radiating elements.

[0030] In some embodiments, for example, frequency domain I / Q data packets are transmitted to a set of serially connected transceiver ICs distributed on an active antenna panel. The aggregated data packets are superpositions of frequency domain subcarrier-specific data, typically representing resource blocks (RBs) allocated across many data layers and possibly many users, to which different beamforming weights are applied, and thus containing fully beamforming (including MIMO precoding, if used) subcarrier IQ sample data for a given bandwidth, component carriers, and signal ports. Each IQ data packet may have a single header, but nevertheless may contain concatenated or interleaved data for multiple signal ports, such as H and V signal ports. Such packets may be called dual-signal port packets. In some embodiments, the packet header may contain identification data associated with a particular transceiver IC, and may contain IQ data for any number of signal ports processed by that transceiver IC, and may generally be called multi-signal port data.

[0031] The user-aggregated frequency domain data of packet 302 in Figure 3 represents a frequency domain IQ data packet that is commonly processed by transceiver ICs within a given transceiver IC subarray. Packet 302 may include a header (not shown for clarity) that identifies various aspects of the type of data contained in the packet, as well as packet identification data such as one or more of the following: frequency band ID, component carrier ID, signal port ID, and / or transceiver ID. The primary payload data within packet 302 includes subcarrier-specific IQ data for a signal port (but is not limited to, for example, a horizontally polarized RF signal for a particular component carrier labeled "H" in Figure 3). The same packet (or, in some embodiments, a separate packet with a separate header and ID data field) includes subcarrier IQ data for a second signal port (for example, a vertically polarized RF signal for the same component carrier, labeled "V" in Figure 3). In many embodiments described herein, a single transceiver IC is configured to process two separate signal port IQ packets, and the corresponding IQ data for the two signal ports may be combined into a single packet having a single header, sometimes referred to herein as a “dual signal port packet.” Packet 302 is shown as a concatenated IQ dataset for the subcarriers of the H-polarized and V-polarized signal ports, although the IQ data may be interleaved, such as IQ sample pairs for the H-signal port and for the V-signal port for subcarrier 1, followed by IQ pairs for H and V for subcarrier 2. Each I and Q sample may be represented as several bits, such as 12, 14, or 16, depending on the desired signal resolution. Packet 302 may include IQ sample data for each signal port, for a particular carrier, and for a frequency band, for several subcarriers, such as 612, 1,596, 3,276, or more subcarriers.

[0032] As described above, aggregated beamforming IQ data packets communicated from / to a BFP (Beamformer Processor) and between transceiver ICs via a serial data connection (link) may contain either frequency-domain (subcarrier-specific) IQ data or time-domain (subcarrier-specific) IQ data. In this regard, it should be noted that packet data transmission of aggregated beamforming frequency-domain IQ data packets via serial data connections from / to a BFP and between transceiver ICs is more efficient than packet data transmission of aggregated beamforming time-domain IQ data. In particular, frequency-domain IQ data specifies the in-phase and orthogonal (IQ) values ​​of specific subcarriers used for data transmission (and reception) in a given communication system. However, in the case of DL signals in OFDM communication systems (e.g., LTE or 5G communication systems), before converting frequency-domain IQ data to time-domain digital data via iFFT, it may be necessary to insert zero values ​​into the IQ dataset to account for unused subcarriers within a given component carrier (e.g., subcarriers used as guard bands), thereby resulting in a time-domain sequence of converted IQ data with more IQ data points that need to be carried to the transceiver IC / transceiver IC subarray (e.g., first carried from the BFP and then distributed accordingly among the transceiver ICs within the given transceiver IC subarray). Similarly, in the case of UL signals, while frequency-domain IQ data processed via FFT can exclude frequency-domain values ​​of unused subcarriers, the equivalent time-domain IQ data associated with the unused subcarriers is a component of the time-domain IQ data that may not be removed before transmission of time-domain data over a serial data connection, as described herein.

[0033] In this regard, depending on the bandwidth of a given communication channel, the increased efficiency of communicating frequency-domain IQ data over corresponding time-domain IQ data can be relatively important. For example, in the case of a 20MHz wide LTE channel, the ratio of unused subcarriers to data-modulated subcarriers is greater than the similar ratio for a 100MHz wide LTE channel. Therefore, it becomes more efficient to communicate subcarrier-specific IQ data in the frequency domain rather than the time domain. More specifically, as explained above, even if a subset of subcarriers remains unused (not modulated / loaded with data), the time-domain representation of those subcarriers still yields complex time-domain samples, thereby increasing the amount of data that needs to be transmitted over the serial data link. Furthermore, serial data links between BFP subarrays and transceiver IC subarrays, as well as serial data links interconnecting individual transceiver ICs within a given transceiver subarray, may have limited data carrying capacity (e.g., how much data can be communicated over those links per given period (data rate)). Therefore, in some embodiments, it may be more desirable to perform IQ packet data transmission in the frequency domain, from / to the BFP and between the transceiver ICs.

[0034] Nevertheless, various embodiments of the signal processing methods and apparatus described herein can instead utilize time-domain IQ data packets. More specifically, as will be described in more detail, in some embodiments, the beamforming processor (BFP) (e.g., BFP202, 300, 400, etc.) may be configured to include a digital signal processing architecture (e.g., iFFT and FFT processing elements) for transmitting and receiving time-domain IQ data packets to and from transceiver ICs / transceiver IC subarrays. For example, in some embodiments, the beamforming processor may include a digital signal processor (DSP) configured with appropriate programming instructions for executing algorithms for IFFT and FFT operations. For illustrative purposes, assuming, for example, that the IQ data packets communicated to and from BFP300 and between individual transceiver ICs are frequency-domain IQ data packets, various operating principles related to the arrangement shown in Figure 3 can be described below.

[0035] The transceiver subarray shown in Figure 3 is one of many such subarrays on the panel, and each serially connected transceiver IC group receives a unique data stream of aggregated signal port (or dual signal port, or multi-signal port) IQ data packets. It should be noted that each serially connected transceiver IC group has at least two serially connected transceiver ICs, which are physically located within the transceiver IC subarray. The transceiver IC subarray is then positioned element by element adjacent to the corresponding radiating antenna elements located in the corresponding antenna subarray.

[0036] The transceiver IC 312 receives a unique data stream of aggregated signal port IQ data packets, such as the user aggregated frequency domain data of packet 302 (as described above), at the serial port receiver 314 and provides the data to the split copy register 318 for further processing. In one embodiment, the split copy register 318 is a packet header processor configured to examine the packet header to determine whether the IQ data is intended to be processed by its corresponding transceiver IC, and if so, forward the packet to the signal port split processor 320. The signal port split processor 320 (also labeled H / V split) identifies packets or portions of packets that are destined for different signal ports within the transceiver IC and may be H and V polarized signals, or other configurations as described herein. The signal port split processor 320 may be implemented as a register that performs memory write operations to a digital signal processor (DSP) memory space integrated within the transceiver IC 312. Furthermore, the split copy register 318 can determine that the same packet should also be forwarded to the next transceiver IC in the transceiver IC subarray for processing by one or more of the serially connected transceiver ICs. To reduce latency, the packet header processor or the split copy register 318 does not need to buffer the entire signal port IQ data packet before making the decision to forward the packet to the next transceiver IC by sending the data to the serial data transmitter 332 for transmission over the serial link 348. In a further embodiment, the packet header processor 318 may be configured to operate in transparent mode, in which case all packets are stored for local processing and forwarded to the second serial transceiver without header checking.

[0037] With respect to the signal port packet format 302, the aggregated IQ signal port packets are transferred to each transceiver IC using split copy circuits 318, 352, and 368, and processed in common by each transceiver IC. Note that transceiver IC 366 is the last transceiver IC in the chain, and in the shown embodiment, the split copy register 368 transfers the packets to the corresponding signal port split processor, but serial transceivers 372 / 374 are not used.

[0038] Next, each transceiver IC processes the packets by first separating the IQ data for the first signal port (H IQ data 322) and the second signal port (V IQ data 338), and providing the data to the transmitters in transceivers 321 and 335 for conversion to the time domain via an inverse fast Fourier transform (iFFT). As previously described, individual IQ port-specific data may be carried in separate packets, in which case the signal port data may be stored directly for further processing without requiring any separation or deinterleaving. The iFFT processing and subsequent time domain processing generate aggregated signal port discrete time domain baseband data signals, which are then converted to amplified radio frequency (RF) signals at ports 328 and 344. The transmitters of transceivers 321 and 335, which are described more fully with reference to Figures 12A and 13A, include a DSP for calculating the iFFT, frequency-domain and time-domain signal processing elements (such as cyclic prefix addition, phase and gain adjustment, frequency offset, filtering and sample rate conversion, crest factor reduction (CFR), and digital pre-distortion (DPD)), as well as RF modulation and amplification circuits in the form of a multiphase carrier generator and a digital power amplifier. Note that in alternative embodiments, such as those involving the communication of aggregated signal port / user IQ data packets in the time domain (as described above), the iFFT processing may be performed in a beamformer processor instead of the transceiver IC itself.

[0039] Accordingly, some embodiments involve receiving a unique data stream of aggregated signal port IQ data packets in each serially connected transceiver IC group of a plurality of serially connected transceiver IC groups, wherein each serially connected transceiver IC group includes at least two serially connected transceiver ICs physically located within a transceiver IC subarray and adjacent to each corresponding radiating antenna element located within a corresponding antenna subarray, and within each serially connected transceiver IC group, transferring at least a subset of the aggregated signal port IQ data packets from the first transceiver IC to the next serially connected transceiver IC, and each serially connected transceiver IC group A method may include, in a group of serially connected transceiver ICs, processing at least a portion of the aggregated signal port IQ data packets using the transceiver IC's integrated inverse fast Fourier transform (IFFT) processor to convert the aggregated signal port IQ data packets into aggregated signal port discrete-time domain baseband data signals; using the transceiver IC's integrated digital power amplifier and multiphase carrier generator to convert the aggregated signal port discrete-time domain baseband data signals into amplified modulated radio frequency signals; and transmitting the amplified modulated radio frequency signals on at least one of the corresponding adjacent radiating antenna elements.

[0040] Furthermore, some embodiments may include a device comprising a plurality of transceiver IC subarrays, each transceiver IC subarray comprising: a first transceiver IC having (i) a first serial digital data port providing serial data connectivity to a beamformer processor and configured to receive a unique data stream of aggregated signal port IQ data packets; and (ii) a second serial digital data port; and a second transceiver IC connected to the second serial data port of the first transceiver IC and having a third serial digital data port providing serial data connectivity to the first transceiver IC. The first and second transceiver ICs may be physically arranged within the transceiver IC subarray and adjacent to each element of a plurality of radiating antenna elements arranged within the antenna subarray. The first transceiver IC in each transceiver IC subarray may further include a packet processor configured to transfer at least a subset of aggregated signal port IQ data packets received from the beamformer processor to their respective second transceiver ICs. The first transceiver IC and the second transceiver IC may each include a digital signal processor configured to perform an inverse fast Fourier transform (IFFT) to convert aggregated signal port IQ data packets into aggregated signal port discrete-time domain baseband data signals; a time domain processing circuit configured to convert the aggregated signal port discrete-time domain baseband data signals into oversampled signal port discrete-time domain data signals; and an integrated digital power amplifier and a multiphase carrier generator configured to convert the oversampled signal port discrete-time domain data signals into analog-modulated radio frequency signals.

[0041] When receiving an uplink (UL) signal, the receiver portion of transceivers 321 and 335 performs frequency down-conversion and analog-to-digital conversion, followed by further time-domain processing (e.g., sample rate conversion, quadrature error correction, filtering, frequency offset correction, cyclic prefix detection and removal), and then performs an FFT conversion to frequency-domain IQ data values ​​for each of the multiple subcarriers in the OFDM signal. Thus, in receive operation mode, the transceiver ICs generate IQ data packets 322 and 338 from the received RF signal, as shown in Figure 3.

[0042] In one embodiment, the transceiver IC includes a digital signal processor (DSP) that not only performs all iFFT calculations to generate downlink (DL) transmit time-domain signal port signals, but also processes received uplink (UL) data samples via FFT to generate received frequency-domain IQ data signals associated with each of the signal ports. However, in an alternative embodiment, for example, involving the communication of aggregated signal port / user IQ data packets in the time domain, the FFT processing may be performed in a beamformer processor instead of the transceiver IC itself (as described in more detail in relation to Figure 12B).

[0043] With regard to embodiments relating to packet structure 302, UL frequency domain IQ data from each signal port may first be concatenated into a single packet in the format of packet 302, having H and V portions representing locally generated UL received frequency domain IQ information in the transceiver IC. However, since received IQ packets are carried along a transceiver IC subarray, a received UL frequency domain IQ packet received via a serial data link from another transceiver IC in the subarray may be combined with locally generated received IQ data before transmission to the next transceiver IC. Specifically, when transceiver IC 350 receives a UL IQ packet from transceiver IC 366 on link 362, the UL IQ packet processor 358 combines the received IQ data with its locally generated UL IQ data. As will be more fully described herein, the combination may involve sample-by-sample addition (i.e., for each subcarrier, I data samples are added and Q samples are added), or the I data and Q data of a single packet may be phase-rotated and added before combination. Next, the combined UL IQ data packets received on link 346 via the Serdes receiver 330 are further combined with locally generated UL IQ data from transceivers 321 and 335, which are stored in the UL signal port IQ data coupler 336. In this way, in embodiments relating to packet data format 302, the amount of received data transmitted along links 362, 346, and 310 remains the same for each serial data link along the transceiver IC subarray.

[0044] Accordingly, in a further embodiment, the method includes receiving modulated RF signals at multiple signal ports of each transceiver IC in a subarray of serially connected transceiver ICs; generating one or more frequency-domain digital data packets of subcarrier IQ data associated with each signal port by demodulating each modulated RF signal from each signal port using an FFT processor in each transceiver IC; forming multiple coupled frequency-domain digital data packets from the transceiver ICs using a set of serial data links between the transceiver ICs in the subarray of serially connected transceiver ICs; and transmitting the multiple coupled frequency-domain digital data packets from the subarray of transceiver ICs to a beamformer processor.

[0045] Furthermore, in some embodiments, each transceiver IC may be configured to process signals from two signal ports, such as from a cross-polarized antenna element or a set of parallel-connected elements. Other embodiments may use a transceiver IC having four separate signal ports. In each embodiment, a given signal port may receive a plurality of modulated carriers (each having a set of subcarriers), and the demodulated frequency-domain data may be packetized according to the component carriers it receives. Thus, one or more frequency-domain digital data packets of subcarrier IQ data associated with each signal port may be packetized with header information that identifies the signal port (e.g., signal port ID), component carriers (e.g., component carrier ID), and additional identification information (e.g., subcarrier subset ID for use in multilayer beamforming). Each transceiver IC may participate in the formation of a plurality of combined frequency-domain digital data packets by receiving frequency-domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining them with its own locally generated frequency-domain digital data packets of subcarrier IQ data. Depending on the location of a given transceiver IC in a transceiver IC subarray, some transceiver ICs actually receive partially formed combinations of frequency-domain digital data packets.

[0046] In embodiments relating to packet structure 304 (note that the header is not shown for clarity), six separate signal port packets may be provided to the transceiver IC subarray from which six independent transmit signals may be generated. Generally, the ability of an AAU system to generate independent RF transmit signals from separate digital IQ data associated with each radiating element is referred to herein as full-dimensional beamforming. In this embodiment, all six packets, representing the full-dimensional digital beamforming signals, are received at the transceiver IC 312 via link 308 at the receiving Serdes 314 and provided to the split copy processor 318. The split copy processor 308 examines the packet header and forwards the first set of two signal port packets (the rightmost H / V portions 324 and 340 of format 304) to the signal port split processor 320 for the transmission of IQ data 324 (for port 328) by transceiver 321 and IQ data 340 (for port 344) by transceiver 335, and forwards the remaining four packets to the Serdes transmitter 332. The next transceiver IC 350 receives the four packets via link 348 at its Serdes receiver, and the split copy processor 352 performs packet header analysis and forwards two signal port packets to its signal port split processor 354 within 350, and forwards the remaining two packets to the Serdes transmitter (TX#0 of transceiver IC 350) for transmission to transceiver IC 366 via link 364. The signal port splitting processor 354 provides the H and V signal port IQ data to its transceivers for transmission on signal ports 356 and 360, respectively. Transceiver IC 366 receives the remaining two IQ data packets and processes them in a similar manner for transmission on ports 370 and 378. Note that the amount of serial data decreases along the transceiver IC subarray for DL ​​IQ data packets. In this embodiment, the receive processing does not involve any UL IQ packet data binding.Rather, the packets are simply retransmitted from each transceiver IC (using UL IQ packet processors 358 and 334 for concatenation / retransmission), and as a result, all six received UL signaling port IQ packets are carried to the beamformer processor via link 310 (the packets may be formatted with individual headers or carried as a concatenated payload with a single header). Note that the amount of data increases as packets on link 362 from transceiver IC 366 are concatenated with IQ data from transceiver IC 350 in UL IQ packet processor 358 for transmission via link 346. The amount of data increases again on link 310 as UL IQ data 340 and 324 from UL signaling port IQ data concatenate by UL IQ packet processor 334.

[0047] In some embodiments, a full-dimensional beamforming packet unique to each signal port may be provided for smaller bandwidth signals, such as a 20 MHz data bandwidth. This may be desirable in some deployments where the AAU panel consists of lower-rate serial data connections in the transceiver IC subarray. Thus, even in systems with slower serial data interconnects, complete control of signal port signals (and corresponding radiating elements) can be supported by concatenating separate IQ data of interconnected transceiver ICs and extracting relevant datasets at each IC. This enables MU-MIMO support in the vertical plane with much higher precision and supports use cases associated with flying drones (either drones with data connectivity as users in the system, or drones by blocking interference from high-altitude interfering drones).

[0048] In a third embodiment of the antenna array system, a multilayer beamforming signaling scheme may be used to provide data transmission and reception. In this embodiment, several transmit IQ data packets are processed in common among multiple transceiver ICs to achieve a first level of beamforming resolution, an additional set of IQ data packets is distributed to each of the transceiver IC subarrays, and each packet of a given additional set of transmit IQ data packets is processed among fewer (or even one) transceiver ICs within the transceiver IC subarray to obtain a second, higher resolution level of beamforming. Specifically, data format 306 provides a combination of beamforming resolutions, thereby processing two signal port IQ data packets (e.g., the first two H and V portions of 306, 326, and 342) for transmission by each of the transceiver ICs 312, 350, and 366 in a manner similar to the signal processing described above with respect to packet format 302. Since the same IQ data is transformed and transmitted by multiple corresponding radiating elements within the subarray, these IQ data packets, referred to herein as “commonly processed” IQ data, result in the first layer beamforming resolution, where the beam is formed as a result of phase signal contributions emanating from other subarrays (i.e., inter-subarray beamforming). However, further, an additional set of six signal port IQ data packets (three additional sets of 306 H / V data) are distributed across a given transceiver IC subarray in a manner similar to the signal processing described above with respect to packet format 304 for full digital beamforming data. These additional packets are specific to a given signal port and / or transceiver IC and provide a unique IQ data stream for transmission by each individual signal port within a given transceiver IC subarray, thereby providing transmission and reception of the second layer beamforming resolution.Specifically, the beam is formed as a result of phase signal contributions from other transceiver ICs within a given subarray, as well as phase signal contributions from other transceiver ICs within other transceiver IC subarrays (i.e., second-layer beamforming from both intra-subarray beamforming and inter-subarray beamforming).

[0049] Multilayer beamforming having a packet of form 306, shown in Figure 3 and further described below with respect to Figures 12A-12B, 13A and 13B, utilizes the processing of two separate signal port IQ packets, such as IQ data 326 and IQ data 327 (and likewise 342, 343), which are shown to be coupled for transmission on the same signal port. In one embodiment, separately beamforming IQ packets may contain IQ data points for different subcarriers within a set of subcarriers of a single component carrier. Thus, each transceiver IC may form its own unique coupled set of IQ data points for its respective signal port before iFFT processing. Specifically, transceiver IC 312 couples IQ data 326 and 327 for transmission on signal port 328 via coupling, and couples IQ data 342 with IQ data 343 for transmission on signal port 344. Transceiver IC 350, the next transceiver IC in the transceiver IC subarray, combines IQ data 326 (the same as that processed by transceiver 321 of transceiver IC 312) with signal port IQ data 355, and combines IQ data 342 (the same commonly processed IQ data as that processed by transceiver 335 of transceiver IC 312) with signal port IQ data 359. A similar unique concatenated combination is shown for transceiver IC 366, where IQ signal port data packets 326 and 342 are combined with unique signal port IQ data 369 and 377, respectively. Within the transceiver IC subarray, the commonly processed IQ packets 326 and 342 provide a first-layer beamforming component contributed by the subarray, and an additional set of distributed IQ packets within the transceiver IC subarray provides a second-layer beamforming component associated with that subarray.

[0050] In a further embodiment, a separate IQ packet may have overlapping subcarriers, in which case the transceiver IC processing includes forming a weighted average of the overlapping subcarriers before the iFFT processing. In such an embodiment, the beamformer processor can carry one or more weights for the transceiver IC to use when forming the combination of IQ transmit data for the overlapping subcarriers.

[0051] Accordingly, in one embodiment, multilayer beamforming includes receiving a first-layer beamforming IQ packet and a plurality of second-layer beamforming packets via serial data connections interconnecting the transceiver ICs in a plurality of transceiver IC subarrays; forming a multilayer beamforming packet in each transceiver IC by combining the first-layer beamforming IQ packet with at least one of the plurality of second-layer beamforming packets; generating a time-domain signal from the multilayer beamforming packet; and transmitting the multilayer beamforming signal by transmitting the respective amplified radio frequency time-domain signals from the transceiver ICs of the transceiver IC subarray via the corresponding adjacent antenna element subarrays.

[0052] In some embodiments, each of the first layer beamforming IQ packets and the plurality of second layer beamforming packets includes frequency domain IQ data. In other embodiments, each of the first layer beamforming IQ packets and the plurality of second layer beamforming packets includes time domain IQ data.

[0053] In some embodiments, multilayer beamforming packets are formed by concatenating IQ samples of distinct subcarriers, and then the packets are processed using the same iFFT operation. In other embodiments, multilayer beamforming packets are formed by concatenating overlapping subcarriers using weights provided via a management plane message, and then processed using the same iFFT operation.

[0054] In further embodiments, IQ packets carrying data used for second-layer beamforming may be associated with subcarriers of separate component carriers. In such embodiments, additional higher-resolution beamforming data may be processed independently using separate iFFTs before combining the two-layer time-domain signals of the beamforming signal. Accordingly, in one embodiment, multilayer beamforming includes: receiving a first-layer beamforming IQ packet and a plurality of second-layer beamforming packets in a plurality of transceiver ICs of a transceiver IC subarray via a serial data connection interconnecting the transceiver ICs; in each transceiver IC, converting the first-layer (commonly processed) beamforming IQ packet into a time-domain signal; separately converting at least one of the plurality of second-layer beamforming IQ packets into a time-domain signal via a separate iFFT; combining the two time-domain signals to form a signal port-specific multilayer beamforming time-domain signal; and transmitting a multilayer beamforming signal by transmitting an amplified radio frequency time-domain signal generated from the respective signal port-specific multilayer beamforming time-domain signals from the transceiver ICs of the transceiver IC subarray via the corresponding adjacent antenna element subarray. The plurality of transceiver IC subarrays and their corresponding antenna element subarrays cooperate to generate the multilayer beamforming signal.

[0055] In multilayer beamforming that uses the distribution of multilayer IQ packet data among multiple transceiver IC subarrays, one set of users may be served by aggregated IQ signal port packets that are copied and forwarded for processing by each transceiver IC along a given transceiver IC subarray, resulting in a first level of beamforming resolution (determined, for example, by the total number of unique, independent signal port IQ packet streams sent to the total number of corresponding transceiver IC subarrays for processing by each transceiver IC). However, a separate set of users may be served by higher-resolution beamforming by further distributing additional signal port-specific IQ data packets along the transceiver IC subarray for separate processing by each individual transceiver IC (i.e., IQ data not processed in common).

[0056] It should be noted that in many embodiments, the IQ packets commonly processed in multilayer beamforming signal processing are unique to a particular transceiver IC subarray. However, in some scenarios, to achieve a desired beam emission pattern (i.e., one with a lower degree of beamforming resolution), some commonly processed IQ packets may be identical for two or more transceiver IC subarrays.

[0057] Received UL signal processing for multilayer beamforming is also a hybrid of the UL received signal processing described above, where IQ data coupling may be performed for a first pair of signal port IQ packets, and IQ data concatenation may be performed for an additional set of independent UL signal port IQ data packets. Thus, first-layer beamforming is performed by each transceiver IC involved in the formation of a UL coupled frequency domain digital data packet by receiving frequency domain digital data packets of subcarrier IQ data from adjacent transceiver ICs via a serial data link and coupling them with its own locally generated frequency domain digital data packets of subcarrier IQ data. Second-layer beamforming processing involves transporting the UL received IQ packets along the transceiver IC subarray not by coupling, but rather by concatenation (sample-by-sample or packet-by-packet, so as not to change the IQ samples).

[0058] In some embodiments configured as an array of N × M transceiver ICs, each comprising a set of N transceiver IC subarrays, each having M serially connected transceiver ICs, multilayer beamforming may be characterized by processing a first set of aggregated beamforming frequency domain IQ user data according to the beamforming resolution of the first layer to generate N unique beamforming IQ data packets (or sets of packets such as IQ data sets for each signal port (e.g., H and V) in the transceiver IC), each distributed to one of the N transceiver IC subarrays, and processing a second set of beamforming aggregated frequency domain IQ user data sets according to the beamforming resolution of the second layer to generate N different sets of M unique beamforming IQ data packets (or sets of packets for each set of signal ports in each transceiver IC), each of the N sets of M packets being distributed to one of the N transceiver IC subarrays. Each of the different packets is transmitted to the N transceiver IC subarrays via their respective serial data links. Each transceiver in a given subarray processes packets associated with Layer 1 beamforming data in common, combining them separately with only a portion of the Layer 2 beamforming packets.

[0059] Referring to Figure 16, an embodiment of two-layer beamforming is shown, in which the panel may be configured to process UL and DL data according to first-layer beamforming that provides a beam (e.g., 1612) within a scanning range 1614, using subarray-level beamforming (as shown in configuration 1604) with three dual-polarization elements per subarray 1606. In the embodiment shown, the subarray-level beamformer generates beamforming IQ packets for frequency content 1618 that are processed in common within each respective subarray, as described with respect to IQ data 326 and 342. The same panel can be configured simultaneously (as shown in configuration 1600) to provide another or second-layer beamforming with higher phase resolution, using a unique beamforming IQ dataset to generate a unique signal at each cross-polarization element 1602. In the embodiment of Figure 16, frequency content 1616 may be assigned to high-resolution beamforming layers such as data 327, 343, 355, 359, 369, and 377. The frequency content of frequency ranges 1616 and 1618 may correspond to different subcarriers within a single component carrier, or to separate component carriers, as described herein.

[0060] It should be noted that in second-layer beamforming, individual beams (e.g., 1608) can be directed over a wider scanning range 1610 due to higher phase resolution. In contrast, the scanning angles in subarray beamforming (where multiple signal ports transmit and receive signals processed according to a common IQ beamforming packet) have a limited scanning range due to increased quantization errors in the beamforming weights, as shown in Figure 17. In particular, the scanning angles of two representative beams, represented by the diagonal lines labeled "Desired BF Weights," represent two individual beams with different scanning angles. In full-dimensional beamforming, the IQ data for each signal port is formed using desired weights with phases as shown, including, for example, points 1702, 1710, and 1706 for lower scanning angles, and exemplary points 1712, 1720, and 1716 for steeper scanning angles (shown as dashed lines). However, in subarray beamforming, the commonly processed beamforming IQ data can be generated using the average phase for the desired beam across elements in a given subarray, indicated by exemplary phases 1704, 1710, 1708 for a single beam and phases 1714, 1718, 1720 for steeper beams. The corresponding beamforming weight phase error is indicated by the line labeled “BF weight error”. Note that steeper scanning angles have higher beamformer weight errors. As a result, second-layer beamforming allows for larger scanning angles because there is no quantization error and subarray beamforming has a reduced scanning range. Note that in the case of a two-element subarray, the beamforming weights used in forming individual beams can be the average value between two desired phase values, or otherwise a value between two desired weight phases. Finer phase control avoids what is sometimes called a “quantization lobe,” which is generated because the weights applied are constrained to be the same for several adjacent elements in the subarray. The quantization lobe increases as the scanning angle increases.

[0061] In short, full-dimensional beamforming is performed with a higher level of precision in beamformer weights, whereas subarray beamforming is performed on an average of the desired weights, introducing errors. Therefore, elements configured according to configuration 1600 with full-dimensional control have a larger scanning range than subarray beamforming configuration 1604, in which beamforming is performed using an average bf weight for each given beam (such as a UE intrinsic beam or spatially multiplexed layer beam).

[0062] The multi-layer beamforming described herein can be used to provide high-quality service to a set of users, such as users located in high-rise buildings within a cell sector, without sacrificing coverage for other user devices located at ground level (e.g., by limiting allocated data bandwidth). Similarly, the system can be used in conjunction with ground-level user devices to support communication with drones and other high-altitude devices. The system described herein is configured to provide these alternative beamforming transmissions between user devices within a single radio unit.

[0063] A multimode beamforming system may be configured to sequentially or dynamically allocate OFDM transmissions to each slot according to two or more levels of beamforming resolution. In particular, a first time-transmitting time interval (TTI) or even a first OFDM symbol time slot may be allocated to a user device that is beamformed according to first-layer subarray level beamforming so that during transmit signal processing, the transmit IQ data packets sent to each transceiver IC subarray are processed in common by each of the transceiver ICs in each such subarray. Similarly, during signal reception, the processed IQ data packets from each transceiver IC are coupled as they are carried from transceiver IC to transceiver IC along the serially connected transceiver ICs in each subarray. In a second or subsequent time slot, a frequency resource block may be allocated to a user device for higher-resolution beamforming, including fully controlled beamforming IQ data according to the higher phase-resolution beamforming of the second layer, where individual transmit IQ packets are separately formed for serial data transmission and sent to each transceiver IC subarray for individual processing by a specifically addressed transceiver IC within each transceiver IC subarray.

[0064] In some embodiments, the transmit bandwidth associated with a fully controlled digital beamforming IQ data packet (i.e., the number of IQ sample pairs corresponding to the number of modulation subcarriers) may be smaller than the bandwidth utilized by the commonly processed IQ data packet, such as a comparison between commonly processed packet data 302 and fully digital beamforming packet data 304. In some embodiments, the multilayer beamforming method involves receiving a first-layer beamforming frequency domain IQ data packet and a plurality of second-layer beamforming frequency domain IQ data packets in a transceiver IC subarray having a plurality of interconnected transceiver integrated circuits (ICs), wherein the transceiver ICs are interconnected via a plurality of serial data connections, and each transceiver IC in the transceiver IC subarray receives beamforming frequency domain IQ data from the first-layer beamforming frequency domain IQ data packet and the second-layer beamforming from the plurality of second-layer beamforming frequency domain IQ data packets. The process includes forming a multilayer beamforming frequency domain IQ dataset by combining beamforming frequency domain IQ data from one selected frequency domain IQ data packet; generating discrete-time domain signals from the multilayer beamforming frequency domain IQ dataset using a digital signal processor (DSP) in a transceiver IC; generating modulated radio frequency (RF) signals from the discrete-time domain signals; and transmitting the multilayer beamforming signals by transmitting the respective modulated RF signals from the transceiver ICs of the transceiver IC subarrays via corresponding adjacent antenna element subarrays. Transmitting the multilayer beamforming signals can be done by transmitting the respective modulated RF signals from the transceiver ICs of multiple transceiver IC subarrays via corresponding multiple adjacent antenna element subarrays.

[0065] In some embodiments, the method includes receiving a Layer 1 beamforming frequency domain IQ data packet and a plurality of Layer 2 beamforming frequency domain IQ data packets in a transceiver integrated circuit (IC) subarray, the receiving further including, for common processing, transferring the Layer 1 beamforming frequency domain IQ data packets from a first transceiver IC in the transceiver IC subarray to additional transceiver ICs in the transceiver IC subarray, and transferring only a subset of the Layer 2 beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver ICs. In some embodiments, the subset of Layer 2 beamforming frequency domain IQ data packets is identified according to the packet header. Several methods combine beamforming frequency domain IQ data from Layer 1 beamforming frequency domain IQ data packets with beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet, by concatenating the beamforming frequency domain IQ data from Layer 1 beamforming frequency domain IQ data packets with the beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet, before frequency-time domain conversion. In some examples, this combination of beamforming frequency domain IQ data from Layer 1 beamforming frequency domain IQ data packets with beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet is performed by forming a weighted sum of the beamforming frequency domain IQ data from Layer 1 beamforming frequency domain IQ data packets and beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet, before frequency-time domain conversion. The weighted sum can be calculated according to the beamforming weights received from the beamformer.

[0066] In a further embodiment, the combination of beamforming frequency domain IQ data from a first-layer beamforming frequency domain IQ data packet with beamforming frequency domain IQ data from a selected second-layer beamforming frequency domain IQ data packet is performed in the time domain by converting the beamforming frequency domain IQ data from the first-layer beamforming frequency domain IQ data packet into a first-layer beamforming time domain signal, converting the beamforming frequency domain IQ data from a selected second-layer beamforming frequency domain IQ data packet into a second-layer beamforming time domain signal, and adding the first-layer beamforming time domain signal and the second-layer beamforming time domain signal.

[0067] The Layer 1 beamforming frequency domain IQ data packets and one of the selected Layer 2 beamforming frequency domain IQ data packets may be associated with different component carriers. This method may include queuing data packets according to the intended transceiver IC location such that the Layer 2 beamforming frequency domain IQ data packets are received for processing by the last transceiver IC in the transceiver IC subarray before the Layer 2 beamforming frequency domain IQ data packets are received for processing by the first transceiver IC in the transceiver IC subarray.

[0068] In some alternative embodiments, as described above, the multilayer (transmit) beamforming method may include receiving first-layer beamforming time domain IQ data packets and a plurality of second-layer beamforming time domain IQ data packets in a transceiver integrated circuit (IC) subarray, and further include, for common processing, transferring the first-layer beamforming time domain IQ data packets from a first transceiver IC in the transceiver IC subarray to additional transceiver ICs in the transceiver IC subarray, and transferring only a subset of the second-layer beamforming time domain IQ data packets from the plurality of second-layer beamforming time domain IQ data packets to the additional transceiver ICs. In some embodiments, the subset of second-layer beamforming time domain IQ data packets is identified according to the packet header. Several alternative methods allow beamforming time domain IQ data from Layer 1 beamforming time domain IQ data packets to be directly combined in the time domain with beamforming time domain IQ data from selected Layer 2 beamforming time domain IQ data packets, for example, by adding the beamforming time domain IQ data from Layer 1 beamforming time domain IQ data packets to beamforming time domain IQ data from selected Layer 2 beamforming time domain IQ data packets.

[0069] Some exemplary embodiments of the apparatus include a beamformer processor configured to generate a first-layer beamforming frequency domain IQ data packet and a plurality of second-layer beamforming frequency domain IQ data packets; a transceiver integrated circuit (IC) subarray having a plurality of interconnected transceiver ICs connected to the beamformer processor and interconnected via a plurality of serial data connections; each transceiver IC in the transceiver IC subarray being a digital signal processor (DSP) configured to form a multilayer beamforming frequency domain IQ dataset and generate discrete-time domain signals from the multilayer beamforming frequency domain IQ dataset; a radio frequency modulator configured to generate modulated radio frequency (RF) signals from the discrete-time domain signals; and an antenna element subarray connected to the transceiver IC subarray, configured to transmit multilayer beamforming signals by transmitting their respective modulated RF signals from the transceiver ICs of the transceiver IC subarray. The transceiver IC subarray may include a first transceiver IC having a packet header processor configured to forward first-layer beamforming frequency domain IQ data packets from the first transceiver IC to additional transceiver ICs of the transceiver IC subarray for common processing, and to forward only a subset of second-layer beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver ICs. The packet header processor may be configured to identify the subset of second-layer beamforming frequency domain IQ data packets according to the packet header.

[0070] The DSP may be configured to combine the beamforming frequency domain IQ data from the Layer 1 beamforming frequency domain IQ data packets with the beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet by concatenating the beamforming frequency domain IQ data from the Layer 1 beamforming frequency domain IQ data packets with the beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet before frequency-time domain conversion. The DSP may also be configured to combine the beamforming frequency domain IQ data from the Layer 1 beamforming frequency domain IQ data packets with the beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet by forming a weighted sum of the beamforming frequency domain IQ data from the Layer 1 beamforming frequency domain IQ data packets and the beamforming frequency domain IQ data from a selected Layer 2 beamforming frequency domain IQ data packet before frequency-time domain conversion. The DSP may be configured to calculate a weighted sum according to the beamforming weights received from the beamformer processor.

[0071] In some embodiments, the DSP is configured to convert beamforming frequency domain IQ data from a first-layer beamforming frequency domain IQ data packet into a first-layer beamforming time domain signal, convert beamforming frequency domain IQ data from one of the second-layer beamforming frequency domain IQ data packets into a second-layer beamforming time domain signal, and then add the first-layer beamforming time domain signal and the second-layer beamforming time domain signal together.

[0072] The device may include a packet header processor configured to identify a separate component carrier associated with a Layer 1 beamforming frequency domain IQ data packet and a selected Layer 2 beamforming frequency domain IQ data packet. The beamformer processor may be configured to transmit a Layer 2 beamforming frequency domain IQ data packet for processing by the last transceiver IC in a transceiver IC subarray before transmitting the Layer 2 beamforming frequency domain IQ data packet for processing by the first transceiver IC in the transceiver IC subarray. The device may also include a plurality of transceiver IC subarrays and a plurality of corresponding adjacent antenna element subarrays configured to transmit multilayer beamforming signals.

[0073] Some alternative embodiments of the apparatus include a beamformer processor configured to generate first-layer beamforming time-domain IQ data packets and a plurality of second-layer beamforming time-domain IQ data packets; a transceiver integrated circuit (IC) subarray having a plurality of interconnected transceiver ICs connected to the beamformer processor and interconnected via a plurality of serial data connections; and each transceiver IC in the transceiver IC subarray, which includes a digital front-end signal processing circuit configured to form a multilayer beamforming time-domain IQ dataset and generate discrete-time domain signals from separate first-layer beamforming time-domain IQ datasets and second-layer beamforming time-domain IQ datasets. The first-layer time-domain IQ data and the second-layer time-domain IQ data may have different sampling rates, and the digital front-end circuit may interpolate each of the first-layer time-domain IQ data and the second-layer time-domain IQ data to a common sample rate before summarily combining the discrete-time signals. Some embodiments include a radio frequency modulator configured to generate a radio frequency (RF) signal modulated from a discrete-time domain signal, and an antenna element subarray connected to a transceiver IC subarray, configured to transmit a multilayer beamforming signal by transmitting the respective modulated RF signals from the transceiver ICs of the transceiver IC subarray. The transceiver IC subarray may include a first transceiver IC having a packet header processor configured to transfer first-layer beamforming time domain IQ data packets from the first transceiver IC to additional transceiver ICs of the transceiver IC subarray for common processing, and to transfer only a subset of second-layer beamforming time domain IQ data packets from the first transceiver IC to the additional transceiver ICs. The packet header processor may be configured to identify the subset of second-layer beamforming time domain IQ data packets according to the packet header.

[0074] Several embodiments may utilize a full-dimensional beamforming data stream within a serially connected transceiver array. In these embodiments, each signal port has a unique signal for complete control across the beamforming phase. Thus, unique packets addressed to each transceiver in the subarray (via a combination of one or more field IDs or a combination of sets of IDs) are transmitted to each transceiver IC subarray. The packets may be time-ordered to adapt to latency, with IQ packets addressed to transceiver ICs at the ends of the serially linked chain of transceiver ICs being transmitted first, and therefore they being received at the ends of the array. Thus, the packets may be ordered in a round-robin manner, where a first packet is transmitted to each transceiver IC, and then additional packets are transmitted to each transceiver IC, so that processing can begin at each IC.

[0075] Each transceiver has a serial link and a packet header analyzer circuit for performing header checks, and each stream to each subarray contains a separate data packet with unique digital beamforming data addressed to the individual transceiver in the set of serially connected transceivers. The packet header analyzer in each transceiver Serdes can make per-packet forwarding decisions. In one configuration, packet bandwidth is equally allocated between the two signal paths of each transceiver IC, such as packets for two signal ports (H and V).

[0076] When receiving signals within serially linked transceiver ICs in a subarray, the serial data rate between ICs is limited, and therefore subarray beamforming may involve coupling the received IQ data before transmitting it to and returning it to the beamformer. In some embodiments, coupling weights are provided to the transceivers in a given subarray, and therefore the transceivers adjust their phase as part of the receive coupling. Electron tilt is one such situation.

[0077] Figure 4 shows an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology from a DL / UL beamformer 400 to each group of serially connected transceiver ICs (for example, one such transceiver IC subarray is a set of transceiver ICs connected via serial links 418 and 420). In this embodiment, the beamformer 400 has high-speed serial data connections (e.g., 402) (and connections to 422, 424, and 426) to intermediate Serdes MUX devices 404, each of which then provides a separate serial data connection (e.g., a set of links 406). The separate serial connections from each Serdes MUX may utilize lower data rates for connections to each subset of transceiver IC subarrays 421a, 421b, 421c, and 421d. In the embodiment of Figure 4, the subset of transceiver IC subarray 421a includes eight transceiver IC subarrays, each subarray having three transceiver ICs connected to the corresponding antenna element. Please note that the remaining sets of transceiver IC subarrays 421b, 421c, and 421d are shown in a simplified form for clarity (including connectivity to the simplified set of antenna element subarrays).

[0078] The transceiver IC subarray in Figure 4 also consists of a time-division duplex (TDD) configuration with an SPDT (single-pole double-throw) switch 412. The received signal can be filtered through a filter 410 and amplified by a low-noise amplifier (LNA) 408. Also shown are signal couplers, e.g., 414, 416, which provide a signal copy (typically at much lower power) of the transmitted RF signal to a monitoring or observation transceiver 428 via a calibration port 430.

[0079] Figure 5 shows an embodiment of a synchronization and clock distribution circuit 500 for use with transceiver ICs distributed across an active antenna array assembly. More specifically, some embodiments include a method comprising receiving a clock signal and at least one synchronization pulse signal at each transceiver IC in a plurality of transceiver IC subarrays, each transceiver IC subarray comprising a respective set of serially connected transceiver ICs. The method further includes, at each transceiver IC, (i) synchronizing the transceiver IC with the other transceiver ICs in the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal; (ii) generating a carrier frequency signal using a phase-locked loop (PLL) circuit including the DSM circuit; and (iii) using the generated carrier frequency signal to process frequency-domain in-phase and quadrature (IQ) data.

[0080] Furthermore, some embodiments include a plurality of transceiver IC subarrays, each of which includes a set of serially connected transceiver ICs; a beamformer processor coupled to the plurality of transceiver IC subarrays, configured to generate at least one synchronization pulse signal and provide at least one synchronization pulse signal to each transceiver IC; and a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, each of which outputs a plurality of clock signals and provides each transceiver IC with its respective clock signal. The apparatus includes a plurality of clock buffer circuits configured to provide, each transceiver IC (i) receive its own clock signal and at least one synchronization pulse signal, (ii) synchronize the transceiver IC with other transceiver ICs in each set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state according to the received at least one synchronization pulse signal, (ii) generate a carrier frequency signal using a phase-locked loop (PLL) circuit including a delta-sigma modulator (DSM) circuit, and (iv) use the generated carrier frequency signal to process frequency domain IQ data.

[0081] Referring again to Figure 5, within the beamformer processor circuit 502, the data interface circuit 506 may be used to generate a clock signal from the clock and data recovery (CDR) circuit 508, which is then supplied to a dual PLL clock circuit 512 that provides clock signals 522, 524 for use by the beamformer processor 502, which may then generate further clock signals on line 526. The distribution of the clock signal to the transceiver IC (e.g., one such transceiver IC 540 is depicted in Figure 5) via the clock line 538 is provided by a clock buffer 536 that receives input from a clock distribution circuit 534 driven by PLL2 532, PLL1, 530 based on a selection from MUX 528, in conjunction with a system reference clock. Thus, in some embodiments, the clock distribution circuit 534 is driven by the clock signal (on line 526) from the beamformer processor 502 and the system reference clock.

[0082] In some embodiments, the distributed clock signal is a high-frequency signal within the frequency range of 50 MHz to 150 MHz. Furthermore, in some embodiments, the clock buffer clock circuit 536 is configured to adjust the clock signal timing at the output of each clock buffer circuit so that each clock signal is received substantially simultaneously by each transceiver IC. For example, in one exemplary embodiment, the clock buffer circuit 536 is programmable and configurable to correspond to the signal transmission latency associated with the clock signal path by adjusting the clock signal timing at each output so that the clock signal (specifically, the rising edge transitions and / or falling edge transitions of the clock signal) arrives at each transceiver IC with low relative skew. In this regard, low skew means substantially simultaneous arrival with arrival time distributions in the range of less than 1 or 2 nanoseconds relative to each other. In some embodiments, low skew refers to less than 333 picoseconds (1 / 3 nanosecond). In this regard, the clock buffer 536 may be adjusted according to a calibration procedure.

[0083] In some embodiments, in addition to receiving a substantially synchronized clock signal, the transceiver ICs (e.g., transceiver IC 540) are also synchronized with each other at a macro-timing level by at least one additional synchronization pulse signal for one or more purposes. In particular, the transceiver ICs may be interconnected within a transceiver IC subarray via an asynchronous serial data bus and also have one or more subsystems that are directly or indirectly interconnected with a beamformer processor 502, as described herein, and can benefit from further synchronization. In some embodiments, as shown in Figure 5, such a synchronization pulse signal (indicated as a "SYNC" pulse signal) is generated by the beamformer processor 502 and provided to each transceiver IC for further synchronization.

[0084] In some embodiments, as commonly shown in Figure 5, the synchronization pulse signals ("SYNC" pulses) generated by the beamformer processor 502 may be processed through an additional buffer tree network 527 so that each synchronization pulse signal, like the clock signal, is received by each transceiver IC substantially simultaneously. More specifically, in some embodiments, several transceiver ICs grouped into a transceiver IC subarray may be distributed at different locations across the antenna panel. Similar to the clock distribution described above, each synchronization pulse signal may have different signal transmission latencies associated with different physical signal paths to individual transceiver ICs that may be distributed across the antenna panel. For example, depending on the physical location of a given transceiver IC on the panel, a longer signal path for the SYNC pulse may suffer greater signal degradation than a shorter signal path.

[0085] In some embodiments, the buffer tree network 527 may be configured to distribute the synchronization pulse signal in a tree-like manner by synchronously branching the SYNC pulse to different panel regions. For example, in such a network, a primary buffer circuit may provide a given number of outputs that drive a corresponding number of at least secondary buffer circuits, which are distributed across different regions of the panel and provide the synchronization pulse signal to transceiver ICs located in each of those regions. In some embodiments, the timing of the output signals from the primary buffer circuit may be adjusted as appropriate (e.g., delayed) so that the distributed secondary buffers receive the synchronization pulse signal substantially simultaneously. Each secondary buffer circuit can then provide several distinct outputs to drive a corresponding number of transceiver ICs in each region of the panel, and the output signal timing (e.g., signal delay) can be adjusted so that each synchronization pulse signal is received by each transceiver IC for substantially the same amount of time / simultaneously.

[0086] In one exemplary embodiment, the buffer tree network 527 may be implemented by a signal distribution chip / IC, which may be programmable through appropriate calibration procedures for adjusting the timing of the synchronization pulse signals so that the SYNC pulses actually arrive at each transceiver IC substantially simultaneously. In this regard, such a distribution chip may be configured, for example, to selectively delay the buffered signal output to accommodate the signal transmission latency associated with different signal paths of the SYNC pulse.

[0087] In one embodiment, each of the transceiver ICs physically distributed across the antenna array assembly is configured to independently process a low-skew dispersion (e.g., high frequency) clock signal and, in response, generate a carrier frequency signal for processing the transmit and receive modulated RF signals. Thus, the voltage-controlled oscillators (VCOs) of each transceiver IC used to modulate the transmit signal and generate the carrier phase for mixing / downconverting the received RF signal are closely matched across the transceiver IC subarrays distributed across the antenna array assembly.

[0088] In some embodiments, the transceiver IC VCO used herein utilizes a VCO tuning loop comprising a delta-sigma modulator (DSM) 544, a multiplexer divider (MMD) 546, a phase / frequency detector (PFD) 548, a loop filter 550, a VCO 552, and a phase-locked loop (PLL) circuit including the divider 554. The fractional divider in the VCO tuning loop functions to adjust the frequency divider coefficient (i.e., the division ratio) used by the MMD 546. The MMD 546 utilizes a sequence of divisors obtained from the DSM 544.

[0089] In this regard, as described above, some embodiments described herein include a method that (in particular) synchronizes a transceiver IC with other transceiver ICs in each set of serially connected transceiver ICs (in each transceiver subarray) by resetting the DSM circuit to a predetermined state in accordance with at least one received synchronization pulse signal, and generates a carrier frequency signal using a PLL circuit including the DSM circuit.

[0090] Furthermore, in one embodiment, each transceiver IC is configured to (i) set the division ratio of the MMD using the DSM circuit to generate a carrier frequency signal, and (ii) provide the divided frequency signal from the MMD to the PFD for comparison with a clock signal to further adjust the division ratio of the MMD. In a further embodiment, the DSM circuit includes a plurality of accumulators, and each transceiver IC is further configured to set the plurality of accumulators of the DSM circuit according to the received at least one sync pulse signal to reset the DSM circuit to a predetermined state according to the received at least one sync pulse signal.

[0091] As a general principle, the various embodiments described herein utilize DSM circuits (such as the DSM544) to enhance the frequency resolution of the carrier frequency signals generated by each transceiver IC for processing transmit and receive modulated RF signals. In this regard, in some embodiments, the DSM circuit is configured to use a time-varying sequence that represents a fractional input portion in combination with a fixed integer input portion to obtain a relatively high-resolution carrier frequency. In one example, by using a DSM circuit in a PLL circuit, the VCO frequency resolution can be made as fine as 114 Hz. The operation of the DSM circuit is described in more detail below.

[0092] As shown in Figure 5, the DSM544 may include a fractional input (FRAC IP) block 572, a DSM accumulator (DSM ACC) 574, a fractional output (FRAC OP) block 576, and an adder circuit 578. During operation, the FRAC IP receives input 570 containing a digital fractional input value and generates the corresponding fractional input portion which is input to the DSM ACC 574. As further shown, the DSM accumulator 574 and FRAC OP 576 form a loop. In general, in this loop, the fractional input portion passed to the DSM accumulator 574 for the current time is also referenced back to the DSM accumulator from the FRAC OP 576. Here, the current fractional output is subtracted from the current fractional input portion value stored in the accumulator 574. Although not explicitly shown in Figure 5, in an exemplary embodiment, the DSM ACC574 includes multiple accumulators, each of which can (i) receive a previously stored version of its accumulated power, (ii) subtract the current fractional output using feedback from the FRAC OP576, and (iii) pass the result to a subsequent accumulator.

[0093] As a result of the operations described above, the entire fractional output generated by the FRAC OP576 is provided to the adder 578. The adder 578 then sums (adds) the fractional output portion with the actual integer input portion 580 to generate a desired divisor value, which is provided as input to the MMD546. In some embodiments, the output of the DSM544 is in the form of a divisor control word (e.g., a set of data bits) that sets which divisor to use in the MMD546. Due to the time-varying characteristics of the fractional input portion, the control word also changes over time. However, on average, the desired ratio can be achieved over a given operating interval.

[0094] As described above, in one embodiment, transceiver IC 540 is synchronized with other transceiver ICs in its respective transceiver IC subarray by resetting the DSM circuit (such as DSM 544) to a predetermined state according to at least one received synchronization pulse signal. In this regard, as further shown in the example of Figure 5, transceiver 540 is configured to receive such a synchronization pulse signal (here, a “SYNC” pulse signal from beamformer processor 502), and the synchronization pulse signal is provided to DSM ACC 574 to set up multiple accumulators of DSM ACC 574 according to the synchronization pulse signal.

[0095] In some embodiments, the reset provided by the synchronization pulse signal is a one-time event performed, for example, during startup. Transceiver IC synchronization can then be automatically achieved due to a globally shared high-speed clock distributed to each transceiver IC (as described above).

[0096] During normal operation, the MMD546 utilizes a sequence of divisors obtained from the DSM544. In this way, the sequence of divisors used to divide the VCO frequency from the VCO552 (or an already divided signal supplied by a frequency divider such as the frequency divider 554) is the same across all transceiver ICs. Therefore, in some embodiments, the MMD546 is configured to utilize a sequence of divisors provided by the DSM544, and the sequence of divisors is synchronized across all transceiver ICs according to a synchronization pulse signal.

[0097] As further shown in Figure 5, the divided frequency signal from the MMD546 is provided to the PFD548 for comparison with the high-frequency distributed clock signal from the clock buffer 536. The PFD548 generates a phase error signal, which is then filtered by a loop filter 550 having a transfer function H(z). The filtered phase error signal is then supplied to the VCO552 to correct the phase error. Synchronization of the VCO phase error measurement circuit, such as the DSM544 divisor sequence, across the transceiver ICs provides a reduction in carrier frequency jitter used for transmit and receive signal processing between the transceiver ICs.

[0098] Furthermore, as shown in Figure 5, the output carrier frequency signal from the frequency divider 554 may be supplied to a digital delay line (DDL) 556. In some embodiments, the DDL 556 is configured to generate a carrier frequency signal having multiple phases at output 558. As an example, in one embodiment, the multiple phases may include at least four phases of 0, 45, 90, and 135 degrees, and the carrier frequency is in the range of 3.6 GHz to 4 GHz. As will be described in more detail below, the generated carrier phases (and, for example, their inversions) may be used by a multiphase digital power amplifier for RF modulation. More specifically, in some embodiments, a discrete-time domain signal representing DL (downlink) frequency domain IQ data may be modulated on the generated carrier frequency signal using a multiphase DPA, which uses a selected phase of the generated carrier frequency signal for RF modulation. The phase may be selected according to the discrete-time domain signal.

[0099] In another embodiment, the transmit and receive signal processing circuits within the transceiver IC may use a numerically controlled oscillator (NCO), such as the NCO542 shown in Figure 5. The NCO may be used to provide frequency shifting (conversion) via time-domain complex multiplication, as described herein with respect to Figures 13A and 13B.

[0100] NCOs can also utilize components that benefit from synchronization via a SYNC pulse signal. In some embodiments, the NCO utilizes a phase accumulator that is incremented by a frequency control word (FCW) at each clock interval. If various NCOs in different transceiver ICs have different phase accumulator values, this can introduce a phase offset in transmit and receive signal processing. Synchronizing the NCO phase accumulator circuits across transceiver ICs provides a reduction in the phase offset in transmit and receive signal processing between transceiver ICs.

[0101] Referring again to the example in Figure 5, the NCO542 includes an FCW register 562, a phase accumulator (PACC) 564, and a phase-amplitude converter (PAC) 566. As shown in Figure 5, the FCW register 562 can receive an FCW input 560 (e.g., from a DSP) and, in response, generate an FCW to be loaded into the PACC 564 at each clock interval. Generally, the FCW is a series of data bits representing a phase increment value. In some embodiments, the FCW register 562 is configured to use the FCW to generate the corresponding phase increment (e.g., via a lookup table). In some embodiments, the PACC 564 is configured to add the corresponding phase increment to its internal memory register. Thus, the phase value accumulated by the PACC 564 through a stepwise phase increment is a binary representation of an angle that starts at 0 degrees, ramps up to 360 degrees, wraps around back to 0 degrees, and starts all again at the next cycle (clock interval). Next, the output phase value of PACC564 is passed to PAC566 to be converted into a complex sine wave output by NCO542. PAC566 is configured to convert the accumulated phase value from PACC564 into dual outputs of sine and cosine functions of the angle corresponding to that phase value, representing the real and imaginary components that form the complex sine wave in NCO output 568.

[0102] Furthermore, in some embodiments, the NCO542 receives a synchronization pulse signal and resets itself according to that synchronization pulse signal. This can synchronize the NCO phase accumulator circuits across the transceiver ICs, as described above. More specifically, in some embodiments, the NCO's phase accumulator is reset according to the received synchronization pulse signal. As shown in the example in Figure 5, the SYNC pulse signal is provided to the PACC564 of the NCO542 to reset the PACC564. The advantage of having such phase accumulation remaining in each transceiver IC is that all transceiver ICs distributed across the active antenna array assembly can begin accumulating phase values ​​at 0 degrees.

[0103] It should be noted that in some embodiments (as described in relation to the operation of the DSM circuit), the synchronization pulse signal reset is provided as a one-time event performed, for example, at some point during startup. Transceiver IC synchronization can then be automatically acquired (as described above) due to a globally shared high-speed clock distributed to each transceiver IC.

[0104] Furthermore, the synchronous NCO542 may be used to provide frequency shifts (conversions) via time-domain complex multiplication, as will be described in more detail herein in relation to Figures 13A and 13B. For example, in the transmitting signal processing within the transceiver 540 (Figure 13A), the NCO542 may be configured to multiply the time-domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. On the receiving signal processing side (Figure 13B), the complex multiplication via the NCO542 can be used to shift the signal received by the transceiver IC540 to a desired baseband signal.

[0105] Furthermore, in some embodiments, the synchronized NCO542 may be used to operate on frequency domain data to impart incremental phase rotation to subcarrier intrinsic frequency domain IQ data for electron beam tilt, as described herein. Naturally, multiple instances of the NCO542 may be utilized for various signal processing functions, as described herein.

[0106] Clock distribution is configured according to signal lines routed across panel 102, as shown in the various embodiments shown in Figure 6, to provide clock signals to the transceiver IC subarrays to reduce clock skew. As described above, in some embodiments, multiple clock buffer circuits (e.g., 536) may be configured to coordinate the clock signal timing at the output of each clock buffer circuit so that each clock signal is received substantially simultaneously by each transceiver IC. In some further embodiments, multiple transceiver IC subarrays, beamformer processors (e.g., 502), and multiple clock buffer circuits are all physically located in the same place within the antenna array assembly, and each clock buffer circuit is physically distributed across the antenna array assembly at a physical location corresponding to the physical location of one or more transceiver IC subarrays.

[0107] For illustrative purposes, in one embodiment, the clock signal distribution has a tree-like structure that symmetrically provides clock signals to each transceiver IC subarray, such as subarray 600 (which may be one or more transceiver IC subarrays). Specifically, in the illustrated embodiment, a given branch clock signal from clock buffer 610 is carried to clock signal conductor 606, which is divided and provides clocking signals on lines 602, 608, which in turn drive a further set of clock buffers (e.g., buffer 604 driven by line 602), and then provided to a transceiver IC subarray, e.g., 600. In one embodiment, four clock buffers at the level of 610 may be provided by a clock distribution circuit 534. Furthermore, each clock buffer 536 is physically distributed across the antenna array assembly to serve transceiver IC subarrays that are similarly physically distributed across the antenna array assembly. In the illustrated embodiment, each clock buffer can provide eight distinct clock outputs to eight distinct transceiver ICs. In the embodiment shown in Figure 6, one clock buffer circuit is shown as clock buffers 603 and 604, which, as illustrated, supply clock signals to the four transceiver ICs in block 600 and the four transceiver ICs below them.

[0108] Figure 7 is a system block diagram of a distributed unit (DU) 702 having a baseband transmit unit 706, a precoding unit 710 (receiving scheduler input 708), a channel estimation unit 714, and a baseband receive unit 716. The DU 702 includes an ORAN interface 712 for connecting to a radio unit (RU) 704 via a fronthaul data interface that carries control information (C plane 718), management information (M plane 720), and user data (U plane 722). The hierarchical beamformer architecture 722 within the radio unit 704 is also shown. The hierarchical beamformer 722 includes a main (primary) beamformer processor 724 (or abbreviated as "main beamformer 724") and secondary beamformer processors BF#1(728), BF#2(734), BF#3(736), and BF#4(738) (or abbreviated as "second-layer beamformers") connected by a serial data link (e.g., link 726 from the main beamformer 724 to BF#1). In one embodiment of the hierarchical beamformer architecture 722, the main beamformer 724 calculates the complete beamforming matrix (as will be described in more detail with reference to Figures 8 to 10) and distributes portions of the beamforming matrix to the second-layer beamformers (e.g., BF#1 to BF#4).

[0109] Furthermore, the main beamformer 724 also communicates the associated layer of user data to each second-layer beamformer. As described above, the beamforming processor in the radio unit may be configured to transmit and receive IQ data packets in either the time domain or the frequency domain. In some embodiments, each second-layer beamformer may receive the associated layer of user data from the main beamformer 724 in the form of frequency domain IQ data and then compute a signal port-specific aggregated frequency domain IQ data packet for the transceiver IC (or transceiver IC subarray) that they serve. In alternative embodiments, each second-layer beamformer may similarly receive the associated layer of user data from the main beamformer 724 via its respective serial data link 726 in the form of frequency domain IQ data, but instead first convert its frequency domain IQ data to time domain IQ data and then compute a signal port-specific aggregated IQ data packet (in this case containing time domain data instead) for the transceiver IC (or transceiver IC subarray) that they serve. In this regard, each of the second-layer beamformers 728, 834, 736, and 738 consists of an appropriate iFFT process (e.g., a digital signal processor (DSP) consisting of appropriate programming instructions for executing an algorithm for IFFT operations) to convert frequency-domain IQ data into time-domain IQ data.

[0110] In the embodiment shown in Figure 7, RU704 is shown having a beamformer connection to transceiver IC730, where the transceiver IC element may be an individual transceiver IC having two or four signal ports for driving antenna element 732, or a transceiver IC subarray of serially connected transceiver ICs according to the various embodiments described herein. The Serdes mux device (e.g., 404) in Figure 4 may also implement a partial BF processor 728 of a hierarchical beamformer apparatus.

[0111] As described above, some embodiments, such as those shown in Figure 7, include a hierarchical beamformer apparatus having a main (primary) beamforming processor 724 and a set of secondary beamformer processors 728, 734, 736, 738. In these embodiments, the primary beam processor allocates beamforming coupling weights (in combination with precoder coupling weights as necessary) to form a complete beamforming matrix (as described in more detail with respect to Figure 8), and then distributes portions of the beamforming matrix to the respective secondary beamformer processors. More specifically, in some embodiments, the transceiver IC subarrays may be partitioned according to their physical location on a panel (e.g., 100), and each set of transceiver IC subarrays within a given partition is serviced and interconnected with a corresponding secondary beamformer processor, and the secondary beamformer processors may be distributed across the panel so as to be adjacent to or within the partitions. In some embodiments, each distributed secondary beamformer processor also receives a frequency-domain subcarrier IQ user data layer and applies its respective distributed beamforming weights to the IQ user data layer to compute fully beamforming IQ data points for distribution to its respective segmented subset of the transceiver IC subarray (where the fully beamforming IQ data points may be in either frequency-domain or time-domain format, as described above).

[0112] Embodiments of a secondary beamformer processor may include a digital signal processor circuit that executes software instructions for performing matrix multiplication operations, or may take the form of data registers interconnected with a hardware multiplier circuit that performs matrix operations. The hardware may include a hardware processor, a field-programmable gate array (FPGA), dedicated digital logic, or a combination thereof. Furthermore, in some embodiments, each secondary beamformer processor may also include a digital signal processor (DSP) configured to execute software instructions for performing iFFT operations to convert frequency-domain IQ data to time-domain IQ data (e.g., if the IQ data received from the primary beamformer processor is in the frequency domain) and for performing FFT operations to convert time-domain IQ data to frequency-domain IQ data (e.g., if the IQ data sent to the primary beamformer processor is in the time domain).

[0113] Figure 8 is a graphical representation of the downlink transmit beamforming operation. User data is represented by data layers along dimension 818, with subcarrier-specific IQ data for each such layer shown along dimension 816. In some embodiments, the user data layer along dimension 818 is a frequency domain IQ data layer (e.g., data layers distributed on each link 726 to individual secondary beamformers, as described in relation to Figure 7). Each data layer, such as layers 820, 822, etc., may actually be aggregated user data for one or more users, and different users are assigned / allocated different subsets of subcarriers represented along dimension 816. Furthermore, a given user may be assigned one or more data layers (along dimension 818), such as in the case of spatial multiplexing.

[0114] The beamformer (e.g., 202, 300, 400, 724 (first-order beamformer)) calculates beamforming weights for the set of carriers along dimension 802, for the user data layer represented by IQ data along dimension 800, and for the signal ports along dimension 804. As shown in Figure 8, according to matrix multiplication, the beamforming weights shown in the top layer of the matrix (i.e., the horizontal slice of the matrix along dimension 802 × 800) are applied to the data layer (816 × 818) to produce the top layer of beamforming IQ data (top of dimension 824) with subcarriers along dimension 826. For simplicity, it should be noted that the rows or layers along beamforming dimension 804 alternate between H-polarization and V-polarization, and as a result, for example, elements 806 and 808 contain separate signal port weights such as "H" weights and "V" weights, respectively, which are used independently to combine data layers such as layers 820 and 822, respectively. The H / V pairs of weights, indicated to be interleaved in a vertical (dimension 804) matrix column, may be associated in several operating modes, or they may be beams selected completely independently of the H and V components (i.e., signal ports). Columns of the beamforming matrix, such as column 807 or 809, may be applied to a given set of subcarriers in a corresponding given data layer according to the desired beamforming operation. Note that the beamforming matrix may also incorporate precoding matrix calculations to form a linear combination of data layers according to a desired precoding matrix. In this way, the beamformer matrix is ​​used to operate on the user data layer to generate signal port-specific IQ data.

[0115] In the embodiment shown in Figure 8, as described with respect to Figure 3, each set of beamforming IQ data points is packetized and transmitted to the corresponding transceiver IC subarray. In some embodiments, the packetized IQ data may remain in the frequency domain. However, in other embodiments, the packetized IQ data may instead be converted to time-domain IQ data. In some embodiments, the IQ data for 64 signal ports along dimension 826 includes IQ data for 32H and 32V signal ports. Each of the four sections 828, 830, 832, and 834 of the signal port-specific IQ data of 826 contains 16 beamforming IQ data packets, which can be combined via concatenation into eight separate dual signal port H / V packets similar in format to packet 302 in Figure 3. Each of these eight H / V IQ packets contains either time-domain or frequency-domain IQ data and is transmitted via a single serial data link to each transceiver IC subarray, such as one of the eight transceiver IC subarrays along the row of subarray 238a shown in Figure 2. The IQ data from sections 830, 832, and 834 are each similarly packetized into eight unique IQ data packet streams and transmitted to eight corresponding transceiver subarrays in transceiver subarray rows 238b, 238c, and 238d, respectively. In this embodiment, each dual-signal port IQ data packet may be processed in common by two serially connected transceiver ICs. Alternatively, each of the eight H / V packets obtained from section 828 may be transmitted to the respective transceiver IC subarray in the first row of transceiver IC subarray 421a in Figure 4, along with a similar distribution of dual-signal port IQ packets to rows of transceiver IC subarrays 421b, 421c, and 421d. In the embodiment of Figure 4, each beamforming IQ data packet is processed in common by three serially connected transceiver ICs.

[0116] With respect to a multilayer beamforming IQ data packet 850 representing beamforming IQ data for one embodiment of a transceiver IC subarray, the beamformer processor may be configured to generate a commonly processed IQ data packet 864 (either in a time-domain or frequency-domain format) for one signal port (e.g., representing subcarrier IQ data for all subcarriers, or a subset of subcarriers of one component carrier of the signal port) and a second commonly processed IQ data packet 866 for a second signal port (the second commonly processed IQ data packet 866 is either in a time-domain or frequency-domain format, depending on the format of the commonly processed IQ data packet 864 for the first port), for use by a transceiver IC that processes signals according to first-layer beamforming, while simultaneously generating higher-resolution beamforming for the second layer. Layer 2 beamforming is performed according to fully digital beamforming IQ packets 852, 854, and 856 for processing by individual transceiver ICs and their respective horizontal signal ports (H1, H2, and H3 shown in Figure 8), as previously described with respect to Figure 3, and fully digital beamforming IQ packets 858, 860, and 862 for processing by individual transceiver ICs and their respective vertical signal ports (V1, V2, and V3 shown in Figure 8). Furthermore, as previously described, Layer 2 beamforming IQ data packets may include subcarriers associated with the same component carrier as the IQ data packets that are processed in common, or subcarriers associated with a second component carrier.

[0117] More specifically, the first beamforming IQ data packet may include IQ data 864 (labeled Hc, where "c" indicates IQ data for common processing) and 866 (Vc) for common processing by all transceiver ICs in a given transceiver IC subarray (e.g., three separate transceiver ICs, each capable of 2T2R operation). Three additional packets of transceiver IC-specific IQ data, each containing data 852 concatenated with data 858, data 854 concatenated with data 860, and data 856 concatenated with data 862, are also transmitted to the transceiver IC subarray, where the first transceiver ICs concatenate the commonly processed data 864 with data 852 and the commonly processed data 866 with data 858. Another transceiver IC combines the commonly processed data 864 with data 854 and the commonly processed data 866 with data 860, while a third transceiver IC combines the commonly processed data 864 with data 856 and the commonly processed data 866 with data 862.

[0118] Figure 9 is a graphical representation of the conversion of user data layers 906, 916, and 918, represented by a matrix [X]900 of dimension L (i.e., the number of layers), to beamforming downlink transmit IQ data packets at logical baseband port 926'm,k=uiu, represented by a matrix [Z]904 of dimension M. In some embodiments, user data layers 906, 916, and 918 remain in frequency domain format until the data associated with them is beamformed. After the beamforming operation is complete, in some embodiments, the beamforming downlink transmit IQ data may be packetized to form frequency domain beamforming downlink transmit IQ data. However, in other embodiments, after the beamforming operation is complete, the beamformed downlink transmit frequency domain IQ data may instead be converted to the initially beamformed downlink transmit time domain IQ data, and then packetized before transmission to each transceiver IC (e.g., transceiver IC 730 as shown in Figure 7) or transceiver IC subarray (e.g., transceiver subarray 914 as shown in Figure 9). According to the simplified signal processing shown in Figure 9, data layer [X] 900, following precoding operations, receives precoding operations by matrix PM 920 to acquire logical antenna port signals 922 represented by matrix [Y] 902, and then beamforming operations by digital beamforming matrix DB 924 apply beam weights using various beamforming beam indices (e.g., "beam IDx") with weights such as "beam 1" 910, and distribute appropriately weighted precoded signals at node 908 (a precoded linear combination of data layers 906, 916, 918) across various logical baseband ports 926 represented by matrix [Z] 904 (also shown as IQ data 828, 830, 832, 834). Each beamforming packet in matrix [Z], such as IQ data packet 912, is carried to its corresponding transceiver IC subarray 914.

[0119] As described above, in some embodiments, the IQ data that has undergone precoding and beamforming operations is frequency domain IQ data that can then be packetized to generate frequency domain IQ data packets 912 that are carried to the corresponding transceiver IC subarray 914. However, in other embodiments, following the precoding and beamforming operations, the beamforming / precoded frequency domain IQ data may instead be first converted to the time domain and then packetized to generate time domain IQ data packets 912 that are carried to the corresponding transceiver IC subarray 914.

[0120] Figure 10 illustrates the transformation of the user data layer into a beamforming IQ data stream by an operation 1000 of a generalized combined precoding and beamforming matrix 1012 obtained from matrix multiplication of the precoding matrix PM920 and the beamforming matrix DB924. The user IQ data layer [X]1004 is provided by a processor 1002 that provides user IQ data processed according to standard coding, cyclic redundancy check (CRC), rate matching (RM), and resource element (RE) mapping. The data layer [X]1004 is processed according to the generalized spatial multiplexer / beamformer matrix PM in the transformation 1000 to generate logical baseband port IQ signal packets 1014 represented by the signal port IQ data matrix [Z]1006 for transmission over the respective serial data links to transceiver IC subarrays such as subarray 1008. As used herein, the terms “beamforming” and “beamforming matrix” refer to the combined beamforming / precoding operation described, whether implemented in a single matrix operation or in multiple separate matrix operations. As illustrated in relation to Figure 9, the IQ data packets (and therefore subsequent beamforming / precoding operations) carried from each logical baseband port 1014 to its corresponding transceiver IC subarray 1008 may be either time-domain IQ data packets (when converted to the time domain) or frequency-domain IQ data packets.

[0121] Figure 11 is a diagram of the received uplink signal processing, including received beamforming and layer decoding. Each transceiver IC subarray 1108 provides the received IQ data to the beamformer processor as a logical baseband port 1116 represented by matrix [Z] 1106. In some embodiments, the IQ data received by the beamformer processor may be either frequency-domain IQ data or time-domain IQ data. In embodiments where the received IQ data is in the time domain, the conversion to frequency-domain IQ data may be performed in the beamformer processor via an FFT operation (when received via the logical baseband port 1116). The virtual antenna port signal 1112 may be formed according to matrix [Y] 1104. Finally, the individual data layers 1110, represented by matrix [X] 1102, can be reconstructed.

[0122] Figure 12A shows a block diagram of an example of a single transceiver IC device architecture according to several embodiments. The transceiver IC device architecture shown in Figure 12A is also suitable for forming a group of serially connected transceivers. The transceiver IC is suitable for operation in FDD mode and TDD mode. As an example, the configuration shown in Figure 12A is connected for operation in TDD mode. Furthermore, it should be noted that the embodiment in Figure 12A illustrates a scenario in which transceiver IC 1200 receives and transmits frequency domain IQ data packets (e.g., from a beamformer processor (e.g., BFP200, 300, 400, 722, etc.) or directly to / from another transceiver IC). Transceiver IC 1200 includes multiple signal processing paths for both transmit signal processing and receive signal processing. For DL ​​transmit signal processing, transceiver IC 1200 receives frequency domain IQ data packets via serial data receiver RX#0 1202. The serial data receiver 1202 includes a data buffer for storing several deserialized data words and a data analysis circuit for performing packet header analysis to determine whether an incoming packet is intended to be processed by the current transceiver IC and / or by one or more other transceiver ICs in the transceiver IC subarray. If the packet is to be processed locally, the packet is transferred via 1206 to a DSP memory 1210 accessible to the integrated digital signal processor (DSP) 1215 via a memory storage device or direct memory access (DMA) operation, etc. In an alternative embodiment, header inspection may be performed by the DSP 1215, which places the data in the DSP memory 1210 designated for retransmission via Serdes transmitter TX#1 1262.

[0123] The DSP1215, when executed, includes programming stored in non-volatile memory that causes the DSP1215 to execute algorithm 1214 for converting frequency-domain digital IQ data into time-domain digital data. The stored algorithm instructions include processor instructions for the iFFT operation 1214 and further include instructions for extending the converted data by adding cyclic prefixes (CPs).

[0124] In the subarray beamforming described herein, each IC in a given subarray processes the same frequency-domain (or time-domain) IQ packets (referred to herein as “commonly processed” IQ data) for transmission, and generates frequency-domain (or time-domain) IQ packets during reception, which are aggregated at each transceiver IC as they traverse a cascade set of transceiver ICs on their way to the beamformer processors (e.g., secondary and primary beamformer processors as described in relation to Figure 7). Since the signal commonly processed by the transceiver ICs is an aggregated beamforming signal having components from multiple data layers and multiple individual beams, it is not possible to adjust the individual beams in a given subarray of the commonly processed IQ data packets. However, at each element in the subarray (i.e., each signal port), it is possible to apply a unique phase rotation to the aggregated beamforming signal, which has the effect of tilting the entire combined / aggregated beamforming signal. Therefore, when beam tilt is desired, the transceiver is configured to incrementally adjust the phase of each IQ data packet being processed in common, according to the position of the radiating element driven by the transceiver IC within the IC subarray. Without incremental phase adjustment at each subarray element, perhaps only one of the elements would be matched, and the wavefronts from the remaining elements would incrementally lead (or lag) with respect to a given downward (upward) tilt according to their position within the subarray, thus not achieving true tilt. In this way, beam tilt can be obtained through digital baseband signal processing without directly adjusting any signal components in the analog domain (including not adjusting the VCO phase).

[0125] More specifically, when a linear array of antenna elements is physically "tilted" (either a vertical array tilted up / down in height, or a horizontal array tilted left / right in azimuth), the result can be considered an incremental time delay of signal transmission (or reception) across the antenna elements of the array, thereby changing the direction in which the propagating wavefronts are added reinforcementally to form the main lobe (and destructively coupled to form the null). Electronic tilt is the process of imposing a suitable signal delay without actually physically rearranging the antenna. The relationship between the time delay and the corresponding phase shift of the signal depends on the tilt angle as well as the frequency of the signal. That is, a given time delay between two signals corresponds to a linear phase shift in the frequency content of the signal, and a given time delay results in a lower phase shift at lower frequencies and a linearly higher phase shift at higher frequencies within the signal. Thus, for narrowband signals, a particular time delay is almost equivalent to a particular phase shift between the delayed signals. However, for broadband signals such as OFDM signals of 50 or 100 MHz or higher, a given time delay has a different effect on the phase of the OFDM subcarriers. Nevertheless, in a phased array where each subcarrier is rotated by the same phase, this results in a nonlinear phase characteristic commonly known as beam oblique. A certain amount of beam oblique is acceptable in OFDM signals with a bandwidth of around 100 MHz.

[0126] Therefore, electron beam tilt in a physically static array can be achieved by various methods performed by the individual transceivers described herein, including (i) applying incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO), (ii) applying constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) imposing a time delay on the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. It should be noted that methods (ii) and (iii) result in a certain amount of beam oblique distortion.

[0127] In this regard, beam tilt can be implemented by applying a linearly increasing phase rotation across subcarriers by a complex multiplier 1212 implemented as a numerically controlled oscillator (NCO), as described for NCO542 in Figure 5. NCO1212 is configured to provide a sequence of complex numbers with a linearly increasing phase for multiplication by the corresponding sequence of subcarrier frequency domain IQ data points. For a desired beam tilt, the initial phase and the increment rate at which the phase increases from subcarrier to subcarrier are determined, and the values ​​are loaded into the NCO phase accumulator 564 and FCW register 562, respectively. The phase increment value can be determined according to one or more different factors, including (i) the desired beam tilt angle, (ii) the subcarrier spacing, (iii) the carrier frequency, and (iv) the position of a particular radiating element driven by the transceiver IC. In general, to achieve a beam tilt of angle φ, the phase rotation θ at position n in the array for a given subcarrier frequency 1 / λ is given by the following equation:

[0128]

number

[0129] Here, the element is the carrier wavelength λ c For a given distance d = λ c It is positioned with / 2. In the receive beam tilt operation, the NCO can be implemented in the complex multiplier 1238 after the FFT processing.

[0130] Alternatively, the complex multiplier 1212 may be configured to impose a constant phase rotation on each frequency-domain IQ data point before the transformation via the iFFT 1214 in order to implement an approximate time delay for achieving the beam tilt. For a desired beam tilt, a frequency-domain phase rotation represented by a single complex number is determined and the value is loaded into the complex multiplier 1212. The frequency-domain phase value may be determined according to one or more different factors, including (i) the desired beam tilt angle, (ii) the array position of a particular radiating element driven by the transceiver IC, and (iii) the carrier frequency. In the receive beam tilt operation, the constant phase rotation may be implemented in the complex multiplier 1238 after the FFT processing.

[0131] In some embodiments, beam tilt is implemented by applying a constant phase rotation to each sample of the baseband time-domain signal (e.g., via complex multiplication). For a desired beam tilt, a time-domain phase rotation represented by a single complex number is determined, and the value is loaded into a complex multiplier (which may also implement a gain function). Such a complex multiplier may be, for example, the complex multiplier 1306 shown in Figure 13A, which illustrates the transmit time-domain signal processing portion of the transceiver IC, as will be described in more detail below. The time-domain phase value may be determined according to one or more different factors, including (i) the desired beam tilt angle and (ii) the position of a particular radiating element driven by the transceiver IC. In receive beam tilt operation, the constant phase rotation may be implemented in the complex multiplier (while also implementing a gain function) before the FFT processing which may be performed in either the transceiver IC or the beamformer processor, for example, as described above. Such a complex multiplier could be, for example, the complex multiplier 1386 shown in Figure 13B, which represents the receive time domain signal processing portion of a transceiver, as will be explained in more detail below.

[0132] In some further embodiments, beam tilt is implemented by imposing a time delay on the discrete-time domain signal of the transmitted baseband signal (instead of phase rotation via complex multiplication as in the embodiments described above). For a desired beam tilt, a time-domain delay is determined and its value is loaded into a delay buffer 1312, which is shown in Figure 13A. The time-domain delay value may be determined according to one or more different factors, including (i) the desired beam tilt angle, (ii) the time-domain sample rate, and (iii) the position of a particular radiating element driven by the transceiver IC. In the receive beam tilt operation, the time delay may be implemented in a delay buffer 1378, shown in Figure 13B.

[0133] In further embodiments, a combination of the above methods may be used. In a particular embodiment, the electron beam tilt may consist of coarse and fine adjustments, the coarse beam tilt may be implemented by applying a phase rotation that increases linearly across subcarriers by a complex multiplier 1212 implemented as an NCO using a limited resolution or a limited number of bits, and the fine resolution may be implemented by further adjustments in the time domain, such as a time delay or a time-domain constant phase rotation.

[0134] In various embodiments of beam tilt phase adjustment, the phase rotation may be specified by a control message provided to the transceiver IC. A specific phase value may be provided, a phase index value may be included in the control message, or it may be included in the header of the IQ data packet itself. The phase index value may be used, for example, to retrieve a pre-calculated phase value from a lookup table. In some embodiments, the transceiver IC may combine coefficients to calculate a specific rotation to be applied (for example, a desired tilt angle may be given, and the transceiver IC may adjust the phase rotation according to its given position in the array and / or transceiver IC subarray). Such a phase rotation may be used to implement beam tilt phase rotation.

[0135] In some embodiments, beam tilt can be implemented using a combination of a linear phase rotation applied in the frequency domain, followed by a constant phase rotation in the time domain, or a time delay in the time domain after the iFFT transformation. In some embodiments, the frequency domain rotation can achieve a coarse tilt or an approximation of the desired beam tilt, while the time domain rotation may achieve a fine tilt. This may be particularly useful when a larger tilt angle is desired.

[0136] In further embodiments, dynamic adjustment of the tilt angle may be implemented on a per-slot basis, significantly improving the available scanning range and coverage from a panel array using subarray beamforming. In such embodiments, beam tilt information, as well as which time slots, subcarriers, or component carriers may be specified via control messages, are indicated.

[0137] In one embodiment, electron antenna beam tilt is implemented in a transceiver subarray by distributing beamforming IQ data packets to a plurality of serially connected transceiver ICs for common processing by the transceivers. The IQ data packets have individual IQ values ​​for each of the multiple subcarriers. At each transceiver IC, electron beam tilt phase rotation is applied. In some embodiments, applying beam tilt phase rotation is done by changing the phase of each IQ-modulated subcarrier based on the desired antenna tilt and array position. The phase change may be a constant phase rotation applied to all subcarriers, or it may be a linearly increasing phase rotation that increases from subcarrier to subcarrier. Phase adjustment may be specified according to one or more control messages. The control messages may be specific to a given subarray, a transceiver IC within the subarray, or an individual transceiver IC. Phase adjustment may be specified in terms of time delay, frequency-domain multiplicative rotation, or time-domain complex rotation, or equivalent data. A given transceiver IC may also calculate the final phase adjustment by combining the phase adjustment data with array position data unique to the transceiver IC.

[0138] Referring again to Figure 12A, the time-domain IQ data is stored in a DSP memory 1216 accessible by a transmit time-domain signal processing circuit 1217 (further described in relation to Figure 13A). In the embodiment of Figure 12, the circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time-domain signal processing circuits 1220, 1230, each providing baseband time-domain OFDM signals (each being a single or multi-component carrier signal) to corresponding digital power amplifier (DPA) circuits 1222, 1232.

[0139] In one embodiment, DPAs 1220, 1232 perform simultaneous RF modulation and amplification, which may be final power amplification of the RF signal. In some embodiments, the DPA provides pre-amplification of the RF signal applied to external power amplifiers driving radiating antenna elements. The external power amplifiers are distributed adjacent to each element across the active antenna panel assembly. DPAs 1220, 1232 are provided with multiple RF carrier phases arising from a system phase-locked loop (SYSPLL), which are further processed by a synchronous RF PLL 1262 driving an RF carrier generator VCO 1260. The selected RF carrier phases are used to switch amplifier cells within the DPA. As described herein, the number of activated cells that determine specific RF carrier phases and their relative magnitudes is selected according to time-domain IQ data points provided by circuits 1220, 1230.

[0140] The transceiver IC1200A also includes a received time-domain signal processing circuit 1241 (further described with reference to Figure 13B) for downconverting the analog RF signal via an IQ mixer driven by a VCO1260 to generate separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) in circuits 1244 and 1252. The sampled signal is then processed by time-domain filtering and downsampling circuits 1242 and 1250. The processed time-domain signal is then stored in DSP memory 1216 for further processing, including conversion to subcarrier intrinsic frequency-domain IQ data by CP rejection and an FFT algorithm ("FFT" 1240 in Figure 12). DSP 1215 includes programming stored in non-volatile memory that, when executed, causes DSP 1215 to execute an algorithm for converting the time-domain digital data to frequency-domain digital IQ data. Next, an NCO (e.g., 1238) can be used to apply a linearly increasing phase rotation to each frequency domain IQ (i.e., subcarrier) value, which is also an embodiment of electron beam tilt. The received IQ frequency domain data is then processed by the MUX / coupler circuit 1264 for transmission to the serial data bus via the serial transmitter TX#0 1204.

[0141] Figure 12B shows a block diagram of another example of a single transceiver IC device architecture according to several embodiments. Similar to the embodiment in Figure 12A, the transceiver IC device architecture shown in Figure 12B is also suitable for forming a group of serially connected transceivers. Similar to Figure 12A, the transceiver IC 1200B is suitable for operation in FDD mode and TDD mode. As an example, the configuration shown in Figure 12B is connected for operation in TDD mode. Furthermore, unlike the embodiment in Figure 12A, it should be noted that the alternative embodiment in Figure 12B shows a scenario in which the transceiver IC 1200B receives and transmits time-domain IQ data packets to and from a beamformer processor (e.g., directly to and from BFP 200, 300, 400, 722, etc., or to and from another transceiver IC). Each transceiver IC 1200B includes multiple signal processing paths for both transmit signal processing and receive signal processing. However, in this embodiment, the transceiver IC 1200B is configured to process IQ data entirely in the time domain without additional processing elements involving frequency-time domain conversion of IQ data (transmitter side) and frequency-time domain conversion of IQ data (receiver side), as described in relation to the transceiver IC device architecture shown in Figure 12A.

[0142] More specifically, for DL ​​transmit signal processing, the transceiver IC 1200B includes a serial data receiver RX#0 1202 configured to receive time-domain IQ data packets via the serial data receiver 1202. As shown in the transceiver IC device architecture of Figure 12A, the serial data receiver 1202 includes a suitable data buffer for storing several deserialized data words and a data analysis circuit that performs packet header analysis to determine whether the received time-domain IQ data packet is intended for processing by the current transceiver IC and / or by one or more other transceiver ICs in the transceiver IC subarray. If the packet is to be processed locally, the packet is transferred to memory 1211 via link 1206, via a memory storage device or direct memory access (DMA) operation, etc. In an alternative embodiment, header checking may be performed, for example, via a dedicated DSP element (not shown) coupled to memory 1211, which then places the data to be retransmitted via Serdes transmitter TX#1 1262 into memory 1211.

[0143] In the embodiment of Figure 12A, frequency domain IQ data packets are stored in a DSP memory 1210 accessible by a DSP 1215 configured to execute an algorithm 1214 for converting frequency domain digital IQ data to time domain digital IQ data, and it should be noted that such an algorithm includes processor instructions for the iFFT operation 1214 and further processor instructions for extending the converted data by adding a cyclic prefix (CP). Although not explicitly shown, in some embodiments, memory 1211 may be a DSP memory readable by a DSP processor (not shown) configured with appropriate programming instructions for performing the addition of CP to time domain digital IQ data. In alternative embodiments, such CP addition may instead be performed by a dedicated circuit (not shown) configured to re-read a portion of the time domain IQ data from memory 1211, so that such re-read portion acts as a CPE and can then be supplied by the dedicated circuit to a transmit time domain signal processing circuit 1217 along with the rest of the time domain IQ data.

[0144] It should be noted that adding CP to time-domain IQ data typically increases the amount of data required for subsequent time-domain baseband signal processing. Therefore, ideally, the addition of CP is performed in the digital front-end circuitry of the transceiver IC 1200B to reduce the amount of data that needs to be communicated over the serial data link between the beamformer processor and a given transceiver IC / transceiver subarray. However, in alternative embodiments, the addition of CP may instead be performed in the beamformer processor.

[0145] Referring again to Figure 12B, in some embodiments, time-domain IQ data is stored in memory 1211, which is accessible (directly or indirectly) by a transmit time-domain signal processing circuit 1217 (further described in relation to Figure 13A). As previously mentioned in relation to Figure 12A, circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time-domain signal processing circuits 1220, 1230, each providing baseband time-domain OFDM signals (each being a single or multi-component carrier signal) to corresponding digital power amplifier (DPA) circuits 1222, 1232. The operation of DPAs 1220 and 1232 is essentially the same as described in relation to the embodiment in Figure 12A and is omitted here for brevity.

[0146] Similar to transceiver IC 1200A, in some embodiments, transceiver IC 1200B also includes a received time-domain signal processing circuit 1241 (further described with reference to Figure 13B) for downconverting the analog RF signal via an IQ mixer driven by VCO 1260 to generate separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) in circuits 1244, 1252. As shown in Figure 12A, the sampled signal is then processed by time-domain filtering and downsampling circuits 1242, 1250.

[0147] In this embodiment, the processed time-domain signal may then be stored in memory 1211 for further processing. In some embodiments, the further processing may include CP removal. As described above, in some embodiments, memory 1211 may be a DSP memory readable by a DSP processor (not shown) configured with appropriate programming instructions for further performing receiver-side CP removal from time-domain digital IQ data. In alternative embodiments, such CP removal may instead be performed by a dedicated circuit (not shown) configured, for example, to reread a portion of the time-domain IQ data from memory 1211, remove the reread portion as CP, and then store the modified time-domain IQ data back in memory 1211.

[0148] As described above, in some embodiments, the transceiver IC 1200B is configured to process IQ data entirely in the time domain without additional processing elements involving frequency-time domain conversion of IQ data (transmitter side) and frequency-time domain conversion of IQ data (receiver side), as described in relation to the transceiver IC device architecture shown in Figure 12A. Therefore, at the receiver side, the processed time-domain digital data does not need to be converted to frequency-domain digital IQ data via FFT calculations, as in the embodiment of Figure 12A. Rather, the received time-domain IQ data can be processed by the MUX / coupler circuit 1264 for transmission to a serial data bus via the serial transmitter TX#0 1204, for example, for transmission to a beamformer processor. Subsequent time-frequency IQ data conversion may be performed in the beamformer processor, as previously described herein.

[0149] As previously stated, if beam tilt is desired, the transceiver IC described herein may be configured to incrementally adjust the phase of each IQ data packet processed in common according to the position of the radiating elements driven by the transceiver IC in a given IC subarray. Furthermore, electron beam tilt is a process that imposes appropriate signal delay without actually physically repositioning the antenna. As previously stated, electron beam tilt in a physically static array can be achieved by various methods performed by the individual transceivers described herein, including (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) imposing a time delay on the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. A detailed description of these various methods has been given above and will not be repeated here.

[0150] However, it should be noted that in the embodiment of Figure 12B (unlike the embodiment of Figure 12A), the transceiver IC 1200B is configured to process the IQ data entirely in the time domain. Therefore, electron beam tilt methods (or, more precisely, any other suitable frequency domain-based electron beam tilt techniques) that include applying, for example, a phase rotation (e.g., incremental or constant) to each subcarrier frequency domain IQ data point are not applicable to the transceiver IC device architecture of Figure 12B. Instead, electron beam tilt can be achieved through any suitable time domain technique, such as applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication) or imposing a time delay on the discrete time domain signal of the transmitted baseband signal, as described herein. For example, in Figure 12B, the time domain IQ data (after CP additional calculation) is passed to the transmitted time domain signal processing circuit 1217 (further described with respect to Figure 13A), where it is processed for electron beam tilt by performing complex multiplication in the time domain or by imposing a time delay.

[0151] Figure 13A is a block diagram 1300 of an example of a time-domain signal processing circuit 1217 according to several embodiments. Time-domain IQ data is received directly or indirectly from memory via line 1302 (and similarly, lines 1304, 1344, and 1346) and applied to a signal path power detector and a gain unit 1306 for adjusting the power level. As described above, the memory may be a DSP memory or a memory coupled to a dedicated circuit (for example, as in some embodiments described in relation to Figure 12B). Furthermore, in some embodiments, the gain multiplier may also include a complex phase that rotates each time-domain value by the same phase. This time-domain phase rotation may be used to apply an approximate time delay that can be used to implement electron beam tilt. This corresponds to a phase rotation of each constituent subcarrier by the same phase, rather than a linearly incremental phase rotation, but is sufficiently accurate for bandwidths of about 100 MHz within the frequency range of the bands used for LTE and 5G signals. The signal is filtered by an FIR filter stage 1308, which also includes one or more interpolation stages to increase the sample rate of the discrete-time domain signal. The discrete-time digital UL signal is then processed by a numerically controlled oscillator (NCO) 1310. The NCO (e.g., 1310) may be configured to multiply the time-domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. In some embodiments, two time-domain signals representing, for example, two component carriers may be slightly shifted up in frequency so that the frequency contents of one signal can be added together without overlapping with the frequency contents of the other signal, while another transmit signal, such as a separate component carrier provided on connection 1304, may be slightly shifted down using the corresponding NCO. The signal is further processed by a delay buffer 1312, which allows for precise time offset adjustment of the transmit signal. In some embodiments, the delay buffer 1312 is used to provide per-carrier delay adjustment.The delay buffer 1312 compensates for different processing times for different supported subcarrier spacings (SCS) and bandwidths. Assuming all filtering is performed using FIR filters for all carriers, the adjustable delay per carrier is the difference between the largest and smallest delays, which is approximately 10 μs. However, sharing this function with windowing relaxes this requirement.

[0152] Other discrete-time domain signals on lines 1304, 1344, and 1346 are processed similarly to the discrete-time domain signal on line 1302. In some embodiments, the discrete-time domain signals on lines 1302, 1304, 1344, and 1346 arise from frequency-domain to time-domain conversion from DSP 1215, as described in more detail in relation to Figure 12A. In other embodiments, the discrete-time domain signals on lines 1302, 1304, 1344, and 1346 arise from received time-domain IQ data by the transceiver IC, as described in more detail in relation to Figure 12B. Each of these signals may then be coupled and / or routed to transmit signal processing circuits 1316, 1348 via MUX / ADD circuit 1314 for crest factor reduction (e.g., CFR 1318), further FIR filtering (including further upsampling / interpolation), and IQ multiplication (e.g., FIR IQ circuit 1322) to perform phase adjustment and / or correction. Each signal may also undergo digital pre-distortion (DPD, e.g., DPD circuit 1324) to correct for phase and amplitude distortion present in modulator / amplifier DPA 1328a, 1328b to signal port 1350 (and to DPA 1328c, 1328d) from RF signal adder 1340. Each section 1328a to 1328d of each DPA (for example, DPAs 1222 and 1232 as shown in Figures 12A to 12B) includes a clock domain crossing circuit 1330, a cascaded integrator comb (CIC) filter 1332, a mapper circuit 1334, a delay circuit 1336, and a final DPA stage 1338.

[0153] Figure 13B shows an example of a received time-domain signal processing circuit 1241 according to several embodiments. Digital samples from the ADC are received by a clock-domain crossing circuit 1362 and adjusted for DC offset by a DC offset circuit 1364. An IQ multiplier 1366 may be used to provide automatic gain control of the baseband time-domain signal in response to power measured by a power detector PD 1368. A quadrature error compensation circuit (QEC 1370) provides compensation for frequency-dependent quadrature errors in the RX analog front end. In one embodiment, the QEC circuit 1370 divides the time-domain signal (e.g., having a sample rate of 245.76 MHz) into 16 frequency bins, each of 15.36 MHz. Each frequency bin is added to the contents of a Miller frequency bin shaped by a complex multiplier. A notch filter 1372 may be used to reduce any undesirable out-of-band signals.

[0154] The MUX1374 can be configured to selectively direct received signal samples from either path RX0 (1360) or RX1 (1394) to one or all of the RX signal paths 1376, 1392, 1396, or 1398. Some examples of different possibilities are all four RX signal paths from RX0, all four RX signal paths from RX1, RX signal paths 1376 and 1392 from RX0, RX signal paths 1396 and 1398 from RX1, RX signal path 1376 from RX0, and RX signal paths 1392, 1396, and 1398 from RX1. Each RX signal path includes a delay buffer (e.g., 1378), an NCO (e.g., 1380), an FIR filter and downsampler (e.g., 1384, 1382), and a power detector (e.g., PD1390). It should be noted that a gain multiplier (e.g., 1386) may also implement a constant phase rotation for the time-domain signal. In such embodiments, this is equivalent to a constant phase shift applied to each subcarrier rather than a linearly increasing phase shift across subcarriers, but still provides a good approximation of the time delay for the purpose of implementing electron beam tilt. FIR1382 may also include a notch filter for removing component carriers not processed by a given signal path. In some embodiments, NCO1380 may be used to apply a time-domain frequency shift that moves the desired component carriers into the low-pass passband of the notch filter 1382.

[0155] Figure 14 shows a generalized configuration of exemplary signal processing via the transceiver IC devices of Figures 12A-12B and 13A-13B for dual-carrier, dual-polarization communication signals, according to several embodiments. More specifically, the example signal processing configuration shown in Figure 14 may be applicable to embodiments involving the communication of data packets associated with two different carriers (e.g., two component carriers), each carrier signal having two polarizations (e.g., horizontal and vertical polarization as previously described herein). In the exemplary embodiment, the transceiver device is a transceiver IC. Furthermore, in the exemplary configuration of Figure 14, the transceiver IC operates in TDD mode within an OFDM-modulated wireless network such as an LTE or 5G-based communication system.

[0156] As shown in Figure 14, the transceiver device (IC) 1400 includes a first serial communication port 1406 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 0" in Figure 14) and a second serial communication port 1434 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 1" in Figure 14). However, it should be noted that although the transceiver IC is shown having two separate serial communication ports (1406 and 1434), in the exemplary embodiment of Figure 14 only one of ports 1406 and 1434 is used. More specifically, as shown, only serial communication port 1406 is connected to serial data links 1402 and 1404 to communicate data to and from the transceiver IC, and serial communication port 1434 is not actively used. However, in some embodiments, the transceiver IC may be further serially connected to a second transceiver IC via port 1434 (see, for example, various embodiments described herein (see, for example, Figures 2 to 4)).

[0157] Generally, as previously described, a transceiver IC may be configured to handle four distinct transmit component carriers and four distinct receive component carriers. The transceiver IC consists of at least two distinct transmit signal port paths (chains) and at least two distinct receive signal port paths (chains) and is typically associated with two corresponding antenna radiating elements, but other configurations are possible as described herein. Also, generally, a transceiver IC may include a number of signal processing elements, such as an integrated digital signal processor (DSP) for converting time-domain digital data to and from frequency-domain digital data (via several iFFTs and FFTs) and for adding and removing cyclic prefixes (in embodiments where the IQ data packets received / transmitted by the transceiver IC are in the frequency domain), multiple integrated modulated digital power amplifiers (DPAs) for converting digital baseband time-domain signals to amplified analog RF signals, analog RF downconverters, and analog-to-digital converters.

[0158] Referring to Figure 14, in some embodiments, the serial communication port 1406 can receive data packet streams for DL ​​(downlink) transmission (e.g., four multiplexed data packet streams) (e.g., from a beamformer processor) via the serial data link 1402, and the packets include packets for a first component carrier (hereinafter, "carrier C1") and IQ data packets for a second different component carrier (hereinafter, "carrier C2"), each for horizontal (H) polarization and vertical (V) polarization. For brevity, in this specification, the combinations of two different component carriers and horizontal and vertical polarization are denoted as "C1H", "C2H", "C1V", and "C2V", respectively. In the UL (uplink) direction, serial communication port 1406 can receive IQ data packet streams (e.g., four multiplexed sets of IQ data for four sets of OFDM subcarriers) for each of the two carriers C1 and C2, and for each of the two H-polarizations and V-polarizations, and transmit them (e.g., to a beamformer processor) via serial data link 1404.

[0159] It should be noted that the exemplary transceiver IC configuration shown in Figure 14 assumes that data packets received or transmitted on serial port communication port 1406 include frequency-domain subcarrier-specific digital IQ data. However, it should be understood that in alternative embodiments, transceiver IC 1400 may instead be configured to receive and transmit data packets containing time-domain subcarrier-specific digital IQ data (e.g., to / from a beamformer processor) (see, for example, Figure 12B and the corresponding description of an example of such a configuration). In such alternative (time-domain only) embodiments, iFFT and FFT processing may be shifted from the transceiver IC to, for example, a beamformer processor, as described above. Furthermore, in some embodiments, different carrier packets destined for the same transceiver IC (containing either frequency-domain or time-domain IQ data) may include a unique carrier ID and be addressed to the same transceiver IC.

[0160] As shown in Figure 14, the serial communication port 1406 may be coupled to a signal processing unit 1408 which includes several elements configured to provide various digital signal processing functions, for example, as previously described in relation to Figures 12A_B and 13A_B. In some embodiments, the signal processing unit 1408 may be a single digital signal processor (DSP) that performs all iFFT and FFT calculations, as well as other signal processing functions (not explicitly stated) related to, for example, frequency domain / time domain I / Q data signals.

[0161] During operation, in the downlink (DL) transmission direction, the IQ packet data stream received via link 0 (1406) for DL ​​transmission may be provided to a demultiplexer (or a similar element such as a section of memory by memory mapping) 1410, which can separate the received data into two separate data streams for two distinct transmission chains: one stream of IQ data for dual-carrier horizontally polarized signals (C1H / C2H signals) transmitted from a signal port coupled to radiating element 1430, and the other stream of IQ data for dual-carrier vertically polarized signals (C1V / C2V signals) transmitted from a signal port coupled to radiating element 1422. Element 1412 (for example, in the form of a DSP memory) can further separate the horizontal and vertical frequency domain components (data points) for the subcarriers of each component carrier C1 and C2, which are then transmitted to four separate iFFT / CP (IFFT / cyclic prefix) elements 1414 for frequency-to-time domain conversion to generate four separate discrete-time domain baseband data signals (two for each carrier frequency and two for each signal polarization). Although not explicitly shown, additional time-domain and frequency-domain processing may include, for example, cyclic prefix addition, frequency offset, phase and gain adjustment, filtering, and sample rate conversion.

[0162] In practice, as described above, the incoming data is divided into four separate transmission paths. More specifically, as shown in Figure 14, the output of unit 1408 includes (i) two separate discrete-time domain baseband data signals 1416 and 1418, indicated as C1H(1416) and C2H(1418), and (ii) two separate discrete-time domain baseband data signals 1426 and 1428, indicated as C1V(1426) and C2V(1428). As shown in the diagram, following the conversion from the frequency domain to the time domain, the time domain signals C1H(1416) and C2H(1418) are added together in time, and C1V(1426) and C2V(1428) are added together in time. The result of the signal addition is supplied to the respective TX / DPA elements 1420, which generally represent the transmit RF chain and digital power amplifier, to generate the amplified analog RF signals C1H / C2H(1424) for the horizontal signal port and the amplified analog RF signals C1V / C2V(1432) for the vertical signal port. Signals 1424 and 1432 are then provided to the corresponding radiating elements 1422 and 1430 via their respective SPDTs for transmission. Note that, although not explicitly shown, additional time domain processing may include, for example, additional sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc., as previously described herein.

[0163] During operation, in the receiving direction, the data-modulated dual-component carrier RF uplink signal can be received by the transceiver IC (1400) at the horizontal and vertical signal ports via radiating elements 1422 and 1430. For ease of explanation and for illustrative purposes only, we assume that the amplified analog RF signals C1H / C2H (1424) and C1V / C2V (1432) are the uplink signals received here by the transceiver IC. As shown in Figure 14, the horizontally polarized RF signal and the vertically polarized RF signal can be supplied to separate LNA / DC / ADC elements 1446 via their respective SPDTs. The LNA / DC / ADC elements 1446 perform RF-to-baseband signal conversion, analog-to-digital signal conversion, and then may perform further time-domain processing (e.g., orthogonal error correction, filtering, etc. (not explicitly shown)).

[0164] As further shown, the output of element 1446 contains two copies of the discrete-time domain baseband data signal. The two signals are filtered by FIR filters 1442 and 1444, but one of the signals is first frequency-shifted by an NCO (in either filter 1442 or 1444) to isolate the component carriers. The isolated carriers are shown as C1H(1442) and C2H(1444). Two additional identical discrete-time domain baseband data signals are fed to filters 1426 and 1428, generating time-domain signals representing the component carrier time-domain signals (after NCO transformation and FIR filtering), shown as C1V (provided by filter 1448) and C2V (provided by filter 1450). These four distinct time-domain baseband signals 1442, 1444, 1148, and 1450 (two for each carrier and two for each polarization) are then input to the DSP 1408 for signal processing, which includes CP rejection and conversion (via FFT element 1440) from time-domain IQ signal samples to frequency-domain IQ data representing the magnitude and phase of each subcarrier of the corresponding component carriers.

[0165] Therefore, in this embodiment, the received RF signal is effectively divided into four discrete-time domain baseband data signals processed on four separate receiving paths. More specifically, the C1H signal (1442), C2H signal (1444), C1V signal (1448), and C2V signal (1450) are analyzed by memory mapping or the like for four separate FFT signal processing operations (e.g., 1440) for time-domain to frequency-domain conversion (by FFT), generating four separate frequency-domain IQ data packets (or streams of packets, where each packet in the stream represents symbol time in a slot) for each of the two component carrier frequencies and each signal polarization.

[0166] Although not explicitly shown, other time-frequency pre-transformation signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, as described above. Following the transformation performed by FFT element 1440, elements 1436, 1438 (e.g., in the form of DSP memory and digital logic) can then formulate IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V). Note that in alternative embodiments without time-frequency domain transformation (as described above), the IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V) may instead be formulated in the time domain.

[0167] As a further example of other embodiments, Figure 15 shows a generalized configuration of exemplary signal processing through two serially connected transceiver devices of Figures 12 and 13 for generating a four-carrier dual-polarization communication signal, according to several embodiments. More specifically, Figure 15 shows a transceiver device architecture 1500 including a first transceiver device 1504a and a second transceiver device 1504b. As in Figure 14, in the exemplary embodiment, the transceiver device is a transceiver IC that operates in TDD mode within an OFDM modulation system such as a 5G or LTE-based communication system. Note that various operating principles and nomenclature described in relation to Figure 14 apply to the embodiment of Figure 15, and therefore, for the sake of clarity, some details of operation are omitted or generalized.

[0168] Referring to Figure 15, the first transceiver device (IC) 1504a includes a first serial communication port 1506 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 0" in Figure 15) and a second serial communication port 1530 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 1" in Figure 15). Similarly, the second transceiver device (IC) 1504b includes a first serial communication port 1546 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 0" in Figure 15) and a second serial communication port 1562 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver) (indicated as "Link 1" in Figure 15). The transceiver devices (ICs) 1504a and 1504b are serially connected via a bidirectional serial data link 1544.

[0169] In some embodiments, the serial communication port 1506 can receive (e.g., from a beamformer processor) via a bidirectional serial data link 1502 an IQ data packet stream for DL ​​transmission (packetized in four carrier-specific H / V combinations, or eight sets of IQ data packetized as eight separate data packet streams in the illustrated embodiment), the packets containing IQ subcarrier data for four different component carriers for horizontal (H) polarization and vertical (V) polarization, respectively (hereinafter, "carrier C1", "carrier C2", "carrier C3", and "carrier C4"). For brevity, the four different carrier combinations on horizontal and vertical polarization are referred to herein as "C1H", "C2H", "C3H", "C4H", "C1V", "C2V", "C3V", and "C4V", respectively. In the UL (uplink) direction, serial communication port 1506 can receive data packet streams (e.g., eight multiplexed data packet streams) for each of the four carriers C1, C2, C3, and C4 for each of the two H-polarizations and V-polarizations, and transmit them (e.g., to a beamformer processor) via the same bidirectional serial data link 1502.

[0170] Note that in the transceiver device architecture 1500 shown in Figure 15, it is assumed, for example, that packets received at or transmitted from the serial port communication port 1506 contain frequency domain subcarrier-specific digital IQ data. However, in alternative embodiments, each transceiver device 1504a and 1505b may be configured accordingly such that packets received at or transmitted from the serial port communication port 1506 (e.g., from / to the beamformer processor) instead contain time domain subcarrier-specific digital IQ data (see, for example, Figure 12B and the corresponding description of an example of such a configuration). In this regard, the iFFT and FFT processing may be shifted from the transceiver device (IC) side to the beamformer processor, as described above.

[0171] During operation, in the DL transmission direction, the first transceiver IC (1504a) receives a packetized IQ data stream via port 1506 for DL ​​transmission. The first transceiver IC is configured to process data related to the first two carriers for each polarization, i.e., C1H, C2H, C1V, and C2V. Similar to the transmission operation described in relation to Figure 14, the first transceiver IC (1504a) performs signal processing to separate the received IQ data for carriers C1 and C2 into separate datasets for two distinct transmission paths, i.e., one stream of IQ data for dual-carrier horizontally polarized signals (C1H / C2H signals) and another stream of IQ data for dual-carrier vertically polarized signals (C1V / C2V signals) (via a demultiplexer or similar element (1508)). As shown in Figure 14, the horizontal and vertical frequency domain components for the subcarriers of each component carrier C1 and C2, as generally indicated by elements 1510 and 1520 (indicated as "C1H / C2H" and "C1V / C2"), can be further divided and processed by four separate iFFT / CP elements to generate four separate discrete-time domain baseband data signals (two for each component carrier and two for each signal polarization). These signals are then added together in time, and the results of the signal addition (C1H+C2H and C1V+C2V) are provided to the respective TX / DPA elements 1512 and 1522 to generate the modulated and amplified analog RF signals C1H / C2H for the horizontal signal port of transceiver IC 1504a and the amplified analog RF signals C1V / C2V for the vertical signal port of transceiver IC 1504a.

[0172] Unlike the embodiment in Figure 14, packet data related to the other two carriers C3 and C4 received at port 1506 is forwarded to a second transceiver IC (1504b) for processing. More specifically, the first transceiver IC (1504a) may be configured to forward IQ data packets for carriers C3 and C4 for each polarization, i.e., C3H, C4H, C3V, and C4V, to the second transceiver IC (1504b) for processing. In some embodiments, different carrier packets destined for either the first or second transceiver IC may include a unique carrier ID and be addressed to the respective transceiver IC via one or more identification fields in the IQ data packet. Thus, the first transceiver IC may be configured to examine incoming packets to determine which packets are destined for the first transceiver IC and which packets should be forwarded to the second transceiver IC.

[0173] In some embodiments, the first transceiver IC may forward these packets via an internal path 1532 to a second serial communication port 1530 which is serially interconnected with a second transceiver IC (i.e., a serial communication port 1546 in the second transceiver IC) via a serial data link 1544. The second transceiver IC performs signal processing similar to that of the first transceiver IC via elements 1548, 1550, 1556, 1552, and 1558 (with respect to carriers C3 and C4) to output amplified analog RF signals C3H / C4H and C3V / C4V on the two signal ports of transceiver IC 1504b.

[0174] Next, (i) two signals C1H / C2H and C3H / C4H for horizontal polarization can be combined via an adder 1514 to produce a combined signal 1518 that is provided to the radiating element 1526 via a first SPDT for transmission, and (ii) two signals C1V / C2V and C3V / C4V for vertical polarization can be combined via an adder 1524 to produce a combined signal 1528 that is provided to the radiating element 1516 via a second SPDT for transmission.

[0175] Similarly, in the receiving direction, the data-modulated 4-carrier dual-polarization RF uplink signal can be received by two serially connected transceiver ICs (1504a and 1504b) via radiating elements 1516 and 1526 corresponding to the horizontal and vertical signal ports, respectively. As in the case of Figure 14, for the sake of clarity and for illustrative purposes only, we assume that the analog RF signals C1H / C2H / C3H / C4H (1518) and C1V / C2V / C3V / C4V (1628) are currently the received uplink signals.

[0176] As shown in Figure 15, the RF signal (1518) received by the horizontal polarization antenna element 1516 is supplied to the RX / LNA element 1538 in the first transceiver IC (1504a) via its respective SPDT, and the RF signal (1528) received by the vertical polarization antenna element is supplied to the RX / LNA element 1570 in the second transceiver IC (1504b) via its respective SPDT. Similar to the process shown in Figure 14, each of the horizontal receiving RX / LNA chains and the vertical receiving RX / LNA chain may be configured to perform RF-to-baseband signal conversion, analog-to-digital signal conversion, etc., to output a first 4-carrier discrete-time domain signal on the horizontal receiving path and a second 4-carrier discrete-time domain signal on the vertical path. Therefore, in some embodiments, the output of RX / LNA element 1538 may be a first four-carrier discrete-time domain signal on a horizontally polarized receiving path, and the output of RX / LNA element 1570 may be a second four-carrier discrete-time domain signal on a vertically polarized receiving path. Note that in this embodiment, each transceiver IC processes the four component carriers in one of the RX / LNA elements, and the other RX / LNA elements (1542, 1576) are disabled.

[0177] Referring back to the signal processing shown in Figure 15, with respect to horizontal polarization, the output of RX / LNA element 1538 may include discrete-time domain baseband data signals 1536 and 1540, which are processed on two separate signal processing branches: (i) carriers C1 and C2, represented as C1H / C2H(1536), are processed on one branch, and (ii) carriers C3 and C4, represented as C3H / C4H(1540), are processed on the other branch. Similarly, with respect to vertical polarization, the output of RX / LNA element 1570 may include discrete-time domain baseband data signals 1568 and 1574, which are to be processed on two separate signal processing branches: (i) carriers C1 and C2, represented as C1V / C2V(1568), are processed on one branch, and carriers C3 and C4, represented as C3V / C4V(1574), are processed on the other branch.

[0178] Various principles of operation for received signal processing (e.g., conversion from time-domain signals to frequency-domain IQ data) are similarly applied to the receiving path in the arrangement of Figure 15, as described in relation to Figure 14, and will not be repeated in detail here. For illustrative purposes, in some embodiments, the received C1H / C2H signal (1536) for horizontal polarization may be separated from C3H / C4H by time-domain FIR filtering, notch filtering, etc., and further separated into constituent component carriers C1H and C2H by time-domain filtering in one signal path to remove the C2H component in order to obtain C1H, while another path may include complex multiplication over a numerically controlled oscillator (NCO) frequency to shift the C2H component to a desired baseband signal, followed by additional filtering to remove the residual component of C1H. Thus, one transceiver IC (1504a) may receive four component carriers on a single receiving RF signal port (e.g., via either an H-polarized antenna element or a V-polarized antenna element) and decompose the signal into four distinct component carriers. In the embodiments shown, the four distinct component carriers C1H, C2H, C3H, and C4H are all separated using time-domain signal processing and then sent to four distinct FFT operations (in some embodiments, all performed by a single DSP processor) for time-domain to frequency-domain conversion. Similarly, the C1V / C2V / C3V / C4V signals (1528) for vertical polarization, initially processed by a single LNA and ADC1570, are processed through filtering, frequency offset (i.e., NCO modulation), and further filtering to be adjusted for four distinct FFT operations for time-domain to frequency-domain conversion. Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample-rate conversion, filtering, cyclic prefix detection and removal, as described above.

[0179] Following the time-frequency domain conversion, in this embodiment, elements 1534 and 1566 (on the horizontal and vertical paths, respectively) then route and / or store in memory IQ data points for the subcarriers associated with the individual component carriers C1, C2, C3, and C4 for each respective polarization (H or V). The frequency-domain IQ data for all four component carriers can be further coupled, per polarization, into packet data streams (e.g., eight packet data streams, or four coupled V / H packet streams) for transmission from two serially connected transceiver ICs (1504a and 1504b) via a bidirectional serial link 1502 (e.g., to a beamformer processor).

[0180] More specifically, in this regard, frequency domain IQ packet data corresponding to vertically polarized signals for the four carriers C1, C2, C3, and C4 may be received at the serial communication port 1562 of the second transceiver IC (1504b). The second transceiver IC may be configured to forward those data packets via the internal link 1564 to other serial communication ports 1530 which are serially interconnected with the first transceiver IC (i.e., serial communication port 1546 in the first transceiver IC) via the serial data link 1544. Although not explicitly shown in Figure 15, in some embodiments, the packet data corresponding to the vertical polarization signals of the four carriers C1, C2, C3, and C4 received at the serial communication port 1530 can be multiplexed to combine the packet data output by element 1534 (for the horizontal polarization of all four carriers C1, C2, C3, and C4) to generate an IQ data packet stream that is sent to the serial data link transceiver 1506 on the data link 1532 for communication with the beamformer processor via the serial communication link 1502. However, it should be noted that in alternative embodiments that do not involve time-frequency domain conversion (as described above), the frequency domain IQ data for all four component carriers for each polarization may instead be combined into a packet data stream in the time domain (for transmission via the bidirectional serial link 1502 (e.g., to the beamformer processor)).

[0181] Furthermore, in the embodiment shown in Figure 15, DL and UL signal processing are not performed symmetrically across the serially connected transceiver ICs. DL transmit signal processing is divided according to the component carrier (both H and V polarities of C1 and C2 are processed by the first transceiver IC (1504a), and both polarities of C3 and C4 are processed by the second transceiver IC (1504b)), while UL receive signal processing is divided according to polarity (all H polarities of C1, C2, C3, and C4 are processed by the first transceiver IC (1504a), and all V polarities of C1, C2, C3, and C4 are processed by the second transceiver IC (1504b)). In some embodiments, this has the advantage on the transmitting side of relaxing the bandwidth requirements in the transmit modulator to span only two component carriers (e.g., C1, C2 processed in the first transceiver IC (1504a) and C3, C4 processed in the second transceiver IC (1504b)), while on the receiving side of not splitting the received RF signal into two different signal ports of two different transceiver ICs before processing by down-conversion and sampling by the ADC. Thus, in the embodiments described, a dual-polarized four-component-carrier system can be implemented by using the broadband capability of the receiver portion of the transceiver IC to process a received signal having a four-component-carrier bandwidth while relaxing the transmit modulator / amplifier bandwidth requirements to accommodate a transmit signal having a bandwidth of only two component carriers.

Claims

1. It is a device, A plurality of transceiver integrated circuit (IC) subarrays, each transceiver IC subarray comprising at least a first transceiver IC and a second transceiver IC physically disposed within the subarray, The first transceiver IC is, A first serial digital data port providing serial data connectivity to a beamformer processor, the first serial digital data port is configured to receive control message packets and a series of aggregated signal port IQ data packets for common processing in each of the plurality of transceiver ICs in a given subarray, each aggregated signal port IQ data packet comprising individual IQ data points for a plurality of subcarriers, the first serial digital data port, A transmit signal processing circuit configured to process the series of aggregated signal port IQ data packets by (i) digitally processing the IQ data points for the plurality of subcarriers based on a desired antenna tilt received in the control message packet, and (ii) a subarray position of the first transceiver IC for converting the series of aggregated signal port IQ data packets into a first baseband time domain signal, It has a second serial digital data port, The second transceiver IC mentioned above is A third serial digital data port is connected to the second serial digital data port of the first transceiver IC, provides a serial data connection to the first transceiver IC, and is configured to receive the control message packets and the series of aggregated signal port IQ data packets from the first transceiver IC, A plurality of transceiver IC subarrays having: (i) digitally processing the IQ data points for the plurality of subcarriers based on the desired antenna tilt received in the control message packet; and (ii) a transmit signal processing circuit configured to process the series of aggregated signal port IQ data packets by the subarray position of the second transceiver IC for converting the series of aggregated signal port IQ data packets into a second baseband time domain signal; A device comprising: a plurality of radiating antenna elements arranged within an antenna subarray, each element positioned adjacent to the plurality of transceiver integrated circuit (IC) subarrays.

2. The apparatus according to claim 1, wherein each transmitting signal processing circuit is configured to perform one or more signal processing techniques to achieve an electron beam tilt selected from the group consisting of (i) applying an incremental phase rotation to each subcarrier IQ data point via a numerically controlled oscillator (NCO), and (ii) applying a constant phase rotation to each subcarrier IQ data point.

3. The apparatus according to claim 1, wherein the first transceiver IC further comprises a received signal processing circuit configured to convert a received baseband time domain signal into a received aggregated signal port IQ data packet according to (i) beam tilt information received in a control message packet and (ii) the subarray position of the first transceiver IC, and to process the received aggregated signal port IQ data packet.

4. The apparatus according to claim 3, wherein the receiving signal processing circuit is configured to perform one or more signal processing techniques selected from the group consisting of (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point via a numerically controlled oscillator (NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point via complex multiplication, (iii) applying a constant phase rotation to each sample of the received baseband time domain signal via complex multiplication, and (iv) imposing a time delay on the received baseband time domain signal.

5. It is a method, The beamforming frequency domain in-phase and quadrature-phase (IQ) data packets are distributed to multiple serially connected transceiver integrated circuits (ICs) for common processing by the transceiver ICs. A method comprising applying electron beam tilt phase rotation in each transceiver IC by changing the phase of each IQ-modulated subcarrier, at least partially, based on a desired antenna tilt and the position of the corresponding radiating element in the antenna array.

6. The method according to claim 5, wherein the phase change is either a constant phase rotation applied to all subcarriers, or a linearly increasing phase rotation that increases from subcarrier to subcarrier.

7. The method according to claim 5, wherein the phase change may be specified according to one or more control messages.

8. The method according to claim 5, further comprising receiving a control message containing beam tilt information in the form of a phase adjustment parameter selected from the group consisting of time delay, frequency domain multiplicative rotation, time domain complex rotation, and phase index value.

9. The method according to claim 5, wherein the electron beam tilt includes coarse beam tilt phase rotation adjustment and fine beam tilt adjustment, the coarse beam tilt adjustment is implemented by applying a phase rotation that increases linearly across the subcarriers, and the fine beam tilt adjustment is implemented by further adjustment in the time domain.

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