Semiconductor equipment

Abstract

To flexibly and easily change a detection threshold value of overcurrent protection.SOLUTION: A semiconductor device 10 comprises an output element M0 and an overcurrent detection circuit 13. If the overcurrent detection circuit 13 detects that an abnormal high current flows to the output element M0 from rating when the output element M0 is on, the overcurrent detection circuit transmits an overcurrent detection signal to a logic circuit 11. In this case, the overcurrent detection circuit 13 uses a first potential difference between a reference voltage obtained by stepping down a current flowing to a resistor Rv of a power voltage VCC by the resistor Rv connected between a power terminal VT and an external terminal A and an output voltage VOUT determined from an on-resistance of the output element M0 and a current flowing to the output element M0 and applied from an output terminal OUT to a load 2 as an overcurrent detection threshold value. The overcurrent detection circuit 13 detects an overcurrent on the basis of comparison between a second potential difference between the power voltage VCC and the output voltage VOUT based on the current flowing when the output element M0 is on and the detection threshold value.SELECTED DRAWING: Figure 1

Claims

1. An output element that is connected to the power supply voltage via a power supply terminal and connected to the load via an output terminal, and switches based on a drive signal to operate the load, An external terminal to which a resistive element of any resistance value is connected between the power supply terminal and the device, The system includes an overcurrent detection circuit that detects overcurrent based on a current mirror circuit, which measures a reference voltage obtained by stepping down the power supply voltage by the amount of current flowing through the resistive element, a first potential difference between the output voltage applied to the output terminal determined by the on-resistance of the output element and the current flowing through the output element, and a second potential difference between the power supply voltage and the output voltage. The current mirror circuit described above is When the resistive element is connected between the power supply terminal and the external terminal, overcurrent is detected based on whether the first potential difference is greater than or equal to a detection threshold. If the resistive element is not connected between the power terminal and the external terminal, overcurrent detection is performed based on whether the second potential difference is greater than or equal to a detection threshold. Semiconductor equipment.

2. The overcurrent detection circuit comprises a detection unit, a potential generation unit, and an output unit. The detection unit comprises a differential pair element whose first high-potential end is connected to the external terminal and whose second high-potential end is connected to the output terminal, and the current mirror circuit connected to the low-potential side of the differential pair element. The potential generation unit outputs the generated potential to the control terminal of the differential pair element of the detection unit. The output unit is connected to the low-potential side of the element on which the second high-potential end of the differential pair element is connected to the output terminal, and outputs an overcurrent detection signal representing the overcurrent detection result. The semiconductor device according to claim 1.

3. The potential generation unit comprises a first PMOS transistor and a first constant current source. The source of the first PMOS transistor is connected to the back gate of the first PMOS transistor and the power supply terminal. The drain of the first PMOS transistor is connected to the input terminal of the first constant current source, the gate of the first PMOS transistor, and the output terminal of the potential generation unit. The output terminal of the first constant current source is connected to ground. The semiconductor device according to claim 2.

4. The differential pair element of the detection unit comprises a second PMOS transistor and a third PMOS transistor. The control terminals of the differential pair are connected to the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the output terminal of the potential generation unit. The source of the second PMOS transistor is connected to the external terminal via the first high-potential terminal. The source of the third PMOS transistor is connected to the output terminal via the second high-potential terminal. The back gates of the second PMOS transistor and the third PMOS transistor are connected to the power supply terminals. The current mirror circuit of the detection unit comprises a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor is connected to the gate of the first NMOS transistor, the gate of the second NMOS transistor, and the drain of the second PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the third PMOS transistor. The source and back gate of the first NMOS transistor and the source and back gate of the second NMOS transistor are connected to ground. The semiconductor device according to claim 3.

5. The output section consists of a second constant current source and a third NMOS transistor. The input terminal of the second constant current source is connected to the power supply terminal. The gate of the third NMOS transistor is connected to the terminal between the drain of the third PMOS transistor and the drain of the second NMOS transistor. The source and back gate of the third NMOS transistor are connected to ground. The overcurrent detection signal is output from the connection node between the output terminal of the second constant current source and the drain of the third NMOS transistor. The semiconductor device according to claim 4.

6. The external terminal is connected to the source of the second PMOS transistor, and the gate-source voltage of the second PMOS transistor is adjusted by the current value from the first constant current source included in the potential generation unit and the potential difference determined by the resistive element. The semiconductor device according to claim 4.

7. The first constant current source is a depletion-type NMOS transistor with the drain at the input terminal, the gate and back gate connected to the source which is the output terminal. The semiconductor device according to claim 3.

8. The second constant current source is a depletion-type NMOS transistor with the drain at the input terminal, the gate and back gate connected to the source which is the output terminal. The semiconductor device according to claim 5.

9. The second constant current source is a PMOS transistor whose input terminals are the source and back gate, and whose output terminal is the drain, with the gate connected to the output terminal of the potential generation unit. The semiconductor device according to claim 5.

10. The semiconductor device according to claim 4, wherein, when the first gate-source voltage of the second PMOS transistor and the second gate-source voltage of the third PMOS transistor are the same, the first size of the second PMOS transistor and the second size of the third PMOS transistor are adjusted such that the second drain current output from the third PMOS transistor is greater than the first drain current output from the second PMOS transistor.

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