Printed circuit board

Abstract

To provide a printed wiring board having high quality.SOLUTION: A printed wiring board has: a first conductor layer including a first pad; a first resin insulation layer which is formed on the first conductor layer and has a first opening for exposing the first pad; a second conductor layer which is formed on the first resin insulation layer and includes a second pad; a first via conductor which is formed in the first opening and connects the first pad and the second pad; a second resin insulation layer which is formed on the second conductor layer and the first resin insulation layer and has a second opening for exposing the second pad; a third conductor layer which is formed on the second resin insulation layer and includes a third pad; and a second via conductor which is formed in the second opening and connects the second pad and the third pad. In the upper surface of the second pad, a recess which is recessed downward from the upper surface of the second pad is formed. In the lower end of the second via conductor, a fitting part which enters into the lower part of the bottom surface of the recess and is connected to the second pad is formed.SELECTED DRAWING: Figure 1

Description

【Technical Field】 【0001】 The technology disclosed by this specification relates to printed wiring boards. 【Background Art】 【0002】 Patent Document 1 discloses a multilayer printed wiring board including a build-up layer formed by sequentially laminating a conductor circuit and an interlayer resin insulating layer on a substrate. In this multilayer printed wiring board, via holes of different layers are laminated so as to form a stack via structure. 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 Japanese Patent Application Laid-Open No. 2002-280740 【Summary of the Invention】 [[ID=3*]] 【0004】 [Problems of Patent Document 1] In the multilayer printed wiring board of Patent Document 1, it is considered that a large stress is applied to the connection portion between the lower end of the upper via hole and the land of the lower via hole in the stack via structure. It is considered that peeling is likely to occur between the lower end of the upper via hole and the land of the lower via hole due to the application of a large stress. 【Means for Solving the Problems】 【0005】 The printed circuit board of the present invention comprises: a first conductor layer including a first pad; a first resin insulating layer formed on the first conductor layer and having a first opening that exposes the first pad; a second conductor layer formed on the first resin insulating layer and including a second pad; a first via conductor formed in the first opening and connecting the first pad and the second pad; a second resin insulating layer formed on the second conductor layer and the first resin insulating layer and having a second opening that exposes the second pad; a third conductor layer formed on the second resin insulating layer and including a third pad; and a second via conductor formed in the second opening and connecting the second pad and the third pad. A recess is formed on the upper surface of the second pad, recessed below the upper surface of the second pad. A fitting portion is formed at the lower end of the second via conductor, which extends further below the bottom surface of the recess and connects to the second pad. 【0006】 In the printed circuit board of the embodiment of the present invention, a recess is formed on the upper surface of the second pad, and a fitting portion is formed at the lower end of the second via conductor. Therefore, compared to a configuration without a recess in the second pad and a fitting portion in the second via conductor, the connection area between the second via conductor and the second pad is larger. Stress is less likely to concentrate at the lower end of the second via conductor. The reliability of the connection between the second via conductor and the second pad is improved. A high-quality printed circuit board is provided. [Brief explanation of the drawing] 【0007】 [Figure 1] A schematic cross-sectional view showing a printed circuit board of the embodiment. [Figure 2] A schematic, enlarged cross-sectional view showing a portion of the printed circuit board of the embodiment. [Figure 3A] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3B] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3C] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3D] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3E] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3F] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3G] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3H] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3I] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3J] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3K] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Figure 3L] A schematic cross-sectional view illustrating the manufacturing method of a printed circuit board according to this embodiment. [Modes for carrying out the invention] 【0008】 [Embodiment] Figure 1 is a cross-sectional view showing a printed circuit board 2 of an embodiment. Figure 2 is an enlarged cross-sectional view showing a part of the printed circuit board 2 of Figure 1. As shown in Figure 1, the printed circuit board 2 has an insulating layer 4, a first conductor layer 10, a first resin insulating layer 20, a second conductor layer 30, a first via conductor 40, a second resin insulating layer 50, a third conductor layer 60, and a second via conductor 70. 【0009】 The insulating layer 4 is formed using resin. The insulating layer 4 may contain inorganic particles such as silica. The insulating layer 4 may contain reinforcing materials such as glass cloth. The insulating layer 4 can form a core substrate. The insulating layer 4 can form a resin insulating layer that forms a build-up layer. 【0010】 The first conductor layer 10 is formed on the insulating layer 4. The first conductor layer 10 includes signal wiring 12, 14 and a pad 16. Although not shown in the figure, the first conductor layer 10 also includes conductor circuits other than the signal wiring 12, 14 and the pad 16. The first conductor layer 10 is mainly made of copper. The first conductor layer 10 is formed of a seed layer 10a on the insulating layer 4 and an electroplating layer 10b on the seed layer 10a. The seed layer 10a is an electroless plating layer. In modified examples, the seed layer 10a may be a sputtered layer. A mating recess 18 is formed on the upper surface of the pad 16. The mating recess 18 is recessed downward from the upper surface of the pad 16. 【0011】 The first resin insulating layer 20 is formed on the insulating layer 4 and the first conductor layer 10. The first resin insulating layer 20 is made of a resin and a number of inorganic particles dispersed within the resin. The resin is an epoxy resin. Examples of resins include thermosetting resins and photocurable resins. The inorganic particles are, for example, silica and alumina. The first resin insulating layer 20 has an opening 25 that exposes the pad 16 of the first conductor layer 10. The opening 25 exposes the upper surface of the pad 16. The fitting recess 18 is formed on the portion of the upper surface of the pad 16 that is exposed from the opening 25. 【0012】 The second conductor layer 30 is formed on the first resin insulating layer 20. The second conductor layer 30 includes signal wiring 32, 34 and pad 36. Although not shown in the figure, the second conductor layer 30 also includes conductor circuits other than the signal wiring 32, 34 and pad 36. The second conductor layer 30 is mainly made of copper. The second conductor layer 30 is formed of a seed layer 30a on the first resin insulating layer 20 and an electroplating layer 30b on the seed layer 30a. The seed layer 30a is an electroless plating layer. In modified examples, the seed layer 30a may be a sputtered layer. 【0013】 As shown in Figures 1 and 2, a recess 37 is formed on the upper surface of the pad 36, which is recessed below the upper surface of the pad 36. Furthermore, a fitting recess 38 is formed in a part of the bottom surface of the recess 37 (the part exposed from the opening 55 (described later)). The fitting recess 38 is recessed further below the bottom surface of the recess 37, with an increased opening diameter. 【0014】 The first via conductor 40 is formed within the opening 25. The first via conductor 40 connects the first conductor layer 10 and the second conductor layer 30. In FIG. 1, the first via conductor 40 connects the pad 16 and the pad 36. The first via conductor 40 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the first via conductor 40 and the seed layer 30a forming the second conductor layer 30 are common. 【0015】 At the lower end of the first via conductor 40, a fitting portion 42 that fits into the fitting recess 18 of the pad 16 is formed. The fitting portion 42 enters further below the upper surface of the pad 16 and is connected to the pad 16. The fitting portion 42 fills the inside of the fitting recess 18. The diameter of the fitting portion 42 is larger than the opening diameter at the lower end of the opening 25. The diameter of the fitting portion 42 is 1.1 times or more and 1.3 times or less the opening diameter at the lower end of the opening 25. The depth of the lower end portion of the fitting portion 42 from the upper surface of the pad 16 is 5 μm or more and 10 μm or less. 【0016】 The second resin insulating layer 50 is formed on the first resin insulating layer 20 and the second conductor layer 30. The second resin insulating layer 50 is formed of a resin and a large number of inorganic particles dispersed in the resin. The resin is an epoxy resin. Examples of the resin are thermosetting resins and photocurable resins. The inorganic particles are, for example, silica or alumina. An opening 55 that exposes the pad 36 of the second conductor layer 30 is formed in the second resin insulating layer 50. The opening 55 exposes the bottom surface of the recess 37 of the pad 36. The fitting recess 38 is formed in a portion of the bottom surface of the recess 37 of the pad 36 that is exposed from the opening 55. 【0017】 The third conductor layer 60 is formed on the second resin insulating layer 50. The third conductor layer 60 includes signal wiring 62, 64 and a pad 66. Although not shown in the figures, the third conductor layer 60 also includes conductor circuits other than the signal wiring 62, 64 and the pad 66. The third conductor layer 60 is mainly made of copper. The third conductor layer 60 is formed of a seed layer 60a on the second resin insulating layer 50 and an electroplating layer 60b on the seed layer 60a. The seed layer 60a is an electroless plating layer. In modified examples, the seed layer 60a may be a sputtered layer. As shown in Figures 1 and 2, a recess 67 is formed on the upper surface of the pad 66, recessed below the upper surface of the pad 66. 【0018】 The second via conductor 70 is formed within the opening 55. The second via conductor 70 connects the second conductor layer 30 and the third conductor layer 60. In Figures 1 and 2, the second via conductor 70 connects pad 36 and pad 66. The second via conductor 70 is formed of a seed layer 60a and an electroplating layer 60b on the seed layer 60a. The seed layer 60a forming the second via conductor 70 and the seed layer 60a forming the third conductor layer 60 are common. 【0019】 The lower end of the second via conductor 70 has a fitting portion 72 that fits into the fitting recess 38 of the pad 36. The fitting portion 72 extends further below the bottom surface of the recess 37 of the pad 36 and is connected to the pad 36. The fitting portion 72 fills the inside of the fitting recess 38. 【0020】 In Figure 2, the symbol A indicates the distance between the upper surface of the second resin insulating layer 50 and the bottom surface of the recess 37 of the pad 36. The symbol B indicates the distance between the upper surface of the second resin insulating layer 50 and the upper surface of the pad 36. The symbol C indicates the distance between the upper surface of the second resin insulating layer 50 and the bottom surface of the mating recess 38 (i.e., the depth of the second via conductor 70). The symbol D indicates the distance between the recess 37 of the pad 36 and the bottom surface of the mating recess 38 (i.e., the depth of the mating recess 38). 【0021】 The depth (AB) of the recess 37 from the top surface of the pad 36 is 5 μm or more and 15 μm or less. The depth (D: depth of the fitting recess 38) of the lower end portion of the fitting portion 72 from the bottom surface of the recess 37 of the pad 36 is 5 μm or more and 10 μm or less. The diameter R2 of the fitting portion 72 is larger than the opening diameter R1 at the lower end of the opening 55. The diameter R2 of the fitting portion 72 is 1.1 times or more and 1.3 times or less the opening diameter R1 at the lower end of the opening 55. 【0022】 [Manufacturing method of printed circuit board 2 according to the embodiment] Figures 3A to 3L show the manufacturing method of the printed circuit board 2 according to the embodiment. Figures 3A to 3L are cross-sectional views. Figure 3A shows the insulating layer 4 and the first conductor layer 10 formed on the insulating layer 4. The first conductor layer 10 is formed by a semi-additive method. The seed layer 10a is formed by electroless plating. The electroplated layer 10b is formed by electroplating. At this point, the fitting recess 18 (Figure 1) is not formed on the upper surface of the pad 16. 【0023】 As shown in Figure 3B, the first resin insulating layer 20 is formed on the insulating layer 4 and the first conductor layer 10. 【0024】 A laser is irradiated onto the first resin insulating layer 20. As shown in Figure 3C, an opening 25 is formed in the first resin insulating layer 20 directly above the pad 16. The opening 25 exposes the pad 16. The inside of the opening 25 is cleaned simultaneously with the surface roughening treatment of the first resin insulating layer 20. The cleaning of the inside of the opening 25 includes a wet desmear treatment. The wet desmear treatment is performed with a solution of sodium permanganate and sulfuric acid. The pad 16 exposed from the opening 25 is partially removed by a soft etching treatment. The soft etching treatment is performed with a sodium persulfate solution. The depth of the fitting recess 18 and the diameter of the fitting portion 42 are adjusted within the range of a processing temperature of 20°C to 80°C and a processing time of 30 seconds to 400 seconds. As a portion of the pad 16 at the contact area between the first resin insulating layer 20 and the pad 16 is removed by etching, the diameter of the fitting portion 42 becomes larger than the laser aperture diameter. The fitting recess 18 has a depth of 5 μm or more and 10 μm or less at the lower end of the fitting portion 42 of the pad 16. The diameter of the fitting portion 42 is larger than the opening diameter at the lower end of the opening 25. The diameter of the fitting portion 42 is 1.1 times or more and 1.3 times or less the opening diameter at the lower end of the opening 25. 【0025】 As shown in Figure 3D, a seed layer 30a is formed on the first resin insulating layer 20. The seed layer 30a is formed by electroless plating. In the modified example, the seed layer 30a may be formed by sputtering. The seed layer 30a is also formed on the upper surface of the pad 16 exposed from the opening 25 (i.e., the inner surface of the fitting recess 18) and on the inner wall surface of the opening 25. 【0026】 As shown in Figure 3E, a plating resist 100 is formed on the seed layer 30a. The plating resist 100 has openings for forming signal lines 32, 34 and pads 36 (Figure 1). 【0027】 As shown in Figure 3F, an electroplating layer 30b is formed on the seed layer 30a exposed from the plating resist 100. The electroplating layer 30b fills the opening 25. The electroplating layer 30b also fills the mating recess 18. The seed layer 30a and the electroplating layer 30b on the first resin insulating layer 20 form the signal wiring 32, 34 and the pad 36. The second conductor layer 30 is formed. The seed layer 30a and the electroplating layer 30b in the opening 25 form the first via conductor 40. The seed layer 30a and the electroplating layer 30b in the mating recess 18 form the fitting portion 42. The first via conductor 40 connects the pad 16 and the pad 36. The signal wiring 32, 34 form a pair wiring. 【0028】 When the electroplating layer 30b fills the opening 25, it fills the bottom and side walls of the opening 25 first. Therefore, the formation of the electroplating layer 30b is slower near the center of the opening 25 compared to the land area of ​​the pad 36. The formation of the electroplating layer 30b is adjusted so that the depth (AB) of the recess 37 from the top surface of the pad 36 is between 5 μm and 15 μm. As a result, a recess 37 is formed near the center of the top surface of the formed pad 36, recessed below the top surface of the pad 36. 【0029】 As shown in Figure 3G, the plating resist 100 is removed. The seed layer 30a exposed from the electroplating layer 30b is removed. The second conductor layer 30 and the first via conductor 40 are formed simultaneously. 【0030】 As shown in Figure 3H, a second resin insulating layer 50 is formed on the first resin insulating layer 20 and the second conductor layer 30. 【0031】 A laser is irradiated onto the second resin insulating layer 50. As shown in Figure 3I, an opening 55 is formed in the second resin insulating layer 50 directly above the pad 36. The opening 55 exposes the pad 36 (recess 37). The inside of the opening 55 is cleaned simultaneously with the surface roughening treatment of the first resin insulating layer 20. The cleaning of the inside of the opening 55 includes a wet desmear treatment. The wet desmear treatment is performed with a solution of sodium permanganate and sulfuric acid. The pad 36 exposed from the opening 55 is partially removed by a soft etching treatment. The soft etching treatment is performed with a sodium persulfate solution. The depth D of the fitting recess 38 and the diameter R2 of the fitting portion 72 are adjusted within the range of a processing temperature of 20°C to 80°C and a processing time of 30 seconds to 400 seconds. As a portion of the pad 36 at the contact area between the first resin insulating layer 20 and the pad 36 is removed by etching, the diameter R2 of the fitting portion 72 becomes larger than the laser aperture diameter R1. As shown in Figure 3I, a fitting recess 38 is formed on the bottom surface of the recess 37 exposed from the opening 55. The depth of the fitting recess 38 from the top surface of the pad 36 (AB) of the recess 37 is 5 μm or more and 15 μm or less. The depth of the lower end portion of the fitting portion 72 from the bottom surface of the recess 37 of the pad 36 (D: depth of the fitting recess 38) is 5 μm or more and 10 μm or less. The diameter R2 of the fitting portion 72 is larger than the opening diameter R1 at the lower end of the opening 55. The diameter R2 of the fitting portion 72 is 1.1 times or more and 1.3 times or less the opening diameter R1 at the lower end of the opening 55. 【0032】 As shown in Figure 3J, a seed layer 60a is formed on the second resin insulating layer 50. The seed layer 60a is formed by electroless plating. In the modified example, the seed layer 60a may be formed by sputtering. The seed layer 60a is also formed on the upper surface of the pad 36 exposed from the opening 55 (i.e., the bottom surface of the recess 37 and the inner surface of the fitting recess 38) and on the inner wall surface of the opening 55. 【0033】 As shown in Figure 3K, a plating resist 110 is formed on the seed layer 60a. The plating resist 110 has openings for forming signal lines 62, 64 and pads 66 (Figure 1). 【0034】 As shown in Figure 3L, an electroplating layer 60b is formed on the seed layer 60a exposed from the plating resist 110. The electroplating layer 60b fills the opening 55. The electroplating layer 60b also fills the mating recess 38. The seed layer 60a and the electroplating layer 60b on the second resin insulating layer 50 form the signal wiring 62, 64 and the pad 66. A third conductor layer 60 is formed. The seed layer 60a and the electroplating layer 60b in the opening 55 form the second via conductor 70. The seed layer 60a and the electroplating layer 60b in the mating recess 38 form the fitting portion 72. The second via conductor 70 connects the pad 36 and the pad 66. The signal wiring 62, 64 form a pair wiring. 【0035】 When the electroplating layer 60b fills the opening 55, it fills the bottom and side walls of the opening 55 first. Therefore, the formation of the electroplating layer 60b is slower near the center of the opening 55 compared to the land area of ​​the pad 66. The formation of the electroplating layer 60b is adjusted so that the depth (AB) of the recess 67 from the top surface of the pad 66 is between 5 μm and 15 μm. As a result, a recess 67 is formed near the center of the top surface of the formed pad 66, recessed below the top surface of the pad 66. 【0036】 Subsequently, the plating resist 110 is removed. The seed layer 60a exposed from the electroplating layer 60b is removed. The third conductor layer 60 and the second via conductor 70 are formed simultaneously. The printed circuit board 2 of the embodiment (Figure 1) is obtained. 【0037】 In the printed circuit board 2 of the embodiment (Figures 1 and 2), a recess 37 is formed on the upper surface of the pad 36, and a fitting portion 72 is formed at the lower end of the second via conductor 70. Therefore, in the printed circuit board 2 of the embodiment, the connection area between the second via conductor 70 and the pad 36 is larger compared to a configuration without the recess 37 of the pad 36 and the fitting portion 72 of the second via conductor 70. Stress is less likely to concentrate at the lower end of the second via conductor 70. The connection reliability between the second via conductor 70 and the pad 36 is improved. A high-quality printed circuit board 2 is provided. 【0038】 Pad 16 is an example of a "first pad," and opening 25 is an example of a "first opening." Pad 36 is an example of a "second pad," and opening 55 is an example of a "second pad." Pad 66 is an example of a "third pad." 【0039】 [Another example of an embodiment] In an alternative example, the first resin insulating layer 20 may be a core substrate. The opening 25 may be a through-hole. [Explanation of symbols] 【0040】 2: Printed circuit board 4: Insulating layer 10: First Conductor Layer 16: Pad 18: Fitting recess 20: First resin insulating layer 25:Aperture 30: Second conductor layer 36: Pad 37: Recess 38: Fitting recess 40: First via conductor 42: Inset part 50: Second resin insulating layer 55:Aperture 60: Third Conductor Layer 66: Pad 67: Recess 70: Second via conductor 72: Inset part

Claims

[Claim 1] A first conductor layer including a first pad, A first resin insulating layer formed on the first conductor layer and having a first opening that exposes the first pad, A second conductor layer is formed on the first resin insulating layer and includes a second pad, A first via conductor formed within the first opening and connecting the first pad and the second pad, The second conductor layer and the second resin insulating layer are formed on the first resin insulating layer and have a second opening that exposes the second pad, A third conductor layer is formed on the second resin insulating layer and includes a third pad, A printed circuit board having a second via conductor formed within the second opening and connecting the second pad and the third pad, The upper surface of the second pad has a recess formed therein that is lower than the upper surface of the second pad. The lower end of the second via conductor has a recessed portion that extends further below the bottom surface of the recess and is connected to the second pad. [Claim 2] The printed circuit board according to claim 1, wherein the depth of the recess from the upper surface of the second pad is 5 μm or more and 15 μm or less. [Claim 3] The printed circuit board according to claim 1, wherein the depth of the lower end portion of the recess from the bottom surface of the recess is 5 μm or more and 10 μm or less. [Claim 4] A printed circuit board according to claim 1, wherein the diameter of the fitting portion is larger than the opening diameter of the lower end of the second opening. [Claim 5] The printed circuit board according to claim 4, wherein the diameter of the fitting portion is 1.1 times or more and 1.3 times or less the opening diameter at the lower end of the second opening.

Images