Power supply device

Abstract

The present invention makes it possible to suppress uneven distribution of current even in a state in which a plurality of semiconductor elements are mounted in a limited surface area on a circuit board.　This power supply device comprises a secondary battery cell, charge / discharge FETs (21 to 28), and a circuit board 30 provided with a first terminal block (31) and a second terminal block (32). The first charge / discharge FET (21) and the third charge / discharge FET (23) are arranged on the first-terminal-block side, and the second charge / discharge FET (22) and the fourth charge / discharge FET (24) are arranged on the second-terminal-block side. A first current path (41) that serially connects the first charge / discharge FET (21) and the second charge / discharge FET (22) is formed to be longer than a second current path (42) that serially connects the third charge / discharge FET (23) and the fourth charge / discharge FET (24). The first current path (41) is provided with a first current inhibition region (51) that inhibits the flow of current. The second current path (42) is provided with a second current inhibition region (52). A second electrical resistance (52R) of the second current inhibition region (52) is higher than a first electrical resistance (51R) of the first current inhibition region (51).

Description

Technical Field

[0001] The present invention relates to a power supply device.

Background Art

[0002] Power supply devices in which a large number of secondary battery cells are connected in series and parallel are used as backup power supplies for servers, or as power supply devices for household, commercial, and industrial use in stationary energy storage applications. They are also used as drive power sources for vehicles such as hybrid vehicles, electric vehicles, electric carts, and electric scooters, and as drive power sources for assist bicycles and electric tools. Such power supply devices are configured to increase the capacity and output by connecting a large number of secondary battery cells in series and parallel.

[0003] Power supply devices having a large number of secondary battery cells mount a plurality of power semiconductor devices such as charge / discharge FETs for charging and discharging the secondary battery cells on a circuit board. For example, in a battery module in which secondary battery cells are connected in many series and many parallel as in Patent Document 1, in order to control large current charging and discharging, a method of reducing the load by connecting a plurality of field effect transistors in parallel is common.

[0004] However, in such a substrate, due to the structure of the module, the large current input / output part has to be determined at one location such as a terminal block. Also, in many cases, the arrangement of each FET and the board pattern have to be configured under structural constraints. In such a case, if the arrangement is such that current easily concentrates on some FETs, current unevenness occurs in some elements during charge and discharge, exceeding the current rating of the elements and leading to thermal breakdown of the elements.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One of the objectives of the present invention is to provide a power supply device that can suppress current uneven distribution even when multiple semiconductor elements are mounted on a limited area of ​​a circuit board. [Means for solving the problem]

[0007] A power supply device according to one aspect of the present invention comprises a plurality of secondary battery cells, a plurality of semiconductor elements connected to the plurality of secondary battery cells, and a circuit board on which the plurality of semiconductor elements are mounted and which has a first terminal block and a second terminal block formed spaced apart from the first terminal block for electrically connecting the plurality of semiconductor elements to the plurality of secondary battery cells, wherein the plurality of semiconductor elements comprises a first semiconductor element and a third semiconductor element arranged on the first terminal block side, a second semiconductor element and a fourth semiconductor element arranged on the second terminal block side, the first semiconductor element and the third semiconductor element are connected in parallel, the second semiconductor element and the fourth semiconductor element are connected in parallel, and the first semiconductor element and the second semiconductor element are connected in series. A first current path is formed, the third semiconductor element and the fourth semiconductor element are connected in series to form a second current path, the first current path and the second current path are connected in parallel to each other, the first semiconductor element is positioned close to the first terminal block on a straight line in the alignment direction of the first and third semiconductor elements, and / or the second semiconductor element is positioned close to the second terminal block on a straight line in the alignment direction of the second and fourth semiconductor elements. The aforementioned The One current path is the aforementioned The It is formed to be longer than the two current paths, and the first current path is Between the first semiconductor element and the second semiconductor element A first current-inhibiting region is provided to inhibit the flow of current, and the second current path is Between the third semiconductor element and the fourth semiconductor element A second current-inhibiting region is provided to inhibit the flow of current, and the second electrical resistance of the second current-inhibiting region is made higher than the first electrical resistance of the first current-inhibiting region. [Effects of the Invention]

[0008] According to a power supply device in one aspect of the present invention, by providing a second current-inhibiting region in the second current path, which is shorter than the first current path and more prone to current flow, where current flow is more difficult, it is possible to suppress current concentration, avoid excessive heat generation in the second and fourth semiconductor elements, and suppress heat generation evenly. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram of a power supply device according to Embodiment 1 of the present invention. [Figure 2A] Figure 1 is a plan view showing the circuit board of the power supply unit. [Figure 2B] This is a plan view showing the circuit board of a modified power supply device. [Figure 3] Figure 1 is a plan view showing the circuit board of the power supply unit. [Figure 4] This is a plan view showing a circuit board according to Embodiment 2. [Figure 5] This is a plan view showing a circuit board according to Embodiment 3. [Figure 6] This is a plan view showing a circuit board according to Embodiment 4. [Modes for carrying out the invention]

[0010] Embodiments of the present invention may be defined by the following configurations.

[0011] In addition to the above configuration, the power supply device according to one embodiment of the present invention has the first current-blocking region and the second current-blocking region forming a plurality of thermal vias that penetrate the circuit board, and the number of thermal vias formed in the second current-blocking region can be greater than the number of thermal vias formed in the first current-blocking region.

[0012] In another embodiment of the present invention, the power supply device further comprises, in addition to any of the above configurations, a fifth semiconductor element located on the first terminal block side and a sixth semiconductor element located on the second terminal block side, wherein the fifth semiconductor element is connected in parallel with the first semiconductor element, the sixth semiconductor element is connected in parallel with the second semiconductor element, the third current path connecting the fifth and sixth semiconductor elements in series is longer than the second current path, the third current path is provided with a third current inhibiting region that inhibits the flow of current, and the third electrical resistance of the third current inhibiting region can be made equivalent to the first electrical resistance.

[0013] Further, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention is such that the third current-inhibiting region forms a plurality of thermal vias penetrating the circuit board, and the number of thermal vias formed in the third current-inhibiting region can be made equal to the number of thermal vias formed in the first current-inhibiting region.

[0014] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention further includes a seventh semiconductor element disposed on the first terminal block side and an eighth semiconductor element disposed on the second terminal block side among the plurality of semiconductor elements. The seventh semiconductor element is connected in parallel with the first semiconductor element, and the eighth semiconductor element is connected in parallel with the second semiconductor element. A fourth current path connecting the seventh semiconductor element and the eighth semiconductor element in series is formed to have the same length as the second current path. The fourth current path is provided with a fourth current-inhibiting region that inhibits the flow of current, and the fourth electrical resistance of the fourth current-inhibiting region can be made equal to the second electrical resistance.

[0015] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention further is such that the fourth current-inhibiting region forms a plurality of thermal vias penetrating the circuit board, and the number of thermal vias formed in the fourth current-inhibiting region can be made equal to the number of thermal vias formed in the second current-inhibiting region.

[0016] Furthermore, in addition to any of the above configurations, the first current-inhibiting region and the second current-inhibiting region of the power supply device according to another embodiment of the present invention each form a thermal via penetrating the circuit board, and the electrical resistance can be adjusted by the area of the opening of the thermal via.

[0017] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention is such that the first semiconductor element and the third semiconductor element can be arranged close to each other, and the second semiconductor element and the fourth semiconductor element can be arranged close to each other.

[0018] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention, the first terminal block and the second terminal block are through holes.

[0019] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention, the plurality of semiconductor elements are FETs.

[0020] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention, among the first semiconductor element and the third semiconductor element, the First semiconductor device source terminal of the FET is arranged closer to the first terminal block than the Source terminal of the third semiconductor device, the FET It was done is.

[0021] Furthermore, in addition to any of the above configurations, the power supply device according to another embodiment of the present invention, among the second semiconductor element and the fourth semiconductor element, the Second semiconductor device source terminal of the FET is arranged closer to the second terminal block than the Source terminal of the fourth semiconductor device, the FET It was done is.

[0022] ​​Embodiments of the present invention will be described below with reference to the drawings. However, the embodiments shown below are illustrative examples for realizing the technical concept of the present invention, and the present invention is not limited to these. Furthermore, this specification does not limit the members shown in the claims to the members of the embodiments. In particular, the dimensions, materials, shapes, relative arrangements, etc. of the constituent members described in the embodiments are not intended to limit the scope of the present invention to those, unless otherwise specifically stated, but are merely illustrative examples. Note that the size and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. Furthermore, in the following description, the same name and reference numerals indicate the same or similar members, and detailed explanations are omitted as appropriate. Furthermore, each element constituting the present invention may be configured such that multiple elements are made of the same material, with one material serving multiple elements, or conversely, the function of one material can be shared among multiple materials. In addition, some of the contents described in some embodiments may be applicable to other embodiments.

[0023] Furthermore, in this specification, "equivalent" does not only mean strictly identical, but also includes the meaning of being roughly identical with some minor differences.

[0024] The power supply unit according to this embodiment can be used for various purposes, such as a backup power supply for servers, a power supply installed in electric vehicles such as hybrid cars and electric vehicles to supply power to the drive motor, a power supply for storing electricity generated from natural energy sources such as solar power and wind power, or a power supply for storing off-peak electricity. It is particularly suitable as a power supply for high-power and high-current applications. The following example describes a power supply unit used as a backup power supply for servers. [Embodiment 1]

[0025] Figures 1 to 3 show a power supply device 100 according to Embodiment 1 of the present invention. In these figures, Figure 1 is a circuit diagram of the power supply device according to Embodiment 1 of the present invention, Figure 2A is a plan view showing the circuit board of the power supply device in Figure 1, Figure 2B is a plan view showing the circuit board of a modified power supply device, and Figure 3 is a plan view showing the circuit board of the power supply device in Figure 1. (Power supply 100)

[0026] The power supply unit 100 shown in the circuit diagram of Figure 1 comprises a plurality of secondary battery cells 10, a plurality of semiconductor elements, which are charge / discharge FETs 20, connected to these secondary battery cells 10, and a circuit board 30 on which these charge / discharge FETs 20 are mounted. The charge / discharge FETs 20 include a charging FET 20C for charging and a discharge FET 20D for discharging. Due to their voltage ratings and other factors, multiple charging FETs 20C and discharge FETs 20D can be connected in series or parallel to distribute the load on each element. In this case, multiple charging FETs 20C and discharge FETs 20D are connected in parallel to reduce the current value per element.

[0027] Furthermore, the parallel-connected charging FET 20C and the parallel-connected discharging FET 20D are connected in series, and a current-inhibiting region 50 is formed between them. The current-inhibiting region 50 has a predetermined electrical resistance. In Figure 1, for illustrative purposes, the electrical resistance of the current-inhibiting region 50 is virtually shown as an equivalent circuit with electrical resistance 50R, but no physical resistor is implemented.

[0028] In this embodiment, the power supply unit 100 is often subject to structural constraints on the arrangement of each charge / discharge FET 20 mounted on the circuit board 30 and the circuit pattern of the circuit board 30 in order to control high-current charging and discharging. In such cases, if the arrangement is such that current tends to concentrate on some of the charge / discharge FETs 20, current uneven distribution may occur during charging and discharging, potentially causing some of the charge / discharge FETs 20 to overheat excessively. Therefore, current uneven distribution is suppressed by providing current-inhibiting regions 50 in each current path of the circuit board 30, adjusting their resistance values, that is, adjusting the virtual electrical resistance 50R, and increasing the electrical resistance in the regions where current tends to concentrate. (Secondary battery cell 10)

[0029] Multiple secondary battery cells 10 are connected in series at least. Alternatively, secondary battery cells 10 connected in series may be further connected in parallel. The output of the battery assembly composed of secondary battery cells 10 including the series connection is output from the power supply unit 100. Rechargeable batteries such as lithium-ion batteries or nickel-metal hydride battery cells can be used as secondary battery cells 10. (Charge / discharge FET20)

[0030] Multiple charge / discharge FETs 20 are used to control the charging and discharging of the secondary battery cell 10. Existing charge / discharge FETs, such as MOSFETs, can be used for these charge / discharge FETs 20. Figure 2A shows one embodiment of the charge / discharge FET 20. The charge / discharge FET 20 shown in this figure uses a surface-mount type MOSFET with two source terminals S and one gate terminal G at one end, and a tab-shaped drain terminal D at the other end. However, the number of terminals, arrangement, and package configuration of the charge / discharge FET in this embodiment can be arbitrary; for example, a type with seven terminals at one end may be used.

[0031] The number of charge / discharge FETs 20 can be adjusted as appropriate depending on the circuit board on which they are mounted. For example, in this embodiment, the first charge / discharge FETs 21 to the eighth charge / discharge FETs 28 are mounted on the circuit board 30 described later. In this example, the first charge / discharge FET 21, the third charge / discharge FET 23, the fifth charge / discharge FET 25, and the seventh charge / discharge FET 27 correspond to FETs for charging, while the second charge / discharge FET 22, the fourth charge / discharge FET 24, the sixth charge / discharge FET 26, and the eighth charge / discharge FET 28 correspond to FETs for discharging. (Circuit board 30)

[0032] The circuit board 30 shown in Figure 2A comprises a first terminal block 31 that electrically connects multiple charge / discharge FETs 20 to multiple secondary battery cells 10, and a second terminal block 32 formed spaced apart from the first terminal block 31. Existing circuit boards can be used for this circuit board 30, and in this embodiment, a 6-layer multilayer board is used. However, the circuit board 30 is not limited to 6 layers; it may have 5 layers or less, or 7 layers or more. Furthermore, while the thickness of each film is approximately 70 μm as an example, it can be adjusted as appropriate.

[0033] The shape of the circuit board 30 can be any shape, and in this embodiment, it is generally rectangular in shape, consisting of a short side 30a and a long side 30b when viewed from above. For example, the short side 30a is about 6 cm and the long side 30b is about 10 cm. However, the lengths of the short side 30a and the long side 30b can be adjusted as appropriate to suit the components to be mounted. (First terminal block 31 and second terminal block 32)

[0034] The first terminal block 31 and the second terminal block 32 are for inputting and outputting current. Figure 2A shows one embodiment of the first terminal block 31 and the second terminal block 32. As shown in this figure, the first terminal block 31 and the second terminal block 32 are through holes formed near the two short sides 30a, spaced apart from each other. A conductive pattern is provided around the through holes to form the terminal connection area. These first terminal block 31 and the second terminal block 32 function as current input and output sections, enabling large currents to flow across the entire surface of the circuit board 30, from the first terminal block 31 to the second terminal block 32, or from the second terminal block 32 to the first terminal block 31.

[0035] Furthermore, the first charge / discharge FET 21 and the third charge / discharge FET 23 are arranged on the first terminal block 31 side, and the second charge / discharge FET 22 and the fourth charge / discharge FET 24 are arranged on the second terminal block 32 side. The number of charge / discharge FETs 20 can be adjusted as appropriate according to the size of the circuit board. Therefore, in this embodiment, the fifth charge / discharge FET 25 and the seventh charge / discharge FET 27 are further arranged on the first terminal block 31 side, and the sixth charge / discharge FET 26 and the eighth charge / discharge FET 28 are arranged on the second terminal block 32 side.

[0036] As an example, between the first terminal block 31 and the second terminal block 32, the first charge / discharge FET 21, the third charge / discharge FET 23, the seventh charge / discharge FET 27, and the fifth charge / discharge FET 25 are arranged on the first terminal block 31 side, generally in a direction along the short side 30a of the circuit board 30. Here, the first charge / discharge FET 21 and the fifth charge / discharge FET 25 are arranged near the two long sides 30b, respectively. In addition, the third charge / discharge FET 23 and the seventh charge / discharge FET 27 are arranged between the first charge / discharge FET 21 and the fifth charge / discharge FET 25. In this case, the third charge / discharge FET 23 is placed on the first charge / discharge FET 21 side, and the seventh charge / discharge FET 27 is placed on the fifth charge / discharge FET 25 side.

[0037] These first charge / discharge FETs 21, third charge / discharge FET 23, seventh charge / discharge FET 27, and fifth charge / discharge FET 25 are arranged in close proximity to each other. They may also be arranged in a straight line in the alignment direction, or they may be arranged offset from each other. For example, among the first charge / discharge FET 21, third charge / discharge FET 23, seventh charge / discharge FET 27, and fifth charge / discharge FET 25, the charge / discharge FET whose source terminal S is closer to the first terminal block 31 is arranged closer to the first terminal block 31 than the other charge / discharge FETs.

[0038] In other words, the first charge / discharge FET 21 and the fifth charge / discharge FET 25 are positioned closer to the first terminal block 31 than the third charge / discharge FET 23 and the seventh charge / discharge FET 27. This arrangement shortens the distance between the source terminals S of the first charge / discharge FET 21 and the fifth charge / discharge FET 25, which are located further from the first terminal block 31, compared to when each charge / discharge FET is arranged in a straight line. This makes it easier for current to flow from the first terminal block 31 to the source terminals S of the first charge / discharge FET 21 and the fifth charge / discharge FET 25.

[0039] On the second terminal block 32 side, the second charge / discharge FET 22 is positioned opposite the first charge / discharge FET 21, the fourth charge / discharge FET 24 is positioned opposite the third charge / discharge FET 23, the sixth charge / discharge FET 26 is positioned opposite the fifth charge / discharge FET 25, and the eighth charge / discharge FET 28 corresponds to the seventh charge / discharge FET 27.

[0040] Similar to the first terminal block 31 side, the second charge / discharge FET 22, fourth charge / discharge FET 24, eighth charge / discharge FET 28, and sixth charge / discharge FET 26 are arranged in close proximity to each other. They may also be arranged in a straight line in the alignment direction, or they may be arranged offset from each other. Furthermore, among the second charge / discharge FET 22, fourth charge / discharge FET 24, eighth charge / discharge FET 28, and sixth charge / discharge FET 26, the charging FET whose source terminal S is closer to the second terminal block 32 may be arranged closer to the second terminal block 32 than the other charging FET.

[0041] On the other hand, as shown in Figure 2A, the four charge / discharge FETs 21, 23, 27, and 25 on the first terminal block 31 and the corresponding four charge / discharge FETs 22, 24, 28, and 26 on the second terminal block 32 are spaced apart from each other. In a configuration such as the circuit board 30 where inputs and outputs are determined in one place by terminal blocks, for example, the heat generated at the drain terminals D of each charge / discharge FET 21 to 28 may become excessive. In such a case, if each charge / discharge FET 21 to 28 is placed in the central part of the board with the drain terminals D close together, there is a risk that a part of the board will overheat excessively. Therefore, as in this embodiment, by placing each charge / discharge FET 21 to 28 near the first terminal block 31 or the second terminal block 32, spaced apart from each other, the concentration of heat is avoided while ensuring safety.

[0042] Furthermore, the charging and discharging FETs 21-28 are connected in parallel, with the first charging and discharging FET 21 on the first terminal block 31 side connected in parallel with the third charging and discharging FET 23, the fifth charging and discharging FET 25, and the seventh charging and discharging FET 27. Similarly, the second charging and discharging FET 22 on the second terminal block 32 side connected in parallel with the fourth charging and discharging FET 24, the sixth charging and discharging FET 26, and the eighth charging and discharging FET 28. In addition, the first charging and discharging FET 21 is connected in series with the second charging and discharging FET 22, the third charging and discharging FET 23 with the fourth charging and discharging FET 24, the fifth charging and discharging FET 25 with the sixth charging and discharging FET 26, and the seventh charging and discharging FET 27 with the eighth charging and discharging FET 28. [Differentiation]

[0043] In this embodiment, an example has been described in which the charge / discharge FETs 21-28 are arranged so that their drain terminals face each other in a plan view. However, the arrangement of the charge / discharge FETs in this embodiment is not limited to the above configuration, and it goes without saying that, for example, the positions of the charge FET 20C and the discharge FET 20D may be swapped in Figure 1. Such an example is shown in the circuit diagram of Figure 2B as a modified power supply device. In the circuit board 30' shown in this figure, the charge / discharge FETs 21-28 are arranged so that their source terminals face each other in a plan view. (First current path 41 to fourth current path 44)

[0044] The first current paths 41 to the fourth current paths 44 are formed by connecting the charge / discharge FET on the first terminal block 31 side and the charge / discharge FET on the second terminal block 32 side in series, as shown in Figure 3. Specifically, the first current path 41 is formed by the first charge / discharge FET 21 and the second charge / discharge FET 22. Similarly, the second current path 42 is formed by the third charge / discharge FET 23 and the fourth charge / discharge FET 24, the third current path 43 is formed by the fifth charge / discharge FET 25 and the sixth charge / discharge FET 26, and the fourth current path 44 is formed by the seventh charge / discharge FET 27 and the eighth charge / discharge FET 28. Current flows along these first current paths 41 to the fourth current paths 44 from the first terminal block 31 side to the second terminal block 32 side, or from the second terminal block 32 side to the first terminal block 31 side. In this embodiment, an example in which current flows from the first terminal block 31 side to the second terminal block 32 side is described, but it goes without saying that the embodiment is not limited to this configuration.

[0045] The positional relationship between the first current path 41 and the fourth current path 44 is such that the first current path 41 and the third current path 43 are formed near the ends of the two long sides 30b of the circuit board 30, respectively. The second current path 42 and the fourth current path 44 are formed between the first current path 41 and the third current path 43. In other words, the first current path 41 and the third current path 43 are formed further away from the first terminal block 31 and the second terminal block 32 compared to the second current path 42 and the fourth current path 44. Due to this arrangement, the first current path 41 and the third current path 43 are of similar length, and are formed to be longer than the second current path 42. The fourth current path 44 is formed to be of the same length as the second current path 42.

[0046] In the configuration shown in Figure 3, where terminal blocks are provided at both ends of the short side 30a of the circuit board 30, and multiple FETs are placed close to each terminal block, a problem of current uneven distribution can occur. This is because current tends to flow through the shortest path and the path with the lowest resistance in the input / output section. Therefore, current tends to flow through the shortest paths, the second current path 42 and the fourth current path 44, while current does not flow through the first current path 41 and the third current path 43. In other words, current tends to concentrate in the third charge / discharge FET 23, the fourth charge / discharge FET 24, the seventh charge / discharge FET 27, and the eighth charge / discharge FET 28, which are located on the second current path 42 and the fourth current path 44. As a result, current uneven distribution occurs in some of the charge / discharge FETs during charging and discharging, exceeding the current rating of the charge / discharge FETs and potentially leading to thermal breakdown of the charge / discharge FETs. Therefore, a current inhibition region 50, described later, is provided to suppress current uneven distribution. (First current inhibition region 51 to fourth current inhibition region 54)

[0047] The current-blocking region 50 obstructs the flow of current by its electrical resistance 50R, which indicates its resistance value. The number and size of the current-blocking regions 50 can be adjusted as appropriate. In this embodiment, the current-blocking regions 50 consist of a first current-blocking region 51 to a fourth current-blocking region 54. As shown in Figure 3, the first current path 41 has a first current-blocking region 51 which includes a first electrical resistance 51R. Similarly, the second current path 42 has a second current-blocking region 52 which includes a second electrical resistance 52R, the third current path 43 has a third current-blocking region 53 which includes a third electrical resistance 53R, and the fourth current path 44 has a fourth current-blocking region 54 which includes a fourth electrical resistance 54R. The first electrical resistances 51R to the fourth electrical resistances 54R are adjusted so that the second electrical resistance 52R of the second current-blocking region 52 is higher than the first electrical resistance 51R of the first current-blocking region 51. Furthermore, the third electrical resistance 53R of the third current inhibition region 53 is made equivalent to the first electrical resistance 51R. In addition, the fourth electrical resistance 54R of the fourth current inhibition region 54 is made equivalent to the second electrical resistance 52R.

[0048] In other words, the second electrical resistance 52R of the second current-blocking region 52 and the fourth electrical resistance 54R of the fourth current-blocking region 54 are made higher than the first electrical resistance 51R of the first current-blocking region 51 and the third electrical resistance 53R of the third current-blocking region 53. As a result, current flows more easily through the low-resistance paths of the first current path 41 and the third current path 43. Consequently, more current flows through the first charge / discharge FET 21, second charge / discharge FET 22, fifth charge / discharge FET 25, and sixth charge / discharge FET 26 in the first current path 41 and the third current path 43, which are less prone to current flow, thus suppressing current uneven distribution. Furthermore, by suppressing current concentration, it is possible to avoid excessive heat generation in the third charge / discharge FET 23, fourth charge / discharge FET 24, seventh charge / discharge FET 27, and eighth charge / discharge FET 28, and to suppress heat generation evenly. (Thermal Via 60)

[0049] As described above, there are various ways to adjust the first electrical resistance 51R to the fourth electrical resistance 54R, such as changing the width, thickness, and material of the conductive pattern in each current-inhibiting region. In this embodiment, an example using thermal vias 60 will be described. Figure 3 shows one embodiment of thermal vias 60. As shown in this figure, thermal vias 60 are multiple through holes formed in the circuit board 30. The method for forming thermal vias 60 can be a known method; for example, in this embodiment, they are formed by drilling holes. This allows thermal vias 60 to be formed in a simple manner. The hole diameter is generally 0.3 mm to 0.5 mm, but it can be adjusted as appropriate according to the size of the circuit board and the arrangement of each charge / discharge FET, etc.

[0050] The number of thermal vias 60 in the second current-blocking region 52 is greater than the number of thermal vias 60 in the first current-blocking region 51. By increasing the number of thermal vias 60 in the second current-blocking region 52, the area of ​​the circuit board 30 in the second current-blocking region 52 can be reduced. In other words, since the area over which current flows is reduced, the second electrical resistance 52R can be increased, making it more difficult for current to flow through the second current path 42.

[0051] Similarly, the number of thermal vias 60 in the fourth current-blocking region 54 is greater than the number of thermal vias 60 in the third current-blocking region 53. By increasing the number of thermal vias 60 in the fourth current-blocking region 54, the area of ​​the circuit board 30 in the fourth current-blocking region 54 is reduced, the fourth electrical resistance 54R is increased, and it becomes more difficult for current to flow through the fourth current path 44. In this way, the resistance value of each current path can be easily adjusted by changing the number of thermal vias 60 formed.

[0052] The number of thermal vias 60 can be adjusted as appropriate depending on the size of the circuit board, the number and size of the charge / discharge FETs to be mounted, and the arrangement of each mounted component. For example, in this embodiment, approximately 30 to 40 thermal vias 60 are formed in the first current inhibition region 51 and the third current inhibition region 53, and approximately 80 to 90 thermal vias are formed in the second current inhibition region 52 and the fourth current inhibition region 54.

[0053] Furthermore, while thermal vias are typically used to improve heat dissipation, in this embodiment, a large number of thermal vias are deliberately formed to increase the resistance. In this way, the electrical resistance can be adjusted with the simple process of drilling holes, and the advantage of improved heat dissipation can also be obtained. [Embodiment 2]

[0054] In Embodiment 1, the thermal vias 60 are formed aligned vertically and horizontally in the plan view shown in Figures 2A and 3. However, the thermal vias in the embodiments of the present invention are not limited to the above configuration. For example, in Embodiment 2, as shown in Figure 4, a plurality of thermal vias 60B are formed offset from each other. This arrangement allows for the even distribution of thermal vias 60B across each current-inhibiting region, further suppressing current uneven distribution. [Embodiment 3]

[0055] Furthermore, in Embodiment 1, the hole diameters of the thermal vias 60 are generally the same, but the thermal vias in the embodiments of the present invention are not limited to the above-described form. For example, in Embodiment 3, as shown in Figure 5, the hole diameters of the thermal vias 60C are not the same, and the hole diameters of the thermal vias 60C in the second current inhibition region 52C and the fourth current inhibition region 54C are larger than the hole diameters of the thermal vias 60C in the first current inhibition region 51C and the third current inhibition region 53C. In other words, the area of ​​the circuit board 30 in the second current inhibition region 52C of the second current path 42 and the fourth current inhibition region 54C of the fourth current path 44, where current tends to concentrate, is smaller than that of the first current inhibition region 51C and the third current inhibition region 53C.

[0056] This increases the second electrical resistance 52R and the fourth electrical resistance 54R, allowing more current to flow through the first current path 41 and the third current path 43, which are less prone to current flow, thereby suppressing current uneven distribution. In other words, the resistance value of each current path can be easily adjusted by changing the area of ​​the opening of the thermal via 60C. Furthermore, in Embodiment 3, the electrical resistance can be increased simply by increasing the hole diameter of the thermal via, thus eliminating the need to form a large number of thermal vias. [Embodiment 4]

[0057] Furthermore, while the thermal via 60 is generally circular in shape in Embodiment 1, the thermal via in the embodiments of the present invention is not limited to the above shape. For example, it can be generally rectangular, as shown in the thermal via 60D of Embodiment 4 in Figure 6. [Industrial applicability]

[0058] The power supply device according to the present invention can be suitably used as a backup power supply device that can be mounted on the power supply module of a computer server. It can also be appropriately used as a backup power supply device for wireless base stations such as mobile phones, a power supply for energy storage in homes and factories, a power supply for streetlights, an energy storage device combined with solar cells, a backup power supply for traffic lights, or a power supply for plug-in hybrid electric vehicles, hybrid electric vehicles, electric vehicles, etc., that can switch between EV driving mode and HEV driving mode. [Explanation of symbols]

[0059] 100...Power supply device 10…Secondary battery cell 20…Charge / discharge FET; 20C…Charge FET; 20D…Discharge FET 21...First charge / discharge FET 22…Second charge / discharge FET 23…Third charge / discharge FET 24…Fourth charge / discharge FET 25…Fifth charge / discharge FET 26…Sixth charge / discharge FET 27...Seventh charge / discharge FET 28...Eighth charge / discharge FET 30, 30'... Circuit board 30a... Short side 30b...longer side 31...First terminal block 32…Second terminal block 41...First current path 42...Second current path 43...Third current path 44...Fourth current path 50...Current inhibition region 50R…Electrical resistance 51, 51C...first current inhibition region 51R...First Electrical Resistor 52, 52C...Second current inhibition region 52R…Second electrical resistance 53, 53C...Third current inhibition region 53R…Third electrical resistance 54, 54C...Fourth current inhibition region 54R…Fourth electrical resistance 60, 60B, 60C, 60D… Thermal vias

Claims

1. Multiple secondary battery cells, Multiple semiconductor elements connected to the aforementioned multiple secondary battery cells, A circuit board comprising a first terminal block on which the plurality of semiconductor elements are mounted and which electrically connects the plurality of semiconductor elements to the plurality of secondary battery cells, and a second terminal block formed spaced apart from the first terminal block, A power supply device comprising, The aforementioned plurality of semiconductor elements are The first semiconductor element and the third semiconductor element are arranged on the first terminal block side. The second semiconductor element and the fourth semiconductor element are arranged on the second terminal block side. Equipped with, The first semiconductor element and the third semiconductor element are connected in parallel. The second semiconductor element and the fourth semiconductor element are connected in parallel. The first semiconductor element and the second semiconductor element are connected in series to form a first current path. The third semiconductor element and the fourth semiconductor element are connected in series to form a second current path. The first current path and the second current path are connected in parallel to each other. The first semiconductor element is positioned close to the first terminal block on a straight line in the alignment direction between the first and third semiconductor elements, and / or the second semiconductor element is positioned close to the second terminal block on a straight line in the alignment direction between the second and fourth semiconductor elements. The first current path is formed to be longer than the second current path. The first current path includes a first current inhibiting region that inhibits the flow of current between the first semiconductor element and the second semiconductor element. The second current path includes a second current-blocking region that obstructs the flow of current between the third semiconductor element and the fourth semiconductor element. A power supply device in which the second electrical resistance of the second current-inhibiting region is higher than the first electrical resistance of the first current-inhibiting region.

2. A power supply device according to claim 1, The first current-inhibiting region and the second current-inhibiting region form a plurality of thermal vias that penetrate the circuit board. A power supply device wherein the number of thermal vias formed in the second current-inhibiting region is greater than the number of thermal vias formed in the first current-inhibiting region.

3. A power supply device according to claim 1 or 2, further, The aforementioned plurality of semiconductor elements are The fifth semiconductor element located on the first terminal block side, The sixth semiconductor element, which is located on the second terminal block side, Equipped with, The fifth semiconductor element is connected in parallel with the first semiconductor element. The sixth semiconductor element is connected in parallel with the second semiconductor element, The third current path connecting the fifth semiconductor element and the sixth semiconductor element in series is formed to be longer than the second current path. The aforementioned third current path includes a third current-inhibiting region that obstructs the flow of current. A power supply device in which the third electrical resistance in the third current inhibition region is made equal to the first electrical resistance.

4. The power supply device according to claim 3, wherein the third current inhibition region forms a plurality of thermal vias that penetrate the circuit board, A power supply device wherein the number of thermal vias formed in the third current-inhibiting region is equal to the number of thermal vias formed in the first current-inhibiting region.

5. A power supply device according to any one of claims 1 to 4, further, The aforementioned plurality of semiconductor elements are The seventh semiconductor element, which is located on the first terminal block side, The eighth semiconductor element, which is located on the second terminal block side, Equipped with, The seventh semiconductor element is connected in parallel with the first semiconductor element, The eighth semiconductor element is connected in parallel with the second semiconductor element, The fourth current path connecting the seventh semiconductor element and the eighth semiconductor element in series is formed to be of the same length as the second current path. The fourth current path is provided with a fourth current-inhibiting region that obstructs the flow of current. A power supply device wherein the fourth electrical resistance in the fourth current-inhibiting region is made equal to the second electrical resistance.

6. The power supply device according to claim 5, wherein the fourth current inhibition region forms a plurality of thermal vias that penetrate the circuit board, A power supply device wherein the number of thermal vias formed in the fourth current-inhibiting region is equal to the number of thermal vias formed in the second current-inhibiting region.

7. A power supply device according to claim 1, The first current-inhibiting region and the second current-inhibiting region each form a thermal via that penetrates the circuit board. A power supply device that adjusts the electrical resistance by the area of ​​the opening of the thermal via.

8. A power supply device according to any one of claims 1 to 7, The first semiconductor element and the third semiconductor element are arranged in close proximity. The power supply device wherein the second semiconductor element and the fourth semiconductor element are arranged in close proximity.

9. A power supply device according to any one of claims 1 to 8, The first and second terminal blocks are power supply devices with through-holes.

10. A power supply device according to any one of claims 1 to 9, A power supply device in which the aforementioned plurality of semiconductor elements are FETs.

11. A power supply device according to claim 10, A power supply device comprising the first semiconductor element and the third semiconductor element, wherein the source terminal of the FET of the first semiconductor element is positioned closer to the first terminal block than the source terminal of the FET of the third semiconductor element.

12. A power supply device according to claim 10, A power supply device wherein, among the second and fourth semiconductor elements, the source terminal of the FET of the second semiconductor element is positioned closer to the second terminal block than the source terminal of the FET of the fourth semiconductor element.

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