Indication device

Abstract

Provided is a display device with little chromaticity variation and good gradation control characteristics. This is a display device capable of carrying out PAM and PWM control (pulse width control involving changes in amplitude) on light emitted by a light emitting device, and capable of improving control characteristics on the low-gradation side while minimizing the amount of variation in chromaticity. The display device has a pulse signal generation unit and a light emission control unit in each pixel, and after the light emission control unit has been charged to a signal potential, can cause the signal potential to be discharged in response to a pulse signal generated by the pulse signal generation unit. Consequently, a light emitting device can be caused to emit light for a desired period of time at a desired light emission intensity.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, their operating methods, or their manufacturing methods.

[0003] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] Display devices and lighting devices equipped with micro light-emitting diodes (hereinafter, micro LEDs (LED: Light Emitting Diode)) have been proposed (for example, Patent Document 1). A display device equipped with micro LEDs can display with high brightness, has high reliability, and is promising as a next-generation display.

[0005] In addition, a technique for constructing a transistor using a metal oxide formed on a substrate has attracted attention. For example, techniques for using a transistor using zinc oxide or an In-Ga-Zn-based oxide as a switching element of a pixel of a display device are disclosed in Patent Document 2 and Patent Document 3.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2014 / 0367705 [Patent Document 2] Japanese Patent Publication No. 2007-123861 [Patent Document 3] Japanese Patent Publication No. 2007-96055 [Overview of the project] [Problems that the invention aims to solve]

[0007] In display devices using light-emitting devices (also called light-emitting elements), the brightness can be changed by controlling the current flowing through the light-emitting device. However, LEDs, one type of light-emitting device, have the characteristic that their chromaticity changes easily depending on the current density.

[0008] Therefore, controlling the brightness of an LED using pulse amplitude modulation (PAM) can result in poor color reproduction. Consequently, it is preferable to use pulse width modulation (PWM) control, which controls brightness by the duty cycle, to drive the LED. PWM control allows for a constant current density, enabling brightness adjustment without causing chromaticity shifts.

[0009] On the other hand, due to the transistors driving the LEDs and the response characteristics of the LEDs themselves, there is a lower limit to the duty cycle that can be stably controlled. Therefore, PWM control of LEDs has the problem of being difficult to control at lower grayscale levels where the duty cycle becomes smaller.

[0010] Therefore, one aspect of the present invention aims to provide a display device with small chromaticity changes and high gradation controllability. Alternatively, one aspect aims to provide a display device having a pixel circuit that generates pulse signals. Alternatively, one aspect aims to provide a display device having a pixel circuit capable of PAM control and PWM control. Alternatively, one aspect aims to provide a display device with excellent display characteristics. Alternatively, one aspect aims to provide a narrow-bezel display device.

[0011] Alternatively, one of the objectives is to provide a low-power display device. Alternatively, one of the objectives is to provide a highly reliable display device. Alternatively, one of the objectives is to provide a novel display device, etc. Alternatively, one of the objectives is to provide an operating method for the above-mentioned display device. Alternatively, one of the objectives is to provide a novel semiconductor device, etc.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One aspect of the present invention relates to a display device having a pixel circuit capable of PAM control and PWM control.

[0014] A first aspect of the present invention is a display device having a pulse signal generation unit and a light emission control unit in a pixel, wherein the light emission control unit has a light-emitting device, and causes the light-emitting device to emit light in accordance with the data potential charged in the light emission control unit, and discharges the data potential in accordance with the pulse signal generated by the pulse signal generation unit, causing the light-emitting device to turn off.

[0015] A second aspect of the present invention is a display device having a pulse signal generation unit, a first transistor, a second transistor, a third transistor, and a light-emitting device in a pixel, wherein the gate of the first transistor is electrically connected to one of the source or drain of the second transistor and one of the source or drain of the third transistor, one of the source or drain of the first transistor is electrically connected to one electrode of the light-emitting device, the gate of the third transistor is electrically connected to the pulse signal generation unit, a first data potential is charged to the gate of the first transistor via the second transistor to cause the light-emitting device to emit light, the third transistor is made to conduct in accordance with the pulse signal generated by the pulse signal generation unit, and the first data potential charged to the gate of the first transistor is discharged to turn off the light-emitting device.

[0016] The pulse signal generation unit includes a fourth transistor, a fifth transistor, and a sixth transistor. One of the sources or drains of the fourth transistor can be electrically connected to one of the sources or drains of the fifth transistor and the gate of the third transistor. The gate of the fourth transistor can also be electrically connected to one of the sources or drains of the sixth transistor.

[0017] A sloped signal potential can be input to the fourth transistor, a reset potential can be input to the fifth transistor, and a second data potential can be input to the sixth transistor.

[0018] Furthermore, a third aspect of the present invention is a display device comprising first to sixth transistors, a first capacitor, a second capacitor, and a light-emitting device, wherein the gate of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the third transistor, and one of the electrodes of the first capacitor, one of the source or drain of the first transistor is electrically connected to one of the electrodes of the light-emitting device and the other electrode of the first capacitor, the gate of the third transistor is electrically connected to one of the source or drain of the fourth transistor and one of the source or drain of the fifth transistor, and the gate of the fourth transistor is electrically connected to one of the source or drain of the sixth transistor and one of the electrodes of the second capacitor.

[0019] In the second and third embodiments of the present invention, a seventh transistor may be included, wherein one of the sources or drains of the seventh transistor may be electrically connected to the one of the sources or drains of the first transistor.

[0020] The first to third transistors, the fifth transistor, and the sixth transistor are all n-channel transistors, while the fourth transistor can be a p-channel transistor.

[0021] In this case, it is preferable that the first transistor, the second transistor, the fifth transistor, and the sixth transistor each have a metal oxide in their channel formation region, and the third transistor and the fourth transistor each have silicon in their channel formation region.

[0022] Alternatively, the second, fourth, and sixth transistors may each be n-channel transistors, and the first, third, and fifth transistors may each be p-channel transistors.

[0023] In this case, it is preferable that the second transistor, the fourth transistor, and the sixth transistor each have a metal oxide in their channel formation region, and the first transistor, the third transistor, and the fifth transistor each have silicon in their channel formation region.

[0024] The light-emitting device is preferably a mini-LED or micro-LED. [Effects of the Invention]

[0025] By using one aspect of the present invention, a display device with small chromaticity changes and high gradation controllability can be provided. Alternatively, a display device having a pixel circuit that generates pulse signals can be provided. Alternatively, a display device having a pixel circuit capable of PAM control and PWM control can be provided. Alternatively, a display device having excellent display characteristics can be provided. Alternatively, a narrow-bezel display device can be provided.

[0026] Alternatively, a low-power display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a method for operating the above-mentioned display device can be provided. Alternatively, a novel semiconductor device can be provided. [Brief explanation of the drawing]

[0027] Figure 1 is a diagram illustrating the pixel circuit. Figures 2A and 2B illustrate the display device. Figure 3 is a timing chart illustrating the operation of the pixels. Figures 4A and 4B illustrate the operation of the pixel circuit. Figures 5A and 5B illustrate the operation of the pixel circuit. Figures 6A to 6C illustrate modified examples of the pixel circuit. Figure 7 is a diagram illustrating the pixel circuit. Figure 8 is a timing chart illustrating the operation of the pixel circuit. Figures 9A and 9B illustrate the operation of the pixel circuit. Figures 10A and 10B illustrate the operation of the pixel circuit. Figures 11A to 11C illustrate modified examples of the pixel circuit. Figure 12A shows the relationship between gray level and brightness. Figure 12B explains the operation in response to brightness using the light intensity and light emission time of the light-emitting device. Figures 13A and 13B illustrate the range of chromaticity shift. Figures 14A and 14B illustrate the pixel circuit. Figure 15 is a block diagram illustrating the display device. Figure 16 is a diagram illustrating the pixel circuit used in the simulation. Figures 17A and 17B illustrate the simulation results. Figures 18A and 18B illustrate the display device. Figure 19 is a diagram illustrating a display device. Figure 20 is a diagram illustrating a display device. Figures 21A and 21B illustrate the display device. Figures 22A to 22D illustrate electronic devices. [Modes for carrying out the invention]

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0029] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0030] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0031] (Embodiment 1) In this embodiment, a display device that is one aspect of the present invention will be described with reference to the drawings.

[0032] One aspect of the present invention is a display device that can control the emission of light from a light-emitting device using PAM+PWM control (pulse width control with amplitude change). The display device has a pulse signal generation unit and a light emission control unit in each pixel, and after charging the light emission control unit with a signal potential, the signal potential can be discharged according to the pulse signal generated by the pulse signal generation unit. Therefore, the light-emitting device can emit light at a desired light intensity for a desired period of time.

[0033] In this embodiment, PAM control refers to controlling brightness by keeping the light emission time (corresponding to the width of the pulse signal generated by the pixel) constant and changing the light emission intensity (corresponding to the current flowing through the light-emitting device). PWM control refers to controlling brightness by keeping the light emission intensity constant and changing the light emission time.

[0034] LEDs, a type of light-emitting device, have the characteristic that their chromaticity changes depending on the current density, making PAM control unsuitable in some cases. On the other hand, PWM control has the problem of being difficult to control low gradation due to the influence of the response characteristics of the drive transistor and the LED. In one embodiment of the present invention, a display device can perform a display operation that combines PWM control and PAM control in order to mitigate these problems.

[0035] For example, the low- and high-gradation sides can be displayed using PAM control, while the intermediate tones can be displayed using PWM control. This operation allows for improved controllability of the low-gradation side while minimizing the amount of chromaticity change. However, the display device according to one aspect of the present invention is not limited to this, and the LED light emission operation can be performed across a wide gradation range using only PAM control or only PWM control.

[0036] <Configuration Example 1> Figure 1 is a circuit diagram of a pixel 10a in a display device according to one aspect of the present invention. The pixel 10a can be broadly divided into a pulse signal generation unit 11 and a light emission control unit 12.

[0037] The pulse signal generation unit 11 may include transistor 101, transistor 102, transistor 103, and capacitor 111. Here, transistor 101 can be a p-channel transistor. Although Figure 1 shows an example in which n-channel transistors are used for the other transistors, the transistor that functions as a switch may also be a p-channel transistor.

[0038] The light emission control unit 12 includes transistors 104, 105, 106, and 107, a capacitor 112, and a light-emitting device 110. While Figure 1 shows an example where n-channel transistors are used for transistors 104 to 107, the transistor functioning as a switch may be a p-channel transistor. Furthermore, while an LED (e.g., a micro-LED or mini-LED) is preferred for the light-emitting device 110, an organic EL element can also be used.

[0039] In the pulse signal generation unit 11, one of the source or drain of transistor 101 is electrically connected to one of the source or drain of transistor 102 and the gate of transistor 106 in the light emission control unit 12. The gate of transistor 101 is electrically connected to one electrode of capacitor 111 and one of the source or drain of transistor 103.

[0040] Here, node N is defined as the point (wiring or electrode, etc.) connecting the gate of transistor 101, one electrode of capacitor 111, and one of the source or drain of transistor 103. Also, node W is defined as the point (wiring or electrode, etc.) connecting one of the source or drain of transistor 101, one of the source or drain of transistor 102, and the gate of transistor 106.

[0041] In the light emission control unit 12, the gate of transistor 104 is electrically connected to one of the source or drain of transistor 105, one electrode of capacitor 112, and one of the source or drain of transistor 106. One of the source or drain of transistor 104 is electrically connected to one of the source or drain of transistor 107, the other electrode of capacitor 112, and one electrode (anode) of light emission device 110.

[0042] Here, node A is defined as the point (wiring or electrode, etc.) connecting the gate of transistor 104, either the source or drain of transistor 105, one electrode of capacitor 112, and either the source or drain of transistor 106.

[0043] The connection relationships between each transistor and the wiring are as follows: The other source or drain of transistor 101 is electrically connected to wiring 123. The other source or drain of transistor 102 is electrically connected to wiring 124. The other source or drain of transistor 103 is electrically connected to wiring 121. The other source or drain of transistor 104 is electrically connected to wiring 125. The other source or drain of transistor 105 is electrically connected to wiring 122. The other source or drain of transistor 106 is electrically connected to wiring 128. The other source or drain of transistor 107 is electrically connected to wiring 126. The other electrode of capacitor 111 is electrically connected to wiring 127. The other electrode (cathode) of light-emitting device 110 is electrically connected to wiring 129. The gate of transistor 102 is electrically connected to wiring 132. The gate of transistor 103 is electrically connected to wiring 131. The gate of transistor 105 is electrically connected to wiring 133. The gate of transistor 107 is electrically connected to wiring 134.

[0044] Wires 121, 123, and 124 are for supplying signal potentials for PWM control. Wire 121 is a first source line that supplies a signal potential to determine the pulse width and can be electrically connected to a first source driver. Wire 123 is for supplying a slope signal and can be electrically connected to a slope potential generation circuit. Wire 124 is for supplying a reset potential to node W.

[0045] In this specification, slope potential refers to a type of ramp wave, which is a slope-shaped signal potential that changes in potential from high to low or low to high.

[0046] Wiring 122 is a wire that supplies a signal potential for PAM control. Wiring 122 is a second source wire that supplies a signal potential that determines the amplitude (voltage), and can be electrically connected to a second source driver.

[0047] Wires 131 to 134 are gate wires for controlling the conduction or non-conductivity of each transistor and can be electrically connected to a gate driver. Wires 131 to 134 may also be common wires. Wires 125 and 129 are power lines, with wire 125 being a high-potential power line and wire 129 being a low-potential power line. Wire 126 is a wire for supplying a reset potential to fix the source potential of transistor 104. Wire 128 is a fixed-potential wire and can supply a potential smaller than the smallest signal potential supplied from wire 122. Wire 127 is a fixed-potential wire and can be, for example, a low-potential wire. Note that one of wires 124, 126, 127, 128, and 129 may be common wires with one or more of the others.

[0048] Here, transistors 102, 103, 105, and 107 function as switches. Transistors 101 and 106 have the function of generating pulse signals. Transistor 104 functions as a drive transistor for the light-emitting device 110 and performs switching operations according to the generated pulse signal. The amplitude of the pulse signal can be varied by the signal potential input from wiring 122. Capacitors 111 and 112 function as holding capacitances.

[0049] As the transistors 101 to 107 described above, transistors having silicon in the channel formation region (hereinafter referred to as Si transistors) or transistors having metal oxide in the channel formation region (hereinafter referred to as OS transistors) can be used. Furthermore, both Si transistors and OS transistors can be used.

[0050] For example, in the circuit configuration shown in Figure 1, it is preferable to use Si transistors for transistors 101 and 106 and OS transistors for the other transistors. Since OS transistors can be provided in the wiring layer process on top of the Si transistors, the integration density can be increased.

[0051] Since transistor 101 is a p-channel type transistor, it can be easily formed from a Si transistor. Furthermore, because transistor 106 preferably has rapid charge / discharge characteristics, it is preferable that it be a transistor with a large transconductance (gm). Since Si transistors have relatively high mobility, they can be used as transistors with a large gm. Note that an OS transistor may also be used for transistor 106.

[0052] OS transistors are suitable for use as the drive transistor (transistor 104) of the light-emitting device 110 because they have better drain current saturation characteristics even with shorter channel lengths compared to Si transistors.

[0053] Furthermore, because OS transistors have a large energy gap in the semiconductor layer, they can exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm channel width). This low off-current enhances the node's potential retention capability, allowing for proper image display even at lower frame frequencies. For example, by using a first frame frequency (e.g., 60 Hz or higher) for moving images and switching to a second frame frequency lower than the first (e.g., around 1 to 10 Hz) for still image displays, the display device can be made more power-efficient.

[0054] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0055] The OS transistor has characteristics different from those of a transistor having silicon in the channel formation region (hereinafter referred to as Si transistor), such as impact ionization, avalanche breakdown, and short channel effect not occurring, and can form a highly reliable circuit.

[0056] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn oxide can typically be formed by a sputtering method. Alternatively, it may be formed using the ALD (Atomic layer deposition) method.

[0057] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide by the sputtering method preferably satisfies In≥M and Zn≥M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0058] As the semiconductor layer, an oxide semiconductor with a low carrier concentration is used. For example, the semiconductor layer has a carrier concentration of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, still more preferably 1×10 11 / cm 3 or less, even more preferably 1×10 10 / cm 3It is less than 1 × 10 -9 / cm 3 The above oxide semiconductors can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. These oxide semiconductors can be said to have a low defect level density and stable properties.

[0059] However, the invention is not limited to these examples, and an oxide semiconductor with an appropriate composition may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor required. Furthermore, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc., of the semiconductor layer appropriately.

[0060] In oxide semiconductors that constitute a semiconductor layer, the presence of silicon or carbon, which are Group 14 elements, increases oxygen vacancies and causes n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0061] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0062] Furthermore, if nitrogen is present in the oxide semiconductor constituting the semiconductor layer, electrons, which act as carriers, are generated, increasing the carrier concentration and making it easier for the transistor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻⁶. 18 atoms / cm 3 The following is preferable:

[0063] Furthermore, if the oxide semiconductor constituting the semiconductor layer contains hydrogen, it can react with oxygen bonded to metal atoms to form water, thus potentially creating oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor may exhibit normally-on characteristics. Moreover, a defect containing hydrogen can function as a donor, generating electrons as carriers. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics.

[0064] Defects where hydrogen fills an oxygen vacancy can function as donors in oxide semiconductors. However, quantitatively evaluating such defects is difficult. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0065] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount missing]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0066] Furthermore, the semiconductor layer may have a non-single-crystal structure, for example. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, while CAAC-OS has the lowest defect level density.

[0067] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0068] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0069] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS, which is one form of a non-single-crystal semiconductor layer.

[0070] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0071] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0072] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0073] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0074] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is an integer greater than or equal to 1), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is an integer greater than or equal to 1).

[0075] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0076] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0077] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0078] Note that GaO X3The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0079] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0080] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable; for example, an oxygen gas flow rate ratio of 0% or more and less than 30%, preferably 0% or more and 10% or less, is preferable.

[0081] CAC-OS is characterized by the absence of a clear peak when measured using the θ / 2θ scan method, an out-of-plane X-ray diffraction (XRD) measurement technique. In other words, X-ray diffraction measurements indicate that no orientation in the ab-plane direction or the c-axis direction of the measurement region is observed.

[0082] Furthermore, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness and multiple bright spots within this ring-shaped region are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0083] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0084] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0085] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1 In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, InX2 Zn Y2 O Z2 、 or InO X1 By the region mainly composed of [Zn, O, or InO] being distributed in a cloud shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0086] On the other hand, the region mainly composed of GaO X3 etc. is a region with high insulation compared to the region mainly composed of In X2 Zn Y2 O Z2 、 or InO X1 That is, by the region mainly composed of GaO X3 etc. being distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized.

[0087] Therefore, when using CAC-OS in a semiconductor device, the insulation caused by GaO X3 etc. and the conductivity caused by In X2 Zn Y2 O Z2 、 or InO X1 act complementarily to achieve a high on-current (I on ) and a high field-effect mobility (μ).

[0088] In addition, a semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0089] For the channel formation region of a Si transistor, amorphous silicon, microcrystalline silicon, polycrystalline silicon, single-crystalline silicon, etc. can be used. When providing a transistor on an insulating surface such as on a glass substrate, it is preferable to use polycrystalline silicon.

[0090] High-quality polycrystalline silicon can be easily obtained by using processes such as laser crystallization. Alternatively, high-quality polycrystalline silicon can also be obtained by solid-phase growth, which involves adding a metal catalyst such as nickel or palladium to amorphous silicon and heating it. Furthermore, the crystallinity of polycrystalline silicon formed by solid-phase growth using a metal catalyst may be further enhanced by laser irradiation. Since the metal catalyst remains in the polycrystalline silicon and degrades the electrical properties of the transistor, it is preferable to create regions outside the channel formation area where phosphorus or a noble gas is added, thereby trapping the metal catalyst in these regions.

[0091] Furthermore, to obtain the effects of one aspect of the present invention, the configuration is not limited to those described above; all transistors in the pixel may be formed from Si transistors. Alternatively, one or more transistors in the pixel may be formed from p-channel transistors.

[0092] Figure 2A shows an example of a display device having a stacked structure, and Figure 2B is an unfolded view and a partially enlarged view thereof. A display device having a stacked structure can be configured by sequentially stacking a layer 310 having a silicon substrate, a layer 320 having wiring, and a layer 330 having a light-emitting device. In this stacked structure, circuits can be formed by overlapping, so the display device can have a narrow bezel.

[0093] Layer 310 may have Si transistors 311 and functional circuits 312, which are components of the pixel circuit. Note that the Si transistors 311 can be placed in a region that does not interfere with the functional circuits 312. Layer 320 may have OS transistors 321, which are components of the pixel circuit. Layer 330 may have an LED array 331.

[0094] The LED array 331 has a configuration in which LEDs are arranged in a matrix. As LEDs, for example, microLEDs formed with a diameter or side length of 50 μm or less, or miniLEDs formed with a diameter or side length greater than 50 μm and 200 μm or less can be used.

[0095] The functional circuit 312 can include, for example, one or more of the following: a source driver, a gate driver, a memory circuit, an arithmetic circuit, and a power supply circuit. Note that some or all of the gate driver and memory circuit can be formed using OS transistors. Details of the stacked configuration will be described in Embodiment 2.

[0096] <How Configuration Example 1 works> Next, the operation of pixel 10a will be explained using the timing chart shown in Figure 3 and the circuit operation diagrams shown in Figures 4A to 5B. Note that the dashed arrows in Figures 4A to 5B indicate the potential supplied to the circuit, and the dotted arrows indicate the current (I) flowing through the light-emitting device 110. LED This shows that... Also, in timing charts, the switching of the supplied signal and the switching of the signal controlling the conduction and non-conductivity of the switch (transistor) are sometimes illustrated as occurring at the same time. In reality, these occur at different timings, and the changes in the potential of each node follow the explanation below.

[0097] First, at time T1, when a low potential ("L") is supplied to wires 131, 133, and 134 and a high potential ("H") is supplied to wire 132, transistor 102 conducts, and the potential VRESW (low reset potential) of wire 124 is supplied to node W (see Figure 4A). This operation is a reset operation of node W, and at this time, transistor 106 becomes non-conductive.

[0098] At time T2, when a high potential ("H") is supplied to wires 131, 133, and 134, and a low potential ("L") is supplied to wire 132, transistor 103 conducts, and the potential DATAW (data potential for determining the width of the generated pulse signal) of wire 121 is supplied to node N. Also, transistor 105 conducts, and the potential DATAA (data potential for determining the amplitude) is supplied to node A (the gate of transistor 104). At this time, transistor 107 is also conducting, so the source potential of transistor 104 becomes the reset potential supplied from wire 126, and an appropriate gate-source voltage (Vgs) can be written (see Figure 4B). Note that although transistor 104 conducts at this time, current flows through wire 126, so the light-emitting device 110 does not emit light.

[0099] At time T3, when a low potential ("L") is supplied to wirings 131, 132, 133, and 134, transistor 103 becomes non-conductive, and potential DATAW is held at node N. Also, transistor 105 becomes non-conductive, and potential DATAA is held at node A. Then, because transistor 107 becomes non-conductive, a current corresponding to potential DATAA flows from transistor 104 to light-emitting device 110, causing light-emitting device 110 to emit light.

[0100] Furthermore, from time T3, a slope potential SLO, which changes in the direction of increasing potential over time, is supplied to wiring 123. Figure 5A shows the state in transistor 101 where Vgs = potential DATAW - slope potential SLO, and |Vgs| < |Vth| (where Vth is the threshold voltage), i.e., the state when transistor 101 is not conducting. At this time, there is no change in the potential of node A, so the light emission of the light-emitting device 110 continues.

[0101] Then, as shown in Figure 5B, as the slope potential SLO rises further, for example after time T6, |Vgs| > |Vth|. At this time, transistor 101 conducts, so the potential of node W immediately rises to the slope potential SLO at that time, and transistor 106 also conducts. Then, the potential of node A is rapidly discharged from potential DATAA to potential VER of wiring 128 (potential VER < potential DATAA). At this time, transistor 104 becomes non-conductive, and the light-emitting device 110 turns off.

[0102] As described above, pixel 10a first emits light according to the potential DATAA written to node A. Then, the potential of node A is discharged according to the width of the pulse signal generated by potential DATAW and slope potential SLO, and the light emission is terminated.

[0103] In other words, it is possible to perform PAM control, which keeps the emission time constant and changes the emission intensity, or PWM control, which keeps the emission intensity constant and changes the emission time. Furthermore, since the emission time and emission intensity can be set arbitrarily, it can also be said that PAM+PWM control (pulse width control with amplitude changes) is possible.

[0104] <Variations of Configuration Example 1> Figures 6A to 6C show modified versions of the pixel 10a circuit shown in Figure 1.

[0105] Figure 6A shows an example in which a transistor 108 is added to pixel 10a shown in Figure 1. One source or drain of transistor 108 is electrically connected to one source or drain of transistor 106, and the other source or drain of transistor 108 is electrically connected to the gate of transistor 104. The gate of transistor 108 is electrically connected to wiring 135. Wiring 135 is a gate wire that controls the conduction and non-conductivity of transistor 108.

[0106] As mentioned above, for transistor 106, a Si transistor with a large gm is suitable for rapid discharge. On the other hand, from the viewpoint of maintaining the potential of node A, a transistor with a small off-current is preferable. Since Si transistors have a relatively large off-current, in the configuration shown in Figure 1, the potential of node A may not be sufficiently maintained depending on the operating method.

[0107] In such cases, it is preferable to provide a transistor 108 formed from an OS transistor. Because OS transistors have an extremely small off-current, the potential of node A can be maintained even when the off-current (leakage current) of transistor 106 is large. This is particularly effective for display devices that operate at a frame frequency of 10 Hz or less.

[0108] Figure 6B shows an example where the connection configuration of the light-emitting device 110 differs from that of the pixel 10a shown in Figure 1. LEDs can be used as light-emitting devices 110 in various forms, and if the cathode of the LED is in a form that is easy to connect to the pixel electrode, it is preferable to electrically connect the cathode of the light-emitting device 110 to the other side of the source or drain of the transistor 104, and to electrically connect the anode of the light-emitting device 110 to the wiring 125. In this configuration, the source of the transistor 104 can be connected to the wiring 129, which is a low-potential power line, so the transistor 107 can be omitted.

[0109] Figure 6C shows an example of modifying the connection configuration of transistor 105 to create a circuit dedicated to PWM control. In the configuration shown in Figure 1, any signal potential can be input to node A via transistor 105. However, in the configuration shown in Figure 6C, since the other end of either the source or drain of transistor 105 is electrically connected to wiring 125, a high-potential constant potential is input to node A. Therefore, node A is always charged at a constant potential and discharged according to the pulse signal, making it a circuit dedicated to PWM control.

[0110] <Configuration Example 2> Figure 7 is a circuit diagram of pixel 10b, which differs from that of pixel 10a in Configuration Example 1. Pixel 10b differs from pixel 10a in Configuration Example 1 in that the conductivity types of transistors 101 and 102 in the pulse signal generation unit 11 and transistors 104 and 106 in the light emission control unit 12 are different. It also differs in that it does not have transistor 107. Explanations common to Configuration Example 1 are omitted.

[0111] The pulse signal generation unit 11 may include transistor 101, transistor 102, transistor 103, and capacitor 111. Here, transistor 102 can be a p-channel transistor. Although Figure 7 shows an example in which n-channel transistors are used for the other transistors, the transistor that functions as a switch may also be a p-channel transistor.

[0112] The light emission control unit 12 includes transistors 104, 105, and 106, a capacitor 112, and a light-emitting device 110. Here, transistors 104 and 106 can be p-channel transistors. In Figure 7, an example is shown in which an n-channel transistor is used for transistor 105, but a p-channel transistor may also be used.

[0113] The configuration of the connections between transistors 101, 102, 103 and capacitor 111 in the pulse signal generation unit 11 is the same as that of pixel 10a.

[0114] In the light emission control unit 12, the gate of transistor 104 is electrically connected to one of the source or drain of transistor 105, one electrode of capacitor 112, and one of the source or drain of transistor 106. One of the source or drain of transistor 104 is electrically connected to one electrode (anode) of light emission device 110. The other of the source or drain of transistor 104 is electrically connected to the other electrode of capacitor 112.

[0115] The connection relationships between each transistor and each wiring, and the functions of each transistor, are the same as in pixel 10a. Wiring 128 is a fixed potential line and can supply a potential greater than the largest signal potential supplied from wiring 122. Any one of wirings 124, 125, or 128 may be common with any one or more of the others. Also, wirings 127 and 129 may be common wiring.

[0116] Since transistor 104 is a p-channel type, its source will be connected to wiring 125, which is a high-potential power line. Therefore, transistor 107 can be omitted.

[0117] As the transistors 101 to 106, Si transistors or OS transistors can be used. In particular, it is preferable to use a combination of Si transistors and OS transistors.

[0118] For example, in the circuit configuration shown in Figure 7, it is preferable to use Si transistors for transistors 102, 104, and 106, and OS transistors for the other transistors. OS transistors can be provided during the wiring layer process on top of the Si transistors.

[0119] <How Configuration Example 2 works> Next, the operation of pixel 10b will be explained using the timing chart shown in Figure 8 and the circuit operation diagrams shown in Figures 9A to 10B.

[0120] First, at time T1, when a low potential ("L") is supplied to wires 131, 132, and 133, transistor 102 conducts, and the potential VRESW (high potential reset potential) of wire 124 is supplied to node W (see Figure 9A). This operation is a reset operation of node W, and at this time, transistor 106 becomes non-conductive.

[0121] At time T2, when a high potential ("H") is supplied to wires 131, 132, and 133, transistor 103 conducts, and the potential DATAW (data potential for determining the width of the generated pulse signal) of wire 121 is supplied to node N. Also, transistor 105 conducts, and the potential DATAA (data potential for determining the amplitude) is supplied to node A (the gate of transistor 104). Then, a current corresponding to the potential DATAA flows from transistor 104 to the light-emitting device 110, and the light-emitting device 110 emits light (see Figure 9B).

[0122] Next, at time T3, when a low potential ("L") is supplied to wires 131 and 133 and a high potential ("H") to wire 132, transistor 103 becomes non-conductive, and potential DATAW is held at node N. Also, transistor 105 becomes non-conductive, and potential DATAA is held at node A.

[0123] Furthermore, from time T3, a slope potential SLO, which changes in the direction of decreasing potential over time, is supplied to wiring 123. Figure 10A shows the state in transistor 101 where Vgs = potential DATAW - slope potential SLO, and |Vgs| < |Vth| (where Vth is the threshold voltage), i.e., the state when transistor 101 is not conducting. At this time, there is no change in the potential of node A, so the light emission of the light-emitting device 110 continues.

[0124] Then, as shown in Figure 10B, as the slope potential SLO decreases further, for example after time T6, |Vgs| > |Vth|. At this time, transistor 101 conducts, so the potential of node W immediately decreases to the slope potential SLO at that time, and transistor 106 also conducts. Then, the potential of node A is quickly charged from potential DATAA to potential VER of wiring 128 (potential VER > potential DATAA). At this time, transistor 104 becomes non-conductive, so the light-emitting device 110 turns off.

[0125] As explained above, pixel 10b first emits light according to the potential DATAA written to node A. Then, it charges the potential of node A according to the width of the pulse signal generated by potential DATAW and slope potential SLO, and terminates the light emission.

[0126] <Modified version of configuration example 2> Figures 11A to 11C show modified versions of the pixel 10b circuit shown in Figure 7.

[0127] Figure 11A shows an example in which a transistor 108 is added to pixel 10b shown in Figure 7. One source or drain of transistor 108 is electrically connected to one source or drain of transistor 106, and the other source or drain of transistor 108 is electrically connected to the gate of transistor 104. The gate of transistor 108 is electrically connected to wiring 135. Wiring 135 is a gate wire that controls the conduction and non-conductivity of transistor 108.

[0128] As mentioned above, for rapid charging, it is suitable to use a Si transistor with a large gm for transistor 106. On the other hand, from the viewpoint of maintaining the potential of node A, a transistor with a small off-current is preferable. Since Si transistors have a relatively large off-current, in the configuration of Figure 7, depending on the operating method, the potential of node A may not be sufficiently maintained.

[0129] In such cases, it is preferable to provide a transistor 108 formed from an OS transistor. Because OS transistors have an extremely small off-current, the potential of node A can be maintained even when the off-current (leakage current) of transistor 106 is large. This is particularly effective for display devices that operate at a frame frequency of 10 Hz or less.

[0130] Figure 11B shows an example where the connection configuration of the light-emitting device 110 differs from that of the pixel 10b shown in Figure 7. LEDs can be used as light-emitting devices 110 in various forms, and if the cathode of the LED is in a form that is easy to connect to the pixel electrode, it is preferable to electrically connect the cathode of the light-emitting device 110 to the other side of the source or drain of the transistor 104, and to electrically connect the anode of the light-emitting device 110 to the wiring 125.

[0131] Figure 11C shows an example of modifying the connection configuration of transistor 105 to create a circuit dedicated to PWM control. In the configuration shown in Figure 7, any signal potential can be input to node A via transistor 105. However, in the configuration shown in Figure 11C, since the other end of either the source or drain of transistor 105 is electrically connected to the wiring 129, a low-potential constant potential is input to node A. Therefore, node A always discharges at a constant potential and charges according to the pulse signal, making it a circuit dedicated to PWM control.

[0132] <Effects> Figure 12A shows the relationship between the gray level (input value 8 bits) and brightness (output value) according to a gamma curve (gamma value = 2). In one embodiment of the present invention, pixels 10a and 10b can perform the input and output shown in Figure 12A, and the operation method can be switched within a desired range of the gray level.

[0133] For example, the low brightness range of 32 levels (equivalent to brightness levels 0 to 31) and the high brightness range of 128 levels (equivalent to brightness levels 128 to 255) can be operated using PAM control, while the intermediate range of 96 levels (equivalent to brightness levels 32 to 127) can be operated using PWM control. This operation allows for the display of images with minimal chromaticity shift. However, the operation method and switching timing can be set arbitrarily. It is also possible to operate using either PAM control or PWM control across the entire range.

[0134] Figure 12B illustrates the above operation using the light intensity and light duration of the light-emitting device. The numbers indicated inside the markers or through the arrows represent the input values ​​for the gray level.

[0135] The low-brightness 32-level gradation uses PAM control operation with a relatively short first light emission time. PAM control allows for control of the light emission intensity of the light-emitting device by controlling the amplitude, enabling precise control even at low brightness levels, which is difficult with PWM control.

[0136] The 96 intermediate levels utilize PWM control by varying the width of the pulse signal at a moderate, constant light intensity to illuminate the light-emitting device. Since the 96 intermediate levels do not require extremely short light emission periods (extremely short pulse signals), they can be controlled without problems using PWM control.

[0137] The high-brightness 128-level gradation uses a relatively long second emission time for PAM control operation to cause the light-emitting device to emit light.

[0138] Figure 13A illustrates an example of the change in peak wavelength when the brightness of a light-emitting device is changed in PAM control. In this characteristic, the difference between the minimum and maximum values ​​is the chromaticity shift range (R1). When light emission operation is performed with PAM control from low brightness to high brightness, the chromaticity shift is large, which can degrade the display quality.

[0139] Figure 13B illustrates an example of the change in the peak wavelength of the luminance of the light-emitting device when the operation described using Figures 12A and 12B is performed. Since PWM control is performed in the range near the minimum value in Figure 13A, the peak wavelength in that range can be made flat. Therefore, the range of chromaticity shift (R2) can be made smaller than R1. In other words, by using a display device according to one embodiment of the present invention and performing the operation in the above example, the deterioration of display quality can be mitigated.

[0140] In the configuration of pixels 10a and 10b, when an OS transistor is used as the n-channel transistor, a configuration with a back gate may be used, as shown in Figure 14A or Figure 14B. By supplying the same potential to the back gate as to the front gate, the on-current can be increased. Alternatively, a configuration that can supply a constant potential to the back gate may be used. By supplying a constant potential to the back gate, the threshold voltage can be controlled.

[0141] Figure 15 is a block diagram illustrating a display device according to one aspect of the present invention. The display device includes a pixel array 13, a first source driver 20a, a second source driver 20b, and a gate driver 30. The pixel array 13 has pixels 10 arranged in the column and row directions. The pixels 10 can be either pixels 10a or pixels 10b as described in this embodiment. Note that the wiring is shown in a simplified manner, and wiring is provided to connect to the elements of the pixels 10 according to the aforementioned aspect of the present invention.

[0142] Furthermore, a slope potential supply circuit 40 is provided and electrically connected to the pixel 10. The slope potential supply circuit 40 is electrically connected to the slope potential generation circuit 50.

[0143] The first source driver 20a, the second source driver 20b, the gate driver 30, and the slope potential supply circuit 40 can use sequential circuits such as shift registers. The first source driver 20a can supply potential DATAW to the pixel 10. The second source driver 20b can supply potential DATAA to the pixel 10.

[0144] The first source driver 20a, the second source driver 20b, the gate driver 30, and the slope potential supply circuit 40 can be formed on the layer 310 shown in Figures 2A and 2B. Alternatively, they can be provided on the connected IC chip using methods such as COF (chip on film), COG (chip on glass), or TCP (tape carrier package).

[0145] Although the example shown illustrates the gate driver 30 being located on one side of the pixel array 13, two gate drivers may be placed opposite each other across the pixel array 13 to divide the drive row.

[0146] <Simulation> Next, we will explain the simulation results regarding the operation of the pixels. Figure 16 shows the configuration of the pixel PIX used in the simulation. The pixel PIX has a configuration similar to the pixel circuit shown in Figure 1, with transistor Tr1 being a p-channel Si transistor and transistors Tr2 to Tr7 being n-channel OS transistors. Figure 16 also shows the potential supplied to each wiring.

[0147] The parameters used in the simulation are as follows: Transistor sizes were set to W / L = 3μm / 3μm (transistors Tr1, Tr2, Tr3, Tr5, Tr7) and W / L = 3μm / 6μm (transistors Tr4, Tr6).

[0148] Furthermore, the capacitance values ​​of capacitors C1 and C2 were 20fF, the potentials of the wiring connected to the gates of transistors Tr2, Tr3, Tr5, and Tr7 (RSTW, SCNW, SCNA, and RSTA) were +12V for "H" and -7V for "L", the power supply potential (LVDD) was +20V, the power supply potential (LVSS) was -5V, potentials V0 and VB were 0V, potentials VER and VRESW were -5V, the slope potential (SLO) was 0~10V, and the light-emitting device was a red-emitting μLED with Vf=1.3V. SPICE was used as the circuit simulation software.

[0149] Figure 17A shows the simulation results of the current flowing through a light-emitting device (LED) when the potentials DATAW and DATAA input to the pixel PIX within one frame period are set to +1V to +8V (1V steps). The horizontal axis represents time (milliseconds), and it is assumed that the slope potential (SLO) changes from its minimum value to its maximum value within one frame period.

[0150] The results confirmed that as the values ​​of potentials DATAW and DATAA increased, the current value increased and the emission period also lengthened. In other words, it was confirmed that PAM+PWM control (pulse width control with amplitude changes) is possible.

[0151] Figure 17B is a graph plotting the current integral value against the digital input value. The digital input value corresponds to the gray level, and the current integral value corresponds to the brightness. The curve of the current integral value is proportional to the gamma power of the digital input value (here, γ=3 because DATAW=DATAA), confirming that input and output following a gamma curve is possible.

[0152] Based on the above simulation results, the effectiveness of one embodiment of the present invention could be confirmed.

[0153] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0154] (Embodiment 2) In this embodiment, the stacked structure of a display device according to one aspect of the present invention, as shown in Figures 2A and 2B, will be described.

[0155] Figure 18A shows a cross-sectional view of a display device 100A, which is one embodiment of the present invention. The display device 100A has a configuration in which a layer 310 on which transistors, such as those in the pixel circuit's driving circuit, are provided, a layer 320 on which transistors and wiring, etc., of the pixel circuit are provided, and a layer 330 on which light-emitting devices, such as LEDs, of the pixel circuit are provided are stacked in order.

[0156] In this embodiment, the display device is described as being divided into multiple layers for convenience, but the boundaries between layers are not strictly defined. For example, even if an element is described as an element of layer 310, if that element is near the boundary between layer 310 and layer 320, that element can also be considered an element of layer 320. Furthermore, if the function of the element is not hindered, that element may be located in a layer other than layer 310. In addition, in one embodiment of the present invention, other insulating layers and conductive layers may be provided as needed, in addition to the insulating layer and conductive layer of each layer. Furthermore, some of the insulating layers and conductive layers of each layer may be omitted as needed.

[0157] Layer 310 has transistors 140, which are components of the pixel circuit, such as the drive circuit (gate driver and source driver, or both), memory circuit, and arithmetic circuit. Since high-speed operation is required for transistor 140, it is preferable to use a transistor (hereinafter referred to as a Si transistor) that has silicon (such as single-crystal silicon, polycrystalline silicon, or amorphous silicon) in the channel formation region. Figure 18A shows an example in which single-crystal silicon is used for the substrate 150, and the transistor 140 has a channel formation region in the substrate 150.

[0158] Furthermore, a portion of the pixel circuit's driving circuit may be provided within an external IC chip connected to the pixel circuit.

[0159] The transistor 140 has a conductive layer 145, an insulating layer 144, an insulating layer 146, and a pair of low-resistance regions 143. The conductive layer 145 functions as the gate. The insulating layer 144 is located between the conductive layer 145 and the substrate 150 and functions as a gate insulating layer. The insulating layer 146 covers the sides of the conductive layer 145 and functions as a sidewall. The pair of low-resistance regions 143 are impurity-doped regions in the substrate 150, one of which functions as the source of the transistor and the other as the drain of the transistor. An element isolation layer 142 is also provided around the transistor.

[0160] An insulating layer 149 is provided covering the transistor 140, and a conductive layer 148 is provided on the insulating layer 149. A conductive layer 147 is embedded in an opening in the insulating layer 149. The conductive layer 148 is electrically connected to one of a pair of low-resistance regions 143 via the conductive layer 147. An insulating layer 151 is provided covering the conductive layer 148. The conductive layer 148 functions as wiring. This wiring can electrically connect other transistors, pixel circuits, or other circuits in a circuit that has transistor 140 as an element.

[0161] Layer 320 includes a transistor 160, insulating layer 152, insulating layer 162, insulating layer 163, insulating layer 181, insulating layer 182, insulating layer 183, conductive layer 184a, conductive layer 184b, insulating layer 185, insulating layer 186, insulating layer 187, conductive layer 192, conductive layer 195, conductive layer 196, and conductive layer 197, which are components of the pixel circuit. Although one or more of these elements may be considered components of a transistor, in this embodiment they will not be included as components of a transistor in the description. Note that each conductive layer and each insulating layer of layer 320 is not limited to a single-layer structure but may also be a multilayer structure.

[0162] The insulating layer 152 is provided on layer 310. The insulating layer 152 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from layer 310 to transistor 160, and prevents oxygen from detaching from the metal oxide layer 165 of transistor 160 towards layer 310. As the insulating layer 152, for example, a film that is less permeable to the diffusion of hydrogen and oxygen than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0163] The transistor 160 includes a conductive layer 161, an insulating layer 163, an insulating layer 164, a metal oxide layer 165, a pair of conductive layers 166, an insulating layer 167, and a conductive layer 168, etc.

[0164] The transistor 160 is preferably an OS transistor having a metal oxide layer 165 in the channel formation region. The metal oxide layer 165 has a first region overlapping with one of the pair of conductive layers 166, a second region overlapping with the other of the pair of conductive layers 166, and a third region between the first region and the second region.

[0165] OS transistors do not require bonding processes and can be formed in the region overlapping with Si transistors via an insulating layer. Therefore, stacked devices can be manufactured using a simple process, reducing manufacturing costs.

[0166] Furthermore, OS transistors have features such as higher mobility, faster operation, and greater reliability compared to transistors using amorphous silicon. Also, the metal oxides used in OS transistors can be formed in a thin-film deposition process, eliminating the need for laser equipment and other devices required in the crystallization process of polycrystalline silicon. Therefore, using OS transistors makes it possible to manufacture inexpensive and highly reliable display devices.

[0167] A conductive layer 161 and an insulating layer 162 are provided on the insulating layer 152, and an insulating layer 163 is provided covering the conductive layer 161 and the insulating layer 162. An insulating layer 164 is provided on the insulating layer 163, and a metal oxide layer 165 is provided on the insulating layer 164.

[0168] The conductive layer 161 functions as a gate electrode, and the insulating layers 163 and 164 function as gate insulating layers. The conductive layer 161 has a region that overlaps with the metal oxide layer 165 via the insulating layers 163 and 164. The insulating layer 163 is preferably formed of a material that functions as a barrier layer, similar to the insulating layer 152. For the insulating layer 164 in contact with the metal oxide layer 165, it is preferable to use an oxide insulating film such as a silicon oxide film.

[0169] A pair of conductive layers 166 are provided spaced apart on the metal oxide layer 165. One of the pair of conductive layers 166 functions as the source of the transistor, and the other functions as the drain. An insulating layer 181 is provided covering the metal oxide layer 165 and the pair of conductive layers 166, and an insulating layer 182 is provided on the insulating layer 181.

[0170] The insulating layers 181 and 182 are provided with openings that reach the metal oxide layer 165, and the insulating layer 167 and the conductive layer 168 are embedded inside these openings. These openings are located in positions that overlap with a third region of the metal oxide layer 165. The insulating layer 167 has regions that overlap with the sides of the insulating layer 181 and the insulating layer 182. The conductive layer 168 has regions that overlap with the sides of the insulating layer 181 and the insulating layer 182 via the insulating layer 167.

[0171] The conductive layer 168 functions as a gate electrode, and the insulating layer 167 functions as a gate insulating layer. The conductive layer 168 has a region that overlaps with the metal oxide layer 165 via the insulating layer 167.

[0172] Furthermore, insulating layers 183 and 185 are provided, covering the upper surfaces of insulating layer 182, insulating layer 167, and conductive layer 168.

[0173] It is preferable that the insulating layer 181 and insulating layer 183 are formed from a material that functions as a barrier layer, similar to the insulating layer 152. By covering the pair of conductive layers 166 with the insulating layer 181, oxidation of the pair of conductive layers 166 by oxygen contained in the insulating layer 182 can be suppressed.

[0174] A plug electrically connected to one of the pair of conductive layers 166 and conductive layer 195 is embedded in an opening provided in insulating layers 181, 182, 183, and 185. The plug may have a conductive layer 184b in contact with the side surface of the opening and the upper surface of one of the pair of conductive layers 166, and a conductive layer 184a embedded inside the conductive layer 184b. The conductive layer 184b is preferably made of a conductive material that does not easily allow hydrogen and oxygen to diffuse.

[0175] A conductive layer 192, a conductive layer 195, and an insulating layer 186 are provided on the insulating layer 185. A conductive layer 196, a conductive layer 197, and an insulating layer 187 are provided on the insulating layer 186. The conductive layer 195 is electrically connected to the conductive layer 196 via a plug. The conductive layer 192 is electrically connected to the conductive layer 197 via a plug.

[0176] Here, the insulating layer 186 can have a planarization function. The insulating layer 187, the conductive layer 196, and the conductive layer 197 function as a bonding layer. The conductive layer 196 and the conductive layer 197 have regions embedded in the insulating layer 187.

[0177] Layer 330 has a light-emitting device 110 provided on the support layer 118. The sides of the light-emitting device 110 are sealed with an insulating layer 189, and the upper surface of the light-emitting device 110 is provided with an insulating layer 188, a conductive layer 198, and a conductive layer 199. The conductive layer 198 is electrically connected to one electrode of the light-emitting device 110, and the conductive layer 199 is electrically connected to the other electrode of the light-emitting device 110. It is preferable to use an insulating resin layer or the like as the insulating layer 189.

[0178] Here, the insulating layer 188, the conductive layer 198, and the conductive layer 199 function as bonding layers. The conductive layer 198 and the conductive layer 199 have regions embedded in the insulating layer 188.

[0179] The surface of layer 330 (insulating layer 188, conductive layer 198, and conductive layer 199) is bonded to the surface of layer 320 (insulating layer 187, conductive layer 196, and conductive layer 197). Here, insulating layer 188 is bonded to insulating layer 187. Conductive layer 198 is bonded to conductive layer 196, and the two are electrically connected. Conductive layer 199 is bonded to conductive layer 197, and the two are electrically connected.

[0180] It is preferable that insulating layer 188 and insulating layer 187 are composed of the same component. Furthermore, it is preferable that conductive layer 198 and conductive layer 196 are formed of the same metal as their main component. Furthermore, it is preferable that conductive layer 199 and conductive layer 197 are formed of the same metal as their main component.

[0181] For example, the insulating layers 187 and 188 are preferably formed using a single layer or laminate having one or more inorganic insulating materials such as silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, hafnium oxide, and titanium nitride.

[0182] Furthermore, the conductive layers 196 to 199 can be made of copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold. For ease of bonding, copper, aluminum, tungsten, or gold are preferred.

[0183] Transistor 160 can be used as a transistor constituting a pixel circuit. Transistor 140 can be used as a transistor constituting a drive circuit (such as one or both of a gate driver and a source driver) for driving the pixel circuit. Transistor 140 may also be a transistor constituting a pixel circuit. Furthermore, transistors 140 and 160 can also be used as transistors constituting various circuits such as arithmetic circuits and memory circuits.

[0184] This configuration allows for the formation of elements such as transistors in the drive circuit, as well as elements such as transistors in the pixel circuit, directly beneath the light-emitting device. This enables miniaturization of the display device compared to cases where the drive circuit is located outside the display unit. Furthermore, it allows for the realization of a display device with a narrow bezel (a small non-display area).

[0185] The light-emitting device 110 has a semiconductor layer 113, a light-emitting layer 114, and a semiconductor layer 115, which are arranged sequentially on the support layer 118 in that order. A conductive layer 116 is also provided on the semiconductor layer 113. The laminated light-emitting layer 114 and semiconductor layer 115 and the conductive layer 116 are covered with an insulating layer 117. The semiconductor layer 115 is electrically connected to the conductive layer 198 through a first opening provided in the insulating layer 117. The conductive layer 116 is electrically connected to the conductive layer 199 through a second opening provided in the insulating layer 117.

[0186] For example, a support layer 118 is formed on a sapphire substrate by epitaxial growth, such as gallium nitride. A semiconductor layer 113, an emissive layer 114, another semiconductor layer 115, an insulating layer 117, and a conductive layer 116 are then processed on the support layer 118 to form multiple light-emitting devices 110. The multiple light-emitting devices formed in this process can be called light-emitting devices formed in a monolithic structure.

[0187] Then, an insulating layer 189 and a bonding layer are formed on the light-emitting device 110, and multiple light-emitting devices 110 are bonded to the layer 320 in the same process. Finally, the sapphire substrate is peeled off to obtain the structure shown in the display device 100A.

[0188] The light-emitting layer 114 is sandwiched between semiconductor layers 113 and 115. In the light-emitting layer 114, electrons and holes combine to emit light. One of the semiconductor layers 113 and 115 can be an n-type semiconductor layer, and the other can be a p-type semiconductor layer. Furthermore, the light-emitting layer 114 can be an n-type, i-type, or p-type semiconductor layer.

[0189] The laminated structure, comprising a semiconductor layer 113, a light-emitting layer 114, and a semiconductor layer 115, is formed to emit light such as red, green, blue, blue-violet, violet, or ultraviolet light. For example, compounds containing group 13 and group 15 elements (also called group 3-5 compounds) can be used in the laminated structure. Examples of group 13 elements include aluminum, gallium, and indium. Examples of group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0190] For example, a pn junction or pin junction can be formed using gallium-phosphorus compounds, gallium-arsenide compounds, gallium-aluminum-arsenide compounds, aluminum-gallium-indium-phosphorus compounds, gallium nitride, indium-gallium nitride compounds, selenium-zinc compounds, etc., to fabricate a light-emitting device that emits the desired light. Other compounds may also be used.

[0191] Furthermore, the pn junction or pin junction of the light-emitting device 110 may be a homojunction, a heterojunction, or a double heterojunction. Other light-emitting devices, such as those with quantum well junctions or those using nanocolumns, may also be used.

[0192] For example, materials such as gallium nitride can be used for light-emitting devices that emit light in the ultraviolet to blue wavelength range. Materials such as indium-gallium nitride compounds can be used for light-emitting devices that emit light in the ultraviolet to green wavelength range. Materials such as aluminum-gallium-indium-phosphorus compounds or gallium-arsenide compounds can be used for light-emitting devices that emit light in the infrared wavelength range. Materials such as gallium-arsenide compounds can be used for light-emitting devices that emit light in the infrared wavelength range.

[0193] If multiple light-emitting devices 110 arranged on the same surface have different light-emitting colors, such as R (red), G (green), and B (blue), then a color image can be displayed.

[0194] Furthermore, all light-emitting devices 110 provided on the same surface may be configured to emit light of the same color. In this case, the light emitted from the light-emitting layer 114 is taken out of the display device via one or both of the color conversion layer and the coloring layer. This configuration will be described in detail in Embodiment 3.

[0195] Furthermore, the display device of this embodiment may have a light-emitting device that emits infrared light. The light-emitting device that emits infrared light can be used, for example, as a light source for an infrared light sensor.

[0196] Although Figure 18A shows a configuration in which layer 330 is bonded to layer 320, a configuration in which a single light-emitting device 110 is mounted using a flip-chip bonder or the like, as shown in the display device 100B in Figure 18B, and then sealed with an insulating layer 189, is also possible.

[0197] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0198] (Embodiment 3) In this embodiment, a configuration is described in which a color conversion layer is provided on the light emission side of the light-emitting device, compared to the display device described in Embodiment 2. Detailed explanations of components common to Embodiment 2 are omitted.

[0199] Figure 19 shows a cross-sectional view of the display device 100E. The display device 100E has pixels 20R that emit red light, pixels 20G that emit green light, and pixels 20B that emit blue light. In addition, layer 340 is provided on layer 330 on which the light-emitting device is provided. Layer 340 is provided with a color conversion layer, a coloring layer, and a light-shielding layer, etc.

[0200] Pixel 20R has a light-emitting device 110R. Pixel 20G has a light-emitting device 110G. Pixel 20B has a light-emitting device 110B. Each of the light-emitting devices 110R, 110G, and 110B emits light of the same color. That is, each of the light-emitting devices 110R, 110G, and 110B can have the same configuration.

[0201] Specifically, it is preferable that each of the light-emitting devices 110R, 110G, and 110B emits blue light. To construct a color image, pixels emitting the three primary colors of light—red (R), green (G), and blue (B)—can be used. In the display device described in this embodiment, a color conversion layer is used in the pixels to convert the light emitted by the light-emitting devices into light of the required color and emit it to the outside. Here, if light-emitting devices that emit blue light are used, there is no need to use a color conversion layer in the blue-emitting pixels, thus reducing manufacturing costs.

[0202] The red pixel 20R is provided with a color conversion layer 360R and a coloring layer 361R in the area overlapping with the light-emitting device 110R. The light emitted by the light-emitting device 110R is converted from blue to red in the color conversion layer 360R, and the purity of the red light is increased in the coloring layer 361R before being emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361R is also possible.

[0203] The green pixels 20G are provided with a color conversion layer 360G and a coloring layer 361G in the area overlapping with the light-emitting device 110G. The light emitted by the light-emitting device 110G is converted from blue to green in the color conversion layer 360G, and the purity of the green light is increased in the coloring layer 361G before being emitted outside the display device 100E. Note that a configuration without the coloring layer 361G is also possible.

[0204] A coloring layer 361B is provided in the blue pixel 20B in the area overlapping with the light-emitting device 110B. The light emitted by the light-emitting device 110B has its blue light purity enhanced by the coloring layer 361B and is emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361B is also possible. As mentioned above, the color conversion layer can be omitted in the blue pixel 20B.

[0205] In the display device 100E, only one type of light-emitting device needs to be manufactured on the substrate, thus simplifying the manufacturing equipment and process compared to manufacturing multiple types of light-emitting devices.

[0206] A light-shielding layer 350 is provided between each color pixel. The light-shielding layer 350 is positioned to block at least the light emitted laterally by the light-emitting device 110. If necessary, it may also be provided to block the light emitted obliquely by the light-emitting device 110. In addition, a light-shielding layer 351 is provided on the support layer 118, covering the area around the pixels.

[0207] By providing the light-shielding layers 350 and 351, it is possible to suppress the light emitted by the light-emitting device from entering adjacent pixel areas of other colors, thereby preventing color mixing. Therefore, the display quality of the display device can be improved. Alternatively, a configuration in which only one of the light-shielding layers 350 or 351 is provided may also be used.

[0208] The materials constituting the light-shielding layers 350 and 351 are not particularly limited. For example, inorganic materials such as metals, or organic materials such as resins containing pigments (such as carbon black) or dyes can be used. The light-shielding layer 351 may also be formed by laminating colored layers of each color. For example, it can be formed by laminating three colored layers of red, green, and blue.

[0209] Furthermore, each of the light-emitting devices 110R, 110G, and 110B may be configured to emit light with a wavelength that has a higher photon energy than blue light. For example, light-emitting devices that can emit blue-violet, violet, or ultraviolet (UV) light can be used. By using light with high photon energy, color conversion can be performed efficiently in the color conversion layer.

[0210] In this case, as shown in the display device 100F in Figure 20, a color conversion layer 360B and a coloring layer 361B are provided in the blue pixel 20B in the area overlapping with the light-emitting device 110B. The light emitted by the light-emitting device 110B is converted from blue-violet, violet, or ultraviolet to blue in the color conversion layer 360B, and the purity of the blue light is increased in the coloring layer 361B before being emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361B is also possible.

[0211] It is preferable to use a phosphor or a quantum dot (QD) as the color conversion layer. In particular, quantum dots have a narrow peak width in their emission spectrum and can produce emission with good color purity. This can improve the display quality of the display device.

[0212] The color conversion layer can be formed using methods such as droplet ejection (e.g., inkjet), coating, imprint, and various printing methods (screen printing, offset printing). Alternatively, a color conversion film such as a quantum dot film may be used.

[0213] When processing the film that will become the color conversion layer, lithography can be used. For example, a resist mask can be formed on the thin film to be processed, the thin film can be processed by etching or the like, and the resist mask can be removed. Alternatively, a method can be used in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape. For example, an island-shaped color conversion layer can be formed by forming a thin film using a photosensitive material mixed with quantum dots, and then processing the thin film using lithography.

[0214] There are no particular limitations on the materials that constitute quantum dots. Examples include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of elements belonging to Groups 4 through 14 and Group 16 elements, compounds of Group 2 elements and Group 16 elements, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, compounds of Group 14 elements and Group 15 elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0215] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, gallium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide Examples include titanium dioxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium, zinc, and cadmium, compounds of indium, arsenic, and phosphorus, compounds of cadmium, selenium, and sulfur, compounds of cadmium, selenium, and tellurium, compounds of indium, gallium, and arsenic, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. In addition, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may also be used.

[0216] Quantum dot structures include core type, core-shell type, and core-multishell type. Furthermore, because quantum dots have a high proportion of surface atoms, they are highly reactive and prone to aggregation. Therefore, to prevent aggregation and improve dispersibility in the dispersion medium, it is preferable that a protective agent is attached to the surface of the quantum dots, or that protective groups are provided. This can also reduce reactivity and improve electrical stability.

[0217] As the size of a quantum dot decreases, its band gap increases, so its size is adjusted appropriately to obtain light of a desired wavelength. As the crystal size decreases, the emission of quantum dots shifts towards the blue side, i.e., towards higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the ultraviolet, visible, and infrared spectral wavelength ranges. The size (diameter) of the quantum dots is, for example, 0.5 nm to 20 nm, preferably 1 nm to 10 nm. The narrower the size distribution of the quantum dots, the narrower the emission spectrum becomes, and the better the color purity of the emission can be obtained. Furthermore, the shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. A quantum rod, which is a rod-shaped quantum dot, has the function of exhibiting directional light.

[0218] A colored layer is a colored layer that transmits light in a specific wavelength range. For example, a color filter that transmits light in the wavelength range of red, green, blue, or yellow can be used. Materials that can be used for the colored layer include metal materials, resin materials, and resin materials containing pigments or dyes.

[0219] Although the basic configurations of display devices 100E and 100F were illustrated using the configuration of display device 100A, the display device 100B shown in Embodiment 2 can also be applied.

[0220] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0221] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 21A and 21B.

[0222] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR (Virtual Reality) devices such as head-mounted displays (HMDs) and AR (Augmented Reality) devices such as glasses.

[0223] Figure 21A shows a perspective view of the display module 280. The display module 280 includes the display device 100A described in the previous embodiment and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 100A, but may be any of the display devices 100B, 100E, or 100F.

[0224] The display module 280 has substrates 291 and 292. The display module 280 has a display unit 281. The display unit 281 is an area in the display module 280 that displays an image, and is an area in which light from each pixel provided in the pixel unit 284, which will be described later, can be seen.

[0225] Figure 21B shows a schematic perspective view illustrating the configuration of the substrate 291. On the substrate 291, a circuit section 282, a pixel circuit section 283 on the circuit section 282, and a pixel section 284 on the pixel circuit section 283 are stacked. In addition, a terminal section 285 for connecting to the FPC 290 is provided in the portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 285 and the circuit section 282 are electrically connected by a wiring section 286 composed of multiple wires.

[0226] The pixel section 284 has a plurality of pixels 284a arranged periodically. A magnified view of one pixel 284a is shown on the right side of Figure 21B. Each pixel 284a has a plurality of subpixels (subpixels 10R, 10G, 10B) with different emission colors. The pixel configuration described in the previous embodiment can be applied to these subpixels.

[0227] The pixel circuit section 283 has a plurality of pixel circuits 283a arranged periodically.

[0228] A single pixel circuit 283a is a circuit that controls the driving of multiple elements in a single pixel 284a. A single pixel circuit 283a can be configured to have three circuits that control the light emission of a single light-emitting device. For example, a single pixel circuit 283a can be configured to have at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active-matrix type display device.

[0229] The circuit section 282 has circuits for driving each pixel circuit 283a of the pixel circuit section 283. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit.

[0230] The FPC290 functions as wiring for supplying video signals or power potential, etc., to the circuit section 282 from an external source. An IC may also be mounted on the FPC290.

[0231] The display module 280 can be configured such that one or both of the pixel circuit section 283 and the circuit section 282 are superimposed on the lower side of the pixel section 284, thereby enabling an extremely high aperture ratio (effective display area ratio) of the display section 281. For example, the aperture ratio of the display section 281 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 284a at an extremely high density, enabling an extremely high resolution of the display section 281. For example, it is preferable that the pixels 284a in the display section 281 are arranged with a resolution of 20000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0232] Because such a display module 280 is extremely high-resolution, it can be suitably used in VR devices such as HMDs or AR devices such as glasses. For example, even in a configuration where the display part of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display part 281, so even when the display part is magnified with lenses, pixels are not visible, and a highly immersive display can be achieved. Furthermore, the display module 280 is not limited to this and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as watches.

[0233] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0234] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 22A to 22D.

[0235] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0236] A display device according to one aspect of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR (Mixed Reality) devices.

[0237] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device that has either high resolution or high detail, or both, it becomes possible to enhance the sense of presence and depth in electronic devices such as portable or home-use devices. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0238] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0239] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0240] Figures 22A to 22D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR (Substitutional Reality) content, and a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0241] The electronic device 700A shown in Figure 22A and the electronic device 700B shown in Figure 22B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0242] A display device according to one aspect of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0243] Furthermore, if the display device has a light-receiving device, it can capture an image of the pupil and perform iris authentication. It can also perform eye-tracking using the same light-receiving device. Eye-tracking allows the device to identify what the user is looking at and their location, enabling it to select functions on the electronic device and execute software accordingly.

[0244] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Since the optical member 753 has translucency, the user can view the image displayed in the display area overlaid on the transmitted image visible through the optical member 753. Accordingly, the electronic device 700A and the electronic device 700B are each an electronic device capable of AR display.

[0245] The electronic device 700A and the electronic device 700B may each be provided with a camera capable of imaging the front as an imaging unit. Further, the electronic device 700A and the electronic device 700B each include an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to the orientation in the display area 756.

[0246] The communication unit has a wireless communication device, and the wireless communication device can supply a video signal or the like. In addition to or instead of the wireless communication device, a connector to which a cable for supplying a video signal and a power potential can be connected may be provided.

[0247] Further, the electronic device 700A and the electronic device 700B are each provided with a battery and can be charged by one or both of wireless and wired charging.

[0248] The electronic device 800A shown in FIG. 22C and the electronic device 800B shown in FIG. 22D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0249] The display device according to one aspect of the present invention can be applied to the display unit 820. Accordingly, an electronic device capable of extremely high-definition display can be obtained. Thereby, a high sense of immersion can be given to the user.

[0250] The display unit 820 is provided at a position inside the housing 821 that can be visually recognized through the lens 832. 3D display using parallax can also be performed by displaying different images on the pair of display units 820.

[0251] The electronic device 800A and the electronic device 800B can each be said to be an electronic device for VR. A user wearing the electronic device 800A or the electronic device 800B can visually recognize the image displayed on the display unit 820 through the lens 832.

[0252] The electronic device 800A and the electronic device 800B preferably each have a mechanism capable of adjusting the left and right positions thereof so that the lens 832 and the display unit 820 are at optimal positions according to the position of the user's eyes. Further, it preferably has a mechanism for adjusting focus by changing the distance between the lens 832 and the display unit 820.

[0253] The user can wear the electronic device 800A or the electronic device 800B on the head by the wearing unit 823. In FIG. 22C and the like, it is exemplified as having a shape like the arm of glasses (also called a temple, etc.), but it is not limited thereto. The wearing unit 823 only needs to be wearable by the user, and for example, it may have a helmet type or a band type shape.

[0254] The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Further, a plurality of cameras may be provided so as to be compatible with a plurality of imaging angles such as telephoto and wide angle.

[0255] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0256] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0257] Electronic devices 800A and 800B may each have input terminals. These input terminals can be connected to cables that supply video signals from video output devices, etc., and power for charging batteries located within the electronic devices.

[0258] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 22A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 22C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0259] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 22B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0260] Similarly, the electronic device 800B shown in Figure 22D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0261] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0262] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0263] Furthermore, an electronic device according to one aspect of the present invention can transmit information to earphones via wired or wireless means.

[0264] Furthermore, an electronic device to which a display device according to one aspect of the present invention can be applied may be connected to an external server via a network. Alternatively, processing requiring high computing power may be performed on a server connected via the network, rather than on the electronic device itself. Such processing is also known as thin client processing, where the user-side (client-side) terminal (in this case, the electronic device) executes only limited processing, and advanced processing such as application execution and management is performed on the server side, thereby reducing the scale of processing on the client-side terminal. As a result, there is no need to use a computing device with high computing power in the electronic device, making it easier to reduce costs, weight, and size. Furthermore, in an electronic device according to one aspect of the present invention, processing may be performed in combination with the above-mentioned thin client processing and processing requiring high computing power on the electronic device side.

[0265] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0266] DATAA: Potential, DATAW: Potential, PIX: Pixel, SLO: Slope Potential, VB: Potential, VER: Potential, VRESW: Potential, 10a: Pixel, 10B: Sub-pixel, 10b: Pixel, 10G: Sub-pixel, 10R: Sub-pixel, 10: Pixel, 11: Pulse signal generation unit, 12: Light emission control unit, 13: Pixel array, 20a: First source driver, 20B: Pixel, 20b: Second source driver, 20G: Pixel, 20R: Pixel, 30: Gate driver, 40: Slope potential supply circuit, 50: Slope potential generation circuit, 100A: Display device, 100B: Display device, 100E: Display Device, 100F: Display device, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Transistor, 110B: Light-emitting device, 110G: Light-emitting device, 110R: Light-emitting device, 110: Light-emitting device, 111: Capacitor, 112: Capacitor, 113: Semiconductor layer, 114: Light-emitting layer, 115: Semiconductor layer, 116: Conductive layer, 117: Insulating layer, 118: Support layer, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125 :Wiring, 126:Wiring, 127:Wiring, 128:Wiring, 129:Wiring, 131:Wiring, 132:Wiring, 133:Wiring, 134:Wiring, 135:Wiring, 140:Transistor, 142:Element isolation layer, 143:Low resistance region, 144:Insulating layer, 145:Conductive layer, 146:Insulating layer, 147:Conductive layer, 148:Conductive layer, 149:Insulating layer, 150:Substrate, 151:Insulating layer, 152:Insulating layer, 160:Transistor, 161:Conductive layer, 162:Insulating layer, 163:Insulating layer, 164:Insulating layer, 165:Metal oxide layer, 166:Conductive layer, 167:Insulating layer, 168:Conductive layer, 18 1: insulating layer, 182: insulating layer, 183: insulating layer, 184a: conductive layer, 184b: conductive layer, 185: insulating layer, 186: insulating layer, 187: insulating layer, 188: insulating layer, 189: insulating layer, 192: conductive layer, 195: conductive layer, 196: conductive layer, 197: conductive layer, 198: conductive layer, 199: conductive layer, 280: display module, 281: display unit, 282: circuit unit, 283a: pixel circuit, 283: pixel circuit unit, 284a: pixel, 284: pixel unit, 285: terminal unit, 286: wiring unit, 290: FPC, 291: substrate, 292: substrate, 310: layer, 311: Si transistor,312: Functional circuit, 320: Layer, 321: OS transistor, 330: Layer, 331: LED array, 340: Layer, 350: Light-shielding layer, 351: Light-shielding layer, 360B: Color conversion layer, 360G: Color conversion layer, 360R: Color conversion layer, 361B: Coloring layer, 361G: Coloring layer, 361R: Coloring layer, 700A: Electronic equipment, 700B: Electronic equipment, 721: Enclosure, 723: Mounting 727: Earphone section, 750: Earphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic equipment, 800B: Electronic equipment, 820: Display unit, 821: Housing, 822: Communication unit, 823: Mounting section, 824: Control unit, 825: Imaging unit, 827: Earphone section, 832: Lens,

Claims

1. It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a light-emitting device. The gate of the first transistor is electrically connected to one of the source or drain electrodes of the second transistor, one of the source or drain electrodes of the third transistor, and one of the electrodes of the first capacitor. Either the source or drain of the first transistor is electrically connected to one electrode of the light-emitting device and the other electrode of the first capacitor. The gate of the third transistor is electrically connected to either the source or drain of the fourth transistor and either the source or drain of the fifth transistor. The gate of the fourth transistor is electrically connected to either the source or drain of the sixth transistor and to one electrode of the second capacitor. The source or drain of the first transistor, the other of which is electrically connected to the first wiring, The source or drain of the second transistor, the other of which is electrically connected to the second wiring, The gate of the second transistor is electrically connected to the third wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The source or drain of the fourth transistor, the other of which is electrically connected to the fifth wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the sixth wiring, The gate of the fifth transistor is electrically connected to the seventh wiring, The source or drain of the sixth transistor, the other of which is electrically connected to the eighth wiring, The gate of the sixth transistor is electrically connected to the ninth wiring, The other electrode of the second capacitor is a display device electrically connected to the tenth wiring, The first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor are n-channel transistors, and the fourth transistor is a p-channel transistor. A display device in which the first transistor, the second transistor, the fifth transistor, and the sixth transistor have a metal oxide in their channel formation regions, and the third transistor and the fourth transistor have silicon in their channel formation regions.

2. It comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a light-emitting device. The gate of the first transistor is electrically connected to one of the source or drain electrodes of the second transistor, one of the source or drain electrodes of the third transistor, and one of the electrodes of the first capacitor. The source or drain of the first transistor is electrically connected to one electrode of the light-emitting device. The source or drain of the first transistor is electrically connected to the other electrode of the first capacitor. The gate of the third transistor is electrically connected to either the source or drain of the fourth transistor and either the source or drain of the fifth transistor. The gate of the fourth transistor is electrically connected to either the source or drain of the sixth transistor and to one electrode of the second capacitor. The source or drain of the first transistor, the other of which is electrically connected to the first wiring, The source or drain of the second transistor, the other of which is electrically connected to the second wiring, The gate of the second transistor is electrically connected to the third wiring. The source or drain of the third transistor, the other of which is electrically connected to the fourth wiring, The source or drain of the fourth transistor, the other of which is electrically connected to the fifth wiring, The source or drain of the fifth transistor, the other of which is electrically connected to the sixth wiring, The gate of the fifth transistor is electrically connected to the seventh wiring, The source or drain of the sixth transistor, the other of which is electrically connected to the eighth wiring, The gate of the sixth transistor is electrically connected to the ninth wiring, The other electrode of the second capacitor is a display device electrically connected to the tenth wiring, The second transistor, the fourth transistor, and the sixth transistor are n-channel transistors, and the first transistor, the third transistor, and the fifth transistor are p-channel transistors. A display device in which the second, fourth, and sixth transistors have a metal oxide in their channel formation regions, and the first, third, and fifth transistors have silicon in their channel formation regions.

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