Indication device

Abstract

To compensate for change of driving characteristics of a display device more accurately and more efficiently.SOLUTION: In the display device, a photo transistor for sensing light of a light-emitting element is arranged in a wire board which is not a panel unit in which the light-emitting element is arranged. The photo transistor senses light and can be used as a compensation unit for compensating for the illuminance deviation according to pixels.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a display device, and more particularly to a display device that combines a plurality of panel units on a wiring board on which link wirings are arranged.

Background Art

[0002] Display devices can be embodied in a very variety of forms, such as televisions, monitors, smartphones, tablet PCs, notebook computers, wearable devices, and the like.

[0003] Among display devices, a self-emitting display device incorporates a light-emitting element or a light source into the display device, and can display information using the light generated by the incorporated self-emitting element or light source.

[0004] A display device including a self-emitting element can be embodied thinner than a display device incorporating a light source, is flexible, and has the advantage of being able to be embodied in a display device that can be folded or rolled up.

[0005] A display device incorporating a self-emitting element may include, for example, an organic light-emitting display device (OLED; Organic Light Emitting Diode Display) including an organic substance as a light-emitting layer, or a micro LED display device (Micro LED; Micro Light Emitting Diode Display) including an inorganic substance as a light-emitting layer.

[0006] Among these, a micro LED display device uses an inorganic substance resistant to moisture and oxygen as a light-emitting layer, and thus is more reliable and has a longer lifespan than using an organic substance as a light-emitting layer.

[0007] In addition, the micro LED element of a micro LED display device not only has a fast lighting speed, but also has low power consumption and can display a high-brightness video, and thus has the advantage of being advantageous for the application of an extra-large screen.

Summary of the Invention

[0008] On the other hand, the display device can compensate for current and voltage using various methods to compensate for changes in driving characteristics.

[0009] For example, in addition to the thin-film transistors that drive the light-emitting elements of the display device, separate thin-film transistors can be formed for compensation to perform current and voltage compensation.

[0010] However, when compensation is performed by forming additional thin-film transistors on the substrate on which the light-emitting element and the thin-film transistor that drives the light-emitting element are formed, there is a problem in that process efficiency decreases as the circuit configuration becomes more complex.

[0011] Furthermore, in the case of transparent display devices, the area of ​​the circuit section increases due to the addition of circuits with a similar configuration to thin-film transistors for compensation, which reduces the area of ​​the transparent section.

[0012] Therefore, the inventors of this specification have invented a display device having a compensation structure that can more efficiently and accurately compensate for changes in the driving characteristics of the display device.

[0013] The problem to be solved by the embodiments of this specification is to provide a display device that can sense light emitted from a light-emitting element and compensate for pixel-specific brightness deviations.

[0014] The problem to be solved by the embodiments of this specification is to provide a display device that can utilize a unit that senses light emitted from a light-emitting element as a standalone compensation unit.

[0015] The problem to be solved by the embodiments of this specification is to provide a display device with a structure that can sense light emitted from a light-emitting element as effectively as possible.

[0016] The problem to be solved by the embodiments of this specification is to provide a display device that can improve the process efficiency and space utilization of signal wiring connected to a structure that senses light emitted from a light-emitting element.

[0017] The problems to be solved by the embodiments of this specification are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0018] The display device according to the embodiments herein includes a plurality of panel units, each containing a plurality of light-emitting elements; a wiring board, each containing a plurality of link wirings for transmitting wiring signals to the panel units, and a plurality of phototransistors for sensing light emitted from the light-emitting elements, wherein the plurality of panel units are tiled together on the wiring board.

[0019] According to one embodiment of this specification, the phototransistor is located above the light-emitting element, but at least one overcoat layer or at least one spacer may be placed between the phototransistor and the light-emitting element.

[0020] Furthermore, according to one embodiment of this specification, the signal wiring connected to the phototransistor may be formed on the same layer as the link wiring that transmits the wiring signal to the panel unit, or may be formed integrally with it.

[0021] According to embodiments of this specification, a phototransistor that senses light from the light-emitting elements is placed on a wiring board separate from the panel unit on which the light-emitting elements are arranged. This allows the phototransistor to sense light and be used as a compensation unit that can compensate for pixel-specific brightness deviations.

[0022] Also, according to the embodiments of the present specification, in a process separate from the process of forming the panel unit, a phototransistor is formed on a wiring board formed to be physically divided, and a plurality of panel units are tile-bonded to the wiring board. Therefore, a highly reliable phototransistor can be easily utilized as a single compensation unit.

[0023] Also, according to the embodiments of the present specification, although the phototransistor is located above the light-emitting element, at least one overcoat layer or at least one spacer is arranged between the phototransistor and the light-emitting element, so that the minimum angle at which the phototransistor can effectively sense the light of the light-emitting element to the maximum extent can be ensured.

[0024] Also, according to the embodiments of the present specification, the signal wiring connected to the phototransistor is formed in the same layer as the link wiring that transmits the wiring signal to the panel unit or is integrally formed. Therefore, the process efficiency and space utilization of forming the signal wiring connected to the structure for sensing the light emitted from the light-emitting element can be improved, and the effect of process optimization can be obtained.

[0025] Also, according to the embodiments of the present specification, since a plurality of panel units can be tile-bonded on the wiring board, the bezel area can be minimized so that the boundary between the panel units is substantially not visible.

[0026] Also, according to the embodiments of the present specification, since a plurality of panel units can be tile-bonded on the wiring board, there is an effect that a display device having a large screen of various sizes and forms can be freely and easily realized.

[0027] Also, according to the embodiments of the present specification, although a plurality of panel units including a plurality of signal wirings are arranged on a wiring board including a plurality of link wirings, the link wiring and the signal wiring can be arranged so as to overlap each other. Therefore, the transmittance of the transparent display device can be improved.

[0028] The above-described effects and the specific effects of the present invention will be described and described while explaining the embodiments for carrying out the following invention.

Brief Description of the Drawings

[0029] [Figure 1] It is a schematic plan view of a display device according to an embodiment of the present specification. [Figure 2] It is a cross-sectional view corresponding to one sub-pixel in a state where a wiring board and a panel unit are combined according to the first embodiment of the present specification. [Figure 3] FIG. 3 is a cross-sectional view corresponding to one sub-pixel in a state where a wiring board and a panel unit are combined according to the second embodiment of the present specification. [Figure 4] It is a plan view of a panel unit according to the first and second embodiments of the present specification. [Figure 5] It is a plan view of a wiring board according to the first and second embodiments of the present specification. [Figure 6] It is a cross-sectional view corresponding to one sub-pixel in a state where a wiring board and a panel unit are combined according to the third embodiment of the present specification. [Figure 7] It is a plan view of a panel unit according to the third embodiment of the present specification. [Figure 8] It is a plan view of a wiring board according to the third embodiment of the present specification. [Figure 9] It is a cross-sectional view corresponding to one sub-pixel in a state where a wiring board and a panel unit are combined according to the fourth embodiment of the present specification. [Figure 10] It is a plan view of a panel unit of a transparent display device according to an embodiment of the present specification. [Figure 11] It is a circuit connection diagram of a wiring board of a transparent display device according to an embodiment of the present specification. [Figure 12] It is a plan view of a panel unit of a display device according to an embodiment of the present specification. [Figure 13] It is a circuit connection diagram of a wiring board of a display device according to an embodiment of the present specification. [Figure 14] This is a circuit diagram of a phototransistor according to one embodiment of this specification. [Figure 15] This figure shows a driving embodiment of a phototransistor according to the fifth embodiment of this specification. [Figure 16] This figure shows a driving embodiment of a phototransistor according to the fifth embodiment of this specification. [Figure 17] This figure shows a driving embodiment of a phototransistor according to the sixth embodiment of this specification. [Figure 18] This figure shows a driving embodiment of a phototransistor according to the sixth embodiment of this specification. [Figure 19] This graph shows the leakage current values ​​of a phototransistor measured under different levels of illumination. [Figure 20] This graph shows the leakage current values ​​of a phototransistor measured under different levels of illumination. [Modes for carrying out the invention]

[0030] The advantages and features of this specification, and the methods for achieving them, will become clear with reference to the embodiments described below in detail, along with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but can be embodied in a variety of different forms. These embodiments are provided to complete the disclosure of this specification and to fully inform those who are ordinary skill in the art to which this specification belongs of the scope of the invention, and this specification is defined only by the scope of the claims.

[0031] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for the purpose of illustrating embodiments of this specification are illustrative, and this specification is not limited to those depicted. The same reference numerals in this specification refer to the same component. In addition, if a detailed explanation of related known technology is deemed to obscure the gist of this specification, such explanation will be omitted. When "includes," "has," "becomes," etc., used in this specification, other parts may be added unless "only" is used. When a component is shown singly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0032] When interpreting the constituent elements, even if not explicitly stated elsewhere, they shall be interpreted as including a margin of error.

[0033] When describing spatial relationships, for example, using phrases like "on top of," "above," "below," or "to the side," one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0034] When describing temporal relationships, for example, when describing the sequence of events using phrases like "after," "following," "next," or "before," it may include cases that are not consecutive, unless "immediately" or "directly" is used.

[0035] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0036] The features of the various embodiments described herein can be combined or linked together, either partially or entirely, and are technically capable of various interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or in conjunction with them.

[0037] In the following sections, various embodiments of the display device described herein will be explained in detail with reference to Figures 1 to 20.

[0038] The display device 1 according to the first and second embodiments of this specification will be described with reference to Figures 1 to 5.

[0039] Panel units 10, each containing multiple signal lines (SL), may be tiled together on a wiring board 20 containing multiple link lines (LL).

[0040] The wiring board 20 may include a second board 200 that supports a plurality of link wirings (LL).

[0041] The second substrate 200 may be an insulating substrate, and for example, it may be made of glass or a transparent plastic material to realize a transparent display device.

[0042] One or more circuit films 30 may be placed on one or both sides of the second substrate 200 and electrically connected to a plurality of link wirings (LL).

[0043] The circuit film 30 may be a flexible circuit film, and data drivers 32 may be arranged on each circuit film 30 in a chip-on-film (COF) manner, but is not limited to this.

[0044] One or more printed circuit boards 34 may be electrically connected to the other side of the circuit film 30 that is opposite to one side of the circuit film 30 connected to the second substrate 200.

[0045] The printed circuit board 34 may be a flexible printed circuit board (FPCB).

[0046] For example, the printed circuit board 34 may include a source printed circuit board and a control printed circuit board.

[0047] In this case, the source printed circuit board and the control printed circuit board may, but are not limited to, be connected to each other by a flat flexible cable (FFC).

[0048] The printed circuit board 34 may also contain a power management circuit, a timing controller, a level shifter, and the like.

[0049] The power management circuit can use an externally supplied input voltage to generate and output various drive voltages necessary for configuring all circuits of the display device 1.

[0050] The timing controller receives video data and input timing control signals from an external host system, and can supply multiple data control signals and video data to the data driver 32, and multiple gate control signals to the gate driver.

[0051] The data driver 32 receives multiple data control signals and video data from the timing controller, converts them into data signals, and supplies data voltages to the data signal wiring.

[0052] A gate driver can receive multiple gate control signals from a timing controller via a level shifter, convert them into gate signals (scan signals), and supply gate voltages, such as scan voltages, to the gate signal wiring.

[0053] For example, the gate driver can be implemented in the panel unit 10 using a gate-in-panel (GIP) method, but is not limited to this.

[0054] The various voltages and wiring signals generated in this manner can be transmitted to the link wiring (LL) of the wiring board 20 via the circuit film 30.

[0055] Multiple link wires (LLs) may be arranged in a unidirectional manner, spaced apart from one another and aligned.

[0056] For example, multiple link connections (LL) may include multiple high-voltage (Evdd) link connections, multiple low-voltage (Evss) link connections, multiple data voltage (Data) link connections, multiple initialization voltage (Ini) link connections, multiple reference voltage (Ref) link connections, and multiple scan (Scan) link connections.

[0057] In this case, the multiple data voltage (Data) link connections may include a first data voltage (Data1) link connection, a second data voltage (Data2) link connection, and a first data voltage (Data3) link connection.

[0058] Multiple link wires (LL) arranged on the wiring board 20 can each be electrically connected to multiple signal wires (SL) arranged on the panel unit 10.

[0059] For example, multiple signal lines (SL) may include multiple high-voltage (Evdd) signal lines, multiple low-voltage (Evss) signal lines, multiple data voltage (Data) signal lines, multiple reference voltage (Ref) signal lines, multiple initialization voltage (Ini) signal lines, and multiple scan (Scan) signal lines.

[0060] In this case, the multiple data voltage (Data) signal lines may include a first data voltage (Data1) signal line, a second data voltage (Data2) signal line, and a first data voltage (Data3) signal line.

[0061] In this way, various voltages and wiring signals transmitted via link wiring (LL) can be supplied to pixels via signal wiring (SL).

[0062] Multiple panel units 10, each containing multiple signal lines (SLs), are provided in a modular form and can be combined in a tile-like manner on a wiring board 20 to realize a tile display device.

[0063] For example, multiple panel units 10 may be arranged on the wiring board 20 in a matrix configuration along multiple rows and columns, and coupled to the wiring board 20.

[0064] In this case, the signal wiring (SL) of the multiple panel units 10 is arranged so that it overlaps with the link wiring (LL) of the wiring board 20 in the vertical direction, thereby minimizing the reduction in the transparent area due to the various wirings. Therefore, when the display device 1 according to the embodiment of this specification is implemented as a transparent display device, the transmittance can be improved.

[0065] Furthermore, since the display device 1 according to the embodiment of this specification can tile multiple panel units 10 onto the wiring board 20, the display device 1 can freely realize screens of various sizes and shapes by changing the number and arrangement of the panel units 10 that are joined.

[0066] In particular, the ability to freely increase the number of panel units 10 has the advantage of making it easier to realize larger screen sizes.

[0067] Furthermore, the display device 1 according to the embodiment of this specification can minimize the non-display area.

[0068] For example, the distance between the outermost light-emitting element of one panel unit 10 and the outermost light-emitting element of another adjacent panel unit 10 can be represented in the same way as the distance between light-emitting elements within one panel unit 10.

[0069] As a result, the display device 1 according to the embodiment of this specification can minimize the non-display area, and furthermore, it can be realized as a zero-bezel display device 1 with substantially no bezel area.

[0070] Furthermore, in the embodiment of this specification, the display device 1 has multiple panel units 10 arranged on a wiring board 20, so that the multiple panel units 10 can be freely attached to and detached from the wiring board 20.

[0071] As a result, in the display device 1 according to one embodiment of the present invention, if a defect occurs in a specific panel unit 10, only the defective panel unit 10 can be separated from the wiring board 20 and replaced, thus enabling a simpler and faster repair process.

[0072] Furthermore, in the display device 1 according to the embodiments herein, a plurality of link wirings (LL) arranged on the wiring board 20 can function as auxiliary wiring for signal wirings (SL) arranged on the panel unit 10.

[0073] Multiple link wires (LL) and multiple signal wires (SL) of the panel unit 10 are arranged in parallel so as to overlap in the vertical direction and can be electrically connected by the connecting member 300.

[0074] Therefore, the display device 1 according to one embodiment of the present invention can reduce the resistance of multiple signal lines (SL), thereby reducing signal delays such as RC delay and the decrease in brightness uniformity due to voltage drop, and can be implemented as a low-power and high-brightness display device.

[0075] Referring further to Figures 10 and 12, Figure 10 is a plan view of a transparent display device showing the portion corresponding to one pixel (P), and Figure 12 is a plan view of a display device showing the portion corresponding to one pixel (P).

[0076] On the other hand, the panel unit 10 may include multiple pixels (P).

[0077] Multiple pixels (P) may each include a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3).

[0078] The first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3) can each be represented in a different hue.

[0079] For example, the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3) may be, but are not limited to, a red subpixel embodying red (R), a green subpixel embodying green (G), and a blue subpixel embodying blue (B), respectively.

[0080] For example, multiple pixels (P) may further include white subpixels that embody white (W).

[0081] Multiple subpixels (SP1, SP2, SP3) may each include a light-emitting section (EA) and a circuit section (CA).

[0082] The light-emitting section (EA) of the panel unit 10 may have a plurality of light-emitting elements (ED), including a plurality of first light-emitting elements (ED1) and a plurality of second light-emitting elements (ED2).

[0083] In this specification, the light-emitting element (ED) is described using a micro-LED as an example, but is not limited to this.

[0084] The first light-emitting element (ED1) may include a first light-emitting element of a first hue (ED11), a first light-emitting element of a second hue (ED12), and a first light-emitting element of a third hue (ED13).

[0085] Furthermore, the second light-emitting element (ED2) may include a second light-emitting element of the first hue (ED21), a second light-emitting element of the second hue (ED22), and a second light-emitting element of the third hue (ED23).

[0086] For example, a pair of first light-emitting elements (ED1) and second light-emitting elements (ED2) that embody the same hue can constitute a single subpixel.

[0087] During the process of forming the first light-emitting element (ED1) on the panel unit 10, defects may occur, potentially preventing the first light-emitting element (ED1) from emitting light properly.

[0088] To address such a case, the display device 1 according to the embodiments of this specification may have a redundancy structure further comprising a plurality of light-emitting elements that embody the same hue in a single subpixel.

[0089] Therefore, the first light-emitting element (ED1) may be the main light-emitting element, and the second light-emitting element (ED2) may be a redundancy light-emitting element.

[0090] Referring to Figure 10, the light-emitting section (EA) and the circuit section (CA) may be arranged in the region where the scan voltage signal wiring (Scan1, Scan2, Scan3) and various signal wiring (Evdd, Data1, Data2, Data3, Ini, Ref, Evss) intersect.

[0091] The circuit section (CA) may include drive circuits containing various types of thin-film transistors (TFTs), such as scan thin-film transistors (SCTs) and sensing thin-film transistors (SETs), as well as storage capacitors (Csts).

[0092] The area where various signal lines (Evdd, data1, data2, data3, Ini, Ref, Evss) are located can be defined as a wiring area (LA).

[0093] Areas other than the light-emitting section (EA), circuit section (CA), and wiring section (LA) may be transparent sections (TA).

[0094] In the case of a transparent display device, the areas of the light-emitting section (EA), circuit section (CA), and wiring section (LA) may be formed more densely in order to secure a larger area of ​​the transparent section (TA).

[0095] Referring to Figure 12, in the case of a typical display device, it is not necessary to include a transparent section (TA). Therefore, compared to a transparent display device, the arrangement of the light-emitting section (EA), circuit section (CA), and wiring section (LA) can be made as widely distributed as possible, taking into consideration the possibility of interference between wiring and electrodes, rather than making the arrangement densely.

[0096] On the other hand, the wiring board 20 may include a plurality of phototransistors (PHTs) that sense light emitted from light-emitting elements (EDs) arranged in the panel unit 10.

[0097] The display device 1 according to this specification includes a phototransistor (PHT) that, in a turn-off state, outputs an off-current in response to light emitted from an emitting element (ED). In this way, the off-current output by the phototransistor (PHT) can be detected to sense the light from an emitting element (ED) located at a specific pixel.

[0098] A phototransistor (PHT) may include a photogate electrode (PGE), a photoactive layer (PACT), a first photoelectrode (PE1), and a second photoelectrode (PE2).

[0099] A photocontrol signal (Vsto) is applied to the photogate electrode (PGE), a photodriving signal (Vdrv) is applied to the first photoelectrode (PE1), and the second photoelectrode (PE2) can output a photosensing signal (Vsen).

[0100] Therefore, the photogate electrode (PGE) may be electrically connected to a photocontrol signal (Vsto) wiring that applies a photocontrol signal (Vsto), the first photoelectrode (PE1) may be electrically connected to a photodrive signal (Vdrv) wiring that applies a photodrive signal (Vdrv), and the second photoelectrode (PE2) may be electrically connected to a photosensing signal (Vsen) wiring that applies a photosensing signal (Vsen).

[0101] For example, when a low-level photocontrol signal (Vsto) voltage is applied to the photogate electrode (PGE) of a phototransistor (PHT) and a high-level photodrive signal (Vdrv) voltage is applied to the first photoelectrode (PE1), and a light source flows in, the phototransistor (PHT) can output an off-current.

[0102] The second photoelectrode (PE2) of the phototransistor (PHT) can be electrically connected to a sensing circuit (not shown) that detects a sensing signal via a lead-out wire (ROL).

[0103] For example, the sensing circuit section (not shown) may include an amplifier electrically connected to a lead-out wire (ROL), an integrator that integrates the output signal of the amplifier and outputs an integrated value, a sample-and-hold circuit that stores the integrated value of the integrator, and an analog-to-digital converter that converts the sensing signal into a digital signal.

[0104] The sensing circuit (not shown) can output sensing data, obtained by converting the sensing signal detected via the lead-out wiring (ROL) into a digital signal format, to the sensing controller.

[0105] In one example, the sensing circuit (not shown) can be manufactured using a data driver 32 and a single IC (Integrated Circuit), and then placed on the display device 1.

[0106] The wiring board 20 and the multiple panel units 10 are bonded to each other by an optical resin layer (OCR) placed between the wiring board 20 and the multiple panel units 10, and can be electrically connected to each other via a plurality of conductive connecting members 300.

[0107] For example, the optical resin layer (OCR) may include optical clear resin (OCR).

[0108] In the display device 1 according to the embodiments of this specification described above, a phototransistor (PHT) that senses light from the light-emitting element (ED) is placed on a wiring board 20 separate from the panel unit 10 on which the light-emitting element (ED) is arranged. Therefore, the phototransistor (PHT) can sense the light and be used as a compensation unit that can compensate for the brightness deviation of each pixel.

[0109] In this way, by using a phototransistor (PHT) to sense the light emitted from the light-emitting element (ED) and compensating for the brightness deviation of each pixel, the compensation for current and voltage sensing at the thin-film transistor terminals that drive the light-emitting element (ED) can be corrected, thereby enabling the display device 1 to have more accurate image quality.

[0110] Furthermore, in the display device 1 according to the embodiment of this specification, phototransistors (PHTs) are formed on a wiring board 20 that is physically separated in a process separate from the panel unit 10 formation process, and multiple panel units 10 are tiled to the wiring board 20. Therefore, highly reliable phototransistors (PHTs) can be easily utilized as individual compensation units.

[0111] Thus, by utilizing highly reliable phototransistors (PHTs) as standalone compensation units, they can be used in applications such as external compensation and camera compensation.

[0112] Various connection structures between the wiring board 20 and the panel unit 10 will be explained by showing a cross-sectional view of a single subpixel in a state where the wiring board 20 and the panel unit 10 are connected.

[0113] In the following, we will first describe the panel unit 10, and then the wiring board 20.

[0114] The panel unit 10 may include a first substrate 100, thin-film transistors (TFTs), storage capacitors (Csts), and various wirings arranged on the first substrate 100.

[0115] The first substrate 100 may be made of a transparent material including glass or plastic.

[0116] A light-blocking layer (LS) is placed on the first substrate 100 to block light incident on the active layer (ACT) of the thin-film transistor (TFT) from below the first substrate 100, thereby reducing leakage current.

[0117] A buffer layer (BUF) is placed on the light-blocking layer (LS) to prevent the penetration of impurities or moisture by the first substrate 100.

[0118] Thin-film transistors (TFTs) may be placed on the buffer layer (BUF).

[0119] The thin-film transistor (TFT) may also be a drive thin-film transistor that provides a drive signal to drive an ED (energy-emitting element).

[0120] A thin-film transistor (TFT) may include a semiconductor layer (ACT), a first source-drain electrode (SD1), a second source-drain electrode (SD2), and a gate electrode (GE).

[0121] A gate insulating layer (GI) may be placed between the active layer (ACT) and the gate electrode (GE).

[0122] An interlayer insulating layer (ILD) is placed on the active layer (ACT) and the gate electrode (GE), and the interlayer insulating layer (ILD) may include a pair of contact holes that expose the source and drain regions of the active layer (ACT).

[0123] A first source-drain electrode (SD1) and a second source-drain electrode (SD2) are arranged on the interlayer insulating layer (ILD), and can be electrically connected to the active layer (ACT) via the pair of contact holes.

[0124] The first source-drain electrode (SD1) may be a drain electrode, and the second source-drain electrode (SD2) may be a source electrode.

[0125] The signal wiring (SL) formed on the panel unit 10, namely the first data voltage (Data1) signal wiring, the second data voltage (Data2) signal wiring, and the first data voltage (Data3) signal wiring, can be formed in the same layer and of the same material as the first source-drain electrode (SD1) and the second source-drain electrode (SD2), and can be electrically connected to each other.

[0126] The storage capacitor (Cst) is positioned away from the thin-film transistor (TFT) and may include a first storage capacitor (Cst1) and a second storage capacitor (Cst2).

[0127] A storage capacitor (Cst) can store voltage so that the light-emitting element (ED) can maintain the same state for an extended period within a single frame.

[0128] A first storage capacitor (Cst1) may be formed between a first capacitor electrode (ST1) and a second capacitor electrode (ST2), and a second storage capacitor (Cst2) may be formed between a second capacitor electrode (ST2) and a third capacitor electrode (ST3).

[0129] The first capacitor electrode (ST1) may be integrated with the light-blocking layer (LS).

[0130] A second capacitor electrode (ST2) is placed on the first capacitor electrode (ST1), and the second capacitor electrode (ST2) can be formed from the same material as the gate electrode (GE).

[0131] A buffer layer (BUF) and a gate insulating layer (GI) are placed between the first capacitor electrode (ST1) and the second capacitor electrode (ST2), which can form a dielectric layer that creates the first storage capacitor (Cst1).

[0132] The third capacitor electrode (ST3) may be integrated with the second source-drain electrode (SD2).

[0133] The second source-drain electrode (SD2) can be electrically connected to the light-blocking layer (LS) via contact holes formed in the buffer layer (BUF) and the interlayer insulating layer (ILD).

[0134] An interlayer insulating layer (ILD) is placed between the second capacitor electrode (ST2) and the third capacitor electrode (ST3), which can become a dielectric layer forming the second storage capacitor (Cst2).

[0135] A first passivation layer (PAS1) can be formed to cover the thin-film transistor (TFT).

[0136] The first passivation layer (PAS1) can serve to prevent the penetration of impurities or moisture into the thin-film transistor (TFT).

[0137] A first overcoat layer (OC1) can be formed on the first passivation layer (PAS1).

[0138] The first overcoat layer (OC1) may also be the first planarization layer, and can play a role in reducing the step caused by the underlying wiring of thin-film transistors (TFTs) and flattening the surface.

[0139] The first overcoat layer (OC1) may contain organic matter, for example, a photoactive compound (PAC), but is not limited to this.

[0140] The first overcoat layer (OC1) and the first passivation layer (PAS1) may have a pair of via holes or a pair of contact holes that expose a portion of the surface of the first source-drain electrode (SD1) and the second source-drain electrode (SD2).

[0141] A second passivation layer (PAS2) containing an insulating material is placed on a first overcoat layer (OC1), and the second passivation layer (PAS2) can extend to the inner side surfaces of a pair of via holes formed through the first overcoat layer (OC1) and the first passivation layer (PAS1).

[0142] However, the second passivation layer (PAS2) can be formed with a pattern that exposes a portion of the surfaces of the first source-drain electrode (SD1) and the second source-drain electrode (SD2).

[0143] A first source-drain connecting electrode (NE1) formed to be electrically connected to the first source-drain electrode (SD1) via a pair of via holes, and a second source-drain connecting electrode (NE2) formed to be electrically connected to the second source-drain electrode (SD2) may be arranged on the second passivation layer (PAS2).

[0144] The first source-drain electrode (SD1) and the first source-drain connecting electrode (NE1) can be named using different terminology, and similarly, the second source-drain electrode (SD2) and the second source-drain connecting electrode (NE2) can also be named using different terminology.

[0145] A light-emitting element (ED) may be placed on the second passivation layer (PAS2).

[0146] In this specification, one embodiment is described in which the light-emitting element (ED) is directly bonded to the panel unit 10 using a self-assembly method, but the specification is not limited thereto.

[0147] In this case, the panel unit 10 can function as a self-assembly substrate for fixing light-emitting elements (EDs) using a self-assembly method, and a self-assembly structure may be formed on the panel unit 10.

[0148] A first assembled electrode (AE1), a second assembled electrode (AE2), a clad electrode (CDE), a first wiring electrode (CE1), and an adhesive layer (AD) may be formed on the second passivation layer (PAS2).

[0149] The first assembled electrode (AE1) and the second assembled electrode (AE2) are arranged spaced apart from each other and can correspond to each of the multiple first light-emitting elements (ED1) assembled by the self-assembly process.

[0150] The assembled electrodes (AE1, AE2) may contain a transparent electrode material containing indium-tin oxide (ITO).

[0151] When a voltage is applied during the self-assembly process, the first assembly electrode (AE1) and the second assembly electrode (AE2) generate an electric field, which allows the light-emitting element (ED) that has moved into the assembly space formed between the first assembly electrode (AE1) and the second assembly electrode (AE2) to be stably fixed in place.

[0152] A clad electrode layer (CDE) is formed on the first assembled electrode (AE1) and the second assembled electrode (AE2), and the clad electrode layer (CDE) can be arranged to cover the first assembled electrode (AE1) and the second assembled electrode (AE2).

[0153] The first assembled electrode (AE1) and the second assembled electrode (AE2) can be formed in the same layer and of the same material as the first source-drain connecting electrode (NE1) and the second source-drain connecting electrode (NE2).

[0154] A clad electrode layer (CDE) is also formed on the first source-drain connecting electrode (NE1) and the second source-drain connecting electrode (NE2), and the clad electrode layer (CDE) can be arranged to cover the first source-drain connecting electrode (NE1) and the second source-drain connecting electrode (NE2).

[0155] The clad electrode layer (CDE) prevents corrosion of the first assembled electrode (AE1) and the second assembled electrode (AE2) during the self-assembly process performed in a fluid, and facilitates the formation of an electric field for the assembly of the light-emitting element (ED).

[0156] The clad electrode layer (CDE) may contain copper (Cu).

[0157] The spacing between the pair of cladding electrode layers (CDE) formed on the first assembled electrode (AE1) and the second assembled electrode (AE2), respectively, can be made smaller than the spacing between the first assembled electrode (AE1) and the second assembled electrode (AE2).

[0158] This allows for more precise fixing of the assembly position of the first light-emitting element (ED1) located within the assembly space formed between the first assembly electrode (AE1) and the second assembly electrode (AE2).

[0159] A third passivation layer (PAS3) may be placed on the clad electrode layer (CDE).

[0160] The third passivation layer (PAS3) can be formed to cover a portion of the upper part of the cladding electrode layer (CDE), while the remaining portion covers the entire surface of the first substrate 100.

[0161] The third passivation layer (PAS3) can be formed such that a region corresponding to the assembly space formed between the first assembly electrode (AE1) and the second assembly electrode (AE2) is exposed.

[0162] The assembly space formed in this way can specify the position where the light-emitting element (ED) is attached.

[0163] An adhesive layer (AD) may be placed on the clad electrode layer (CDE) corresponding to the assembly space, and the adhesive layer (AD) can serve to bond and fix the light-emitting element (ED).

[0164] The adhesive layer (AD) may, but is not limited to, a thermosetting material or a photocuring material.

[0165] A light-emitting element (ED) may be placed on the adhesive layer (AD).

[0166] In this specification, the light-emitting element (ED) is described as a vertical micro-LED (Micro LED) as one embodiment, but the specification is not limited thereto, and the light-emitting element (ED) may be a horizontal micro-LED (Micro LED).

[0167] Furthermore, the light-emitting element (ED) may be a flip-chip shaped micro-LED or a nanoload shaped micro-LED.

[0168] The light-emitting element (ED) may include a semiconductor structure (NSS), a first electrode (E1), and a second electrode (E2).

[0169] The first electrode (E1) of the light-emitting element (ED1) may be the first cathode electrode, and the second electrode (E2) may be the first anode electrode.

[0170] The semiconductor structure (NSS) may be a nitride semiconductor structure and may include a first semiconductor layer, an active layer disposed on one side of the first semiconductor layer, and a second semiconductor layer.

[0171] The first electrode (E1) may be placed on one side of the first semiconductor layer where the active layer is not located, and the second electrode (E2) may be placed on one side of the second semiconductor layer where the active layer is not located.

[0172] For example, the first electrode (E1) can be formed to extend from one surface of the first semiconductor layer to a portion of the side surface of the first semiconductor layer.

[0173] The first semiconductor layer is a layer for supplying electrons to the active layer and may include a nitride semiconductor containing a first conductivity type impurity.

[0174] For example, the first conductivity type impurity may include an N-type impurity.

[0175] The active layer may include a multi-quantum well (MQW) structure. The second semiconductor layer is a layer for injecting holes into the active layer and may include a nitride semiconductor containing a second conductivity type impurity.

[0176] For example, the second type of conductivity impurity may include a p-type impurity.

[0177] A protective layer pattern (PT) may be formed to cover at least a portion of the outer surface of the light-emitting element (ED1).

[0178] The protective layer pattern (PT) can play a role in complementing the characteristics of the device by preventing damage that may occur on the sides of the semiconductor structure (NSS) during the dry etching process performed to form the semiconductor structure (NSS).

[0179] The light-emitting element (ED) can be fixed by having one side of the first semiconductor layer on which the active layer is located, and the other side facing it, in contact with the adhesive layer (AD).

[0180] A first wiring electrode (CE1) is formed on the side surface of the light-emitting element (ED1) so as to surround the first electrode (E1), and can be electrically connected to the first electrode (E1) by contacting it.

[0181] One side of the first wiring electrode (CE1) is formed to cover the clad electrode layer (CDE) and can be electrically connected to the clad electrode layer (CDE) by contacting it.

[0182] Furthermore, a second wiring electrode (CE2) is formed on the light-emitting element (ED1), which can contact and electrically connect with the second electrode (E2).

[0183] A second overcoat layer (OC2) may be formed so as to cover the light-emitting element (ED1).

[0184] The second overcoat layer (OC2) may also be a second planarization layer, and can play a role in reducing the step caused by the underlying wiring such as the light-emitting element (ED1) and making the surface flatter.

[0185] The second overcoat layer (OC2) may contain organic matter, for example, a photoactive compound (PAC), but is not limited to this.

[0186] A first wiring connection electrode (LCE1) and a second wiring connection electrode (LCE2) may be formed on the second overcoat layer (OC2).

[0187] The second wiring electrode (CE2) described above can be named the second wiring connecting electrode (LCE2).

[0188] The first wiring connection electrode (LCE1) and the second wiring connection electrode (LCE2) can be formed in the same layer using the same material.

[0189] The second overcoat layer (OC2) may have a pair of contact holes that penetrate the second overcoat layer (OC2) and the third passivation layer (PAS3) such that a portion of the surface of the cladding electrode layer (CDE) on the first source-drain connecting electrode (NE1) and the second source-drain connecting electrode (NE2) is exposed.

[0190] Furthermore, the second overcoat layer (OC2) may be formed such that at least a portion of the surface of the second electrode (E2) of the light-emitting element (ED) is exposed.

[0191] As a result, the first wiring connection electrode (LCE1) is electrically connected to the first source-drain connection electrode (NE1) by a clad electrode layer (CDE) exposed to the outside through the contact hole, and the second wiring connection electrode (LCE2) is electrically connected to the second source-drain connection electrode (NE2) by a clad electrode layer (CDE) exposed to the outside through the contact hole.

[0192] In this case, the second wiring connection electrode (LCE2), which is electrically connected on one side to the second source-drain connection electrode (NE2), may be positioned to cover the top of the light-emitting element (ED) so as to be electrically connected to the second electrode (E2) as well.

[0193] Therefore, the second wiring connection electrode (LCE2) can be named an anode connection electrode because it is electrically connected to the second electrode (E2), which is the anode electrode.

[0194] In this way, the second wiring coupling electrode (LCE2) electrically connects the second source-drain electrode (SD2) of the thin-film transistor (TFT) to the second electrode (E2), which is the anode electrode of the light-emitting element (ED), allowing the drive signal of the thin-film transistor (TFT) to be applied to the anode electrode of the light-emitting element (ED).

[0195] A spacer (SPC) may be formed between the second overcoat layer (OC2) and the first wiring connecting electrode (LCE1).

[0196] The lower surface of the spacer (SPC) may be in contact with the second overcoat layer (OC2), and the upper surface of the spacer (SPC) may be in contact with the first wiring connection electrode (LCE1).

[0197] As a result, the first wiring connection electrode (LCE1) may be positioned to cover the top surface, including a portion of the side surface of the spacer (SPC).

[0198] The spacer (SPC) may contain organic matter, for example, a photoactive compound (PAC), but is not limited to this.

[0199] The spacer (SPC) can maintain and even increase the separation distance between the wiring board 20 and the panel unit 10.

[0200] When the separation distance between the wiring board 20 and the panel unit 10 is increased by the spacer (SPC), the separation distance between the light-emitting element (ED) and the phototransistor (PHT) also increases.

[0201] This allows the spacer (SPC) to ensure that even when the phototransistor (PHT) is positioned on one side of the light-emitting element (ED), it can still effectively sense the light emitting to the side of the light-emitting element (ED).

[0202] A connecting member 300 may be placed on the first wiring connection electrode (LCE1).

[0203] Specifically, the connecting member 300 may be placed on a first wiring connection electrode (LCE1) that is superimposed on a spacer (SPC) in the vertical direction.

[0204] The connecting member 300 can act as an intermediary to electrically connect the first wiring connection electrode (LCE1) of the panel unit 10 and the link wiring (LL) of the wiring board 20 to each other.

[0205] Furthermore, the connecting member 300 can be made of a conductive material.

[0206] For example, the conductive connecting member 300 can be formed from a metal layer, conductive ink, or a conductive paste such as silver paste, but is not limited to these.

[0207] Furthermore, the connecting member 300 may be an adhesive connecting member containing an adhesive component.

[0208] Thus, because the conductive connecting member 300 has an adhesive component, it can not only electrically connect the first wiring connecting electrode (LCE1) of the panel unit 10 and the link wiring (LL) of the wiring board 20 to each other, but also fix them in place.

[0209] On the other hand, the wiring board 20 may include a second substrate 200, a plurality of phototransistors (PHTs) arranged on the second substrate 200, and various link wirings (LL).

[0210] The second substrate 200 may be made of a transparent material including glass or plastic.

[0211] Therefore, a phototransistor (PHT) may be formed on the second substrate 200.

[0212] Specifically, a photogate electrode (PGE) may be formed, and a gate insulating layer (GI) may be formed to cover the photogate electrode (PGE).

[0213] A photoactive layer (PACT) may be formed on the gate insulating layer (GI), and a first photoelectrode (PE1) in contact with one side of the photoactive layer (PACT) and a second photoelectrode (PE2) in contact with the other side of the photoactive layer (PACT) may be formed on the photoactive layer (PACT).

[0214] A passivation layer (PAS) may be formed on the first photoelectrode (PE1) and the second photoelectrode (PE2), and an overcoat layer (OC) may be formed to cover the passivation layer (PAS).

[0215] The overcoat layer (OC) may also be a planarization layer, and it can play a role in reducing the step caused by the underlying wiring, such as phototransistors (PHTs), and flattening the surface.

[0216] The overcoat layer (OC) may contain organic materials, such as a photoactive compound (PAC), but is not limited to this.

[0217] Furthermore, the overcoat layer (OC) can maintain and even increase the separation distance between the wiring board 20 and the panel unit 10.

[0218] When the separation distance between the wiring board 20 and the panel unit 10 is increased by the overcoat layer (OC), the separation distance between the light-emitting element (ED) and the phototransistor (PHT) also increases.

[0219] This allows the overcoat layer (OC) to effectively ensure the minimum angle necessary to sense light emitting to the side of the light-emitting element (ED), even when the phototransistor (PHT) is positioned on one side of the light-emitting element (ED).

[0220] In the embodiment of the display device 1 described herein, the panel unit 10 on which the light-emitting element (ED) is formed and the wiring substrate 20 on which the phototransistor (PHT) is formed are formed in separate processes and then bonded together. Therefore, the light-emitting element (ED) and the phototransistor (PHT) may be formed on different layers.

[0221] Specifically, in order to effectively sense the light emitted from the light-emitting element (ED), it is preferable that the phototransistor (PHT) be positioned above the light-emitting element (ED).

[0222] However, if the light-emitting element (ED) and the phototransistor (PHT) are arranged to overlap vertically, the phototransistor (PHT) may reduce the light efficiency of the light-emitting element (ED).

[0223] Accordingly, according to one embodiment of this specification, it is preferable that the light-emitting element (ED) and the phototransistor (PHT) are arranged so as not to overlap each other in the vertical direction.

[0224] For example, referring to Figures 4-5 and 10-13, it can be seen that when the region where the light-emitting element (ED) of the panel unit 10 is placed and the region where the phototransistor (PHT) of the wiring board 20 is placed are bonded together, the light-emitting element (ED) and the phototransistor (PHT) are arranged so that they do not overlap each other in the vertical direction.

[0225] However, if the phototransistor (PHT) is too far away from the light-emitting element (ED), the phototransistor (PHT) may have difficulty effectively sensing the light from the light-emitting element (ED). Therefore, it is preferable to place the phototransistor (PHT) as close to the light-emitting element (ED) as possible.

[0226] In this way, the phototransistor (PHT) is positioned so that it does not overlap the light-emitting element (ED) in the vertical direction. This increases the vertical separation distance between the phototransistor (PHT) and the light-emitting element (ED), allowing the phototransistor (PHT) to sense as much light as possible from the side of the light-emitting element (ED).

[0227] Therefore, even if the phototransistor (PHT) and light-emitting element (ED) are arranged so that they do not overlap each other in the vertical direction, it is preferable that the phototransistor (PHT) and light-emitting element (ED) be placed as close together as possible.

[0228] As a result, according to the first embodiment, a spacer (SPC) and an overcoat layer (OC), which may be made of an organic material advantageous for forming a structure having a predetermined height, can be placed between the phototransistor (PHT) and the light-emitting element (ED).

[0229] A second embodiment for increasing the separation distance between the phototransistor (PHT) and the light-emitting element (ED) can be described with reference to Figure 3.

[0230] Referring to Figure 3, the second overcoat layer (OC2) placed on the light-emitting element (ED) and thin-film transistor (TFT) may be formed to be divided into a step-forming layer (OC22) and a reference layer (OC21) having different heights.

[0231] The height of the step-forming layer (OC22) may be formed to be higher than the height of the base layer (OC21).

[0232] Thus, in order to create different heights for the step-forming layer (OC22) and the base layer (OC21) of the same overcoat layer (OC), a photoprocess using a halftone mask can be used.

[0233] In this case, the first wiring connection electrode (LCE1), which is electrically connected to a thin-film transistor (TFT) on one side, may be formed on the step-forming layer (OC22) of the second overcoat layer (OC2).

[0234] Specifically, the lower surface of the first wiring connection electrode (LCE1) can come into contact with the second overcoat layer (OC2).

[0235] Furthermore, the reference layer (OC21) of the second overcoat layer (OC2) can be formed to cover the light-emitting element (ED).

[0236] In other words, the light-emitting element (ED) may be arranged to correspond to the reference layer (OC21).

[0237] As a result, in the second embodiment, unlike the first embodiment, the same effect can be obtained by the height difference of different regions of the overcoat layer without having to form a separate step adjustment member such as a spacer (SPC), which has an effect on process efficiency.

[0238] On the other hand, multiple link wirings (LL) may be formed on the overcoat layer (OC) of the wiring board 20.

[0239] Therefore, the photocontrol signal (Vsto) wiring that transmits the photocontrol signal (Vsto) to the phototransistor (PHT), the photodrive signal (Vdrv) wiring that transmits the photodrive signal (Vdrv) to the phototransistor (PHT), and the photosensing signal (Vsen) wiring that outputs the photosensing signal (Vsen) from the phototransistor (PHT) may be arranged on different layers from multiple link wirings (LL).

[0240] Multiple link wirings (LL) formed on the overcoat layer (OC) can be electrically connected to the first wiring connection electrode (LCE1) of the panel unit 10 by the connecting member 300, thereby enabling the transmission of wiring signals to the signal wiring (SL) of the panel unit 10 via the link wirings (LL) of the wiring board 20.

[0241] Referring to Figures 4 and 5, the multiple high-voltage (Evdd) link wirings, multiple low-voltage (Evss) link wirings, multiple data voltage (Data) link wirings, and multiple scan link wirings formed on the wiring board 20 can be electrically connected to the multiple high-voltage (Evdd) signal wirings, multiple low-voltage (Evss) signal wirings, multiple data voltage (Data) signal wirings, and multiple scan signal wirings formed on the panel unit 10 at the contact portions (CNTs) formed on the wiring board 20.

[0242] In other words, the multiple contact points (CNTs) shown in Figure 5 can correspond to points where the connecting member 300 is placed and the link wiring (LL) and signal wiring (SL) are electrically connected to each other.

[0243] In the following, the display device 1 according to the third embodiment of this specification will be described with further reference to Figures 6 to 8.

[0244] In describing the third embodiment, any content that overlaps with the description of the above embodiments will be omitted, and the description will focus on the differences in configuration.

[0245] This can also be applied to other embodiments described further below.

[0246] Photocontrol signal (Vsto) wiring for transmitting a photocontrol signal (Vsto) to a phototransistor (PHT), photodrive signal (Vdrv) wiring for transmitting a photodrive signal (Vdrv) to a phototransistor (PHT), and photosensing signal (Vsen) wiring for outputting a photosensing signal (Vsen) from a phototransistor (PHT) may be formed on the same layer as at least one of the multiple link wirings (LL).

[0247] For example, on the wiring substrate 20, link branch wiring (LBL) may be formed in the same layer as the photogate electrode (PGE) and made of the same material.

[0248] A gate insulation layer (GI) may be formed on the link branch wiring (LBL), and link wiring (LL) may be formed on the gate insulation layer (GI).

[0249] The link wiring (LL) may be formed in the same layer as the first photoelectrode (PE1) and the second photoelectrode (PE2) and of the same material.

[0250] Link branch wiring (LBL) may be wiring that is branched off from link wiring (LL) so as to be electrically connected.

[0251] A passivation layer (PAS) is formed on the link wiring (LL), and the passivation layer (PAS) is formed such that a portion of the surface area of ​​the link wiring (LL) is exposed, allowing the link wiring (LL) to be electrically connected to the connecting member 300.

[0252] In this way, by arranging the photosignal wiring connected to the phototransistor (PHT) on the same layer as at least one of the link wirings (LL), the process efficiency and space utilization for forming the photosignal wiring connected to the structure that senses light emitted from the light-emitting element (ED) can be improved, thereby achieving a process optimization effect.

[0253] Referring to Figures 7 and 8, the multiple high-voltage (Evdd) link wirings, multiple low-voltage (Evss) link wirings, multiple data voltage (Data) link wirings, and multiple scan link wirings formed on the wiring board 20 can be electrically connected to the multiple high-voltage (Evdd) signal wirings, multiple low-voltage (Evss) signal wirings, multiple data voltage (Data) signal wirings, and multiple scan signal wirings formed on the panel unit 10 at the contact portions (CNTs) formed on the wiring board 20.

[0254] In other words, the multiple contact points (CNTs) shown in Figure 8 can correspond to points where the connecting member 300 is placed and the link wiring (LL) and signal wiring (SL) are electrically connected to each other.

[0255] A display device 1 according to the fourth embodiment of this specification can be further described with reference to Figure 9.

[0256] A sensing circuit section (not shown) for detecting the sensing signal of a phototransistor (PHT) may be formed in the panel unit 10, and a photosensing signal (Vsen) wiring that outputs a photosensing signal from the phototransistor (PHT) can be electrically connected to the sensing circuit section (not shown).

[0257] For example, an overcoat layer (OC) may be formed on a phototransistor (PHT), and multiple link connections (LL) may be formed on the overcoat layer (OC).

[0258] Multiple link connections (LL) may include multiple first link connections (LL1) and multiple second link connections (LL2).

[0259] In this case, the link wiring (LL) can transmit the drive wiring signal to the signal wiring (SL) of the panel unit 10 by the electrical connection between the first link wiring (LL1), which transmits the drive wiring signal of the light-emitting element (ED), and the first wiring connection electrode (LCE1).

[0260] In this case, a first connecting member 310 may be formed between the first link wiring (LL1) and the first wiring connecting electrode (LCE1), and a first spacer (SPC1) may be formed between the first wiring connecting electrode (LCE1) and the second overcoat layer (OC2).

[0261] Furthermore, the link wiring (LL) can transmit the photosensing signal (Vsen) of the phototransistor (PHT) through an electrical connection between the second link wiring (LL2), which transmits the photosensing signal (Vsen) of the phototransistor (PHT), and the sensing circuit section (not shown) formed on the panel unit 10.

[0262] For this purpose, lead-out wiring (ROL) that is electrically connected to a sensing circuit section (not shown) may be formed on the second passivation layer (PAS2) of the panel unit 10.

[0263] The lead-out wiring (ROL) may be formed in the same layer and of the same material as the first source-drain connecting electrode (NE1) and the second source-drain connecting electrode (NE2).

[0264] A clad electrode layer (CDE), a third passivation layer (PAS3), and a second overcoat layer (OC2) may be formed on the lead-out wiring (ROL).

[0265] A third wiring connection electrode (LCE3) may be formed on the second overcoat layer (OC2) in the same layer as the first wiring connection electrode (LCE1) and the second wiring connection electrode (LCE2), and made of the same material.

[0266] The second overcoat layer (OC2) may have contact holes that penetrate the second overcoat layer (OC2) and the third passivation layer (PAS3) so that a portion of the surface of the lead-out wiring (ROL) is exposed.

[0267] This allows the third wiring connection electrode (LCE3) to be electrically connected to the leadout wiring (ROL) by a cladding electrode layer (CDE) exposed to the outside through the contact hole.

[0268] In this case, a second spacer (SPC2) may be formed between the third wiring connection electrode (LCE3) and the second overcoat layer (OC2), and a second connecting member 320 may be formed between the third wiring connection electrode (LCE3) and the second link wiring (LL2).

[0269] The second link wiring (LL2) can be electrically connected to the second photoelectrode (PE2) of the phototransistor (PHT) via contact holes formed in the overcoat layer (OC) and the passivation layer (PAS).

[0270] Therefore, the photosensing signal (Vsen) output from the second photoelectrode (PE2) of the phototransistor (PHT) can be transmitted to a leadout wiring (ROL) that is electrically connected to a sensing circuit section (not shown) by an electrical connection structure such as the second link wiring (LL2), the second connecting member 320, and the third wiring connecting electrode (LCE3).

[0271] In the following, an embodiment of the driving of a phototransistor (PHT) according to the fifth embodiment of this specification will be described with further reference to Figures 14 to 16.

[0272] A phototransistor (PHT) may have a photocontrol signal (Vsto) applied to its gate electrode, the photogate electrode (PGE), a photodrive signal (Vdrv) applied to its source electrode, the first photoelectrode (PE1), and a photosensing signal (Vsen) output from its drain electrode, the second photoelectrode (PE2).

[0273] As explained above, in the case of a phototransistor sensor, when a low-level photocontrol signal (Vsto) is applied to the photogate electrode (PGE) and a high-level photodrive signal (Vdrv) is applied to the first photoelectrode (PE1), the off-current caused by internal or external light sources can be sensed.

[0274] In other words, a phototransistor sensor can be driven by sensing the leakage current (Ioff) generated at the photodrain electrode when light is incident on the phototransistor (PHT) after the phototransistor (PHT) is in an off state, i.e., a low voltage is applied to the photogate electrode (PGE) and a high voltage is applied to the photosource electrode.

[0275] According to embodiments of this specification, the sensing mechanism of these phototransistor sensors can be actively driven (Active matrix; AM) to secure the position coordinates of the sensed values.

[0276] As shown in Figure 14, the addresses of the readout ICs are determined along the X-axis (row direction), and the photo drive signals (Vdrv) can be sequentially driven or switched on / off along the Y-axis (column direction).

[0277] For example, to distinguish the position coordinates of the Y axis, the photo control signal (Vsto) can be fixed at a low voltage, and the photo drive signal (Vdrv) can be driven sequentially from the first stage to the Nth stage.

[0278] In this case, the phototransistor (PHT) can only operate at specific timings when the photo drive signal (Vdrv) is high and sequentially driven, and will not operate in other regions where the photo drive signal (Vdrv) is low.

[0279] In this way, when a sensing value is output at a specific timing, which is when the phototransistor (PHT) is activated, it is determined to be the incidence of a light source, and the Y-axis position coordinate value can be confirmed by the specific timing at which it is sensed.

[0280] In this case, if there is no light source, the sensed value will also disappear at the specific timing when the phototransistor (PHT) is activated.

[0281] Thus, according to one embodiment of this specification, a low-level voltage is applied to a plurality of photocontrol signal (Vsto) wirings that transmit a photocontrol signal (Vsto) to a phototransistor (PHT), and a high-level voltage is sequentially applied along one direction to a plurality of photodrive signal (Vdrv) wirings that transmit a photodrive signal (Vdrv) to a phototransistor (PHT), thereby allowing the position coordinates of the sensed phototransistor (PHT) to be confirmed.

[0282] In this case, a plurality of phototransistors (PHTs) arranged in one direction can share one photosensing signal (Vsen) wiring that outputs a photosensing signal (Vsen) from the phototransistor (PHT).

[0283] The photocontr ol signal (Vsto) wiring for transmitting the photocontr ol signal (Vsto) to the phototransistor (PHT) is formed integrally with the low - potential voltage (Evss) link wiring, and the photosensing signal (Vsen) wiring for outputting the photosensing signal (Vsen) from the phototransistor (PHT) may be formed integrally with the reference voltage (Ref) link wiring.

[0284] In this way, some of the photo signal wirings and the link wirings (LL) are formed integrally with each other and share the same wiring, so there is no need to form separate photo signal wirings from the link wirings (LL), which can improve the efficiency of the process and the space utilization of the wiring substrate 20.

[0285] Hereinafter, referring further to FIGS. 17 to 18, the driving embodiment of the phototransistor (PHT) according to the sixth embodiment of the present specification will be described.

[0286] As shown in FIG. 17, along the X - axis which is the row direction, the address of the lead - out IC is determined, and along the Y - axis which is the column direction, the photocontr ol signal (Vsto) can be driven sequentially or driven in an on / off manner.

[0287] For example, in order to divide the position coordinates of the Y - axis, with the photo drive signal (Vdrv) fixed at a low voltage, the photocontr ol signal (Vsto) can be driven sequentially from the first stage to the Nth stage.

[0288] In this case, the phototransistor (PHT) can be activated only at specific timings when the photocontrol signal (Vsto) is high and sequentially driven, while in other regions where the photocontrol signal (Vsto) is high, the phototransistor (PHT) can generate a full high voltage.

[0289] In this way, when a sensing value is output at a specific timing, which is when the phototransistor (PHT) is activated, it is determined to be the incidence of a light source, and the Y-axis position coordinate value can be confirmed by the specific timing at which it is sensed.

[0290] In this case, if there is no light source, only the fully high-sensing value will be present at the specific timing when the phototransistor (PHT) is activated.

[0291] Thus, according to one embodiment of this specification, a photosensing signal (Vsen) wire that outputs a photosensing signal (Vsen) from a phototransistor (PHT) is shared with a photodrive signal (Vdrv) wire to which a high-level voltage is applied that transmits a photodrive signal (Vdrv) to the phototransistor (PHT). Low-level voltages are sequentially applied along one direction to multiple photocontrol signal (Vsto) wires that transmit a photocontrol signal (Vsto) to the phototransistor (PHT), allowing the position coordinates of the phototransistor (PHT) to be sensed to be confirmed.

[0292] The photodrive signal (Vdrv) wiring that transmits the photodrive signal (Vdrv) to the phototransistor (PHT) can be formed as an integrated unit with the high potential voltage (Evdd) link wiring.

[0293] In this way, some photosignal wiring and link wiring (LL) are formed integrally with each other and share the same wiring, eliminating the need to form link wiring (LL) and separate photosignal wiring. This improves process efficiency and the use of space on the wiring board 20.

[0294] Figures 19 and 20 are graphs showing the leakage current values ​​of a phototransistor measured under different illuminance levels.

[0295] The Vgs value on the X axis represents the difference between the voltage of the photocontrol signal (Vsto) and the voltage of the photosensing signal (Vsen), while the Y axis value represents the leakage current (Id).

[0296] Referring to Figure 19, the leakage current (Off current) was checked with a photo drive signal (Vdrv) of 20V as the baseline. The results showed that while the leakage current increased slightly when the illuminance was 100 Lux and when a red filter (Red CF) was used compared to the dark state, the leakage current increased dramatically by more than 1,000 times when a red laser (Red Laser) was used, or when both a red laser and a red filter were used.

[0297] Furthermore, referring to Figure 20, we confirmed that the leakage current value increases significantly as the illuminance increases, such as to 200 Lux, 500 Lux, and 1000 Lux, compared to the dark state.

[0298] This confirms that the phototransistor (PHT) exhibits a significant difference depending on the illuminance, and that the current value can be increased or decreased by adjusting the Vgs value.

[0299] The display device according to the embodiments described herein, as described above, can be described as follows.

[0300] A display device according to the embodiments of this specification includes a plurality of panel units, each containing a plurality of light-emitting elements; a plurality of link wirings for transmitting wiring signals to the panel units; and a wiring board containing a plurality of phototransistors for sensing light emitted from the light-emitting elements, wherein the plurality of panel units are tiled together on the wiring board.

[0301] According to an embodiment of the present specification, although the phototransistor is located above the light-emitting element, at least one overcoat layer or at least one spacer may be disposed between the phototransistor and the light-emitting element.

[0302] According to an embodiment of the present specification, the overcoat layer and the spacer may be made of an organic material.

[0303] According to an embodiment of the present specification, the phototransistor and the light-emitting element may be arranged so as not to overlap each other in the vertical direction.

[0304] According to an embodiment of the present specification, the panel unit may further include a thin-film transistor that applies a driving signal to the light-emitting element, an overcoat layer disposed on the light-emitting element and the thin-film transistor, a spacer disposed on the overcoat layer, a wiring connection electrode electrically connected to the thin-film transistor and disposed so as to cover the spacer, and a conductive connection member disposed on the wiring connection electrode so as to overlap the spacer in the vertical direction and connected to the link wiring.

[0305] According to an embodiment of the present specification, the panel unit may further include a thin-film transistor that applies a driving signal to the light-emitting element, an overcoat layer disposed on the light-emitting element and the thin-film transistor, a wiring connection electrode electrically connected to the thin-film transistor and disposed on the overcoat layer, and a conductive connection member disposed on the wiring connection electrode and connected to the link wiring. The overcoat layer includes a reference layer and a step-forming layer having a height higher than that of the reference layer, and the conductive connection member may be disposed on the step-forming layer.

[0306] According to an embodiment of the present specification, the light-emitting element may be positioned corresponding to the reference layer.

[0307] According to one embodiment of this specification, the photocontrol signal wiring for transmitting a photocontrol signal to the phototransistor, the photodrive signal wiring for transmitting a photodrive signal to the phototransistor, and the photosensing signal wiring for outputting a photosensing signal from the phototransistor may be arranged on different layers from the link wiring.

[0308] According to one embodiment of this specification, a photocontrol signal wire for transmitting a photocontrol signal to the phototransistor, a photodrive signal wire for transmitting a photodrive signal to the phototransistor, and a photosensing signal wire for outputting a photosensing signal from the phototransistor may be arranged on the same layer as at least one of the plurality of link wires.

[0309] According to one embodiment of this specification, the panel unit further includes a sensing circuit section for detecting a sensing signal from the phototransistor, and a photosensing signal wiring that outputs a photosensing signal from the phototransistor can be electrically connected to the sensing circuit section.

[0310] According to one embodiment of this specification, a plurality of phototransistors arranged in one direction share a single photosensing signal wire that outputs a photosensing signal from the phototransistors, a low-level voltage is applied to a plurality of photocontrol signal wires that transmit a photocontrol signal to the phototransistors, and a high-level voltage is sequentially applied along the one direction to a plurality of photodrive signal wires that transmit a photodrive signal to the phototransistors, thereby allowing the position coordinates of the phototransistors to be sensed to be confirmed.

[0311] According to one embodiment of this specification, a plurality of phototransistors arranged in one direction share one photosensing signal wire that outputs a photosensing signal from the phototransistor and one photodriving signal wire to which a high-level voltage is applied that transmits a photodriving signal to the phototransistor. Low-level voltages are sequentially applied along the one direction to a plurality of photocontrol signal wires that transmit a photocontrol signal to the phototransistor, so that the position coordinates of the phototransistor being sensed can be confirmed.

[0312] According to one embodiment of this specification, the plurality of link wirings include high-potential-voltage link wiring for transmitting a high-potential-voltage to the panel unit, low-potential-voltage link wiring for transmitting a low-potential-voltage to the panel unit, and reference-voltage link wiring for applying a reference voltage to the panel unit, wherein photo-control signal wiring for transmitting a photo-control signal to the phototransistor is formed integrally with the low-potential-voltage link wiring, and photo-sensing signal wiring for outputting a photo-sensing signal from the phototransistor may be formed integrally with the reference-voltage link wiring.

[0313] According to one embodiment of this specification, the plurality of link wirings include high-potential-voltage link wiring for transmitting a high-potential-voltage to the panel unit, low-potential-voltage link wiring for transmitting a low-potential-voltage to the panel unit, and reference-voltage link wiring for applying a reference voltage to the panel unit, and photo-drive signal wiring for transmitting a photo-drive signal to the phototransistor can be formed integrally with the high-potential-voltage link wiring.

[0314] The embodiments of this specification have been described in more detail above with reference to the attached drawings. However, this specification is not necessarily limited to these embodiments, and various modifications are possible within the scope of the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by these embodiments. Accordingly, the embodiments described above should be understood as illustrative in all respects and not limiting. [Explanation of Symbols]

[0315] 1 Display device 10 Panel Units 20 Wiring boards LL Link Wiring LL1 First Link Wiring LL2 Second Link Wiring LBL Link Branch Wiring 30 Circuit Films 32 Data Drivers 34 Printed circuit boards 100 First board BUF (Buffer Layer) LS light-blocking layer TFT Thin-Film Transistor ACT Active Layer SE Source Electrode SD1 First source-drain electrode SD2 Second Source-Drain Electrode GE Terminal GI gate insulating layer ILD (Interlayer Insulation Layer) Cst1 First Storage Capacitor Cst2 Second Storage Capacitor ST1 First Capacitor Electrode ST2 Second Capacitor Electrode ST3 Third Capacitor Electrode PAS1 First Passivation Layer OC1 First overcoat layer PAS2 Second Passivation Layer NE1 First source-drain coupling electrode NE2 Second Source-Drain Connecting Electrode PAS3 Third Passivation Layer OC2 Second Overcoat Layer OC21 reference layer OC22 Step-forming layer CA circuit section EA light-emitting part LA Wiring Section TA transparent part SL signal wiring LCE1,PXL 1st wiring connection electrode LCE2,PXL 2nd wiring connection electrode LCE3 3rd wiring connection electrode ED light-emitting element ED1 First light-emitting element ED11 First color first light-emitting element ED12 Second hue first light-emitting element ED13 First light-emitting element of the third hue ED2 Second light-emitting element ED21 Second light-emitting element of the first hue ED22 Second light-emitting element of the second hue ED23 Second light-emitting element of the third hue CDE clad electrode layer AD adhesive layer E1 1st electrode E2 2nd electrode NSS Semiconductor Structure CE1 1st wiring electrode CE2 2nd wiring electrode PT protective layer pattern AE1 First Assembly Electrode AE2 Second Assembly Electrode PAS Passivation Layer OC Overcoat Layer PHT phototransistor PGE Photographic Photographic Site PACT Photoactive Layer PSD Photosource-Drain Electrodes PE1 First photoelectrode PE2 Second photoelectrode SPC Spacer SPC1 1st Spacer SPC2 2nd Spacer 300 Connecting Member 310 First connecting member 320 Second connecting member ROL leadout wiring CNT Contact Section SCT Scan Thin-Film Transistor SET Sensing Thin Film Transistor OCR optical resin layer

Claims

1. Multiple panel units, each containing at least one light-emitting element; An overcoat layer disposed to cover the light-emitting element; and A wiring board including a plurality of link wirings for transmitting wiring signals to the panel unit, and a plurality of phototransistors for sensing light emitted from the light-emitting element; The plurality of phototransistors are arranged on the light-emitting element and the wiring substrate on the overcoat layer, The aforementioned multiple panel units are coupled to the wiring board in a tile manner, Display device.

2. The phototransistor is located above the light-emitting element, At least one overcoat layer or at least one spacer is placed between the phototransistor and the light-emitting element. The display device according to claim 1.

3. The overcoat layer and the spacer are made of organic material. The display device according to claim 2.

4. The phototransistor and the light-emitting element are arranged so that they do not overlap each other in the vertical direction. The display device according to claim 1.

5. The aforementioned panel unit is A thin-film transistor that applies a drive signal to the light-emitting element; Spacers placed on the aforementioned overcoat layer; A wiring connection electrode electrically connected to the thin-film transistor and positioned to cover the spacer; and A conductive connecting member is positioned on the wiring connecting electrode so as to overlap the spacer in the vertical direction and connects to the link wiring; further comprising The display device according to claim 1.

6. The aforementioned panel unit is A thin-film transistor that applies a drive signal to the light-emitting element; A wiring connection electrode electrically connected to the thin-film transistor and disposed on the overcoat layer; and A conductive connecting member disposed on the wiring connecting electrode and connected to the link wiring; further includes, The overcoat layer is disposed on the thin-film transistor and includes a reference layer and a step-forming layer having a height higher than the reference layer. The conductive connecting member is disposed on the step-forming layer, The display device according to claim 1.

7. The light-emitting element is disposed within the reference layer, The display device according to claim 6.

8. The aforementioned wiring board, Photocontrol signal wiring for transmitting a photocontrol signal to the phototransistor, Photo drive signal wiring for transmitting a photo drive signal to the phototransistor, and Photosensing signal wiring that outputs a photosensing signal from the aforementioned phototransistor. The further includes the photo control signal wiring, the photo drive signal wiring, and the photo sensing signal wiring being located on a different layer from the layer on which the link wiring is located. The display device according to claim 1.

9. The aforementioned wiring board, Photocontrol signal wiring for transmitting a photocontrol signal to the phototransistor, Photo drive signal wiring for transmitting a photo drive signal to the phototransistor, and Photosensing signal wiring that outputs a photosensing signal from the aforementioned phototransistor. The photo control signal wiring, the photo drive signal wiring, and the photo sensing signal wiring are located on the same layer as the layer on which at least one of the plurality of link wirings is located. The display device according to claim 1.

10. The panel unit further includes a sensing circuit section for detecting the photosensing signal of the phototransistor, The wiring board further includes a photosensing signal wiring that outputs a photosensing signal from the phototransistor, and the photosensing signal wiring is electrically connected to the sensing circuit section. The display device according to claim 1.

11. The plurality of phototransistors arranged in one direction share a single photosensing signal wiring that outputs a photosensing signal from the phototransistors. A low-level voltage is applied to the multiple photocontrol signal wires that transmit the photocontrol signal to the phototransistor. A high-level voltage is sequentially applied along the one direction to the multiple photodrive signal wiring that transmits the photodrive signal to the phototransistor. The position coordinates of the sensed phototransistor among the plurality of phototransistors arranged in one direction are confirmed. The display device according to claim 1.

12. The plurality of phototransistors arranged in one direction each share one photosensing signal wire that outputs a photosensing signal from the phototransistor and one photodriving signal wire to which a high-level voltage is applied that transmits a photodriving signal to the phototransistor. Multiple photocontrol signal lines that transmit photocontrol signals to a phototransistor are sequentially subjected to a low-level voltage along the aforementioned one direction. The position coordinates of the sensed phototransistor among the plurality of phototransistors arranged in one direction are confirmed. The display device according to claim 1.

13. The aforementioned multiple link wirings are, High-voltage link wiring for transmitting a high-potential voltage to the panel unit; Low-voltage link wiring for transmitting a low-voltage signal to the panel unit; and Includes a reference voltage link wiring for applying a reference voltage to the panel unit; The aforementioned wiring board is Photocontrol signal wiring for transmitting a photocontrol signal to the phototransistor, and Photosensing signal wiring that outputs a photosensing signal from the aforementioned phototransistor. It further includes, The aforementioned photo control signal wiring is formed integrally with the aforementioned low-voltage link wiring. The photosensing signal wiring is formed integrally with the reference voltage link wiring. The display device according to claim 1.

14. The aforementioned multiple link wirings are, High-voltage link wiring for transmitting a high-potential voltage to the panel unit; Low-voltage link wiring for transmitting a low-voltage signal to the panel unit; and Includes a reference voltage link wiring for applying a reference voltage to the panel unit; The wiring board further includes photo drive signal wiring for transmitting a photo drive signal to the phototransistor, The aforementioned photo drive signal wiring is formed integrally with the aforementioned high-potential voltage link wiring. The display device according to claim 1.

15. Multiple panel units, each including multiple light-emitting elements and multiple signal wiring connected to the multiple light-emitting elements, An overcoat layer is positioned to cover the light-emitting element, The wiring board includes a plurality of link wires connected to the plurality of signal wires on the plurality of panel units, and a phototransistor configured to sense light emitted from the plurality of light-emitting elements, The phototransistor is arranged on the wiring substrate on the overcoat layer and the light-emitting element. The aforementioned multiple panel units are coupled to the wiring board in a tile manner, Display device.

16. The phototransistor, in the turn-off state, outputs an off-current in response to light emitted from the light-emitting element. Based on the detection result of the off-current output from the phototransistor, the light from the light-emitting element located at a specific pixel is sensed. The display device according to claim 15.

17. The current of the thin-film transistor that drives the light-emitting element is sensed to compensate for the brightness difference between the light-emitting elements. The display device according to claim 16.

Images