Integrated method and tool for high-quality selective silicon nitride deposition

JP7874767B2Active Publication Date: 2026-06-16APPLIED MATERIALS INC

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
APPLIED MATERIALS INC
Filing Date
2025-03-17
Publication Date
2026-06-16

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Abstract

To provide processing method and tool for forming a logic and memory device.SOLUTION: A processing method performed in a processing tool without breaking vacuum includes pre-cleaning a top surface of a film stack, the film stack including alternating layers of a first material layer and a second material layer and having one or more of memory holes and slit pattern openings extending through the film stack. The method also includes exposing the top surface of the film stack to a growth inhibitor, selectively depositing a silicon-containing dielectric layer in regions of the film stack, and densifying the silicon-containing dielectric layer.SELECTED DRAWING: Figure 5
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Claims

1. A processing method for forming a logical device or a memory device, wherein the processing method is Pre-cleaning the exposed surface of a memory hole or slit pattern opening of a film stack, wherein the film stack comprises alternating layers of a plurality of first material layers and a corresponding plurality of second material layers, and has one or more of the memory holes and slit pattern openings extending through the film stack. The process involves selectively depositing a silicon-containing dielectric layer within a region of the film stack, wherein the region is adjacent to each of the plurality of first material layers within the memory holes or slit pattern openings of the film stack. To increase the density of the silicon-containing dielectric layer and Includes, A processing method for forming a logical device or memory device, wherein the processing method is performed within a processing tool without disrupting the vacuum.

2. Pre-cleaning the upper surface of the high-density silicon-containing dielectric layer, Selectively depositing a second silicon-containing dielectric layer within the region of the aforementioned film stack, The second silicon-containing dielectric layer is made denser and The processing method according to claim 1, further comprising:

3. Selectively depositing a second silicon-containing dielectric layer within the region of the film stack, The second silicon-containing dielectric layer is made denser and The processing method according to claim 1, further comprising:

4. The processing method according to claim 1, wherein each of the plurality of second material layers includes an oxide layer.

5. The processing method according to claim 1, wherein the region is a concave region formed by recessing each of the plurality of first material layers relative to each of the plurality of second material layers through the memory hole or the slit pattern opening.

6. The processing method according to claim 1, wherein the region is located on the word line side of the film stack.

7. The processing method according to claim 1, wherein each of the plurality of first material layers includes one or more of polysilicon, silicon nitride, silicon carbide, silicon carbonitride, germanium, and titanium nitride.

8. The processing method according to claim 1, wherein the silicon-containing dielectric layer comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride, silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN).

9. The processing method according to claim 8, wherein the silicon-containing dielectric layer contains silicon nitride.

10. The processing method according to claim 1, wherein selective deposition of the silicon-containing dielectric layer includes deposition at a temperature lower than 500°C.

11. The processing method according to claim 1, wherein the silicon-containing dielectric layer has a wet etching rate of less than 1 Å / min.

12. The processing method according to claim 1, wherein increasing the density of the silicon-containing dielectric layer includes subjecting the silicon-containing dielectric layer to a rapid heat treatment (RTP) process.

13. Increasing the density of the silicon-containing dielectric layer involves exposing the silicon-containing dielectric layer to a high-density plasma at a temperature of 500°C or less and a pressure of less than 1 Torre, wherein the high-density plasma is composed of helium (He) and hydrogen (H 2 The processing method according to claim 1, wherein one or more of the following are selected: ) and neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

14. The processing method according to claim 1, wherein the silicon-containing dielectric layer has a thickness in the range of more than 0 Å to 25 Å.

15. The processing method according to claim 1, further comprising oxidizing the silicon-containing dielectric layer.

16. The processing method according to claim 1, wherein the processing tool is selected from the group consisting of a single processing chamber and a batch processing chamber.

17. After selectively depositing the silicon-containing dielectric layer, the film stack is further exposed to a growth inhibitor, The method involves selectively depositing a second silicon-containing layer within a region of the film stack, wherein the region is adjacent to the silicon-containing dielectric layer within the memory holes or slit pattern openings of the film stack. The second silicon-containing layer is made denser and The processing method according to claim 1, further comprising:

18. A second silicon-containing layer is selectively deposited within a region of the film stack, wherein the region is a region adjacent to the silicon-containing dielectric layer within the memory hole or slit pattern opening of the film stack. The second silicon-containing layer is made denser and The processing method according to claim 1, further comprising:

19. The processing method according to claim 1, further comprising repeating one or more of the following: pre-cleaning the upper surface of the film stack, selectively depositing a silicon-containing dielectric layer, and increasing the density of the silicon-containing dielectric layer.

20. It is a processing tool, A central transfer station including a robot configured to move wafers, A plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing area of ​​an adjacent process station, wherein the plurality of process stations include one or more of a pre-washing chamber, an inhibitor immersion chamber, a selective deposition chamber, and a densification chamber, A controller connected to the central transfer station and the plurality of process stations, wherein the controller is configured to operate the robot to move the wafer between the process stations and to control the processes performed at each of the process stations. Includes, The aforementioned controller A pre-cleaning operation of a film stack, wherein the film stack comprises alternating layers of a plurality of first material layers and a corresponding plurality of second material layers, and has one or more memory holes and slit pattern openings extending through the film stack. A deposition operation comprising selectively depositing a silicon-containing dielectric layer within a region of the film stack, wherein the region is a region adjacent to each of the plurality of first material layers within the memory holes or slit pattern openings of the film stack, The operation of increasing the density of the silicon-containing dielectric layer The processing tool is made to execute the above, A processing tool, which is maintained under vacuum.