Clock timing in replicated arrays

Abstract

The present disclosure relates to systems and methods for simulating clock timing distribution across a node array 204. An exemplary method includes accessing a timing model of a computational node 206, where the timing model of the computational node 206 represents timing data related to clock signal propagation between the computational node 206 and four neighboring nodes of the node array 204, each neighboring node abutting the computational node 206, and using a computing device to simulate clock signal timing distribution of a majority of the nodes of the node array 204 using the timing model of the computational node 206.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of priority of U.S. Provisional Application No. 63 / 371,993, filed on August 19, 2022, entitled "CLOCK TIMING IN REPLICATED ARRAYS", the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] The present disclosure generally relates to distributed clocking, and more particularly to techniques for modeling clocking in arrays.

Background Art

[0003] High - density processing systems can be constructed using an array of processing nodes. The nodes can communicate with neighboring nodes to execute processing tasks. Communication between nodes can use synchronous and / or asynchronous methods. A clock signal can be provided to each node so that the nodes can be synchronized, which can enable communication between the nodes.

Summary of the Invention

Means for Solving the Problems

[0004] The technical innovations described in the claims each have several aspects, and only one of which alone bears its desirable attributes. Without limiting the claims, some prominent features of the present disclosure are briefly described here.

[0005] One aspect of the present disclosure is a method for simulating a node array. The method includes accessing a timing model of the compute nodes of the node array, stored in non-temporary computer-readable memory, and using one or more computers to simulate the clock signal timing of most of the nodes in the node array using the compute node timing model. The compute node timing model represents timing data related to clock signal propagation between a compute node and four neighboring nodes in the node array, each of which is adjacent to the compute node.

[0006] This method may also include determining the worst-case timing of clock signals within a node array based on simulation.

[0007] This method may also include adjusting the clock distribution network of the node array based on worst-case timing. In addition, adjusting the clock distribution network may include updating one or more files representing the circuit configuration of the node array. Furthermore, this method may further include accessing a global node timing model of the node array, which is stored in non-temporary computer-readable memory. Determinism may be based on a simulation of clock signal timing using the global node timing model.

[0008] In this method, simulation may include simulating mesochronous clocking in a node array.

[0009] In this method, the timing model of the node array can model a compute node that receives a clock signal from a first pair of four neighboring nodes and a compute node that provides a clock signal to a second pair of four neighboring nodes. In addition, the clock signal may be delayed by one delay unit at the compute node relative to the first pair of neighboring nodes. Furthermore, the clock signal may be delayed by two delay units at the second pair of neighboring nodes relative to the first pair of neighboring nodes.

[0010] In this method, the timing model for the node array is a block group timing model. Furthermore, the node array can essentially consist of instances of compute nodes and instances of global nodes.

[0011] In this method, the majority of the nodes in the node array can include at least 90% of the nodes in the node array.

[0012] This method may further include generating a timing model for a computing node by at least simulating the propagation of clock signals between the computing node and four neighboring nodes.

[0013] Another aspect of the present disclosure is non-temporary computer-readable storage containing instructions that, when executed by one or more processors, cause a method to simulate a node array. The method includes accessing a timing model of the compute nodes of the node array, stored in non-temporary computer-readable memory, and using one or more computers to simulate the clock signal timing of most of the nodes of the node array using the compute node timing model. Furthermore, the compute node timing model represents timing data related to clock signal propagation between a compute node and four neighboring nodes of the node array, each of which is adjacent to the compute node.

[0014] Another aspect of the present disclosure is a computer system for simulating a node array. The system includes non-temporary computer-readable memory for storing a timing model of the compute nodes of the node, and one or more processors configured to at least access the timing model of the compute nodes and to execute instructions for simulating the clock signal timing of most of the nodes in the node array using the timing model of the compute nodes. Furthermore, the timing model of the compute nodes represents timing data related to clock signal propagation between the compute node and four neighboring nodes in the node array, each of which is adjacent to the compute node.

[0015] Another aspect of the present disclosure is a system for simulating clock timing distribution across a node array comprising a plurality of compute nodes. The system may include compute nodes and one or more computing devices configured to store timing models, each of which corresponds to four neighboring compute nodes with neighboring compute codes adjacent to the compute node. Furthermore, individual computing devices of one or more computing devices are configured to access the timing models of compute nodes and to use the computing devices to simulate the clock signal timing distribution of most of the nodes in the node array using the timing models of compute nodes.

[0016] Another aspect of the present disclosure is a non-temporary computer-readable storage medium for storing instructions for simulating clock timing distribution across a node array. When executed by a processor, the instructions cause the processor to perform operations including accessing a timing model of compute nodes and using a computing device to simulate the clock signal timing distribution of most of the nodes in the node array using the compute node timing model. Furthermore, the compute node timing model represents timing data related to clock signal propagation between a compute node and four neighboring nodes in the node array, each of which is adjacent to the compute node.

[0017] In a non-temporary computer-readable storage medium, operation may include determining the worst-case timing of clock signals within a node array based on simulation. Furthermore, the non-temporary computer-readable storage medium may include adjusting the clock distribution network of the node array based on the worst-case timing. Adjusting the clock distribution network may include updating one or more files representing the circuit configuration of the node array.

[0018] In non-temporary computer-readable storage media, operation may involve accessing a timing model of the global nodes of a node array, which is stored in non-temporary computer-readable memory. Decisions are based on simulations of clock signal timing using the global node timing model.

[0019] On non-temporary computer-readable storage media, simulation includes simulating mesochronous clocking in a node array.

[0020] In a non-temporary computer-readable storage medium, the timing model of a node array can model a compute node receiving a clock signal from a first pair of four neighboring nodes, and a compute node providing a clock signal to a second pair of four neighboring nodes. In addition, the clock signal may be delayed by one delay unit at the compute node relative to the first pair of neighboring nodes. Furthermore, the clock signal may be delayed by two delay units at the second pair of neighboring nodes relative to the first pair of neighboring nodes.

[0021] In non-temporary computer-readable storage media, the timing model for a node array can be a block-group timing model. Furthermore, a node array can essentially consist of instances of compute nodes and instances of global nodes.

[0022] In a non-transitory computer-readable memory medium, most of the nodes of the node array can include at least 90% of the nodes of the node array.

[0023] In a non-transitory computer-readable memory medium, the operation can also include generating a timing model of a computing node by at least simulating clock signal propagation between the computing node and four neighboring nodes.

[0024] For the purpose of summarizing the present disclosure, certain aspects, advantages, and novel features of the technological innovation are described herein. It should be understood that not all of such advantages may necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or implemented to achieve or optimize one advantage or group of advantages as taught herein without necessarily achieving other advantages that may be taught or suggested herein.

Brief Description of the Drawings

[0025] Embodiments of the present disclosure will be described by way of non-limiting examples with reference to the accompanying drawings.

[0026] [Figure 1] It is a schematic block diagram of an exemplary chip according to an aspect of the present disclosure.

[0027] [Figure 2A] It is a schematic diagram of a clock distribution network according to an embodiment.

[0028] [Figure 2B] It is a diagram showing an exemplary implementation form of a clock distribution circuit configuration in an exemplary node of the node array of FIG. 2A.

[0029] [Figure 2C] It is a diagram showing another exemplary implementation form of a clock distribution circuit configuration in an exemplary node of the node array of FIG. 2A.

[0030] [Figure 3A] This is a node clock level map associated with an exemplary node array, such as the node array in Figure 2A.

[0031] [Figure 3B] This is the node clock level topology corresponding to the node clock level map in Figure 3A.

[0032] [Figure 4] This figure shows an example implementation of the node array in Figure 1.

[0033] [Figure 5] This figure shows the characterization of the node array in Figure 1 for modeling the clock timing distribution across the node array.

[0034] [Figure 6] This figure shows an example of a node array block in Figure 5.

[0035] [Figure 7] This figure shows an exemplary embodiment of a computing device. [Modes for carrying out the invention]

[0036] The following detailed descriptions of several embodiments present various descriptions of specific embodiments. However, the technological innovations described herein can be embodied in numerous different ways, for example, as defined and encompassed by the claims. In this description, similar reference numbers and / or terms refer to drawings where identical or functionally similar elements may be shown. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements and / or subsets of elements shown in the drawings than those shown. In addition, in some embodiments, any suitable combination of features from two or more drawings may be integrated. The headings provided herein are for convenience only and do not necessarily affect the claims or their meaning. Overview of Distribution Clocking for Node Arrays

[0037] This disclosure relates to a clock distribution network having clock signals that arrive at different nodes of a node array at different times. Generating clock signals with a fixed offset may be referred to as mesochronous clocking. Embodiments disclosed herein relate to a mesochronous clock network constructed modularly with a common circuit configuration. The clock signals of such a network may be locally low-skew and mesochronous at a coarser level.

[0038] The principles and advantages disclosed herein can be applied to any suitable circuit chip. In certain applications, the clock signal distribution disclosed herein can be applied to a chip containing an array of smaller compute nodes, each of which may be referred to as a processor or core. In this way, the clock signal can form an arrival time wave across the array of compute nodes. Each compute node can, in one embodiment, receive a low-skew clock. The compute nodes in the array can be designed using only interfaces to neighboring compute nodes, taking into account the arrival time difference (skew) of the mesochronous clock phases. The techniques described herein can be applied to square node arrays (equal rows and columns) or rectangular node arrays having a different number of rows than columns.

[0039] Figure 1 is a schematic block diagram of an exemplary chip 100 according to an aspect of the present disclosure. Chip 100 may be an integrated circuit die. Chip 100 may include a node array 102 (also referred to as a compute node array) with distribution clocking, one or more serializer / deserializer (SerDes) clock blocks 104, a clock generator 106, and a clock controller 108. The SerDes clock blocks 104 can interface with other chips 100 to form an array of chips 100. In certain application examples, the node array 102 may be included in a system-on-wafer system, an array of chips 100 on a printed circuit board, etc. In certain applications, the node array 102 of Figure 1 may be implemented on a system on a wafer that is packaged in a wafer-level packaging structure. As shown in the embodiment of Figure 1, the clock generator 106 may be implemented outside the node array 102. In some embodiments, the clock generator 106 may include a phase-locked loop (PLL). The clock generator 106 can be positioned to provide clock signals to compute nodes located at the corners of the node array 102. The clock controller 108 can also be implemented outside the node array 102. Nodes within the node array 102 may include inter-node interfaces that can be configured to communicate synchronously. Inter-core-serializer / deserializer (SerDes) interfaces may be asynchronous. In some embodiments, the PLL operates in a 100 MHz reference frequency bandwidth, but other frequency bandwidths are intended to be within the scope of this disclosure. The PLL may be configured to generate source clocks for various operating modes, including functional mode, bypass mode, and test mode. The PLL may operate without glitch source clock selection and may be configured to manage thermal issues and maximum current via clock throttling. In some examples, clock throttling, OGG (on-chip clock control) for scan capture, and clock ramp-up / down are implemented, for example, by cycle skipping to modulate the effective frequency using a 32x32 pattern of first-in, first-out (FIFO).

[0040] In the node array 102 with distribution clocking shown in Figure 1, each node may be an instance of a computing circuit (also referred to as a processing core or compute node). In certain applications, the majority of nodes may be implemented as instances of computing circuits, and one or more nodes may be implemented as instances of different circuits. Each node in the node array 102 may contain instances of substantially the same clock distribution circuit configuration, even if at least some of the other circuit configurations of the node differ from those of the other nodes. For example, the majority of nodes may be implemented as instances of computing circuits, and one or more nodes may be implemented as instances of a global node. The global node may include process, voltage, and temperature (PVT) sensors (not shown in Figure 1). In the node array 102, nodes can be tiled and touching. For example, each node in the node array 102 is self-contained and can interconnect with adjacent nodes (e.g., touching nodes). At the same time, the node array 102 can be implemented without using top-level wiring, gates, or channels. Therefore, nodes can be configured to communicate with neighboring nodes using low-level wiring over relatively short connections. In some embodiments, the nodes of node array 102 can be arranged in a stepped pattern without mirroring or rotation. In certain implementation forms, nodes are connected to power lines (V DD / V SS The nodes can be aligned to the grid pitch. For example, the height and width of each node can be a multiple of the power grid pitch. The power grid pitch can then be further aligned to the bump pitch.

[0041] Each node in node array 102 may include substantially the same instance of the clock distribution circuit configuration. Nodes can be designed so that their output clock wiring aligns with the input clock wiring of their neighboring nodes. Nodes can be arranged in a stepped and tiled configuration within the node array so that their clock output wiring aligns with and is electrically connected to the clock input wiring of neighboring nodes located downstream to receive the clock signal. Such electrical connections allow the node array to be implemented without channels or top-level wiring for clock distribution. In certain embodiments, the fan-out of the clock distribution circuit configuration can be balanced relative to the inverter.

[0042] As described herein, a clock signal received at a root node may propagate from the root node to two neighbor nodes with one delay unit. The root node may be located at a corner of the node array 102. The delay unit can be a fixed offset of a given node array. The delay unit may correspond to the delay from buffering the clock signal (e.g., using an inverter) and the wiring delay associated with the propagation of the clock signal to its neighbor nodes. For example, in one embodiment, one of the two neighbor nodes is in the same row as the root node, and the other of the two neighbor nodes is in the same column as the root node. As an example, the neighbor nodes are located south and east of the root node. In this configuration, the clock signal continues to propagate, in this example, from the two neighbor nodes in the node array to the south and east neighbor nodes with one additional delay unit. Such clock signal propagation continues through the clock distribution network until the clock signal reaches a node in the node array at the corner opposite the root node. In some examples, a signal routed from an originating node (e.g., a node located at the southeast corner of node array 102) to a node located to the north or west may travel upstream and lose one unit delay in the node array, while a signal routed from an originating node (e.g., a node located at the southeast corner of node array 102) to a node located to the south or east may travel downstream and gain one unit delay in the node array. In some applications, a signal traveling upstream can be routed faster than a signal traveling downstream to account for the unit delay and meet setup and hold time specifications.

[0043] One of two neighboring nodes may be located in the same row as the root node, and the other of the two neighboring nodes may be located in the same column as the root node. In some embodiments, neighboring nodes are adjacent to the root node. For example, neighboring nodes are located south and east of the root node, as shown in Figure 2A. For example, the neighboring nodes of node 206A may be nodes 206B and 206C. In this example, the clock signal continues to propagate from the two neighboring nodes of the root node in the node array to the south and east neighboring nodes with one additional delay unit. Such clock signal propagation continues through the clock distribution network in node array 102 until the clock signal reaches a node in node array 102 at the opposite corner from the root node. In some examples, a signal routed from an originating node (e.g., node 206D) to a neighboring node north or west of the originating node may travel upstream to the destination node (e.g., node 206A), losing one unit of delay in node array 102. This signal routing is referred to as upstream signal movement. Signals routed from an originating node (e.g., node 206A) to a neighboring node to the south or east can travel downstream to the destination node (e.g., node 206D), gaining a 1-unit delay in node array 102. This can be referred to as downstream signal movement. Signals traveling upstream can be routed faster than signals traveling downstream, taking into account the unit delay and meeting the setup and hold time specifications.

[0044] Figure 2A is a schematic diagram of a clock distribution network 200 according to one embodiment. The clock distribution network 200 includes a clock management unit (CMU) 202 and a clock distribution circuit configuration of a node array 204 (also referred to as a clock distribution node array) of nodes 206. Each node 206 includes an instance of the clock distribution circuit configuration for distributing clock signals within the node array 204. In the embodiment of Figure 2A, the clock distribution network 200 has a 2D distributed, strapped H-tree topology. The CMU 202 is configured to output a clock signal, which is received by the root node 206A of the node array 204.

[0045] Referring to Figure 2A, the root may be located at the input to node 206 at a corner of node array 204. For example, the root may be located at the input to node 206 (e.g., node 206A) at the northwest or upper left corner of node array 204 as shown in Figure 2A. In other embodiments, the root may be at the input to node 206 at another corner of node array 204 (e.g., node 206D) when the clock signal propagates in different directions along the rows and / or columns of the node. A node 206 that receives the clock signal from outside node array 204 may be referred to as the root node 206.

[0046] Referring further to Figure 2A, the clock distribution network 200 can be implemented using a node array 204. The node array 204 shown in Figure 2A is an example of the node array 102 with distribution clocking in Figure 1. In certain embodiments, each node 206 may be an instance of a computing circuit. In certain applications, most of the nodes 206 include instances of computing circuits, and one or more of the remaining nodes 206 include instances of different circuits, such as a global node. A global node may refer to a node 206 that does not include a circuit configuration for performing processing tasks. In some examples, a global node may include process, voltage, and temperature (PVT) sensors. In some implementations, both computing nodes and global nodes may include a communication interface that enables communication with neighboring nodes 206. In some implementations, the communication interface for the computing nodes may be the same as the communication interface for the global nodes.

[0047] In certain embodiments, each node 206 of the node array 204 may include instances of the same clock distribution circuit configuration, even if one or more other circuit configurations of the node 206 differ from those of other nodes 206. In one embodiment of the node array 204, the nodes 206 can be tiled and touching. At the same time, the node array 204 can be implemented without top-level wiring or gates. Thus, a node 206 can communicate with a neighboring node 206 using low-level wiring via short connections. The nodes 206 of the node array 204 can be stepped without mirroring or rotation. The nodes 206 can also be aligned to the grid pitch of the power (VDD / VSS) lines. For example, the height and width of each node 206 can be a multiple of the power grid pitch. In some embodiments, the power grid pitch can be further aligned to the bump pitch.

[0048] As shown in Figure 2A, each node 206 may contain an instance of substantially the same clock distribution circuit configuration. Figure 2B shows an exemplary implementation of the clock distribution circuit configuration in an exemplary node 206 of the node array 204 in Figure 2A. Referring to Figures 2A and 2B, the clock distribution circuit configuration includes a first input clock wire 222, a second input clock wire 224, a first inverter 226, a second inverter 228, a third inverter 230, a fourth inverter 232, a clock tap point 234, a first output clock wire 236, and a second output clock wire 238.

[0049] The clock distribution circuit configuration for each node 206 is designed such that the output clock traces 236 and 238 of node 206 align with the input clock traces 222 and 224 of neighboring node 206. Node 206 can be stepped and tiled within the node array 204 so that its output clock traces 236 and 238 align with and are electrically connected to the two input clock traces 222 and 224 of neighboring node 206. These electrical connections allow the node array 204 to be implemented without using channels or top-level traces for clock distribution.

[0050] Returning to Figure 2B, input wires 222 and 224 can receive input clock signals from two of the neighboring nodes 206. For example, the first input clock wire 222 receives the input clock signal from a neighboring node 206 above the current node 206, while the second input clock wire 224 receives the input clock signal from a neighboring node 206 to the left of the current node 206. The first input clock wire 222 and the second input clock wire 224 provide the clock signals to the first inverter 226 and the second inverter 228. The first inverter 226 inverts the clock signal and provides the inverted clock signal to the clock tap point 234, which then provides the clock signal to the primary circuit configuration of the corresponding node in the compute node array 102 (e.g., the compute circuit or global circuit in a particular embodiment).

[0051] The second inverter 228 inverts the clock signal and provides the inverted clock signal to the third inverter 230 and the fourth inverter 232. Each of the third inverter 230 and the fourth inverter 232 inverts the inverted clock signal and outputs the resulting clock signal to the first output clock wire 236 and the second output clock wire 238. The first output clock wire 236 and the second output clock wire 238 output the clock signal to the neighboring nodes 206 to the right and below the current node 206.

[0052] Referring back to Figure 2A, the clock signal received at the root node 206 (e.g., node 206A) propagates to its two neighboring nodes below and to its right (e.g., nodes 206B and 206C) with a delay unit. The delay unit can be a fixed offset across the entire node array 204. In some implementations, the delay unit may correspond to the delay from buffering the clock signal (e.g., via inverters 228-232), combined with the wiring delay associated with the clock signal propagating to the downstream neighboring nodes 206. In Figure 2A, one of the downstream neighboring nodes 206 is to the right in the same row as the root node 206, and the other downstream neighboring node 206 is below in the same column as the root node 206. In other words, the neighboring nodes 206 can be located south and east of the root node 206.

[0053] The clock signal continues to propagate to neighboring nodes 206 to the south and east, with an additional delay unit, as the clock signal traverses the entire node array 204 in Figure 2A. Such clock signal propagation continues through the clock distribution network until the clock signal reaches node 206 in node array 204 at the opposite corner from the root node 206 (e.g., node 206D).

[0054] As a clock signal propagates through the node array 204, a node 206 within the node array 204 can receive clock signals from two other neighboring nodes 206 with substantially the same delay. A recombinant mesh topology can combine two clock signals received from two neighboring nodes 206 at a given node 206 in the node array 204. For example, in Figure 2B, clock signals received via the first input clock wire 222 and the second input clock wire 224 can be combined and received at the first inverter 226 and the second inverter 228, respectively. In some embodiments, the clock signals are combined by directly connecting the first input clock wire 222 and the second input clock wire 224 together. Other implementations for providing a recombinant mesh topology are also possible.

[0055] The clock distribution circuit configuration disclosed herein enables a flexible array structure that supports a wide range of array designs. For example, node array 204 may be a square with substantially the same number of rows and columns. Alternatively, node array 204 may be a rectangle with substantially different numbers of rows and columns. The clock distribution circuit configuration disclosed herein also provides a relatively simple reconstruction of the array with respect to the clock, which can also allow for design decisions regarding node array shape at a relatively late schedule. In contrast, array size and shape with other clock distribution networks are typically costly decisions to postpone, due to the amount of clock design time involved. However, in certain cases, such late decisions may result in an optimization of the overall chip design and therefore may be desirable.

[0056] Figure 2C shows another exemplary implementation of the clock distribution circuit configuration within an exemplary node 206 of the node array 204 in Figure 2A. Referring to Figure 2C, the clock distribution circuit configuration includes a first input clock wire 222, a second input clock wire 224, a second inverter 228, a third inverter 230, a fourth inverter 232, a clock tap point 234, a first output clock wire 236, and a second output clock wire 238. In Figure 2C, each clock distribution circuit configuration of node 206 is designed such that the output clock wires 236 and 238 of node 206 are aligned with the input clock wires 222 and 224 of neighboring node 206. Node 206 can be stepped and tiled within the node array 204 so that the output clock wires 236 and 238 are aligned with and electrically connected to the two input clock wires 222 and 224 of neighboring node 206. These electrical connections allow for the implementation of node array 204 without using channels or top-level wiring for clock distribution.

[0057] In an example of a clock distribution circuit configuration, as shown in Figure 2C, input wires 222 and 224 can receive input clock signals from two of the neighboring nodes 206. For example, the first input clock wire 222 receives an input clock signal from a neighboring node 206 above the current node 206, while the second input clock wire 224 receives an input clock signal from a neighboring node 206 to the left of the current node 206. The first input clock wire 222 and the second input clock wire 224 provide the clock signal to the second inverter 228. The second inverter 228 inverts the clock signal and provides the inverted clock signal to the third inverter 230 and the fourth inverter 232. The third inverter 230 and the fourth inverter 232 each invert the inverted clock signal and output the resulting clock signal to the first output clock wire 236 and the second output clock wire 238. The first output clock wiring 236 and the second output clock wiring 238 output clock signals to neighboring nodes 206 to the right and below the current node 206.

[0058] Figure 3A is a node clock level map associated with an exemplary node array, such as node array 204 in Figure 2A. The exemplary node array 204 has 18 rows and 18 columns. In 18 rows and 18 columns, there may be 324 nodes. As another example, node array 204 may include 360 ​​nodes arranged in rows and columns. Node 206 of node array 204 may have a clock distribution circuit configuration corresponding to, for example, the clock distribution circuit configuration in Figure 2B. Node 206 of node array 204 may also have a clock distribution circuit configuration corresponding to the clock distribution circuit configuration in Figure 2C. This clock map shows the number of unit delays of the clock signal output for node 206 of node array 204. For example, the root node 206 has a unit delay of 1. Two neighboring nodes 206 of the root node 206 have a unit delay of 2. Nodes 206 on a diagonal from southwest to northeast may have the same unit delay. Using the clock distribution circuit configurations described herein, the unit delay can be a fixed offset. Nodes 206 along these diagonals can receive clock signals with substantially the same timing delay. These diagonals may be referred to as phases or waves. Phases correspond to different clock signal arrival times at node 206. The clock signal distribution corresponding to the map in Figure 3A can implement a 35-phase mesochronous clock. The number of phases of the mesochronous clock signal for a node array having the clock distribution circuit configuration described herein may be the number of rows + the number of columns - 1.

[0059] In certain embodiments, instead of the clock signal traversing the node array 204 in waves formed along the diagonals of the node array 204, the clock distribution network 200 may be configured to generate waves that traverse the node array 204 in the row or column direction. For example, each node 206 may output a clock signal either south or east, rather than outputting a clock signal south and east. In this way, the clock signal may propagate in waves moving south or east. However, aspects of the present disclosure are not limited to specific directions of movement for the clock signal, and the clock signal may propagate along other diagonals and / or north or west.

[0060] The offset in Figure 3A can be considered when routing signals between nodes 206. Signals routed from the originating node to a node located north or west move upstream and may lose one unit delay in node array 204 corresponding to Figure 3A. Signals routed from the originating node to a node located south or east move downstream and can gain one unit delay in node array 204 corresponding to Figure 3A. Signals moving upstream can be routed faster than signals moving downstream to account for the unit delay and meet the setup and hold time specifications. The timing clock distribution shown in Figure 3A may also be referred to as wave clock distribution.

[0061] Figure 3B shows the node clock level topology 310 corresponding to the node clock level map in Figure 3A. As shown in Figure 3B, the nodes 206 included in groups 310, 320, 330, and 340 may have unit delays of 1, 2, 3, and 4, respectively. Nodes 206 included in the same group may have the same number of unit delays from the clock signal received at the root node. Timing modeling

[0062] Timing in a node array can be critical for computational accuracy and performance, but accurately simulating timing in a highly replicated node array can be difficult. For example, the size of a network-on-chip (NoC) data bus can exponentially increase the netlist size of a node array, and clock phase variations can introduce inaccuracies in simulating timing distribution in a node array. Furthermore, available electronic design automation (EDA) software can struggle to calculate node array timing. In some cases, especially when the node array is large and / or complex, the EDA software may be unable to calculate the node array timing at all. Alternatively, the EDA software may take a considerable amount of time to calculate the node array timing.

[0063] To address at least some of the technical challenges described above, one or more aspects of this disclosure correspond to systems and methods for modeling the timing of clock signal distribution in a node array. According to one aspect, the timing distribution of a node array can be simulated by modeling the timing delay of the node array based on a timing delay analysis on a block of nodes (e.g., a portion of the node array). As described above, each node 206 of the node array 204 may contain substantially the same instance of the clock distribution circuit configuration, even if one or more other circuit configurations of the node 206 differ from those of other nodes 206. For example, the computing node 406 and the global node 408 shown in Figure 4 may have the same clock distribution circuit configuration. Thus, the timing distribution can be modeled by performing a timing analysis on a single block (e.g., a node). For example, since signals travel in one direction (e.g., upstream or downstream), the time delay depending on the signal direction can be determined based on the interface delay between a node and its neighbors (e.g., adjacent or neighboring) nodes. This method may be advantageous because it avoids the need to analyze the time delays of all nodes in the node array and then calculate the analyzed time delays to model the timing distribution of the node array.

[0064] As shown in Figure 4, in some embodiments, the node array may include compute nodes 406, a global node 408, SerDes components 410, general-purpose input / output (GPIO) / security processing 412, etc. The compute node 406 may include circuit configurations for performing processing tasks. The global node 408 does not have to include circuit configurations for performing processing tasks. For example, the global node 408 may include a PVT sensor for monitoring the operating status of the node array. In some implementations, both the compute node 406 and the global node 408 may include communication interfaces that enable communication with neighboring nodes. In some implementations, the communication interface for the compute node 406 may be the same as the communication interface for the global node 408.

[0065] In some embodiments, the techniques disclosed herein can be used to perform static timing analysis on a heavily replicated array having multiple compute nodes 406 and multiple global nodes 408. In some embodiments, dummy blocks (which may be similar to or identical to the global blocks described above) can be devoid of most of their internal circuitry but can maintain interface and / or communication at their edges so that they can directly interface with functional blocks (e.g., compute nodes) in the array. In some embodiments, the array can use mesh clock distribution to distribute clock signals to functional blocks and dummy blocks.

[0066] In some implementations of node arrays, nodes within the node array can only communicate with adjacent nodes. In such implementations, there may be no "flyover" signals, bypass signals, or other signals that cross nodes. The routes connecting adjacent nodes can be horizontal or vertical. Nodes can be connected to neighboring nodes by horizontal and vertical routes. A compute node 406 that is not on an edge of the node array can interface with four neighboring nodes of the node array: two nodes adjacent to the compute node 406 in the same row of the node array, and two nodes adjacent to the compute node 406 in the same column of the node array. A global node 408 can interface with four neighboring compute nodes 406 of the node array: two compute nodes 406 adjacent to the global node 408 in the same row of the node array, and two compute nodes 406 adjacent to the global node 408 in the same column of the node array.

[0067] As mentioned above, modeling the clock distribution across an entire node array is difficult, time-consuming, or even impossible using available EDA tools. Therefore, a simplified method that can accurately model clock timing is desired.

[0068] In some embodiments, the modeling technique may include creating different global static timing model replicas of functional blocks and dummy blocks. The static timing model of a functional block may include models of functional blocks with different surrounding environments (e.g., completely surrounded by functional blocks, having dummy blocks on one side and functional blocks on the other). In some embodiments, only a limited number of arrangements of functional blocks and / or dummy blocks may exist around functional blocks in a node array. The static timing model of a dummy block may take surrounding functional blocks into account. In some embodiments, dummy blocks may be surrounded by functional blocks.

[0069] Large node arrays with mesochronous clocking present technical challenges for static timing analysis using conventional timing tools. Wide two-dimensional buses, even in hierarchical designs, can significantly increase netlist size, potentially increasing simulation execution time. The timing analysis of clock signals in node arrays described herein depends on the direction of data propagation relative to the direction of clock propagation. Since interfaces exist only between neighboring nodes touching each other within the node array, timing can be performed using a block group timing model of nodes and neighboring nodes with communication interfaces to those nodes. Block group timing may involve simulations including five nodes, which may be a small subset of the node array. The block group timing method avoids the need for time-of-arrival annotation and the effort to correlate simulations with actual designs that may exist alongside other methods. By creating block groups for each scenario within the node array, a complete node array can be accurately simulated based on several models. The block group timing method is illustrated with reference to Figure 5. The timing of the node array in this disclosure may utilize one or more of the following simplifications: one block occupies the majority (e.g., 98%) of the array, interfaces exist only between adjacent neighboring nodes, clock phases are systematically synchronized, and most cross-delay variations are common nodes.

[0070] Figure 5 shows an example of selecting nodes in a node array for modeling. In some embodiments, the timing of compute node 406A, neighbor node 406B around compute node 406A, global node 408, and neighbor node 406C around global node 408 can be modeled, while other nodes 416 can be depopulated. In addition, in some embodiments, the lane aggregator 414A and neighbor circuit configuration 414B of the node array can be modeled by modeling corners, while other nodes 416 in the node array can be depopulated by removing internal circuit configurations from the timing model. Such techniques can significantly reduce the number of nets, logic gates, wiring, parasitic capacitances, etc., that will be modeled. For example, the number of logic gates to be modeled can be reduced by about 80%, about 90%, etc. The reduction may depend, for example, on the number of nodes in the node array, the types of nodes in the node array, etc. Such techniques can provide a significant speed improvement in modeling and may be particularly beneficial for replicated designs without global signals. The computation time for modeling can be reduced, for example, from several days or weeks to just a few hours.

[0071] Referring to Figure 5, the timing of clock distribution in the node array can be modeled using the compute node 406A, neighbor node 406B around compute node 406A, global node 408, neighbor node 406C around the global node, lane aggregator 414A, and neighbor circuit configuration 414B. The clock timing within the node array can be simulated using a timing model of a small subset of the node array. Computer node 406A and neighbor compute node 406B can be simulated to create a compute node timing model. The compute node timing model can be used for each compute node in the array. Global node 408 and neighbor compute node 406C can be simulated to create a global node timing model. The global node timing model can be used for each global node in the array.

[0072] In some embodiments, the time delay of the clock signal between compute node 406A and each neighbor node 406B can be created based on a determined delay. Each other compute node in the node array can use the same timing mode as compute node 406A. For example, since each node in the node array contains instances of the same clock distribution circuit configuration and interface circuit configuration and abuts the same neighbor node instances, the same timing model can be used for each of the compute nodes in Figure 3A.

[0073] The time delay of the clock signal between global node 408 and each of the neighboring compute nodes 406C can be created based on the determined delay. Each other global node in the node array can use the same timing mode as global node 408.

[0074] The time delay of the clock signal between the lane aggregator 414A and the neighboring circuit configuration 414B can be determined and used for each similar instance of such a circuit configuration. A model can be determined and used for each similarly positioned lane aggregator. The lane aggregator model can simulate the device under test (DUT) block and its associated interface paths.

[0075] A node array model can cover functional blocks (e.g., compute nodes) and deposited blocks. A node array model can cover global communication node timing within a portion of the design size without a gray-box model.

[0076] A method for generating a model of a circuit design with duplicated instances of circuit blocks (e.g., node arrays) may involve parsing a hardware description language (e.g., Verilog) model of the circuit design and generating models of the circuit blocks (e.g., functional blocks). This method may also involve removing redundant similar instances of circuit blocks to reduce the size of the model. The same or similar method can be applied to all other types of block instances in the design (e.g., global blocks). In this case, the model may contain only specific scenarios. Static timing analysis can be performed on the model. Worst-case scenario timing

[0077] In some implementations of node arrays, the block group timing model, based on the blocks of nodes in the node array, is modeled to include various timing delay scenarios. For example, the delay between any two node clock arrival points in a node array can be different. Block distribution can be variable. For example, the delay between two nodes in a node array (e.g., near the center of the node array) can be derived from the delay between two nodes near the edge of the node array. This can occur, for example, because the capacitance may differ in different regions of the node array due to the manufacturing process (e.g., higher in the center).

[0078] In some embodiments, timing may be simulated to determine the worst-case scenarios for early and late arrival. This information can be used to ensure that any node in the array can satisfy arrival time and hold time specifications. Such techniques can be used, for example, to ensure that the results of a model can be applied to any node in a node array, even if the modeling is performed using a specific node or set of nodes in the array.

[0079] In some embodiments, mesh clock distribution can be traversed in a wave-like distribution across the node array. EDA tools can enable annotation of clock delays for early and late arrival of clock signals. In some embodiments, static timing analysis can be performed using only worst-case scenarios. Clock arrival differences can be generated between different compute nodes and global nodes, allowing identification of worst-case scenarios for any node with respect to arrival across the node array. Static timing analysis can be performed for the worst-case possible combinations of arrival for all nodes in the node array (e.g., all compute nodes and global nodes). By applying worst-case scenarios, the execution time of static timing analysis for the node array can be reduced. Worst-case scenarios can be applied for both setup time and hold time. Simultaneously, this ensures that the static timing of the design converges for all combinations of communication traffic flowing between any two adjacent nodes in the node array.

[0080] In contrast, a typical approach might involve performing a static timing analysis on every node in the array, which could require significant computational resources to complete.

[0081] Timing can be generated between any two nodes in a node array. Figure 6 shows how to determine part of the node array (e.g., block group of node array) timing between a node (e.g., compute node 406A) and an adjacent node (e.g., neighbor compute node 406B) in both the vertical and horizontal directions. For these adjacent nodes, worst-case early and late arrival times can be annotated. This ensures that the setup time and hold time specifications are met.

[0082] Worst-case timing data can be generated by parsing the results of a node array circuit simulation (e.g., SPICE simulation) across the entire grid. The fastest and slowest arrival times through the buffer can be selected. The buffer delay can be annotated in the timing model. This timing model can be optimized.

[0083] Worst-case timing data can be used in the node array model described in the previous section. Since the model uses only specific scenarios, the worst-case scenarios for setup time and hold time can be used for each specific scenario within the model. The model and the worst-case timing data can be used together to efficiently simulate the static timing of the node array and ensure that the setup and hold time specifications are met.

[0084] Worst-case timing data can be used to modify the design of a clock distribution circuit configuration. If the worst-case timing is outside the timing specifications, the clock distribution circuit configuration can be adjusted until the timing specifications are met. Adjusting the clock distribution circuit configuration may include adjusting the size of one or more clock drivers (e.g., increasing or decreasing the inventor's size depending on whether the setup time or hold time specifications are not met) and / or adjusting the width of one or more traces carrying the clock signal (e.g., widening or narrowing the traces regardless of whether the setup time or hold time specifications are not met). Such adjustments to the clock distribution circuit configuration can be applied to each node of the array. Design automation tools can automate the process of adjusting the clock distribution circuit configuration until the worst-case timing meets the timing specifications. In some other applications, circuit designers can use worst-case timing data to update the clock distribution circuit configuration. Exemplary Embodiment of a Node Array Timing Distribution Model

[0085] In some embodiments, a node array timing distribution model can be used to simulate clock timing in a node array. For example, the simulation results of a node array timing distribution model can be used to determine the worst-case scenario for clock timing in a node array. These simulation results can be used to design a clock distribution network that includes interfaces and / or inverters and / or wiring that carry signals between nodes in the node array.

[0086] Figure 7 shows an example of a computing device 710 that can simulate clock timing distribution across a node array. As shown in Figure 7, the computing device 710 implements a timing distribution simulation component 720, a non-volatile storage device 714, and a main processor 712.

[0087] In some examples, the main processor 712 can provide dedicated computing resources that will be used by the timing distribution simulation component 720. Furthermore, according to the examples disclosed herein, the main processor 712 can use the designated computing resources to process data generated from the timing distribution simulation component 720.

[0088] As shown in Figure 7, the timing distribution simulation component 720 may include a timing model generator 722 and a timing model simulator 724. The timing model generator 722 can be configured to model the time delay of a node array by analyzing the timing delay on a block of nodes (e.g., a portion of a node array). Referring to Figures 4 and 5, the timing model generator 722 may utilize modeling techniques that include creating different global static timing model replicas of functional blocks and dummy blocks. The static timing model of a functional block may include a model of a functional block having different surrounding environments (e.g., completely surrounded by functional blocks, having dummy blocks on one side and functional blocks on the other). In some embodiments, only a limited number of arrangements of functional blocks and / or dummy blocks can exist around a functional block in a node array. The static timing model of a dummy block may take surrounding functional blocks into account. In some embodiments, dummy blocks may be surrounded by functional blocks. The timing analysis of clock signals in a node array described herein depends on the direction of data propagation relative to the direction of clock propagation. Since interfaces exist only between neighboring nodes that touch each other within a node array, timing can be performed using a block group timing model of a node and the neighboring nodes that have a communication interface with that node. Block group timing may involve simulations of five nodes (e.g., a central node touched by neighboring nodes), which may be a small subset of the node array. Block group timing methods can avoid the effort of annotating arrival times and correlating simulations with actual designs that may exist alongside other methods. By creating block groups for each scenario within the node array, the entire node array can be accurately simulated based on several models.

[0089] In some embodiments, the timing model generator 722 can model and select compute nodes, neighboring nodes around compute nodes (e.g., four touching neighboring nodes), global nodes, and neighboring nodes around global nodes, while other nodes in the node array can be depopulated. In addition, in some embodiments, the lane aggregator and neighbor circuit configuration of the node array can be modeled by modeling corners, while other nodes in the node array can be depopulated by removing the internal circuit configuration from the timing model. Such techniques can significantly reduce the number of nets, logic gates, wiring, parasitic capacitances, etc., that will be modeled. For example, the number of logic gates to be modeled can be reduced by about 80%, about 90%, etc. The reduction may depend, for example, on the number of nodes in the node array, the types of nodes in the node array, etc. Such techniques can provide a significant speed improvement in modeling and may be particularly beneficial for replicated designs without global signals. The computation time for modeling can be reduced, for example, from days or weeks to hours. In some embodiments, the model generated from the timing model generator 722 can be stored in a non-volatile memory device 714.

[0090] The timing model simulator 724 can be configured to simulate a model stored in a non-volatile storage device 714. In some embodiments, the timing model simulator 724 can access the model by accessing the non-volatile storage device 714. In some embodiments, a model including compute nodes and neighboring compute nodes can be simulated to create a timing model for the compute nodes. The timing model for the compute nodes can also be used for each compute node in an array. The global node and neighboring compute nodes can also be simulated to create a timing model for the global node. The timing model for the global node can be used for each global node in an array.

[0091] In some embodiments, the timing model simulator 724 creates a time delay of the clock signal between the compute node and each neighbor node based on the determined delay. Each other compute node in the node array can use the same timing mode as the compute node. For example, each node in the node array contains instances of the same clock distribution circuit configuration and interface circuit configuration and abuts the same instances of neighbor nodes, so the same timing model can be used for each of the compute nodes in Figure 3A. The time delay of the clock signal between the global node and each of the neighbor compute nodes can also be created based on the determined delay. Each other global node in the node array can use the same timing mode as the global node.

[0092] In some embodiments, the timing model simulator 724 can simulate node arrays by modeling node arrays that cover functional blocks (e.g., compute nodes) and deposited blocks. A method for generating a simulation model of a circuit design having duplicated instances of circuit blocks (e.g., node arrays) may include parsing a hardware description language (e.g., Verilog) model of the circuit design and generating models of the circuit blocks (e.g., functional blocks). This method may also include removing redundant similar instances of circuit blocks to reduce the size of the model. The same or similar method can be performed for all other types of block instances in the design (e.g., global blocks). In that case, the model may contain only specific scenarios.

[0093] In some embodiments, the timing model simulator 724 performs a timing analysis to determine worst-case timing data and includes the determined worst-case timing data in the simulation. For example, timing can be generated between any two nodes in a node array (for example, Figure 6 shows determining part of the node array (e.g., block group of node array) timing between a node (e.g., compute node 406A) and an adjacent node (e.g., neighbor compute node 406B) in both the vertical and horizontal directions). For these adjacent nodes, worst-case early and late arrivals can be annotated. This ensures that the setup time and hold time specifications are met.

[0094] Worst-case timing data can be generated by parsing the results of a node array circuit simulation (e.g., SPICE simulation) across the entire grid. The fastest and slowest arrival times through the buffer can be selected. The buffer delay can be annotated in the timing model. This timing model can be optimized.

[0095] Worst-case timing data can be used in the node array model generated by the timing model generation unit 722. Since the model uses only specific scenarios, the worst-case scenarios for setup time and hold time can be used in each specific scenario within the model. By using the model and the worst-case timing data together, the static timing of the node array can be efficiently simulated and it can be ensured that the setup and hold time specifications are met.

[0096] In some embodiments, worst-case timing data can be used to modify the design of the clock distribution circuit configuration. If the worst-case timing is outside the timing specifications, the clock distribution circuit configuration can be adjusted until the timing specifications are met. Adjusting the clock distribution circuit configuration may include adjusting the size of one or more clock drivers (e.g., increasing or decreasing the inventor's size depending on whether the setup time or hold time specifications are not met) and / or adjusting the width of one or more traces carrying the clock signal (e.g., widening or narrowing the traces regardless of whether the setup time or hold time specifications are not met). Such adjustments to the clock distribution circuit configuration can be applied to each node of the array. Design automation tools can automate the process of adjusting the clock distribution circuit configuration until the worst-case timing meets the timing specifications. In some other applications, circuit designers can use worst-case timing data to update the clock distribution circuit configuration.

[0097] For the sake of simplicity and to avoid limiting the scope of this disclosure, Figure 7 shows only the timing distribution simulation component 720, the non-volatile storage device, and the main processor, although multiple subcomponents or systems may be used. Uses, terminology, and conclusions

[0098] The node arrays disclosed herein can be implemented in a variety of processing systems. Such processing systems can be used in and / or specifically configured for high-performance computing and / or computationally intensive applications such as neural network training, neural network inference, machine learning, artificial intelligence, and complex simulations. In some applications, the processing systems can be used to perform neural network training. For example, such neural network training can generate data for an autopilot system in a vehicle (e.g., an automobile), other autonomous vehicle functions, or advanced driver-assistance systems (ADAS) functions.

[0099] Unless the context clearly indicates otherwise, words such as “comprise,” “comprising,” “include,” and “including” throughout the specification and claims should be interpreted in a comprehensive sense, as opposed to an exclusive or exhaustive sense, i.e., “including, but not limited to.” The term “combined” as commonly used herein refers to two or more elements that can be directly joined or joined by one or more intermediate elements. Similarly, the term “joined” as commonly used herein refers to two or more elements that can be directly joined or joined by one or more intermediate elements. Furthermore, the terms “in this specification,” “above,” “hereafter,” and similar terms, when used in this application, refer to the entire application and not to any particular part thereof. Where the context allows, words in the above detailed description that use singular or plural forms may also include plural or singular forms, respectively. The word "or" in relation to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0100] Furthermore, the conditional language used herein, in particular "can," "could," "might," "may," "eg," "for example," and "such as," is generally intended to convey that a particular embodiment includes a particular feature, element, and / or state, but other embodiments do not, unless otherwise specified or understood in the context in which it is used. Accordingly, such conditional language is not generally intended to imply that a feature, element, and / or state is required in any way in one or more embodiments.

[0101] The above description is based on reference to specific embodiments. However, the above exemplary consideration is not intended to be exhaustive or to limit the invention to the exact form described. Many modifications and variations are possible in light of the above teachings. This will enable those skilled in the art to best utilize the technology and various embodiments with various modifications suitable for various applications.

[0102] While this disclosure and examples have been described with reference to the accompanying drawings, various changes and modifications will be apparent to those skilled in the art. Such changes and modifications should be understood to be within the scope of this disclosure.

Claims

1. A method for simulating a node array, A step of accessing a timing model of a compute node of the node array, which is stored in non-temporary computer-readable memory, wherein the timing model of the compute node represents timing data related to the propagation of clock signals between the compute node and four neighboring nodes of the node array, each of which is adjacent to the compute node. The steps include using one or more computers to simulate the clock signal timing of a majority of the nodes in the node array using a timing model of the computing nodes, Includes, A method wherein the timing model of the node array models the compute node that receives the clock signal from a first pair of the four neighboring nodes and the compute node that provides the clock signal to a second pair of the four neighboring nodes, wherein the clock signal is delayed by one delay unit at the compute node compared to the case of the first pair of neighboring nodes, and the clock signal is delayed by two delay units at the second pair of neighboring nodes compared to the case of the first pair of neighboring nodes.

2. The method according to claim 1, further comprising the step of determining the worst-case timing of the clock signals in the node array based on the simulation step.

3. The method according to claim 2, further comprising the step of adjusting the clock distribution network of the node array based on the worst-case timing.

4. The method according to claim 3, wherein the step of adjusting the clock distribution network includes updating one or more files representing the circuit configuration of the node array.

5. The method of claim 2, further comprising the step of accessing a timing model of the global nodes of the node array, which is stored in the non-temporary computer-readable memory, wherein the decision is based on a simulation of clock signal timing using the global node timing model.

6. The method according to claim 1, wherein the simulating step includes simulating mesochronous clocking in the node array.

7. The method according to claim 1, wherein the timing model of the node array is a block group timing model.

8. The method according to claim 1, wherein the majority of the nodes in the node array include at least 90% of the nodes in the node array.

9. The method according to claim 7, wherein the node array comprises instances of the compute nodes and instances of the global node.

10. The method according to claim 1, further comprising the step of generating a timing model of the computing node by at least simulating the propagation of clock signals between the computing node and the four neighboring nodes.

11. Non-temporary computer-readable storage, which, when executed by one or more processors, includes instructions causing a method to simulate a node array, wherein the method is A step of accessing a timing model of a compute node of the node array, which is stored in non-temporary computer-readable memory, wherein the timing model of the compute node represents timing data related to the propagation of clock signals between the compute node and four neighboring nodes of the node array, each of which is adjacent to the compute node. The steps include: using one or more computers to simulate the clock signal timing of a majority of the nodes in the node array using a timing model of the computing nodes; Includes, Non-transient computer-readable storage, wherein the timing model of the node array models the compute node that receives the clock signal from a first pair of the four neighboring nodes and the compute node that provides the clock signal to a second pair of the four neighboring nodes, wherein the clock signal is delayed by one delay unit at the compute node compared to the case of the first pair of neighboring nodes, and the clock signal is delayed by two delay units at the second pair of neighboring nodes compared to the case of the first pair of neighboring nodes.

12. A computer system for simulating a node array, Non-temporary computer-readable memory for storing a timing model of a compute node in a node array, wherein the timing model of the compute node represents timing data related to clock signal propagation between the compute node and four neighboring nodes of the node array, each of which is adjacent to the compute node. One or more processors configured to at least access the timing model of the compute node and to execute instructions for simulating the clock signal timing of a majority of the nodes in the node array using the timing model of the compute node, Equipped with, A computer system in which the timing model of the node array models the compute node that receives the clock signal from a first pair of the four neighboring nodes and the compute node that provides the clock signal to a second pair of the four neighboring nodes, wherein the clock signal is delayed by one delay unit at the compute node compared to the case of the first pair of neighboring nodes, and the clock signal is delayed by two delay units at the second pair of neighboring nodes compared to the case of the first pair of neighboring nodes.

13. A system for simulating clock timing distribution across a node array including multiple computing nodes, One or more computing devices configured to store a timing model in which a compute node and four neighboring compute nodes that are adjacent to the compute node, wherein each computing device of the one or more computing devices is Accessing the timing model of the aforementioned computing node, Using a computing device, simulate the clock signal timing distribution of the majority of the nodes in the node array using the timing model of the computing node. One or more computing devices configured to perform Equipped with, The timing model of the node array models a computing node that receives the clock signal from a first pair of the four neighboring computing nodes and a computing node that provides the clock signal to a second pair of the four neighboring computing nodes, wherein the clock signal is delayed by one delay unit in the computing node compared to the case of the first pair of neighboring computing nodes, and the clock signal is delayed by two delay units in the second pair of neighboring computing nodes compared to the case of the first pair of neighboring computing nodes.

14. A non-temporary computer-readable storage medium for storing instructions for simulating clock timing distribution across a node array, wherein when the instructions are executed by a processor, the processor receives Accessing the timing model of a compute node, wherein the timing model of the compute node represents timing data related to clock signal propagation between the compute node and four neighboring nodes of the node array, each of which is adjacent to the compute node. Using a computing device, simulate the clock signal timing distribution of the majority of the nodes in the node array using the timing model of the computing node, An action that includes, A non-temporary computer-readable storage medium that causes the timing model of the node array to model a compute node that receives the clock signal from a first pair of the four neighboring nodes and a compute node that provides the clock signal to a second pair of the four neighboring nodes, and to perform an operation in which the clock signal is delayed by one delay unit at the compute node compared to the case of the first pair of neighboring nodes, and the clock signal is delayed by two delay units at the second pair of neighboring nodes compared to the case of the first pair of neighboring nodes.

15. The non-temporary computer-readable storage medium according to claim 14, further comprising determining the worst-case timing of the clock signals in the node array based on the simulation described above.

16. The non-temporary computer-readable storage medium according to claim 15, further comprising adjusting the clock distribution network of the node array based on the worst-case timing.

17. The non-temporary computer-readable storage medium according to claim 16, wherein adjusting the clock distribution network includes updating one or more files representing the circuit configuration of the node array.

18. The non-temporary computer-readable storage medium according to claim 15, further comprising accessing a timing model of the global nodes of the node array stored in the non-temporary computer-readable storage medium, wherein the decision is based on a simulation of clock signal timing using the timing model of the global nodes.

19. The non-temporary computer-readable storage medium according to claim 14, wherein the simulation includes simulating mesochronous clocking in the node array.

20. The non-temporary computer-readable storage medium according to claim 14, wherein the timing model of the node array is a block group timing model.

21. The non-temporary computer-readable storage medium according to claim 14, wherein the majority of the nodes in the node array comprise at least 90% of the nodes in the node array.

22. The non-temporary computer-readable storage medium according to claim 20, wherein the node array comprises instances of the compute nodes and instances of the global node.

23. The non-temporary computer-readable storage medium according to claim 14, further comprising generating a timing model of the computing node by at least simulating the propagation of clock signals between the computing node and the four neighboring nodes.

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