Semiconductor device and method for manufacturing a semiconductor device
The semiconductor device addresses switching and gate drive losses by incorporating a protruding region with controlled impurity concentration, enhancing depletion and preventing parasitic bipolar operation, thus improving performance and reliability.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SHINDENGEN ELECTRIC MANUFACTURING CO LTD
- Filing Date
- 2022-02-07
- Publication Date
- 2026-06-17
Smart Images
Figure 0007874974000002 
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]
[0002] Conventionally, trench gate type semiconductor devices are known (see, for example, Patent Document 1).
[0003] Figure 14 is a cross-sectional view showing a conventional semiconductor device 900. As shown in Figure 14, the conventional semiconductor device 900 is n + A low-resistance semiconductor layer of type n 911, an n-type drift layer 912, a p-type base region 913 formed on the surface of the drift layer 912, and an n-type (n) formed on the surface of the base region 913. + The semiconductor device comprises a semiconductor substrate 910 having a source region 914 of type 1, a trench 920 formed on the surface of the semiconductor substrate 910 with its bottom adjacent to a drift layer 912 and its side walls adjacent to the drift layer 912, the base region 913, and the source region 914, a gate insulating film 922 formed on the side wall of the trench 920, a gate electrode 924 formed inside the trench 920 via the gate insulating film 922, and a surface electrode 940 connected to the source region 914. The conventional semiconductor device 900 is a semiconductor device having a shielded gate structure further comprising a shield electrode 926 formed inside the trench 920 at a position separated from the gate electrode 924 and the inner surface of the trench 920, and an insulating region 928 formed between the gate electrode 924 and the shield electrode 926, and between the shield electrode 926 and the inner surface of the trench 920.
[0004] Conventional semiconductor device 900 is a so-called trench-gate type semiconductor device, comprising a trench 920 and a gate electrode 924 formed inside the trench 920 via a gate insulating film 922. Therefore, channels can be formed in the depth direction of the semiconductor substrate 910, and the chip size can be reduced compared to a planar-gate type semiconductor device. Furthermore, in a planar-gate type semiconductor device, it is necessary to leave a certain amount of channel spacing to prevent the J-FET effect, in which a depletion layer extends from adjacent channel regions and narrows the current path. However, trench-gate type semiconductor devices do not have such constraints, and from this viewpoint as well, the chip size can be reduced. [Prior art documents] [Patent Documents]
[0005] [Patent Document 1] Special Publication No. 2002-528916 [Overview of the project] [Problems that the invention aims to solve]
[0006] Incidentally, in general, semiconductor devices require a high impurity concentration in the drift layer to reduce on-resistance. However, in conventional semiconductor devices 900, increasing the impurity concentration in the drift layer 912 makes it difficult to deplete the drift layer 912. Consequently, in order to deplete the drift layer 912, the drain voltage must be increased, which leads to a larger gate-drain charge Qgd, resulting in increased switching losses and gate drive losses.
[0007] Furthermore, during avalanche breakdown, due to the low potential at the interface between the insulating region 928 (oxide film) and the semiconductor substrate 910, holes generated near the bottom of the trench 920 tend to flow into the base region 913 along the edge of the trench 920 (see Figures 9(c) and (d)). Consequently, a large amount of holes flow into the region of the base region 913 that is in contact with the trench 920, causing the potential of the base region 913 to rise locally, which may lead to parasitic bipolar operation.
[0008] It should be noted that the above-mentioned problem is not limited to semiconductor devices with a shielded gate structure, but can also occur in general trench gate type semiconductor devices.
[0009] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that has low switching loss and gate drive loss, and is less prone to parasitic bipolar operation, even when the impurity concentration of the first conductivity type semiconductor layer is high, and a method for manufacturing such a semiconductor device. [Means for solving the problem]
[0010] The semiconductor device of the present invention comprises a semiconductor substrate having a first conductivity type semiconductor layer, a second conductivity type semiconductor region formed on the surface of the first conductivity type semiconductor layer, and a first conductivity type semiconductor region formed on the surface of the second conductivity type semiconductor region; a plurality of trenches formed on the surface of the semiconductor substrate, the lowest part of which is in contact with the first conductivity type semiconductor layer, and the side walls of which are in contact with the first conductivity type semiconductor layer, the second conductivity type semiconductor region, and the first conductivity type semiconductor region; a gate insulating film formed in at least the region of the side wall of each of the plurality of trenches that is in contact with the second conductivity type semiconductor region; a gate electrode formed inside each of the plurality of trenches via the gate insulating film; and an interlayer insulating film formed above the gate electrode and the semiconductor substrate. The semiconductor substrate comprises a surface electrode formed on the interlayer insulating film and connected to the second conductivity type semiconductor region and the first conductivity type semiconductor region, wherein the semiconductor substrate is formed to protrude from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer in a region sandwiched between adjacent trenches and has a second conductivity type protruding region that is separated from the trenches, the depth position of the deepest part of the protruding region is shallower than the depth position of the deepest part of the trench, the peak position of the impurity concentration in the protruding region is deeper than the bottom of the second conductivity type semiconductor region, and the total amount of impurities in the depth-direction cross-section of the protruding region is the same as or less than the total amount of impurities in the depth-direction cross-section of the second conductivity type semiconductor region.
[0011] In this specification, "total amount of impurities in the depth-direction cross-section" refers to the value obtained by integrating the impurity concentration at each unit depth over the depth direction (see Figure 2(b)).
[0012] The present invention provides a semiconductor device manufacturing method comprising: a semiconductor substrate preparation step of preparing a semiconductor substrate having a first conductivity type semiconductor layer of a first conductivity type, a second conductivity type semiconductor region of a second conductivity type formed on the surface of the first conductivity type semiconductor layer, and a first conductivity type semiconductor region of a first conductivity type formed on the surface of the second conductivity type semiconductor region; a trench formation step of forming a plurality of trenches on one surface of the semiconductor substrate, the lowest part of which is in contact with the first conductivity type semiconductor layer and the side walls of which are in contact with the first conductivity type semiconductor layer, the second conductivity type semiconductor region, and the first conductivity type semiconductor region; a gate insulating film formation step of forming a gate insulating film in at least the region of the side wall of each of the plurality of trenches that is in contact with the second conductivity type semiconductor region; a gate electrode formation step of forming a plurality of gate electrodes inside each of the plurality of trenches via the gate insulating film; and forming an interlayer insulating film on the gate electrodes and the surface of the semiconductor substrate. The method is characterized by comprising: an interlayer insulating film formation step; a contact trench formation step of forming a contact trench in the interlayer insulating film to a depth that reaches at least the second conductivity type semiconductor region of the semiconductor substrate; a second conductivity type impurity introduction step of injecting a second conductivity type impurity into the bottom of the contact trench such that the peak position of the impurity concentration is deeper than the bottom of the second conductivity type semiconductor region; and an overhang region formation step of diffusing the second conductivity type impurity to form an overhang region of the second conductivity type in a region sandwiched between adjacent trenches, which is separated from the trenches and extends outward from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer, the deepest part of which is shallower than the deepest part of the trench, and the total amount of impurities in the depth-direction cross-section is the same as or less than the total amount of impurities in the depth-direction cross-section of the second conductivity type semiconductor region. [Effects of the Invention]
[0013] According to the semiconductor device and method for manufacturing the semiconductor device of the present invention, the semiconductor substrate is formed so as to extend from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer in a region sandwiched between adjacent trenches, and has a second conductivity type protruding region that is separated from the trenches. Therefore, the depletion layer spreads not only vertically from the pn junction between the second conductivity type semiconductor region and the first conductivity type semiconductor layer, but also laterally from the pn junction on the side of the protruding region. Consequently, the first conductivity type semiconductor layer between the trench and the protruding region is easily depleted, so that even if the impurity concentration of the first conductivity type semiconductor layer is high, the first conductivity type semiconductor layer can be depleted without unnecessarily increasing the drain voltage. As a result, the gate-drain charge amount Qgd can be small, and switching losses and gate drive losses can be reduced. Furthermore, because the gate-drain charge Qgd can be small, the time required to charge and discharge the gate-drain capacitance Cgd during gate on / off is reduced, resulting in faster switching speeds. Furthermore, adopting this structure reduces the gate-drain capacity Cgd, decreasing Cgd / (Cgs+Cgd). As a result, it also has the effect of suppressing gate mis-indications, known as self-turn-on or shoot-through.
[0014] Furthermore, according to the semiconductor device and method for manufacturing the semiconductor device of the present invention, because of the above-described configuration, during avalanche breakdown, holes generated near the bottom of the trench flow not only into the region in contact with the trench in the second conductivity type semiconductor region but also into the protruding region (see Figures 9(a) and (b)). Therefore, the path for holes flowing into the second conductivity type semiconductor region is broadened, which prevents the potential of the second conductivity type semiconductor region from becoming locally high, and as a result, parasitic bipolar operation can be prevented.
[0015] By contrast, when the total amount of impurities in the depth direction cross-section of the protruding region is made larger than the total amount of impurities in the depth direction cross-section of the p-type semiconductor region, impact ionization is likely to occur near the middle of adjacent trenches at the time of avalanche breakdown, and the electric field concentrates near the middle of adjacent trenches, resulting in a reduction in breakdown voltage (see FIGS. 11(c) to (e)). On the other hand, according to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, since the total amount of impurities in the depth direction cross-section of the protruding region is equal to or less than the total amount of impurities in the depth direction cross-section of the p-type semiconductor region, impact ionization is likely to occur around the trenches at the time of avalanche breakdown, and the breakdown region is dispersed (see FIG. 11(b)). Therefore, it is possible to prevent the electric field from concentrating near the middle of adjacent trenches, and it is possible to prevent the breakdown voltage from decreasing.
[0016] Also, when the depth position of the deepest part of the protruding region is deeper than the depth position of the deepest part of the trench, the current path when a current flows between the source and the drain is blocked in the gate-on state, so the on-resistance may increase. On the other hand, according to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, since the depth position of the deepest part of the protruding region is shallower than the depth position of the deepest part of the trench, the current path is difficult to be blocked even when a current flows between the source and the drain, and it is difficult for the on-resistance to decrease.
Brief Description of the Drawings
[0017] [Figure 1] It is a figure which shows the semiconductor device 100 which concerns on Embodiment 1. FIG. 1(a) shows a plan view of the semiconductor device 100, and FIG. 1(b) shows a cross-sectional view taken along line A-A of FIG. 1(a). [Figure 2] It is a figure which shows for demonstrating the total amount of the impurity of the depth direction cross section of the base area 113 and the protruding area 115 in the semiconductor device 100 which concerns on Embodiment 1. FIG. 2(a) shows a cross-sectional view of the semiconductor device 100, and FIG. 2(b) shows a graph of the impurity concentration with respect to the depth between the broken lines A-A' and between the broken lines B-B' of FIG. 2(a). [Figure 3] It shows a cross-sectional view taken along line B-B of FIG. 1(a). [Figure 4] This is an enlarged view of the main peripheral part of the semiconductor device 100 according to Embodiment 1. Figure 4(a) is an enlarged plan view of the main peripheral part of the semiconductor device 100, Figure 4(b) is a cross-sectional view taken along A-A' in Figure 4(a), Figure 4(c) is a cross-sectional view taken along B-B' in Figure 4(a), and Figure 4(d) is a cross-sectional view taken along C-C' in Figure 4(a). [Figure 5] This figure shows the manufacturing method of the semiconductor device 100 according to Embodiment 1. Figures 5(a) to (d) are step diagrams. [Figure 6] This figure shows the manufacturing method of the semiconductor device 100 according to Embodiment 1. Figures 6(a) to (d) are step diagrams. [Figure 7] This figure shows the manufacturing method of the semiconductor device 100 according to Embodiment 1. Figures 7(a) to 7(d) are step diagrams. [Figure 8] This figure shows the method for manufacturing the semiconductor device 100 according to Embodiment 1. Figures 8(a) to 8(d) are step diagrams. [Figure 9] This figure illustrates the effects of the semiconductor device 100 according to Embodiment 1. Figure 9(a) is a schematic diagram showing the movement of holes during avalanche breakdown of the semiconductor device according to Embodiment 1, Figure 9(b) shows the Hall current density distribution during avalanche breakdown of the semiconductor device according to Embodiment 1, Figure 9(c) is a schematic diagram showing the movement of holes during avalanche breakdown of the semiconductor device according to Comparative Example 1, and Figure 9(d) shows the Hall current density distribution during avalanche breakdown of the semiconductor device according to Comparative Example 1. [Figure 10] This graph shows the relationship between the dose amount and pressure resistance of the overhang region in Example 2 and Comparative Examples 2-5. [Figure 11] This figure shows the impact ionization distribution in Example 2 and Comparative Examples 2-5. Figure 11(a) shows the impact ionization rate distribution of Comparative Example 2, Figure 11(b) shows the impact ionization rate distribution of Example 2, and Figures 11(c) to 11(e) show the impact ionization rate distributions of Comparative Examples 3-5. [Figure 12] This is a cross-sectional view showing a semiconductor device 102 according to Embodiment 2. [Figure 13]This is a cross-sectional view showing a modified semiconductor device 104. [Figure 14] This is a cross-sectional view showing a conventional semiconductor device 900. Reference numeral 911 indicates a low-resistance semiconductor layer (n+ type semiconductor layer), and reference numeral 950 indicates a drain electrode. [Modes for carrying out the invention]
[0018] The semiconductor device and method for manufacturing the semiconductor device of the present invention will be described below based on the embodiments shown in the figures. Note that the embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.
[0019] [Embodiment 1] 1. Configuration of the semiconductor device 100 according to Embodiment 1 Figure 1 shows a semiconductor device 100 according to Embodiment 1. As shown in Figure 1(a), the semiconductor device 100 according to Embodiment 1 has a substantially rectangular shape in plan view, composed of two long sides X1, X2 and two short sides X3, X4. The semiconductor device 100 according to Embodiment 1 has a source electrode 140, source wiring SL1, SL2, gate pad GP and gate wiring GL1, GL2 arranged on the surface of a semiconductor substrate 110. The semiconductor substrate 110 is defined as a cell region A1 formed in the central region where the source electrode 140 is located, and a peripheral region A2 formed to surround the cell region A1.
[0020] The source electrode (surface electrode) 140 has a rectangular shape when viewed in plan, extending from the center of the semiconductor substrate 110 towards the short side X3. Source wiring SL1 extends from the end of the source electrode 140 on the short side X3 toward the long side X1 along the short side X3, then bends toward the short side X4 at the corner of the semiconductor substrate 110 and extends along the long side X1. Source wiring SL2 extends from the end of the source electrode 140 on the short side X3 toward the long side X2 along the short side X3, then bends toward the short side X4 at the corner of the semiconductor substrate 110 and extends along the long side X2. Both source wiring SL1 and SL2 are connected to the source electrode 140.
[0021] The gate pad GP has a rectangular shape, formed in a planar view near the center of the short side X4 of the semiconductor substrate 110, protruding from the short side X4 toward the center. The gate wiring GL1 extends from the end of the gate pad GP on the short side X4 toward the long side X1 along the short side X4, bends toward the short side X3 midway, and extends along the long side X1 between the source electrode 140 and the source wiring SL1. The gate wiring GL2 extends from the end of the gate pad GP on the short side X4 toward the long side X2 along the short side X4, bends toward the short side X3 midway, and extends along the long side X2 between the source electrode 140 and the source wiring SL2. Both gate wirings GL1 and GL2 are connected to the gate pad GP. The source electrode 140 and source wirings SL1 and SL2 are separated from the gate pad GP and gate wirings GL1 and GL2.
[0022] The source electrode 140, source wiring SL1, SL2, gate pad GP, and gate wiring GL1, GL2 are made of an Al film or Al alloy film (e.g., AlSi film) with a thickness of 1 μm to 10 μm (e.g., 3 μm), and are formed as a single unit.
[0023] Next, the configuration of cell region A1 will be described. In the semiconductor device 100 according to Embodiment 1, as shown in Figure 1(b), cell region A1 includes a semiconductor substrate 110, a plurality of trenches 120, a gate insulating film 122, a gate electrode 124, a shield electrode 126, an insulating region 128, an interlayer insulating film 130, a contact trench 132, a source electrode 140, and a drain electrode 150, forming a MOS (Metal-Oxide-Semiconductor) structure.
[0024] The semiconductor substrate 110 is n-type (n + A low-resistance semiconductor layer 111 of type n, an n-type drift layer (first conductivity type semiconductor layer) 112 with a lower impurity concentration than the low-resistance semiconductor layer 111, a p-type base region (second conductivity type semiconductor region) 113 formed on the surface of the drift layer 112, and an n-type (n +A p-type (p) source region 114 and the region between adjacent trenches 120 are formed so as to extend from the bottom of the base region 113 toward the drift layer 112, and are separated from the trenches 120. - A p-type (p) is formed in the protruding region 115 of the p-type and in the region in contact with the bottom of the contact trench 132, and has a higher impurity concentration than the base region 113. + It has a contact area 116 of type (type).
[0025] Figure 2 is a diagram illustrating the total amount of impurities in the depth-direction cross-section of the base region and the protruding region in the semiconductor device 100 according to Embodiment 1. The overhang region 115 is formed in the center of the region sandwiched between the adjacent trenches 120 and below the contact trench 132. The deepest point of the overhang region 115 is shallower than the deepest point of the trench 120. Also, the peak position of the impurity concentration in the overhang region 115 is deeper than the bottom of the base region 113. Furthermore, the total amount of impurities in the depth-direction cross-section of the overhang region 115 is less than the total amount of impurities in the depth-direction cross-section of the base region 113. Specifically, let y be the depth direction, y=0 indicates the depth position of the surface of the semiconductor substrate 110 along the dashed line A-A' in Figure 2(a), and let N be the impurity concentration per unit volume along the dashed line A-A' in Figure 2(a). A Let (A-A') be the impurity concentration per unit volume along the dashed line B-B' in Figure 2(a), and let N be the impurity concentration per unit volume. A When (B-B') is defined, the following equation holds. Note that "base junction depth" refers to the depth of the region where the bottom of the base region 113 and the drift layer 112 are pn junctioned, and the overhang region depth refers to the depth of the bottommost part of the overhang region 115.
number
[0026] The point that the total amount of impurities in the depth-direction cross-section of the protruding region 115 is less than the total amount of impurities in the depth-direction cross-section of the base region 113 will be explained in detail. The total amount of impurities in the depth-direction cross-section of the protruding region 115 (the hatched area on the right side of Figure 2(b)) is the area enclosed by the straight line indicating the "bottom of the base region," the curve representing the "P-type impurity concentration in the B-B' cross-section," and the horizontal axis in Figure 2(b). On the other hand, the total amount of impurities in the depth-direction cross-section of the base region (the hatched area on the left side of Figure 2(b)) is the area enclosed by the straight line indicating the "bottom of the base region" in Figure 2(b), the curve of "P-type impurity concentration in the A-A' cross-section", and the vertical and horizontal axes. The total amount of impurities in the depth-direction cross-section of the base region is equal to the total amount of impurities in the depth-direction cross-section of the base region when the contact trench 132 and contact region 116 are not formed. Therefore, as can be seen from Figure 2(b), the total amount of impurities in the depth-direction cross-section of the protruding region 115 is smaller than the total amount of impurities in the depth-direction cross-section of the base region 113. It is sufficient that the total amount of impurities in the protruding region 115 is equal to or less than the total amount of impurities in the depth-direction cross-section of the base region 113. For example, the impurity concentration may be high and the depth of the protruding region 115 may be shallow, or the impurity concentration may be low and the depth of the protruding region 115 may be deep.
[0027] Furthermore, in the B-B' section, the total amount of impurities in the depth-direction cross-section of the semiconductor substrate 110 from the contact position between the source electrode 140 and the semiconductor substrate 110 to the bottom of the base region (the sum of the total amount of impurities in the depth-direction cross-sections of the contact region 116 and the base region 113) is the area enclosed by the straight line indicating the "bottom of the base region," the curve representing the "P-type impurity concentration in the B-B' section," and the horizontal axis in Figure 2(b). The total amount of impurities in the depth-direction cross-section of the protruding region 115 is smaller than the total amount of impurities in the depth-direction cross-section of this region.
[0028] In Embodiment 1, multiple trenches 120 extend in parallel at predetermined intervals from a region overlapping with the source wiring SL1 on the long side X1 (viewed in plan), across the region overlapping with the source electrode 140, to a region overlapping with the source wiring SL2 on the long side X2 (not shown). As shown in Figure 1(b), the trenches 120 are formed on the surface of the semiconductor substrate 110, with their bottoms in contact with the drift layer 112, and their sidewalls in contact with the drift layer 112, the base region 113, and the source region 114. The bottom surface of the trenches 120 is rounded, but may be flat or have any other appropriate shape.
[0029] The gate insulating film 122 is formed on the upper part of the sidewall of each of the multiple trenches 120, specifically in contact with a portion of the drift layer 112, the base region 113, and a portion of the source region 114. The gate insulating film 122 is made of a thermal oxide film. The gate electrode 124 is formed inside each of the multiple trenches 120, via the gate insulating film 122, in a position facing the base region 113. The gate electrode 124 is made of polysilicon.
[0030] The shield electrode 126 is formed at a position separated from the gate electrode 124 and the inner surface of the trench 120. The shield electrode 126 is made of polysilicon. The insulating region 128 is formed between the gate electrode 124 and the shield electrode 126, and between the shield electrode 126 and the inner surface of the trench 120, insulating the gate electrode 124 from the shield electrode 126 and the shield electrode 126 from the semiconductor substrate 110. The insulating region 128 is made of an oxide film formed by, for example, the CVD method.
[0031] The gate insulating film 122, gate electrode 124, shield electrode 126, and insulating region 128 are located within the trench 120 and extend in a stripe pattern within the trench 120 from the long side X1 to the long side X2. The gate electrode 124 and gate insulating film 122 extend from the region overlapping with gate wiring GL1 in peripheral region A2, through the region overlapping with source electrode 140, to the region overlapping with gate wiring GL2. The gate electrode 124 is connected to gate wiring GL via contact plug GLC in the region overlapping with gate wirings GL1 and GL2 (see Figure 4(c)). Furthermore, in a plan view, the gate electrode 124 and gate insulating film 122 are not formed at the end on the longer side X1 side of gate wiring GL1 and the end on the longer side X2 side of gate wiring GL2. Within the trench, the shield electrode 126 and insulating region 128 are formed up to the upper side of the trench 120 (see Figure 4(b)). The shield electrode 126 is electrically connected to the source wirings SL1 and SL2, where the gate electrode 124 was formed, via the contact plug SLC2 at the ends on the longer side X1 and the longer side X2 side of the trench 120.
[0032] As shown in Figure 1, the interlayer insulating film 130 is formed on the surface of the gate electrode 124, the gate insulating film 122, and the semiconductor substrate 110. The interlayer insulating film 130 is an oxide film formed, for example, by the CVD method.
[0033] The contact trench 132 extends parallel to the trench 120, from the long side X1 to the long side X2, between adjacent trenches 120 when viewed in plan (not shown). As shown in Figure 1(b), the contact trench 132 penetrates the interlayer insulating film 130 and is formed to a depth greater than the depth position of the bottom of the source region 114. The bottom of the contact trench 132 is in contact with the contact region 116, and the side walls of the contact trench 132 are in contact with the source region 114 and the base region 113.
[0034] The source electrode 140 is formed on the interlayer insulating film 130 and is connected to the base region 113, source region 114, and contact region 116 via a contact trench 132.
[0035] The drain electrode 150 is disposed over the entire back surface side (on the surface of the low-resistance semiconductor layer 111) of the semiconductor substrate 110. The drain electrode 150 is formed of a laminated film in which Ti, Ni, and Au (or Ag) are laminated in this order, and the thickness of the drain electrode 150 is 0.2 μm to 1.5 μm (for example, 1 μm).
[0036] Next, the configuration of the peripheral region A2 will be described. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1(a). FIG. 4 is an enlarged view of a main part of the peripheral portion of the semiconductor device 100 according to Embodiment 1. In the peripheral region A2 of the semiconductor device 100 according to Embodiment 1, as shown in FIGS. 1(a), 3, and 4, a semiconductor substrate 110, an outermost peripheral trench 160, an embedded electrode 162, an insulating region 164, an interlayer insulating film 130, a gate pad GP, gate wirings GL1 and GL2, and source wirings SL1 and SL2 are disposed. Further, as shown in FIG. 4(c), the trench 120 extends from the cell region A1, and the gate electrode 124 in the trench 120 is connected to the gate wirings GL1 and GL2 via a contact plug GC, and the shield electrode 126 in the trench 120 is connected to the source wirings SL1 and SL2 via a contact plug SLC2 (see FIG. 4(b)).
[0037] As shown in FIG. 3, the semiconductor substrate 110 has a low-resistance semiconductor layer 111, a drift layer 112, and a p-type peripheral region 117 in the peripheral region A2.
[0038] The p-type peripheral region 117 is a p-type (p +This is a p-type semiconductor region. The p-type peripheral region 117 is connected to the base region 113 at its end on the cell region A1 side. The p-type peripheral region 117 is also connected to the source electrode 140 via a contact trench 132 on the cell region A1 side, and is connected to the source wiring SL1 and SL2 via contact plugs SLC1 near the ends on the long side X1 and long side X2 (see Figures 4(a) and (b)). The bottom depth of the p-type peripheral region 117 is deeper than the bottom depth of the base region 113. Furthermore, the total amount of impurities in the depth-direction cross-section of the p-type peripheral region 117 is greater than the total amount of impurities in the depth-direction cross-section of the base region 113. Therefore, if the depth of the p-type peripheral region 117 is considerably deep, the impurity concentration may be considerably low, and even if the depth of the p-type peripheral region 117 is relatively shallow, the impurity concentration may be considerably high. Note that no overhang region 115 is formed in the peripheral region A2. Furthermore, the source region 114 and the base region 113 are not formed between the outermost trench 160 and the trench 120.
[0039] As shown in Figures 3 and 4, the outermost trench 160 is formed to encircle the outermost periphery of the semiconductor substrate 110. The embedded electrode 162 is positioned inside the outermost trench 160, separated from the inner surface. The embedded electrode 162 is made of polysilicon. The embedded electrode 162 is electrically connected to the source electrode 140 via a contact plug SLC. The insulating region 164 is positioned inside the outermost trench 160 between the embedded electrode 162 and the inner surface of the outermost trench 160. The insulating region 164 is, for example, an oxide film formed by the CVD method.
[0040] 2. Method for manufacturing a semiconductor device according to Embodiment 1 Next, a method for manufacturing a semiconductor device according to Embodiment 1 will be described. Figures 5 to 8 are diagrams showing a method for manufacturing a semiconductor device 100 according to Embodiment 1. The method for manufacturing a semiconductor device according to Embodiment 1 includes, in this order, a semiconductor substrate preparation step, a trench formation step, an insulating region formation step, a shield electrode formation step, an insulating region formation step, a gate insulating film formation step, a gate electrode formation step, an interlayer insulating film formation step, a contact trench formation step, a first p-type impurity introduction step, a second p-type impurity introduction step, an overhang region and contact region formation step, and a surface electrode and back electrode formation step.
[0041] (1) Semiconductor substrate preparation process First, in cell area A1, the n type (n + A low-resistance semiconductor layer 111 of type n, an n-type drift layer 112 with a lower impurity concentration than the low-resistance semiconductor layer 111, a p-type base region 113 formed on the surface of the drift layer 112, and an n-type (n + It has a source region 114 of type (see Figure 5(a)), and in the peripheral region A2, a low-resistance semiconductor layer 111, a drift layer 112, and a p-type (p) formed on the surface of the drift layer 112. + A semiconductor substrate 110 having a p-type peripheral region 117 is prepared.
[0042] (2) Trench formation process Next, trenches 120 are formed on the surface of the semiconductor substrate 110 (the surface on the source region 114 side) at predetermined intervals, such that the bottom of each trench is in contact with the drift layer 112 and the side walls are in contact with the drift layer 112, the base region 113, and the source region 114 (see Figure 5(b)). In the trench formation process, multiple trenches 120 are formed in parallel at predetermined intervals, extending from the long side X1 towards the long side X2. In addition, an outermost trench 160 is formed to surround the outermost circumference of the semiconductor substrate 110.
[0043] (3) Insulation region formation process Next, an insulating film 128' is formed over the entire surface of the semiconductor substrate 110, including the inner surface of the trench 120 and the inner surface of the outermost trench 160 (see Figure 5(c)). The insulating film 128' is an oxide film formed, for example, by the CVD method.
[0044] (4) Shield electrode formation process Next, polysilicon 126' is deposited over the entire surface of the insulating film 128' (see Figure 5(d)). At this time, polysilicon 126' is deposited in the trench 120 and the outermost trench 160 via the insulating film 128'. Next, the polysilicon 126' is removed by etching, leaving the portion deposited up to a predetermined height in the trench 120 and the portion deposited in the outermost trench 160 (see Figure 6(a)). Specifically, in the region sandwiched between the region where gate wirings GL1 and GL2 are formed in the peripheral region A2 and the region overlapping with it, approximately half of the polysilicon 126' is left in the trench 120. Outside the region overlapping with the region where GL1 and GL2 are formed in the peripheral region A2 (on the long side X1 and the long side X2), the polysilicon 126' is removed, leaving most of the trench 120. The remaining polysilicon 126' in the trench 120 becomes the shield electrode 126. Furthermore, the polysilicon 126' within the outermost trench 160 becomes the embedded electrode 162.
[0045] (5) Insulation region formation process Next, an insulating film 128'' is formed on the insulating film 128' and the shield electrode 126, for example by CVD (see Figure 6(b)). Next, a mask (not shown) is formed on the outermost trench 160 and the embedded electrode 162 in the peripheral region A2. Next, the insulating film 128' and insulating film 128'' are removed by etching, leaving the insulating film 128'' between the shield electrode 126 and the inner surface of the trench 120, and on the shield electrode 126 within the trench 120 (see Figure 6(c)). The insulating film 128'' on the shield electrode 126 constitutes part of the insulating region 128.
[0046] (6) Gate insulating film formation process Next, a thermal oxide film 122' is formed on the semiconductor substrate 110 and on the insulating region 128 within the trench (see Figure 6(d)). At this time, the thermal oxide film 122' formed on the side wall of the trench 120 constitutes the gate insulating film 122. In addition, the thermal oxide film 122' on the insulating film 128' and insulating film 128'' constitutes a part of the insulating region 128.
[0047] (7) Guard electrode formation process Next, a polysilicon layer 124' is formed on the thermal oxide film 122' (see Figure 7(a)). Then, the polysilicon layer 124' is etched away, leaving the portion sandwiched between the thermal oxide film 122' (gate insulating film 122) in the trench 120 (see Figure 7(b)). This forms multiple gate electrodes 124 inside each of the multiple trenches 120 via the gate insulating film 122.
[0048] (8) Interlayer insulating film formation process Next, the mask of the peripheral region A2 is removed. Then, an interlayer insulating film 130 is formed over the entire surface of the semiconductor substrate 110 (see Figure 7(c)).
[0049] (9) Contact trench formation process Next, a predetermined region (the center in Embodiment 1) between adjacent trenches is etched to form a contact trench 132 that is deeper than the bottom of the source region 114 of the semiconductor substrate 110 and in contact with the base region 113 (see Figure 7(d)). At this time, the ends of the contact trench 132 on the long side X1 and the ends on the long side X2 are formed to be in contact with the p-type peripheral region 117. In addition, contact holes are formed in the peripheral region A2 at predetermined positions on the embedded electrode 162, at the ends of the shield electrode 126, and at the ends of the gate electrode 124, thereby forming contact plugs (not shown).
[0050] (10) First p-type impurity introduction step (second conductivity-type impurity introduction step) Next, a mask (not shown) having an opening in the region of the contact trench 132 is formed over the entire surface side of the semiconductor substrate 110. Next, a p-type impurity (e.g., boron) is implanted into the bottom of the contact trench 132 such that the peak position of the impurity concentration is deeper than the bottom of the base region 113 (see FIG. 8(a)). At this time, when the range of the p-type impurity is Rp and the length from the contact position between the semiconductor substrate 110 and the source electrode 140 to the bottom of the base region is D (see FIG. 1(a)), Rp > D is satisfied. The dose amount of the p-type impurity in the first second-conductivity-type impurity introduction step is less than the dose amount of the p-type impurity forming the base region (the dose amount when the base region 113 is formed by ion implantation).
[0051] (11) Second p-type impurity introduction step Next, a p-type impurity (e.g., boron) is implanted into the bottom of the contact trench 132 such that the peak position of the impurity concentration is shallower than the bottom of the base region 113 (see FIG. 8(b)). At this time, when the range of the p-type impurity is Rp and the length from the contact position between the semiconductor substrate 110 and the source electrode 140 to the bottom of the base region is D, Rp < D is satisfied. Also, the dose amount of the p-type impurity in the second second-conductivity-type impurity introduction step is more than the dose amount of the p-type impurity forming the base region (the dose amount when the base region 113 is formed by ion implantation).
[0052] (12) Overhang region and contact region formation step Next, the semiconductor substrate 110 is heated to diffuse the p-type impurity, thereby forming a p-type overhang region 115 and a contact region 116 (see FIG. 8(c)). At this time, the p-type overhang region 115 is formed so as to be separated from the trench 120 and to extend from the bottom of the base region 113 toward the drift layer 112 in the region sandwiched by the adjacent trenches 120, the deepest depth position is shallower than the deepest depth position of the trench 120, and the total amount of impurities in the depth direction cross section is formed to be less than the total amount of impurities in the depth direction cross section of the base region 113.
[0053] (13) Surface electrode and back electrode formation process Next, the masks used in the first and second p-type impurity introduction steps are removed (not shown). Then, a metal film is deposited on the interlayer insulating film 130 and the semiconductor substrate 110 and etched to form the source electrode 140 (see Figure 5(d)), source wiring SL1, SL2, gate pad GP, and gate wiring GL1, GL2. At this time, the metal film also enters the contact trench 132 and is connected to the base region 113 and the source region 114 via the contact trench 132. In addition, the end of the gate electrode 124 is connected to the source wiring SL1, SL2 via the contact plug SLC, and the end of the shield electrode 126 is connected to the gate wiring GL1, GL2 via the contact plug GLC. Furthermore, a drain electrode 150 (backside electrode) is formed on the surface of the back side (low-resistance semiconductor layer 111 side) of the semiconductor substrate 110.
[0054] In this way, the mechanism 100 according to Embodiment 1 can be formed. (1) In the semiconductor substrate preparation process, a p-type base region 113 is formed in advance on the surface of the drift layer 112, and an n-type (n + A semiconductor substrate having a source region 114 of type (n) was prepared, but it is not limited to this, and a semiconductor substrate having a low-resistance semiconductor layer 111 and a drift layer 112 formed on it was prepared and the steps from (2) trench formation to (7) gate electrode formation were carried out, and after the gate electrode formation step (7) a p-type base region 113 and an n-type (n) + A source region 114 of type ) may be formed.
[0055] 3. Test Example 1 Test Example 1 is a test example to confirm that the path of holes flowing into the base region 113 is widened by forming an overhanging region 115.
[0056] (1) About the sample The semiconductor device 800 according to Comparative Example 1 is the same as the semiconductor device according to Embodiment 1, except that it does not have a protruding region and the upper surface of the gate electrode is recessed in the center (see Figure 9(c)). The semiconductor device 100A according to Embodiment 1 is the same as the semiconductor device according to Embodiment 1, except that the upper surface of the gate electrode is concave in the center (see Figure 9(a)).
[0057] (2) Test method For Comparative Example 1 and Example 1, the Hall current density in each region of the semiconductor substrate was calculated by computer simulation and plotted in different colors (see Figures 9(b) and (d)).
[0058] (3) Results In the semiconductor device 800 according to Comparative Example 1, it was found that the hole current density was high only in the region of the drift layer 812 that was in contact with the trench 820, as shown in Figure 9(d). Therefore, it was found that during avalanche breakdown, carriers (holes) generated near the bottom of the trench 820 and approaching the base region 813 moved along the edge of the trench 820 toward the base region 813, and a large amount of holes flowed into the region of the base region 813 that was in contact with the trench 820.
[0059] In contrast, in the semiconductor device 100A according to Example 1, as shown in Figure 9(b), the Hall current density was found to be high not only in the region of the drift layer 112 in contact with the trench 120, but also in the region from there to the protruding region 115. Therefore, it was found that during avalanche breakdown, carriers (holes) generated near the bottom of the trench 120 and approaching the base region 113 not only move along the edge of the trench 120 toward the base region 113, but also flow toward the protruding region 115, and a component flows into the base region 113 via the protruding region 115. Thus, it was confirmed that forming the protruding region 115 widens the path of holes flowing into the base region 113.
[0060] 4. Test Example 2 Test Example 2 is a test example that confirms that by making the total amount of impurities in the depth-direction cross-section of the overhang region less than the total amount of impurities in the depth-direction cross-section of the base region 113, it is possible to prevent the electric field from concentrating near the middle of adjacent trenches during avalanche yielding, thereby preventing a decrease in breakdown voltage.
[0061] (1) About the sample Comparative Example 2 is a semiconductor device similar to the semiconductor device according to Embodiment 1, except that an overhanging region is not formed (see Figure 11(a)). In Example 2 and Comparative Examples 3, 4, and 5, the dose amount of the protruding region 115 was 5 × 10⁻⁶, respectively. 12 cm -3 , 6×10 12 cm -3 , 7×10 12 cm -3 , 1.0 × 10 13 cm -3 Except for the point mentioned above, this semiconductor device is the same as the semiconductor device according to Embodiment 1 (see Figures 11(b) to 11(e)). The dose in the base region is 5.8 × 10⁻⁶. 12 cm -3 Furthermore, the protruding region 115 was formed by implanting p-type impurities with an acceleration energy of 330 KeV and allowing them to diffuse.
[0062] (2) Test method For Example 2 and Comparative Examples 2-5, the withstand voltage against the dose amount of the protruding region was calculated and plotted on a graph with the dose amount of the protruding region on the horizontal axis and the withstand voltage on the vertical axis (see Figure 10). In addition, the impact ionization rate distribution in each region of the semiconductor substrate was calculated by computer simulation and plotted in different colors (see Figure 11).
[0063] (3) Result 1 As shown in Figure 10, in Comparative Example 2 (without protruding region) and Example 2, the withstand voltage was approximately 220V, ensuring sufficient withstand voltage. On the other hand, in Comparative Example 3, the withstand voltage was slightly over 200V, in Comparative Example 4, it was approximately 190V, and in Comparative Example 5, it was approximately 170V. From this, it was confirmed that sufficient withstand voltage can be ensured in Comparative Example 2 (without protruding region) and Example 2. On the other hand, in Comparative Examples 3 to 5, sufficient withstand voltage could not be ensured. Therefore, the dose amount in the protruding region was greater than the dose amount in the base region. big In some cases, it was found that the pressure resistance decreases. From this, it was confirmed that the decrease in pressure resistance can be prevented by making the total amount of impurities in the depth-direction cross-section of the protruding region less than the total amount of impurities in the depth-direction cross-section of the base region 113.
[0064] (4) Result 2 In Comparative Examples 3 to 5, the region where impact ionization is likely to occur is formed near the center of the region sandwiched between adjacent trenches (the region enclosed by the dashed line B in Figures 11(c) to (e)) (see Figures 11(c) to 11(e)). As a result, during avalanche yielding, the electric field concentrates near the middle of the region sandwiched between adjacent trenches (where the breakdown voltage is likely to decrease), causing a decrease in breakdown voltage. In contrast, in Example 2, the region where impact ionization is likely to occur is formed at a position offset from the center (closer to the trench 120 than the center) (see Figures 11(a) and 11(b)). Therefore, the region where impact ionization occurs can be dispersed. Consequently, it is possible to prevent the electric field from concentrating near the middle of adjacent trenches, and from this viewpoint as well, it was confirmed that a decrease in breakdown voltage can be prevented.
[0065] 5. Effects of the semiconductor device 100 and the method for manufacturing the semiconductor device according to Embodiment 1 According to the semiconductor device 100 and the method for manufacturing the semiconductor device according to Embodiment 1, the semiconductor substrate 110 has a p-type overhang region 115 that is formed to protrude from the bottom of the base region 113 toward the drift layer 112 in the region sandwiched between adjacent trenches 120 and is separated from the trenches 120. As a result, the depletion layer spreads not only vertically from the pn junction between the base region 113 and the drift layer 112, but also horizontally from the pn junction on the side of the overhang region 115. Therefore, the drift layer 112 between the trenches 120 and the overhang region 115 is easily depleted, and even if the impurity concentration of the drift layer 112 is high, the drift layer 112 can be depleted without raising the drain voltage unnecessarily. As a result, the gate-drain charge amount Qgd can be small, and switching losses and gate drive losses can be reduced. Furthermore, because the gate-drain charge Qgd can be small, the time required to charge and discharge the gate-drain capacitance Cgd during gate on / off is shorter, resulting in a faster switching speed. In other words, during the period in which the gate-drain charge Qgd is charged and discharged (Miller period), the drain-source voltage Vds decreases and increases, respectively, but because the gate-drain charge Qgd can be small, the switching speed is faster. Furthermore, adopting this structure reduces the gate-drain capacity Cgd, decreasing Cgd / (Cgs+Cgd). As a result, it also has the effect of suppressing gate mis-indications, known as self-turn-on or shoot-through.
[0066] Furthermore, according to the semiconductor device 100 and the method for manufacturing the semiconductor device according to Embodiment 1, because it has the above-described configuration, during avalanche breakdown, holes generated near the bottom of the trench 120 flow not only into the area of the base region 113 in contact with the trench 120 but also into the overhanging region 115 (see Figures 9(a) and (b)). Therefore, the path of holes flowing into the base region 113 is broadened, which prevents the potential of the base region 113 from becoming locally high and prevents parasitic bipolar operation.
[0067] Incidentally, if the total amount of impurities in the depth-direction cross-section of the overhang region 115 is greater than the total amount of impurities in the depth-direction cross-section of the base region 113, impact ionization is more likely to occur near the middle of adjacent trenches 120 during avalanche breakdown, causing the electric field to concentrate near the middle of adjacent trenches 120 (where breakdown voltage is easily reduced), resulting in a decrease in breakdown voltage. For example, if a p-type semiconductor region is formed below the base region, and a p-region with a higher impurity concentration than the base region is formed below it, the electric field will concentrate around the p-region, causing a decrease in breakdown voltage. In contrast, according to the semiconductor device 100 and the manufacturing method of the semiconductor device according to Embodiment 1, the total amount of impurities in the depth-direction cross-section of the overhang region is equal to or less than the total amount of impurities in the depth-direction cross-section of the second conductivity type semiconductor region. Therefore, during avalanche breakdown, impact ionization is more likely to occur around the trenches and less likely to occur near the middle of adjacent trenches 120 (see Figure 11(a)). Consequently, it is possible to prevent the electric field from concentrating near the middle of adjacent trenches, thus preventing a decrease in breakdown voltage.
[0068] Furthermore, if the deepest point of the overhang region 115 is deeper than the deepest point of the trench 120, the current path when current flows between the source and drain may be blocked, resulting in a higher on-resistance. For example, in a semiconductor device having a superjunction structure, a p-type region is formed downward from the base region, but it is necessary to balance the charge with the n-type drift layer, and p-type regions (p-columns) are formed to a region deeper than the trench. In this case, the current path when current flows between the source and drain is blocked by the p-columns, resulting in a lower on-resistance. In contrast, according to the semiconductor device 100 and the manufacturing method of the semiconductor device according to Embodiment 1, the deepest point of the overhang region 115 is shallower than the deepest point of the trench 120, so even when current flows between the source and drain, the current path is less likely to be blocked, and the on-resistance is less likely to decrease.
[0069] Furthermore, according to Embodiment 1, the semiconductor device 100 is provided with a contact trench 132 that penetrates the interlayer insulating film 130 and is formed to a depth that reaches at least the base region 113 of the semiconductor substrate 110. This allows for the flow of relatively large currents and facilitates the extraction of holes that flow from the drift layer 112 into the base region 113, or that flow into the base region 113 via the protruding region 115. Additionally, since the protruding region 115 is formed below the contact trench 132, it facilitates the extraction of holes that flow into the base region 113 via the protruding region 115. Moreover, because of the above configuration, ion implantation to form the protruding region 115 can be performed at a relatively low voltage by implanting ions into the bottom of the contact trench 132.
[0070] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the source region 114 is in contact with the side surface of the contact trench 132, the contact trench 132 is formed to a depth greater than the depth of the source region 114. This makes it possible to implant ions into the bottom of the contact trench 132 to form the protruding region 115 at an even lower voltage.
[0071] Furthermore, according to the semiconductor device 100 of Embodiment 1, the semiconductor substrate 110 has a p-type contact region 116 formed in the region in contact with the bottom of the contact trench 132, and has a higher impurity concentration than the base region 113, thereby reducing the contact resistance with the source electrode 140. Also, because it is formed at the bottom of the contact trench 132, the contact region 116 can be formed at a relatively low voltage.
[0072] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the protruding region 115 is formed in the center of the region sandwiched between adjacent trenches 120, the depletion layer extends laterally from both sides of the protruding region 115 toward each trench, thereby uniformly depleting the region between the protruding region 115 and the adjacent trenches 120. This allows for a higher breakdown voltage.
[0073] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the trench 120 includes a gate electrode 124 and a shield electrode 126 formed at a position separated from the inner surface of the trench 120, and insulating regions 128 formed between the gate electrode 124 and the shield electrode 126, and between the shield electrode 126 and the inner surface of the trench 120, the distance from the gate electrode 124 to the bottom of the trench 120 is increased, reducing the gate-drain capacitance Cgd and enabling faster switching speeds. In addition, the distance from the corners of the trench 120 where electric field concentration is likely to occur to the gate electrode 124 can be increased, and the electric field can be mitigated by the insulating regions 128, thus enabling higher breakdown voltage.
[0074] Furthermore, in the semiconductor device 100 according to Embodiment 1, in the peripheral region A2, the semiconductor substrate 110 is formed on the surface of the drift layer 112 and connected to the base region 113, and has a p-type peripheral region 117 whose lowest point is deeper than the lowest point of the base region 113, and the impurity concentration in the p-type peripheral region 117 is higher than the impurity concentration in the base region 113. Because of this configuration, holes generated in the drift layer 112 can be efficiently recovered even in the peripheral region A2 where trenches 120 are not formed, resulting in a semiconductor device that ensures high breakdown voltage and avalanche withstand capability.
[0075] Furthermore, in the semiconductor device 100 according to Embodiment 1, since the p-type peripheral region 117 is in direct contact with the source electrode 140 formed in the cell region A1, the potential of the p-type peripheral region 117 can be made equal to the source potential, and the collected holes can be efficiently moved to the source electrode 140.
[0076] Furthermore, according to the semiconductor device manufacturing method of Embodiment 1, when Rp is the range of the p-type impurity that forms the protruding region 115, and D is the length from the position where the semiconductor substrate 110 contacts the source electrode 140 to the bottom of the base region 113, Rp > D is satisfied, so the protruding region 115 can be formed at a depth greater than the bottom of the base region 113.
[0077] Furthermore, according to the semiconductor device manufacturing method of Embodiment 1, the dose of p-type impurities that form the protruding region 115 in the first p-type impurity introduction step is less than the dose of p-type impurities that form the base region 113. Therefore, the total amount of impurities in the depth-direction cross-section of the protruding region 115 can be made smaller than the total amount of impurities in the depth-direction cross-section of the base region 113.
[0078] [Embodiment 2] The semiconductor device 102 according to Embodiment 2 has basically the same configuration as the semiconductor device 100 according to Embodiment 1, but differs from the semiconductor device 100 according to Embodiment 1 in that it does not have a shield gate structure (see Figure 12). That is, the semiconductor device 102 according to Embodiment 2 does not have a shield electrode 126 and an insulating region 128, and has an insulating film formed along the inner circumferential surface of the trench 120 (the insulating film on the side wall surface becomes the gate insulating film 122) and a gate electrode 124 disposed in the trench 120 via an insulating film.
[0079] Thus, although the semiconductor device 102 according to Embodiment 2 differs from the semiconductor device 100 according to Embodiment 1 in that it does not have a shield gate structure, similar to the semiconductor device 100 according to Embodiment 1, the semiconductor substrate is formed to protrude from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer in the region sandwiched between adjacent trenches, and has a second conductivity type protruding region that is separated from the trenches. Therefore, even when the impurity concentration of the drift layer 112 is increased, it is possible to create a semiconductor device in which switching losses and gate drive losses are small and parasitic bipolar operation is less likely to occur.
[0080] Furthermore, since the semiconductor device 102 according to Embodiment 2 has the same configuration as the semiconductor device 100 according to Embodiment 1, except that it does not have a shield gate structure, it has the same effects as the semiconductor device 100 according to Embodiment 1.
[0081] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.
[0082] (1) The positions, sizes, etc. described in each of the above embodiments (including each modified example; the same applies hereinafter) are illustrative and can be changed within the scope that does not impair the effects of the present invention. In addition, although the first conductivity type was described as n-type and the second conductivity type as p-type in each of the above embodiments, the first conductivity type may be p-type and the second conductivity type as n-type.
[0083] (2) In each of the above embodiments, the contact trench was formed to a depth greater than the depth position of the bottom of the source region 114, but the present invention is not limited thereto. The contact trench may be formed to the same depth as the bottom of the source region 114 or to a shallower depth, or if the base region 113 is exposed on the surface of the semiconductor substrate 110, it may be made in contact with the semiconductor substrate 110 without excavating the semiconductor substrate.
[0084] (3) In each of the above embodiments, the source electrode and the source wiring were connected, but the present invention is not limited thereto. The source electrode and the source wiring do not need to be connected.
[0085] (4) In each of the above embodiments, one overhang region 115 is formed, but the present invention is not limited thereto. Multiple overhang regions 115 may be formed. Also, in each of the above embodiments, the overhang region 115 is formed in the center of adjacent trenches 120, but the present invention is not limited thereto. The overhang region 115 may be formed in a location other than the center of adjacent trenches 120 (see Figure 13 for a modified semiconductor device 104 where two overhang regions are formed in positions that avoid the center of adjacent trenches 120).
[0086] (5) In each of the above embodiments, a MOSFET was used as the semiconductor device, but the present invention is not limited thereto. IGBTs, thyristors, triacs, and other appropriate devices may be used as the semiconductor device.
[0087] (6) In each of the above embodiments, the total amount of impurities in the depth-direction cross-section of the overhanging region 115 was set to be less than the total amount of impurities in the depth-direction cross-section of the base region 113, but the present invention is not limited thereto. The total amount of impurities in the depth-direction cross-section of the overhanging region 115 may be the same as the total amount of impurities in the depth-direction cross-section of the base region 113. [Explanation of symbols]
[0088] 100, 100A, 900… Semiconductor device, 110, 910… Semiconductor substrate, 111, 911… Low-resistance semiconductor layer, 112, 912… Drift layer, 113, 913… Base region, 114, 914… Source region, 115… Overhang region, 116… Contact region, 117… p-type peripheral region, 120, 920… Trench, 122, 922… Gate insulating film, 122'·M oxide film, 124, 924… Gate electrode, 124'·| Resilicon layer, 126, 926… Shield electrode, 126'·| Lisilicon, 128,928...insulating region, 128',128''...insulating film, 130...interlayer insulating film, 132...contact trench, 140,940...source electrode, 150...drain electrode, 160...outermost trench, 162...embedded electrode, 164...insulating region, A1...cell region, A2...peripheral region, GL1,GL2...gate wiring, GLC,SLC,SLC2,SLC3...contact plug, GP...gate pad, SL1,SL2...source wiring, X1,X2...long side, X3,X4...short side
Claims
1. A semiconductor substrate having a first conductivity type semiconductor layer, a second conductivity type semiconductor region formed on the surface of the first conductivity type semiconductor layer, and a first conductivity type semiconductor region formed on the surface of the second conductivity type semiconductor region, A plurality of trenches are formed on the surface of the semiconductor substrate, the bottom of which is in contact with the first conductivity type semiconductor layer, and the side walls of which are in contact with the first conductivity type semiconductor layer, the second conductivity type semiconductor region, and the first conductivity type semiconductor region. A gate insulating film formed on the side wall of each of the plurality of trenches, A gate electrode formed inside each of the plurality of trenches via the gate insulating film, The gate electrode and the interlayer insulating film formed above the semiconductor substrate, The interlayer insulating film comprises a second conductivity type semiconductor region and a surface electrode connected to the first conductivity type semiconductor region, The semiconductor substrate is formed to extend outwards from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer in a region sandwiched between adjacent trenches, and has a second conductivity type protruding region that is separated from the trenches. The depth position of the deepest part of the aforementioned overhang region is shallower than the depth position of the deepest part of the trench. The peak position of the impurity concentration in the aforementioned protruding region is deeper than the bottom of the second conductivity type semiconductor region. The total amount of impurities in the depth-direction cross-section of the aforementioned protruding region is less than the total amount of impurities in the depth-direction cross-section of the second conductivity type semiconductor region. The aforementioned protruding region is characterized by being formed by implanting a second conductivity type impurity in a dose of 5 × 10¹² cm⁻³.
2. The system further comprises a contact trench formed to penetrate the interlayer insulating film and to a depth that reaches at least the second conductivity type semiconductor region of the semiconductor substrate, The surface electrode is connected to the first conductivity type semiconductor region and the second conductivity type semiconductor region via the contact trench. The semiconductor device according to claim 1, characterized in that the protruding region is formed below the contact trench.
3. The semiconductor device according to claim 2, characterized in that the first conductive semiconductor region is in contact with the side surface of the contact trench.
4. The semiconductor device according to claim 2 or 3, characterized in that the semiconductor substrate is formed in a region in contact with the bottom of the contact trench and further has a second conductivity type contact region having a higher impurity concentration than the second conductivity type semiconductor region.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that the protruding region is formed in the center of the region sandwiched between the adjacent trenches.
6. Within the trench, a shield electrode is formed at a position separated from both the inner circumferential surface of the trench and the gate electrode, The semiconductor device according to any one of claims 1 to 5, characterized by comprising an insulating region formed between the gate electrode and the shield electrode, and between the shield electrode and the inner circumferential surface of the trench.
7. The semiconductor substrate is defined as having a cell region on which a MOS structure is formed, and a peripheral region surrounding the cell region. In the cell region, the semiconductor substrate is The first conductive semiconductor layer and, The second conductivity type semiconductor region and, The first conductivity type semiconductor region and, It has at least the aforementioned protruding region, In the aforementioned peripheral region, the semiconductor substrate is The first conductive semiconductor layer and, It has at least a second conductivity peripheral region formed on the surface of the first conductivity semiconductor layer, connected to the second conductivity semiconductor region, and whose lowest point depth is deeper than the lowest point depth of the second conductivity semiconductor region. The semiconductor device according to any one of claims 1 to 6, characterized in that the total amount of impurities in the depth-direction cross-section in the region surrounding the second conductivity type is greater than the total amount of impurities in the depth-direction cross-section in the semiconductor region of the second conductivity type.
8. The semiconductor device according to claim 7, characterized in that the second conductivity type peripheral region is in direct contact with the surface electrode formed in the cell region.
9. A semiconductor substrate preparation step of preparing a semiconductor substrate having a first conductivity type semiconductor layer, a second conductivity type semiconductor region formed on the surface of the first conductivity type semiconductor layer, and a first conductivity type semiconductor region formed on the surface of the second conductivity type semiconductor region, A trench formation step is to form a plurality of trenches on one surface of the semiconductor substrate, the bottom of which is in contact with the first conductivity type semiconductor layer and the side walls of which are in contact with the first conductivity type semiconductor layer, the second conductivity type semiconductor region and the first conductivity type semiconductor region. A gate insulating film forming step, in which a gate insulating film is formed in at least the region of the side wall of each of the plurality of trenches that is in contact with the second conductivity type semiconductor region, A gate electrode formation step in which a plurality of gate electrodes are formed inside each of the plurality of trenches via the gate insulating film, An interlayer insulating film formation step in which an interlayer insulating film is formed on the surface of the gate electrode and the semiconductor substrate, A contact trench formation step of forming a contact trench in the interlayer insulating film having a depth that reaches at least the second conductivity type semiconductor region of the semiconductor substrate, A second conductivity type impurity introduction step is performed to introduce a second conductivity type impurity toward the bottom of the contact trench such that the peak position of the impurity concentration is deeper than the bottom of the second conductivity type semiconductor region, The process includes a step of forming an overhang region, in which the second conductivity type impurity is diffused to form an overhang region of the second conductivity type in a region sandwiched between adjacent trenches, which is separated from the trenches and extends outward from the bottom of the second conductivity type semiconductor region toward the first conductivity type semiconductor layer, the deepest part of which is shallower than the deepest part of the trench, and the total amount of impurities in the depth-direction cross-section is less than the total amount of impurities in the depth-direction cross-section of the second conductivity type semiconductor region, A method for manufacturing a semiconductor device, characterized in that, in the step of forming the protruding region, the protruding region is formed by implanting a second conductive impurity in a dose of 5 × 10¹² cm⁻³.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, in the second conductivity type impurity introduction step, when Rp is the range of the second conductivity type impurity that forms the protruding region, and D is the length from the position where the semiconductor substrate contacts the surface electrode to the bottom of the second conductivity type semiconductor region, Rp > D.
11. The method for manufacturing a semiconductor device according to claim 9 or 10, characterized in that the dose amount of the second conductivity type impurity that forms the protruding region in the second conductivity type impurity introduction step is less than the dose amount of the second conductivity type impurity that forms the second conductivity type semiconductor region.