Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving reliability of a gate insulation film while suppressing an increase in an on-resistance.SOLUTION: A semiconductor device according to one embodiment includes: a gate electrode extending in a first direction; a gate insulating film that covers the gate electrode; a first semiconductor region of a first conductivity type extending in a second direction orthogonal to the first direction below the gate insulating film; and a second semiconductor region of the first conductivity type that faces the gate insulating film across the first semiconductor region. An impurity concentration of the first conductivity type of the second semiconductor region is lower than an impurity concentration of the first conductivity type of the first semiconductor region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] In a power semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), there is a structure in which a p + type semiconductor region is partially provided below a trench-type gate electrode extending in one direction. According to this structure, the electric field of the gate insulating film covering the gate electrode can be relaxed.

[0003] In such a semiconductor device, if the p + type semiconductor region is thick, it causes an increase in on-resistance. However, if the p + type semiconductor region is thin, the dimensional variation becomes large and the reliability of the gate insulating film may decrease.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of improving the reliability of a gate insulating film while suppressing an increase in on-resistance.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment includes a gate electrode extending in a first direction, a gate insulating film covering the gate electrode, a first semiconductor region of a first conductivity type extending in a second direction perpendicular to the first direction beneath the gate insulating film, and a second semiconductor region of a first conductivity type facing the gate insulating film with the first semiconductor region in between. The concentration of first conductivity type impurities in the second semiconductor region is lower than the concentration of first conductivity type impurities in the first semiconductor region. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view of a semiconductor device according to the first embodiment, taken in a vertical direction. [Figure 2] Figure 2 is a cross-sectional view of the semiconductor device according to the first embodiment, obtained by cutting it vertically at a different location than in Figure 1. [Figure 3] These are cross-sectional views along cutting line AA shown in Figure 1 and cutting line CC shown in Figure 2. [Figure 4] This is a cross-sectional view along the cutting line BB shown in Figure 1 and the cutting line DD shown in Figure 2. [Figure 5] This is a cross-sectional view illustrating the process for forming a p-type semiconductor region. [Figure 6] This is a cross-sectional view illustrating the process of forming the first to third current diffusion regions. [Figure 7] This is a cross-sectional view illustrating the process of forming a p+ type semiconductor region. [Figure 8] This is a cross-sectional view illustrating the process of forming an n-type semiconductor region. [Figure 9] This is a cross-sectional view illustrating the process of forming the fourth current diffusion region. [Figure 10] This is a cross-sectional view illustrating the formation process of the fourth current diffusion region, at a different cutting point than that shown in Figure 9. [Figure 11] This is a cross-sectional view illustrating the process of forming the p-base region, n+ source region, p+ contact region, and trench. [Figure 12]This is a cross-sectional view at a different cutting location than that shown in Figure 11, illustrating the process of forming the p-base region, n+ source region, p+ contact region, and trench. [Figure 13] This is a cross-sectional view illustrating the process of forming a p+-type semiconductor region on the side wall of a trench. [Figure 14] This is a cross-sectional view illustrating the process of forming a gate insulating film, a gate electrode, and an interlayer insulating film. [Figure 15] This is a cross-sectional view illustrating the process of forming the gate insulating film, gate electrode, and interlayer insulating film at a different cutting location than that shown in Figure 14. [Figure 16] This is a cross-sectional view of a semiconductor device according to the first modified example, cut vertically. [Figure 17] This is a cross-sectional view of the semiconductor device according to the first modified example, cut vertically at a different location than that shown in Figure 16. [Figure 18] This is a cross-sectional view of the semiconductor device according to the second embodiment, cut in the vertical direction. [Figure 19] This is a cross-sectional view of the semiconductor device according to the second embodiment, obtained by cutting it vertically at a different location than in Figure 18. [Figure 20] This is a cross-sectional view of a semiconductor device according to the second modified example, cut vertically. [Figure 21] This is a cross-sectional view of the semiconductor device according to the second modified example, cut vertically at a different location than shown in Figure 20. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention.

[0009] (First Embodiment) FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment cut in the vertical direction. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment cut in the vertical direction at a location different from that in FIG. 1. FIG. 3 is a cross-sectional view taken along the cutting line A-A shown in FIG. 1 and the cutting line C-C shown in FIG. 2. FIG. 4 is a cross-sectional view taken along the cutting line B-B shown in FIG. 1 and the cutting line D-D shown in FIG. 2. Note that FIG. 1 corresponds to a cross-sectional view taken along the cutting line E-E shown in FIG. 3 and the cutting line G-G shown in FIG. 4. Also, FIG. 2 corresponds to a cross-sectional view taken along the cutting line F-F shown in FIG. 3 and the cutting line H-H shown in FIG. 4.

[0010] The semiconductor device 1 according to this embodiment is a MOSFET having a trench gate structure. This semiconductor device 1 includes a semiconductor part 10, a gate electrode 20, a drain electrode 30, and a source electrode 40.

[0011] First, the semiconductor part 10 will be described. As shown in FIGS. 1 to 4, the semiconductor part 10 includes a substrate 11, a drift region 12, a p-type semiconductor region 13, a current diffusion region 14, a p + type semiconductor region 15, an n - type semiconductor region 16, a p-base region 17, an n + source region 18, and a p + contact region 19. The current diffusion region 14 further includes a first current diffusion region 14a, a second current diffusion region 14b, a third current diffusion region 14c, and a fourth current diffusion region 14d.

[0012] In this embodiment, the p + type semiconductor region 15 corresponds to a first semiconductor region of the first conductivity type. Also, the p-type semiconductor region 13 corresponds to a second semiconductor region of the first conductivity type. Also, the n - type semiconductor region 16 corresponds to a third semiconductor region of the second conductivity type. Also, the third current diffusion region 14c corresponds to a fourth semiconductor region of the second conductivity type. Also, the first current diffusion region 14a and the second current diffusion region 14b correspond to a fifth semiconductor region of the second conductivity type. Further, the drift region 12 corresponds to a sixth semiconductor region of the second conductivity type.

[0013] Furthermore, in the following explanation, the arrangement and configuration of each part of the semiconductor device may be described using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are mutually orthogonal and represent the X direction (second direction), Y direction (first direction), and Z direction (third direction), respectively. In addition, the Z direction may be described as upward and the opposite direction as downward. In this embodiment, the X and Y directions represent in-plane directions parallel to the substrate 11, and the Z direction represents out-of-plane directions perpendicular to the substrate 11.

[0014] Furthermore, n - , n, n + The notation indicates that the concentration of n-type impurities increases in this order. Furthermore, p, p + This notation indicates that the concentration of p-type impurities increases in this order.

[0015] In the semiconductor section 10, the substrate 11 is, for example, an n-type SiC substrate. A drift region 12 is provided on the substrate 11.

[0016] The drift region 12 is n - This is a p-type semiconductor region. The drift region 12 is depleted by the drain voltage applied between the drain electrode 30 and the source electrode 40 when the semiconductor device 1 is turned off. Therefore, the thickness of the drift region 12 is designed to satisfy a predetermined breakdown voltage requirement. Multiple p-type semiconductor regions 13 are provided on the drift region 12.

[0017] Each of the multiple p-type semiconductor regions 13 extends in the Y direction along the gate electrode 20, as shown in Figure 4. Between the multiple p-type semiconductor regions 13, a first current diffusion region 14a and a second current diffusion region 14b are provided, as shown in Figures 1 and 2. That is, between adjacent p-type semiconductor regions 13 in the Y direction, a first current diffusion region 14a and a second current diffusion region 14b are provided.

[0018] Both the first current diffusion region 14a and the second current diffusion region 14b are n-type semiconductor regions. The first current diffusion region 14a is located on the drift region 12. The second current diffusion region 14b is located on the first current diffusion region 14a.

[0019] The n-type impurity concentration in the second current diffusion region 14b is equal to or greater than the n-type impurity concentration in the first current diffusion region 14a. However, if the concentration in the first current diffusion region 14a is high, there is a concern that the breakdown voltage of the semiconductor device 1 will decrease. Also, since the second current diffusion region 14b is located between the p-type semiconductor regions 13, it is desirable that its resistance be as low as possible. For this reason, it is desirable that the n-type impurity concentration in the second current diffusion region 14b be higher than the n-type impurity concentration in the first current diffusion region 14a.

[0020] As shown in Figure 1, p-type semiconductor region 13 and second current diffusion region 14b are p + A shaped semiconductor region 15 is provided. + A portion of the shaped semiconductor region 15 protrudes in the Z direction and contacts the side surface of the gate insulating film 21. This protruding portion is electrically connected to the source electrode 40. + The shaped semiconductor region 15 extends in the X direction, as shown in Figure 3.

[0021] Furthermore, as shown in Figure 2, above the p-type semiconductor region 13 (between the p-type semiconductor region 13 and the gate insulating film 21 in the Z direction), n - A shaped semiconductor region 16 is also provided. - As shown in Figure 3, the semiconductor region 16 has p in the Y direction. + The semiconductor region 15 is arranged alternately with the n - The n-type impurity concentration in the semiconductor region 16 is approximately the same as the n-type impurity concentration in the drift region 12.

[0022] Also, as shown in Figure 3, multiple n -A third current diffusion region 14c is provided between the n-type semiconductor regions 16 in the X direction. The third current diffusion region 14c is an n-type semiconductor region, similar to the first current diffusion region 14a and the second current diffusion region 14b described above. The n-type impurity concentration in the third current diffusion region 14c is greater than or equal to the n-type impurity concentration in the first current diffusion region 14a, and less than or equal to the n-type impurity concentration in the second current diffusion region 14b.

[0023] However, the third current diffusion region 14c is the current path when the semiconductor device 1 is turned on, so it is desirable that it have low resistance. On the other hand, since the third current diffusion region 14c is located near the bottom of the trench, if the n-type impurity concentration is too high, the electric field of the gate insulating film 21 will become high. For this reason, it is desirable that the n-type impurity concentration in the third current diffusion region 14c be higher than the n-type impurity concentration in the first current diffusion region 14a, and less than or equal to that of the second current diffusion region 14b.

[0024] As shown in Figures 1 and 2, p + On the semiconductor region 15 and n - A gate insulating film 21 and a fourth current diffusion region 14d are provided on the shaped semiconductor region 16. More specifically, multiple gate insulating films 21 are provided in the X direction, and each gate insulating film 21 extends in the Y direction. The fourth current diffusion region 14d is provided between adjacent gate insulating films 21 in the X direction. The gate insulating film 21 is, for example, a silicon oxide film (SiO2).

[0025] The fourth current diffusion region 14d is an n-type semiconductor region, similar to the first current diffusion regions 14a to the third current diffusion regions 14c described above. The n-type impurity concentration in the fourth current diffusion region 14d is greater than or equal to the n-type impurity concentration in the first current diffusion region 14a, and less than or equal to the n-type impurity concentration in the third current diffusion region 14c.

[0026] However, a p-base region 17 is joined to the fourth current diffusion region 14d. Therefore, if the n-type impurity concentration in the fourth current diffusion region 14d is too high, it will deplete the p-base region 17. For this reason, it is desirable that the n-type impurity concentration in the fourth current diffusion region 14d be higher than the n-type impurity concentration in the first current diffusion region 14a, and lower than the n-type impurity concentration in the third current diffusion region 14c.

[0027] On the p-base region 17 provided on the fourth current diffusion region 14d, n + A source area 18 is provided. + Source region 18 is p + It is in contact with the source electrode 40 together with the contact area 19.

[0028] Next, the gate electrode 20, the drain electrode 30, and the source electrode 40 will be described.

[0029] The gate electrode 20 is formed inside the gate insulating film 21. That is, the gate electrode 20 is covered by the gate insulating film 21 and extends in the Y direction. The gate electrode 20 can be formed using, for example, polysilicon. The drain electrode 30 is provided on the back surface of the substrate 11, which is opposite the surface on which the semiconductor portion 10 is provided in the Z direction. The source electrode 40 is positioned opposite the drain electrode 30 in the Z direction, with the semiconductor portion 10 in between. The source electrode 40 is electrically insulated from the gate electrode 20 by the interlayer insulating film 41. The drain electrode 30 and the source electrode 40 can be formed using metal.

[0030] Next, with reference to Figures 5 to 15, an example of a manufacturing method for the semiconductor device 1 configured as described above will be explained.

[0031] First, as shown in Figure 5, a p-type semiconductor region 13 is formed within a drift region 12 on the substrate 11 by ion implantation using a mask. Figure 5 is a cross-sectional view of the same location as in Figure 1. At this point, the cross-section shown in Figure 2 also has the same structure as in Figure 5.

[0032] The mask material used in the formation process of the p-type semiconductor region 13 shown in Figure 5 is, for example, an oxide film or a resist. In addition, aluminum (Al) or boron (B) ions are implanted as p-type impurities. At this time, the ions are implanted with a tilt angle of 0° relative to the surface of the substrate 11. Here, the tilt angle is the angle of inclination with respect to the Z direction perpendicular to the surface of the substrate 11. In other words, when the tilt angle is 0°, the direction of ion implantation is the Z direction. If the substrate 11 is a SiC substrate, the ions are implanted along the crystal axis of the SiC.

[0033] Next, as shown in Figure 6, a first current diffusion region 14a, a second current diffusion region 14b, and a third current diffusion region 14c are sequentially formed within the drift region 12 by ion implantation using a mask. Figure 6 is also a cross-sectional view of the same location as in Figure 1. At this point, the cross-section shown in Figure 2 has the same structure as in Figure 6.

[0034] The mask used in the formation process of the first current diffusion region 14a to the third current diffusion region 14c is newly formed after removing the mask used in the formation process of the p-type semiconductor region 13. This mask protects the terminal region (not shown) of the substrate 11 and has an opening in the cell region shown in Figure 6. Therefore, the ions implanted in this process are bounced back by the p-type semiconductor region 13, thus avoiding misalignment between each current diffusion region and the p-type semiconductor region 13. In this process, nitrogen (N) or phosphorus (P) ions are implanted as n-type impurities. At this time, the ions are implanted with a tilt angle of 0° relative to the surface of the substrate 11. If the substrate 11 is a SiC substrate, the ions are implanted along the crystal axis of SiC. Furthermore, by adjusting the amount and time of ion implantation, the first current diffusion region 14a to the third current diffusion region 14c, each with different n-type impurity concentrations, can be formed.

[0035] Next, as shown in Figure 7, ion implantation using a mask is performed on a portion of the third current diffusion region 14c, and p +A p-type semiconductor region 15 is formed. Figure 7 is a cross-sectional view of the same location as in Figure 1. In this process, aluminum (Al) or boron (B) ions are implanted as p-type impurities. At this time, by adjusting the amount and time of ion implantation, p + The p-type impurity concentration in the p-type semiconductor region 15 is higher than the p-type impurity concentration in the p-type semiconductor region 13.

[0036] Next, as shown in Figure 8, ion implantation using a mask is performed on the p-type semiconductor region 13 within the third current diffusion region 14c. - A shaped semiconductor region 16 is formed. Figure 8 is a cross-sectional view of the same location as in Figure 2.

[0037] n - The mask used in the formation process of the shaped semiconductor region 16 is p + After removing the mask used in the formation process of the shaped semiconductor region 15, a new one is formed. This mask is n - It is open in the formation region of the shaped semiconductor region 16. As a result, as shown in Figure 3, p + Semiconductor region 15 and n - The shaped semiconductor region 16 forms a lattice-like pattern.

[0038] Next, as shown in Figures 9 and 10, p + Semiconductor region 15, n - A fourth current diffusion region 14d is formed on each of the shaped semiconductor region 16 and the third current diffusion region 14c. Figure 9 is a cross-sectional view of the same location as in Figure 1. Also, Figure 10 is a cross-sectional view of the same location as in Figure 2. The fourth current diffusion region 14d can be formed, for example, by epitaxial growth.

[0039] Next, as shown in Figures 11 and 12, ion implantation using a mask is performed to implant a p-base region 17 and n-base region 17 in the upper part of the fourth current diffusion region 14d. + Source region 18 and p + A contact area 19 is formed. Figure 11 is a cross-sectional view of the same location as in Figure 1. Also, Figure 12 is a cross-sectional view of the same location as in Figure 2.

[0040] p base region 17 and p + The contact region 19 can be formed by ion implantation of aluminum or boron. + The source region 18 can be formed by ion implantation of nitrogen or phosphorus.

[0041] Next, a trench 50 is formed, for example, by RIE (Reactive Ion Etching). The trench 50 is a p-based region 17, n + The source region 18 and the fourth current diffusion region 14d are penetrated in the Z direction, p + Semiconductor region 15 and n - The semiconductor region 16 is terminated.

[0042] Next, as shown in Figure 13, ion implantation using a mask is performed on the side wall of the trench 50, p + A shaped semiconductor region 15 is formed. Figure 13 is a cross-sectional view of the same location as in Figure 1.

[0043] The mask used in this process is patterned to partially expose trench 50. + The shaped semiconductor region 15 can be formed by ion implantation in a direction oblique to the Z direction.

[0044] Next, as shown in Figures 14 and 15, the gate insulating film 21 and the gate electrode 20 are sequentially formed in the trench 50. Subsequently, the interlayer insulating film 41 is formed on top of the gate insulating film 21 and the gate electrode 20. Figure 14 is a cross-sectional view of the same location as in Figure 1. Figure 15 is a cross-sectional view of the same location as in Figure 2.

[0045] Finally, as shown in Figures 1 and 2, the semiconductor device 1 according to this embodiment is completed by forming the source electrode 40 and the drain electrode 30.

[0046] The manufacturing process described above is an example of a manufacturing method for the semiconductor device 1 according to the first embodiment, and is not limited to any particular manufacturing method. For example, the p-type semiconductor region 13 may be formed by forming a groove instead of ion implantation and embedding the p-type semiconductor in the groove. Alternatively, the p-type semiconductor region 13 may be formed by ion implantation from the trench 50.

[0047] According to the embodiment described above, as shown in Figure 1, the p-type semiconductor region 13 is p + The gate insulating film 21 is facing the p-type semiconductor region 15. The conductivity of the p-type semiconductor region 13 is p + The conductivity type is the same as that of the p-type semiconductor region 15. Also, the p-type impurity concentration of the p-type semiconductor region 13 is p + It is lower than the p-type impurity concentration in the p-type semiconductor region 15. By providing the p-type semiconductor region 13, + Because the electric field applied to the semiconductor region 15 can be suppressed, p + This eliminates the need to increase the thickness of the p-type semiconductor region 15. Generally, the resistance of an n-type semiconductor region surrounded by p-type semiconductor regions is low if the impurity concentration of the p-type semiconductor region is low. Therefore, in this embodiment as well, the increase in on-resistance can be suppressed. Thus, it is possible to improve the reliability of the gate insulating film while suppressing the increase in on-resistance.

[0048] Furthermore, in this embodiment, as shown in Figure 3, p + Semiconductor region 15 and n - The shaped semiconductor regions 16 are arranged alternately in the Y direction. This allows p + Compared to the case where the semiconductor region 15 does not exist, the area of ​​the gate insulating film 21 and the third current diffusion region 14c facing the gate electrode 20 can be reduced. In other words, this leads to a reduction in the area of ​​the drain electrode 30 facing the gate electrode 20, making it possible to reduce the feedback capacitance of the semiconductor device 1.

[0049] Furthermore, n - The shaped semiconductor region 16 and the third current diffusion region 14c are arranged alternately in the X direction. -The n-type impurity concentration in the semiconductor region 16 is as low as the n-type impurity concentration in the drift region 12, while the n-type impurity concentration in the third current diffusion region 14c is n - It is higher than the n-type impurity concentration in the n-type semiconductor region 16. As shown in Figure 2, n - The shaped semiconductor region 16 is located below the gate insulating film 21, and the third current diffusion region 14c is located below the source electrode 40. This makes it possible to achieve both electric field relaxation of the gate insulating film 21 and reduction of on-resistance.

[0050] (First variation) Figure 16 is a cross-sectional view of the semiconductor device according to the first modified example, cut vertically. Figure 17 is a cross-sectional view of the semiconductor device according to the first modified example, cut vertically at a different location than in Figure 16. In Figures 16 and 17, the same reference numerals are used for components similar to those in the semiconductor device 1 according to the first embodiment described above, and detailed descriptions are omitted. The cross-section shown in Figure 16 corresponds to the cross-section shown in Figure 1. The cross-section shown in Figure 17 corresponds to the cross-section shown in Figure 2.

[0051] In the semiconductor device 1 according to the first embodiment described above, the p-type semiconductor region 13 is terminated at the first current diffusion region 14a, as shown in Figures 1 and 2. On the other hand, in the semiconductor device 1a according to this modified example, the p-type semiconductor region 13 extends to the drift region 12, as shown in Figures 16 and 17. That is, the semiconductor device 1a according to this modified example has a superjunction (SJ) structure.

[0052] According to this modification, multiple p-type semiconductor regions 13 are n ‐ They are arranged at intervals from each other within the drift region 12, which is a type semiconductor region. Therefore, within the drift region 12, the p-type semiconductor region 13 and n ‐ The semiconductor regions are arranged alternately in the X direction. This ensures that when a voltage is applied between the drain electrode 30 and the source electrode 40, the drift region 12 has a uniform electric field strength. Therefore, in this modified example, the resistance of the drift region 12 can be reduced compared to the first embodiment. As a result, the on-resistance can be reduced compared to the first embodiment.

[0053] (Second Embodiment) Figure 18 is a cross-sectional view of the semiconductor device according to the second embodiment, cut vertically. Figure 19 is a cross-sectional view of the semiconductor device according to the second embodiment, cut vertically at a different location than in Figure 18. The cross-section shown in Figure 18 corresponds to the cross-section shown in Figure 1. The cross-section shown in Figure 19 corresponds to the cross-section shown in Figure 2.

[0054] In Figures 18 and 19, components similar to those in the semiconductor device 1 according to the first embodiment described above are denoted by the same reference numerals, and detailed descriptions are omitted. Furthermore, the manufacturing process for the semiconductor device 2 according to this embodiment is the same as that of the first embodiment. Therefore, the manufacturing method for the semiconductor device 2 according to this embodiment is also omitted.

[0055] As shown in Figure 18, in the semiconductor device 2 according to this embodiment, the p-type semiconductor region 13 is the same as in the first embodiment, p + The gate insulating film 21 is facing the semiconductor region 15. On the other hand, as shown in Figures 18 and 19, in the semiconductor device 2 according to this embodiment, p + The semiconductor layer between the shaped semiconductor region 15 and the gate insulating film 21 is n - This is a semiconductor region 16. Therefore, this embodiment differs from the first embodiment in that the current diffusion region 14 does not have a third current diffusion region 14c.

[0056] Furthermore, in the cross-section shown in Figure 19, the p-type semiconductor region 13 is n - It is located in the lower layer of the p-type semiconductor region 16. Therefore, the thickness of this p-type semiconductor region 13 is p + The thickness is greater than that of the p-type semiconductor region 13 (see Figure 18) provided in the lower layer of the p-type semiconductor region 15. In other words, this embodiment differs from the first embodiment in that two types of p-type semiconductor regions 13 with different thicknesses are provided. As shown in Figure 18, the bottom and side surfaces of some of the gate insulating film 21 are p + A shaped semiconductor region 15 is provided for grounding the source electrode 40.

[0057] In this embodiment, when the semiconductor device 2 is in the ON state, n - The semiconductor region 16 becomes part of the current path from the drain electrode 30 to the source electrode 40. Also, when the semiconductor device 2 is in the off state, n - The semiconductor region 16 is depleted, relaxing the electric field of the gate insulating film 21. In this embodiment, n - The n-type impurity concentration in the semiconductor region 16 is preferably lower than the n-type impurity concentration in the drift region 12. - The thickness of the semiconductor region 16 should preferably be as thin as possible.

[0058] According to the embodiment described above, as shown in Figure 18, the p-type semiconductor region 13 is p + The gate insulating film 21 is facing the semiconductor region 15. Therefore, similar to the first embodiment, p + The increase in on-resistance can be suppressed without making the shaped semiconductor region 15 unnecessarily thick or thin. Therefore, it is possible to improve the reliability of the gate insulating film while suppressing the increase in on-resistance.

[0059] Furthermore, in this embodiment, as shown in Figures 18 and 19, p is applied to the bottom surface of the gate insulating film 21. + n - A p-type semiconductor region 16 is provided. In this embodiment as well, the p-type semiconductor region 13 extends in the Y direction along the gate electrode 20. In addition, as shown in Figure 18, a p-type semiconductor region perpendicular to the gate electrode 20 is provided. + The shaped semiconductor region 15 is connected to the source electrode 40. By having such a structure, the semiconductor device 2 according to this embodiment can achieve both improved reliability of the gate insulating film 21 and reduced on-resistance.

[0060] (Second variation) Figure 20 is a cross-sectional view of the semiconductor device according to the second modified example, cut vertically. Figure 21 is a cross-sectional view of the semiconductor device according to the second modified example, cut vertically at a different location than in Figure 20. In Figures 20 and 21, the same reference numerals are used for components similar to those in the semiconductor device 2 according to the second embodiment described above, and detailed explanations are omitted. The cross-section shown in Figure 20 corresponds to the cross-section shown in Figure 18. The cross-section shown in Figure 21 corresponds to the cross-section shown in Figure 19.

[0061] In the semiconductor device 2 according to the second embodiment described above, the p-type semiconductor region 13 is terminated in the first current diffusion region 14a, as shown in Figures 18 and 19. On the other hand, in the semiconductor device 2a according to this modified example, the p-type semiconductor region 13 extends to the drift region 12, as shown in Figures 20 and 21. That is, the semiconductor device 2a according to this modified example has a superjunction (SJ) structure, similar to the semiconductor device 1a according to the first modified example described above.

[0062] Therefore, in this modified example as well, when a voltage is applied between the drain electrode 30 and the source electrode 40, the drift region 12 has a uniform electric field strength. As a result, in this modified example, the resistance of the drift region 12 can be reduced compared to the second embodiment. Consequently, it becomes possible to reduce the on-resistance compared to the second embodiment.

[0063] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0064] 1, 1a, 2, 2a: Semiconductor devices 12: Drift Region 13: p-type semiconductor region 15:p + Semiconductor Region 16:n - Semiconductor Region 14a: First current diffusion region 14b: Second current diffusion region 14c: Third current diffusion region

Claims

1. A gate electrode extending in the first direction, The gate insulating film covering the gate electrode, A first semiconductor region of a first conductivity type extending in a second direction perpendicular to the first direction, beneath the gate insulating film, A second semiconductor region of a first conductivity type facing the gate insulating film, with the first semiconductor region in between, Below the gate insulating film, the first semiconductor region and the third semiconductor region of the second conductivity type are alternately provided in the first direction, The material comprises the third semiconductor region and a fourth semiconductor region of second conductivity type arranged alternately in the second direction, The concentration of the first conductivity type impurity in the second semiconductor region is lower than the concentration of the first conductivity type impurity in the first semiconductor region. The concentration of the second conductivity type impurity in the fourth semiconductor region is higher than the concentration of the second conductivity type impurity in the third semiconductor region. The end of the third semiconductor region in the second direction is in contact with the fourth semiconductor region, A semiconductor device in which the second semiconductor region extends in a first direction along the gate electrode.

2. A gate electrode extending in a first direction, The gate insulating film covering the gate electrode, A first semiconductor region of a first conductivity type extending in a second direction perpendicular to the first direction, beneath the gate insulating film, A second semiconductor region of a first conductivity type facing the gate insulating film, with the first semiconductor region in between, Below the gate insulating film, the first semiconductor region and the third semiconductor region of the second conductivity type are alternately provided in the first direction, The present invention comprises a fifth semiconductor region of a second conductivity type provided below the first semiconductor region and the third semiconductor region, The second semiconductor region is provided within the fifth semiconductor region. A semiconductor device wherein the concentration of the second conductivity type impurity in the fifth semiconductor region is higher than the concentration of the second conductivity type impurity in the third semiconductor region.

3. The semiconductor device according to claim 1, wherein in the second direction, the width of the second semiconductor region is wider than the width of the third semiconductor region.

4. The semiconductor device according to claim 1 or 2, wherein the second semiconductor region is also provided below the third semiconductor region.

5. The semiconductor device according to claim 2, wherein the second semiconductor region extends in the first direction along the gate electrode.

6. The present invention further comprises a fifth semiconductor region of a second conductivity type provided below the first semiconductor region and the third semiconductor region, The semiconductor device according to claim 1, wherein the second semiconductor region is provided within the fifth semiconductor region.

7. The fifth semiconductor region of the second conductivity type is provided below the first semiconductor region and below the third semiconductor region, The present invention further comprises a sixth semiconductor region of a second conductivity type provided below the fifth semiconductor region, The semiconductor device according to claim 1, wherein the second semiconductor region extends from the fifth semiconductor region to the sixth semiconductor region.

8. A gate electrode extending in a first direction, The gate insulating film covering the gate electrode, A first semiconductor region of a first conductivity type extending in a second direction perpendicular to the first direction, beneath the gate insulating film, The first semiconductor region is separated from the gate insulating film by a second semiconductor region of a first conductivity type, and the second semiconductor region of a first conductivity type is separated from the first semiconductor region. The concentration of the first conductivity type impurity in the second semiconductor region is lower than the concentration of the first conductivity type impurity in the first semiconductor region. A third semiconductor region of a second conductivity type is provided at least between the gate insulating film and the first semiconductor region, The device further comprises a drain electrode and a source electrode facing each other in a third direction perpendicular to the first and second directions, with the gate electrode in between. A semiconductor device wherein a portion of the first semiconductor region is in contact with the side surface of the gate insulating film and is electrically connected to the source electrode.

9. The semiconductor device according to claim 8, wherein the position where the first semiconductor region and the second semiconductor region are in contact is closer to the drain electrode than the position where the third semiconductor region and the second semiconductor region are in contact.

10. The semiconductor device according to claim 1, 2, or 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.

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