Electronic circuits and computing devices
The electronic circuit design with intersecting substrate surfaces and conductive members addresses crosstalk and density issues, resulting in high-density circuits with improved characteristics and controlled coupling.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2023-05-17
- Publication Date
- 2026-06-17
AI Technical Summary
Existing electronic circuits and computing devices require improvements in characteristics such as reducing crosstalk and increasing density while maintaining effective capacitor elements.
The electronic circuit incorporates a first substrate with intersecting side surfaces and conductive members forming capacitor elements along these surfaces, utilizing Josephson junctions and conductive films to create high-density circuits with reduced crosstalk.
This configuration allows for the creation of high-density electronic circuits with suppressed crosstalk and improved characteristics, enabling effective capacitor elements and controlled coupling strength through modulated magnetic flux.
Smart Images
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Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to electronic circuits and computing devices.
Background Art
[0002] For example, an electronic circuit including a plurality of non-linear elements is used in a computing device. In electronic circuits and computing devices, improvement of characteristics is desired.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] Embodiments of the present invention provide an electronic circuit and a computing device capable of improving characteristics.
Means for Solving the Problems
[0005] According to embodiments of the present invention, the electronic circuit includes a first substrate and a first structure. The first substrate includes a first surface and a first side surface, a second side surface, a third side surface and a third other side surface. The first side surface, the second side surface, the third side surface and the third other side surface intersect with a plane along the first surface. The first structure includes a first nonlinear element, a first conductive member, a second conductive member and a third conductive member. The first nonlinear element includes a first element portion, a second element portion and an intermediate Josephson junction provided between the first element portion and the second element portion. The first conductive member includes a first region and a first connection region. The first region is provided along the first side surface. A portion of the first connection region is electrically connected to the first region. Another portion of the first connection region is electrically connected to the first element portion. The second conductive member includes a second region and a second connection region. The second region is provided along the second side surface. A portion of the second connection region is electrically connected to the second region. Another portion of the second connection region is electrically connected to the second element portion. The third conductive member includes a third region and a third other region. The third region is provided along the third side surface. The third other region is provided along the third other side surface. The direction from the first region to the third region is along the plane. The direction from the second region to the third other region is along the plane. [Brief explanation of the drawing]
[0006] [Figure 1] Figure 1 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 2] Figures 2(a) to 2(d) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. [Figure 3] Figures 3(a) to 3(d) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. [Figure 4] Figure 4 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 6]Figure 6 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 7] Figures 7(a) to 7(c) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. [Figure 8] Figure 8 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. [Figure 9] Figure 9 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 10] Figure 10 is a schematic plan view illustrating a part of the electronic circuit according to the first embodiment. [Figure 11] Figures 11(a) and 11(b) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. [Figure 12] Figure 12 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view illustrating an electronic circuit according to the first embodiment. [Figure 14] Figure 14 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 15] Figure 15 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 16] Figure 16 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 17] Figures 17(a) and 17(b) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. [Figure 18] Figure 18 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. [Figure 19] Figure 19 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Figure 20] Figure 20 is a schematic plan view illustrating an electronic circuit according to the first embodiment. [Modes for carrying out the invention]
[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the specification of this application and each figure, the same reference numerals are given to elements similar to those described above with respect to the previously shown figures, and detailed descriptions are omitted as appropriate.
[0008] (First Embodiment) FIG. 1 is a schematic plan view illustrating an electronic circuit according to the first embodiment. FIGS. 2(a) to 2(d) and FIGS. 3(a) to 3(d) are schematic cross-sectional views illustrating the electronic circuit according to the first embodiment. FIG. 4 is a schematic diagram illustrating the electronic circuit and the computing device according to the first embodiment. FIG. 2(a) is a cross-sectional view taken along line A1 - A2 of FIG. 1. FIG. 2(b) is a cross-sectional view taken along line A3 - A4 of FIG. 1. FIG. 2(c) is a cross-sectional view taken along line A5 - A6 of FIG. 1. FIG. 2(d) is a cross-sectional view taken along line A7 - A8 of FIG. 1. FIG. 3(a) is a cross-sectional view taken along line B1 - B2 of FIG. 1. FIG. 3(b) is a cross-sectional view taken along line B3 - B4 of FIG. 1. FIG. 3(c) is a cross-sectional view taken along line B5 - B6 of FIG. 1. FIG. 3(d) is a cross-sectional view taken along line B7 - B8 of FIG. 1.
[0009] As shown in FIGS. 2(a) to 2(d) and FIGS. 3(a) to 3(d), the electronic circuit according to the embodiment includes a first substrate 81s and a first structure 10A. The first substrate 81s may be, for example, an insulating substrate. The first substrate 81s may include, for example, a silicon substrate. The first substrate 81s may include an insulating film provided on the surface of the silicon substrate.
[0010] The first substrate 81s includes a first surface 81a and a second surface 81b. The first surface 81a is, for example, the upper surface. The second surface 81b is, for example, the lower surface. The first surface 81a extends along the X-Y plane. One direction along the X-Y plane is defined as the X-axis direction. The Y-axis direction extends along the X-Y plane and is perpendicular to the X-axis direction. The direction perpendicular to the X-Y plane is defined as the Z-axis direction.
[0011] The first substrate 81s includes a first side surface s1, a second side surface s2, a third side surface s3, and a third other side surface sA3. The first side surface s1, the second side surface s2, the third side surface s3, and the third other side surface sA3 intersect the plane (X-Y plane) along the first surface 81a. In one example, these side surfaces extend along the Z-axis direction. These side surfaces may be inclined with respect to the X-Y plane.
[0012] The first structure 10A includes a first non-linear element 50C, a first conductive member 11C, a second conductive member 12C, and a third conductive member 13C.
[0013] As shown in FIGS. 1 and 3(b), the first non-linear element 50C includes a first element portion 20a, a second element portion 20b, and an intermediate Josephson junction 23. The intermediate Josephson junction 23 is provided between the first element portion 20a and the second element portion 20b. The intermediate Josephson junction 23 includes, for example, two conductive layers and an insulating layer 23i provided between the two conductive layers.
[0014] The first conductive member 11C includes a first region 11s and a first connection region 11c. As shown in FIG. 2(a), the first region 11s is provided along the first side surface s1. The first region 11s is, for example, a side surface conductive film. A part of the first connection region 11c is electrically connected to the first region 11s. As shown in FIGS. 1 and 3(c), another part of the first connection region 11c is electrically connected to the first element portion 20a.
[0015] The second conductive member 12C includes a second region 12s and a second connection region 12c. As shown in Figure 2(b), the second region 12s is provided along the second side surface s2. The second region 12s is, for example, a side conductive film. A portion of the second connection region 12c is electrically connected to the second region 12s. As shown in Figures 1 and 3(d), another portion of the second connection region 12c is electrically connected to the second element portion 20b.
[0016] The third conductive member 13C includes a third region 13s and a third other region 13sA. As shown in Figure 3(a), the third region 13s is provided along the third side surface s3. The third other region 13sA is provided along the third other side surface sA3. The third region 13s and the third other region 13sA are, for example, side conductive films. The direction from the first region 11s to the third region 13s is along the XY plane. The direction from the second region 12s to the third other region 13sA is along the XY plane.
[0017] For example, one capacitor element (first capacitor C1, see Figure 4) is formed by the first region 11s and the third region 13s. Another capacitor element (second capacitor C2, see Figure 4) is formed by the second region 12s and the third other region 13sA. By providing multiple capacitor elements based on side conductive films, the area of the first structure 10A can be reduced. For example, a high-density electronic circuit can be obtained. According to this embodiment, an electronic circuit with improved characteristics can be provided.
[0018] The direction perpendicular to the first surface 81a is defined as the first direction D1. The direction from the second surface 81b to the first surface 81a is along the first direction D1. The first direction D1 is, for example, the Z-axis direction. As shown in Figure 3(a), the first substrate 81s includes a first recess 11d and a second recess 12d. The first recess 11d includes a first side surface s1. The second recess 12d includes a second side surface s2. In this example, the above-mentioned side conductive film is provided along the side surface of the recess. The first conductive member 11C may be provided at the bottom of the first recess 11d. The second conductive member 12C may be provided at the bottom of the second recess 12d.
[0019] In this example, as shown in Figures 1 and 3(a), the first substrate 81s includes a first hole h1. The first hole h1 connects to the first surface 81a and the second surface 81b. The third side surface s3 may be a part of the first hole h1. The third other side surface sA3 may be another part of the first hole h1. In this example, the third region 13s and the third other region 13sA are provided along two sides of the first hole h1.
[0020] As shown in Figure 3(a), the first structure 10A may include a second surface conductive film 52f. The second surface conductive film 52f is provided along the second surface 81b. The third conductive member 13C is electrically connected to the second surface conductive film 52f. The third region 13s and the third other region 13sA are electrically connected to the second surface conductive film 52f.
[0021] The second conductive film 52f can be set to a fixed potential, for example. The fixed potential is, for example, the ground potential. The third conductive member 13C can be set to a fixed potential. The third region 13s and the third other region 13sA can be set to a fixed potential.
[0022] The third region 13s and the third other region 13sA can be, for example, TSVs (Through Silicon Vias).
[0023] As shown in Figure 1, a first hole h1 is provided between the first region 11s and the second region 12s. This suppresses crosstalk between the first region 11s and the second region 12s. For example, noise is suppressed.
[0024] As shown in Figure 3(a), the length of the third region 13s in the first direction D1 is defined as the third region length 13sL. The length of the third other region 13sA in the first direction D1 is defined as the third other region length 13sAL. The length of the first region 11s in the first direction D1 is defined as the first region length 11sL. The length of the second region 12s in the first direction D1 is defined as the second region length 12sL. As already explained, the first direction D1 is perpendicular to the first surface 81a.
[0025] The length of the third region 13sL is longer than the length of the first region 11sL. The length of the third other region 13sAL is longer than the length of the second region 12sL. A capacitor element of appropriate size can be obtained from the third region 13s and the first region 11s having such a configuration. A capacitor element of appropriate size can be obtained from the third other region 13sA and the second region 12s having such a configuration.
[0026] For example, the length of the third region 13sL is between 2 and 350 times the length of the first region 11sL. The length of the third other region 13sAL is between 2 and 35 times the length of the second region 12sL. For example, the length of the third region 13sL may be between 2 and 10 times the length of the first region 11sL. The length of the third other region 13sAL may be between 2 and 10 times the length of the second region 12sL.
[0027] In one example, the length of the third region 13sL is between 100 μm and 700 μm. The length of the first region 11sL is, for example, between 2 μm and 80 μm. The length of the third other region 13sAL is, for example, between 100 μm and 700 μm. The length of the second region 12sL is, for example, between 2 μm and 80 μm. The length of the third region 13sL may also be between 100 μm and 300 μm. The length of the first region 11sL may also be, for example, between 10 μm and 80 μm. The length of the third other region 13sAL may also be, for example, between 100 μm and 300 μm. The length of the second region 12sL may also be, for example, between 10 μm and 80 μm.
[0028] For example, the length of the first region 11 sL and the length of the second region 12 sL are approximately 30 μm. The length of the third region 13 sL and the length of the third other region 13 sAL are, for example, approximately 200 μm or less.
[0029] The length of the first recess 11d and the second recess 12d in the X-axis direction is, for example, about 20 μm. The length of the first recess 11d and the second recess 12d in the Y-axis direction is, for example, about 20 μm. The shape of these recesses is arbitrary. Multiple first recesses 11d may be provided. Multiple second recesses 12d may be provided. A conductive film may be provided along the sides of these multiple recesses.
[0030] The length of the first hole h1 in the X-axis direction is, for example, approximately 100 μm. The length of the first hole h1 in the Y-axis direction is, for example, approximately 26 μm. The length of the first hole h1 in the Z-axis direction corresponds to the thickness of the first substrate 81s.
[0031] The distance between the first region 11s and the third region 13s is, for example, between 5 μm and 60 μm. The distance between the second region 12s and the third region 13sA is, for example, between 5 μm and 60 μm.
[0032] As shown in Figure 4, a portion of the first structure 10A is coupled to the first element structure 50A. Another portion of the first structure 10A is coupled to the second element structure 50B. The first structure 10A is, for example, a coupler. The first nonlinear element 50C is, for example, a coupler.
[0033] As shown in Figure 1, the first structure 10A may include a conductive layer 51G. The conductive layer 51G is provided on the first surface 81a. As shown in Figures 2(c) and 2(d), the conductive layer 51G is electrically connected to the second surface conductive film 52f via the third region 13s and the third other region 13sA. The conductive layer 51G can be set to a fixed potential.
[0034] As shown in Figure 1, the first nonlinear element 50C may further include a first Josephson junction 21 and a second Josephson junction 22. One end of the first Josephson junction 21 is electrically connected to the first element portion 20a. The other end of the first Josephson junction 21 is electrically connected to the third region 13s. In this example, the other end of the first Josephson junction 21 is electrically connected to the third region 13s via a conductive layer 51G.
[0035] One end of the second Josephson junction 22 is electrically connected to the second element portion 20b. The other end of the second Josephson junction 22 is electrically connected to the third other region 13sA. In this example, the other end of the second Josephson junction 22 is electrically connected to the third other region 13sA via the conductive layer 51G.
[0036] In this example, the first Josephson junction 21 and the second Josephson junction 22 are provided on the first surface 81a. The first Josephson junction 21 includes, for example, two conductive layers and an insulating layer 21i provided between the two conductive layers. The second Josephson junction 22 includes, for example, two conductive layers and an insulating layer 22i provided between the two conductive layers.
[0037] As shown in Figure 4, the first capacitor C1 is formed by the first region 11s and the third region 13s. The second capacitor C2 is formed by the second region 12s and the third region 13sA. The first Josephson junction 21 is connected in parallel with the first capacitor C1. The second Josephson junction 22 is connected in parallel with the second capacitor C2. An intermediate Josephson junction 23 is provided between the first element portion 20a and the second element portion 20b. A fifth capacitor C5 may be formed between the first element portion 20a and the second element portion 20b.
[0038] As shown in Figure 4, the first element structure 50A includes a first element Josephson junction 51 and a first element capacitor 41. The first element capacitor 41 is connected in parallel with the first element Josephson junction 51. This parallel circuit is coupled to the first element portion 20a via a third capacitor C3. The first element structure 50A is a single qubit.
[0039] As shown in Figure 4, the second element structure 50B includes a second element Josephson junction 52 and a second element capacitor 42. The second element capacitor 42 is connected in parallel with the second element Josephson junction 52. This parallel circuit is coupled to the second element portion 20b via a fourth capacitor C4. The second element structure 50B is a single qubit.
[0040] As shown in Figure 4, the computing device 210 according to this embodiment includes a first structure 10A, a first element structure 50A, and a second element structure 50B.
[0041] The first structure 10A includes a loop 50r containing an intermediate Josephson junction 23, a first Josephson junction 21, and a second Josephson junction 22. In this embodiment, the magnetic flux Φ of the space SP within the loop 50r is moduloable. By modulating the magnetic flux Φ, the coupling strength between the coupler (first structure 10A) and the qubit may be controlled.
[0042] Figures 5 and 6 are schematic plan views illustrating an electronic circuit according to the first embodiment. Figures 7(a) to 7(c) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. Figure 8 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. Figure 5 illustrates the pattern of the conductive member on the first surface 81a of the first substrate 81s. Figure 6 illustrates the pattern of the conductive member on the second surface 81b of the first substrate 81s. Figure 6 is a transparent plan view. Figure 7(a) is a cross-sectional view taken along line A9-A10 of Figure 5. Figure 7(b) is a cross-sectional view taken along line A11-A12 of Figure 5. Figure 7(c) is a cross-sectional view taken along line B9-B10 of Figure 5.
[0043] As shown in Figure 5, in the electronic circuit 111 according to this embodiment, the first structure 10A includes a fourth conductive member 14C. The configuration of the electronic circuit 111, excluding this, may be the same as that of the electronic circuit 110.
[0044] The fourth conductive member 14C includes a fourth region 14s. As shown in Figure 7(c), the first substrate 81s further includes a fourth side surface s4. The fourth side surface s4 intersects the XY plane. The fourth region 14s is provided along the fourth side surface s4.
[0045] As shown in Figures 5, 6 and 7(c), in this example, the first substrate 81s includes a first hole h1, a second hole h2, and a third hole h3. The first hole h1, the second hole h2, and the third hole h3 are connected to the first surface 81a and the second surface 81b. These holes penetrate the first substrate 81s. The third side surface s3 is at least a part of the first hole h1. The third other side surface sA3 is at least a part of the second hole h2. The fourth side surface s4 is at least a part of the third hole h3.
[0046] Let the direction from the second region 12s to the first region 11s be the second direction D2. The second direction D2 is, for example, the Y-axis direction. The position of the fourth region 14s (fourth lateral position) in the second direction D2 lies between the position of the first region 11s (first lateral position) in the second direction D2 and the position of the second region 12s (second lateral position) in the second direction D2.
[0047] The position of the third region 13s (third lateral position) in the second direction D2 is between the fourth lateral position and the first lateral position. The position of the third other region 13sA (third other lateral position) in the second direction D2 is between the fourth lateral position and the second lateral position.
[0048] For example, in the second direction D2, the fourth region 14s lies between the first region 11s and the second region 12s. In the second direction D2, the third region 13s lies between the fourth region 14s and the first region 11s. In the second direction D2, the third other region 13sA lies between the fourth region 14s and the second region 12s.
[0049] In the electronic circuit 111, the first capacitor C1 is formed by the first region 11s and the third region 13s. The second capacitor C2 is formed by the second region 12s and the third other region 13sA. A third hole h3 is provided between the third region 13s and the third other region 13sA. This further reduces crosstalk.
[0050] The fourth region 14s functions, for example, as a control conductive member 61 as illustrated in Figure 8. For example, the current supplied to the fourth region 14s can modulate the magnetic flux Φ of the space SP within the loop 50r, including the intermediate Josephson junction 23, the first Josephson junction 21, and the second Josephson junction 22. For example, a control unit 70 is coupled to the fourth region 14s (e.g., the control conductive member 61). The control unit 70 can supply a control current (e.g., a signal) to the fourth region 14s (e.g., the control conductive member 61). The control operation of the control unit 70 can control the coupling state of the first structure 10A (coupler). Control of the coupling state includes control of the coupling strength. For example, control can be performed with respect to two qubits.
[0051] As shown in Figure 6, a control conductive film 14f may be provided on the second surface 81b. The control conductive film 14f is electrically connected to the fourth region 14s. The control conductive film 14f may be included in the fourth conductive member 14C. The control unit 70 (see Figure 8) may supply current to the fourth region 14s via the control conductive film 14f.
[0052] As shown in Figure 8, the computing device 210 according to this embodiment may include an electronic circuit 111 and a control unit 70.
[0053] Figure 9 is a schematic plan view illustrating an electronic circuit according to the first embodiment. Figure 10 is a schematic plan view illustrating a part of the electronic circuit according to the first embodiment. Figures 11(a) and 11(b) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. Figure 12 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. Figure 10 illustrates a portion of Figure 9. Figure 11(a) is a cross-sectional view taken along line E1-E2 in Figure 9. Figure 11(b) is a cross-sectional view taken along line E3-E4 in Figure 9.
[0054] As shown in Figure 9, the electronic circuit 112 according to this embodiment further includes a first element structure 50A in addition to the first structure 10A. The configuration of the electronic circuit 112, excluding this, may be the same as that of the electronic circuit 110.
[0055] The first element structure 50A includes a first element Josephson junction 51, a first element region 41s, and a first element opposing region 41sA. The first element region 41s is connected to the first element Josephson junction 51.
[0056] As shown in Figure 11(a), the first substrate 81s further includes a first element side surface s41 and a first element opposing side surface sA41. The first element side surface s41 and the first element opposing side surface sA41 intersect the XY plane. The first element region 41s is provided along the first element side surface s41. The first element opposing region 41sA is provided along the first element opposing side surface sA41. The first element opposing region 41sA is electrically connected to the third region 13s. For example, the first element opposing region 41sA is electrically connected to the second surface conductive film 52f. As already described, the third region 13s is electrically connected to the second surface conductive film 52f. The first element opposing region 41sA is electrically connected to the third region 13s via the second surface conductive film 52f. The first element opposing region 41sA can be set to a fixed potential (e.g., ground potential).
[0057] The first element region 41s can be coupled to either the first conductive member 11C or the second conductive member 12C. In this example, the first element region 41s can be coupled to the second conductive member 12C.
[0058] As shown in Figure 9, in this example, in the electronic circuit 112, the first element structure 50A includes a first element Josephson junction 51, a first element region 41s, a second element region 42s, a first element opposing region 41sA, and a second element opposing region 42sA. The first element region 41s is connected to the first element Josephson junction 51. The second element region 42s is connected to the first element Josephson junction 51. The first element structure 50A may further include a third element region 43s and a fourth element region 44s.
[0059] As shown in Figures 11(a) and 11(b), the first substrate 81s includes a first element side surface s41, a second element side surface s42, a first element opposing side surface sA41, and a second element opposing side surface sA42. The first element side surface s41, the second element side surface s42, the first element opposing side surface sA41, and the second element opposing side surface sA42 intersect the XY plane. The first element region 41s is provided along the first element side surface s41. The second element region 42s is provided along the second element side surface s42. The first element opposing region 41sA is provided along the first element opposing side surface sA41. The second element opposing region 42sA is provided along the second element opposing side surface sA42.
[0060] Multiple first structures (in this example, first structure 10A, first structure 10B, first structure 10C, and first structure 10D) are provided. The first element-facing region 41sA is electrically connected to a third region 13s contained in one of the multiple first structures (first structure 10A) (see Figure 12). The second element-facing region 42sA is electrically connected to a third region 13s contained in another of the multiple first structures (first structure 10B) (see Figure 12). These electrical connections are made, for example, via a second surface conductive film 52f.
[0061] The first element region 41s can be coupled to either the first conductive member 11C or the second conductive member 12C included in one of the multiple first structures (for example, the first structure 10A). In this example, the first element region 41s can be coupled to the second conductive member 12C (second element portion 20b) included in the first structure 10A (see Figure 12).
[0062] The second element region 42s can be coupled to either the first conductive member 11C or the second conductive member 12C, which are included in another of the multiple first structures (for example, the first structure 10B). In this example, the second element region 42s can be coupled to the second conductive member 12C (second element portion 20b) included in the first structure 10B (see Figure 12).
[0063] For example, a first element structure 50A is provided between multiple first structures (such as first structure 10A and first structure 10B).
[0064] A capacitor element is formed by the first element region 41s and the first element opposing region 41sA. A capacitor element is formed by the second element region 42s and the second element opposing region 42sA. A capacitor element is formed by the third element region 43s and the third element opposing region 43sA. A capacitor element is formed by the fourth element region 44s and the fourth element opposing region 44sA.
[0065] For example, the first substrate 81s may be provided with a first intermediate hole 41h, a second intermediate hole 42h, a third intermediate hole 43h, and a fourth intermediate hole 44h. The first element-facing region 41sA is provided along the side surface of the first intermediate hole 41h. The second element-facing region 42sA is provided along the side surface of the second intermediate hole 42h. The third element-facing region 43sA is provided along the side surface of the third intermediate hole 43h. The fourth element-facing region 44sA is provided along the side surface of the fourth intermediate hole 44h.
[0066] Thus, the first substrate 81s further includes a first intermediate hole 41h including a first element-facing side surface sA41, and a second intermediate hole 42h including a second element-facing side surface sA42 (see Figures 11(a) and 11(b)). At least a portion of either the first intermediate hole 41h or the second intermediate hole 42h is provided between the first element region 41s and the second element region 42s. Providing such a hole further suppresses crosstalk. For example, at least a portion of the first intermediate hole 41h is provided between the second region 12s of one of the plurality of structures (first structure 10A) and the second region 12s of another of the plurality of structures (first structure 10B). Providing such a hole suppresses crosstalk between one of the plurality of structures and another of the plurality of structures.
[0067] As shown in Figure 10, a pad portion PA1 may be provided on the first element structure 50A. Coupling (or connection) may be performed via the pad portion PA1. As shown in Figure 12, the computing device 210 according to the embodiment includes an electronic circuit 112.
[0068] Figure 13 is a schematic cross-sectional view illustrating an electronic circuit according to the first embodiment. Figures 14 and 15 are schematic plan views illustrating an electronic circuit according to the first embodiment. As shown in Figure 13, the computing device 210 according to this embodiment includes an electronic circuit 113 including a first base 81s, a control unit 70, and a second base 82s. The control unit 70 is provided on the second base 82s. At least a portion of the second base 82s overlaps with the first base 81s.
[0069] In this example, the second substrate 82s includes a third surface 82c and a fourth surface 82d. The third surface 82c is located between the fourth surface 82d and the first surface 81a. The third surface 82c faces the first surface 81a. In this example, the control unit 70 is provided on the third surface 82c. In other embodiments, the control unit 70 may be provided on the fourth surface 82d.
[0070] As shown in Figure 13, in this example, a first substrate conductive film CC1 is provided on the first surface 81a of the first substrate 81s. A second substrate conductive film CC2 is provided on the second substrate 82s. The second substrate conductive film CC2 faces the first substrate conductive film CC1. The second substrate conductive film CC2 is provided on the third surface 82c. In this example, a plurality of first substrate conductive films CC1 and a plurality of second substrate conductive films CC2 are provided. One of the plurality of second substrate conductive films CC2 faces one of the plurality of first substrate conductive films CC1. The first substrate conductive film CC1 can be electromagnetically coupled to the second substrate conductive film CC2. The first substrate conductive film CC1 and the second substrate conductive film CC2 can be capacitively coupled. AC signals are transmitted by coupling. A gap may be provided between the first substrate conductive film CC1 and the second substrate conductive film CC2.
[0071] As shown in Figure 13, connecting members CM may be provided. The connecting member CM electrically connects the conductive member provided on the first base body 81s with the conductive member provided on the second base body 82s. Multiple connecting members CM may be provided. One of the multiple connecting members CM electrically connects one of the multiple conductive members provided on the first base body 81s with one of the multiple conductive members provided on the second base body 82s.
[0072] Figure 14 illustrates an electronic circuit 113. In the electronic circuit 113, pad portions PA1, PA2, PB1, PB2, PB3, and PB4 are provided. Some of these pad portions are connected to a plurality of first structures 10A. Other parts of these pad portions are connected to a first element structure 50A. Except for these pad portions, the configuration of the electronic circuit 113 is the same as that of the electronic circuit 112. The pad portions PA1, PA2, PB1, PB2, PB3, and PB4 correspond to the first substrate conductive film CC1.
[0073] Figure 15 illustrates a conductive pattern provided on the second substrate 82s. In this example, a coupler control line CP1, a qubit control line CQ1, and a readout resonator RO1 are provided. In this example, multiple coupler control lines CP1 are provided. One of the multiple coupler control lines CP1 is electrically connected to a pad QB1. Another of the multiple coupler control lines CP1 is electrically connected to a pad QB2. Another of the multiple coupler control lines CP1 is electrically connected to a pad QB3. Another of the multiple coupler control lines CP1 is electrically connected to a pad QB4. The qubit control line CQ1 is electrically connected to a pad QA2. The readout resonator RO1 is electrically connected to a pad QA2. Pads QA1, QA2, QB1, QB2, QB3, and QB4 correspond to the second substrate conductive film CC2.
[0074] Pad section PA1 and pad section QA1 are joined together. Pad section PA2 and pad section QA2 are joined together. Pad section PB1 and pad section QB1 are joined together. Pad section PB2 and pad section QB2 are joined together. Pad section PB3 and pad section QB3 are joined together. Pad section PB4 and pad section QB4 are joined together.
[0075] Figure 16 is a schematic plan view illustrating an electronic circuit according to the first embodiment. Figures 17(a) and 17(b) are schematic cross-sectional views illustrating an electronic circuit according to the first embodiment. Figure 18 is a schematic diagram illustrating an electronic circuit and computing device according to the first embodiment. Figure 17(a) is a cross-sectional view taken along line E5-E6 in Figure 16. Figure 17(b) is a cross-sectional view taken along line E7-E8 in Figure 16.
[0076] As shown in Figure 16, the electronic circuit 114 according to this embodiment includes a first element structure 50A and a second element structure 50B in addition to the first structure 10A. The configuration of the first structure 10A in the electronic circuit 114 may be the same as the configuration of the first structure 10A in the electronic circuit 110.
[0077] The first element structure 50A includes a first element Josephson junction 51, a first element region 41s, and a first element opposing region 41sA. The first element region 41s is connected to the first element Josephson junction 51.
[0078] The second element structure 50B includes a second element Josephson junction 52, a second element region 42s, and a second element opposing region 42sA. The second element region 42s is connected to the second element Josephson junction 52.
[0079] As shown in Figures 17(a) and 17(b), the first substrate 81s includes a first element side surface s41, a first element opposing side surface sA41, a second element side surface s42, and a second element opposing side surface sA42. The first element side surface s41, the first element opposing side surface sA41, the second element side surface s42, and the second element opposing side surface sA42 intersect the XY plane. The first element region 41s is provided along the first element side surface s41. The first element opposing region 41sA is provided along the first element opposing side surface sA41. The second element region 42s is provided along the second element side surface s42. The second element opposing region 42sA is provided along the second element opposing side surface sA42.
[0080] The first element region 41s can be coupled to the first conductive member 11C (for example, the first region 11s) (see Figure 18). The second element region 42s can be coupled to the second conductive member 12C (for example, the second region 12s) (see Figure 18). For example, the first element region 41s and the first region 11s form a third capacitor C3. The second element region 42s and the second region 12s form a fourth capacitor C4.
[0081] The first structure 10A can be coupled with the first element structure 50A. The first structure 10A can be coupled with the second element structure 50B. High-density electronic circuits can be obtained. Crosstalk is suppressed. Electronic circuits and computing devices with improved characteristics can be provided.
[0082] As shown in Figure 16, the electronic circuit 114 may be provided with another first structure 10X, and yet another first structure 10Y, etc.
[0083] Figures 19 and 20 are schematic plan views illustrating an electronic circuit according to the first embodiment. The electronic circuit 114 (or computing device 210) may include a first substrate 81s and a second substrate 82s. Figure 19 illustrates the first substrate 81s. Figure 20 illustrates the second substrate 82s. The second substrate 82s overlaps with the first substrate 81s.
[0084] Pad sections PA1, PA2, PB1, PB2, PB3, and PB4 are coupled to pad sections QA1, QA2, QB1, QB2, QB3, and QB4 by connection sections. Coupler control line CP1 is electrically connected to coupler control electrode CPE. Qubit control line CQ1 is electrically connected to qubit control electrode CQE. Readout resonator RO1 is electrically connected to readout resonator electrode ROE.
[0085] (Second Embodiment) The second embodiment relates to a computing device. The computing device 210 (see Figure 1, etc.) includes an electronic circuit and a control unit 70 according to the embodiment. The control unit 70 can, for example, supply a signal to the fourth conductive member 14C. A computing device capable of improving characteristics is provided.
[0086] The embodiment may include the following configuration (technical proposal). (Composition 1) First substrate and, The first structure and Equipped with, The first substrate includes a first surface, a first side surface, a second side surface, a third side surface and a third other side surface, The first side, the second side, the third side, and the third other side intersect with the plane along the first surface, The first structure includes a first nonlinear element, a first conductive member, a second conductive member, and a third conductive member. The first nonlinear element includes a first element portion, a second element portion, and an intermediate Josephson junction provided between the first element portion and the second element portion. The first conductive member includes a first region and a first connection region, the first region being provided along the first side surface, a portion of the first connection region being electrically connected to the first region, and another portion of the first connection region being electrically connected to the first element portion. The second conductive member includes a second region and a second connection region, the second region being provided along the second side surface, a portion of the second connection region being electrically connected to the second region, and another portion of the second connection region being electrically connected to the second element portion. The third conductive member includes a third region and a third other region, the third region is provided along the third side surface, the third other region is provided along the third other side surface, the direction from the first region to the third region is along the plane, and the direction from the second region to the third other region is along the plane, in an electronic circuit.
[0087] (Configuration 2) The length of the third region in the first direction is longer than the length of the first region in the first direction of the first region. The first direction is perpendicular to the first plane, The electronic circuit according to configuration 1, wherein the length of the third other region in the first direction is longer than the length of the second region in the first direction of the second region.
[0088] (Composition 3) The length of the third region is between 2 and 350 times the length of the first region. The electronic circuit according to configuration 2, wherein the length of the third other region is 2 times or more and 350 times or less the length of the second region.
[0089] (Composition 4) The length of the third region is 100 μm or more and 700 μm or less. The length of the first region is 2 μm or more and 80 μm or less. The length of the third other region is 100 μm or more and 700 μm or less. The electronic circuit according to configuration 2, wherein the length of the second region is 20 μm or more and 80 μm or less.
[0090] (Composition 5) The first substrate further includes a second surface, The direction from the second surface to the first surface is along the first direction, The first substrate includes a first recess including the first side surface and a second recess including the second side surface, wherein the electronic circuit is according to any one of configurations 2 to 4.
[0091] (Composition 6) The first substrate includes a first hole connected to the first surface and the second surface, The third side is part of the first hole, The third other side is another part of the first hole, the electronic circuit according to configuration 5.
[0092] (Composition 7) The first structure further includes a second surface conductive film provided along the second surface, The third conductive member is electrically connected to the second surface conductive film, and the electronic circuit is as described in configuration 5 or 6.
[0093] (Composition 8) The first region and the third region form a first capacitor. The second region and the third other region form a second capacitor. The third conductive member is an electronic circuit according to any one of configurations 1 to 7, which can be set to a fixed potential.
[0094] (Composition 9) The first nonlinear element further includes a first Josephson junction and a second Josephson junction, One end of the first Josephson junction is electrically connected to the first element portion. The other end of the first Josephson junction is electrically connected to the third region. One end of the second Josephson junction is electrically connected to the second element portion. The other end of the second Josephson junction is electrically connected to the third other region, as described in any one of configurations 1 to 8.
[0095] (Composition 10) The first Josephson junction and the second Josephson junction are provided on the first surface, and are part of the electronic circuit described in configuration 9.
[0096] (Composition 11) The first structure further includes a fourth conductive member including a fourth region, The first substrate further includes a fourth side surface, The fourth side intersects the plane, The fourth region is an electronic circuit according to configuration 1, provided along the fourth side surface.
[0097] (Composition 12) The fourth lateral position of the fourth region in the second direction from the second region to the first region lies between the first lateral position of the first region in the second direction and the second lateral position of the second region in the second direction. The third lateral position of the third region in the second direction is located between the fourth lateral position and the first lateral position. The electronic circuit according to configuration 11, wherein the third other side position of the third other region in the second direction is located between the fourth side position and the second side position.
[0098] (Composition 13) The first substrate further includes a second surface, The first substrate includes a first recess including the first side surface and a second recess including the second side surface, The first substrate includes a first hole, a second hole and a third hole, The first hole, the second hole, and the third hole are connected to the first surface and the second surface, The third side is at least a part of the first hole, The third other side is at least a part of the second hole, The electronic circuit according to configuration 11 or 12, wherein the fourth side surface is at least a portion of the third hole.
[0099] (Composition 14) The first nonlinear element further includes a first Josephson junction and a second Josephson junction, One end of the first Josephson junction is electrically connected to the first element portion. The other end of the first Josephson junction is electrically connected to the third region. One end of the second Josephson junction is electrically connected to the second element portion. The other end of the second Josephson junction is electrically connected to the third other region. The electronic circuit according to any one of configurations 11 to 13, wherein the magnetic flux in the space within the loop, including the intermediate Josephson junction, the first Josephson junction, and the second Josephson junction, can be modulated by the current supplied to the fourth region.
[0100] (Composition 15) Further comprising the first element structure, The first element structure is The first element is a Josephson junction, The first element region connected to the first element Josephson junction, The region opposite the first element, Includes, The first substrate further includes a side surface of the first element and a side surface facing the first element, The side surface of the first element and the side surface opposite the first element intersect the plane, The first element region is provided along the side surface of the first element, The region facing the first element is provided along the side surface facing the first element, The first element-facing region is electrically connected to the third region, The electronic circuit according to any one of configurations 1 to 14, wherein the first element region is connectable to either the first conductive member or the second conductive member.
[0101] (Composition 16) Further comprising the first element structure, The first element structure is The first element is a Josephson junction, The first element region connected to the first element Josephson junction, A second element region connected to the first element Josephson junction, The region opposite the first element, The region opposite the second element, Includes, The first substrate further includes a first element side surface, a second element side surface, a first element opposing side surface, and a second element opposing side surface. The side surface of the first element, the side surface of the second element, the side surface opposite the first element, and the side surface opposite the second element intersect the plane, The first element region is provided along the side surface of the first element, The second element region is provided along the side surface of the second element, The region facing the first element is provided along the side surface facing the first element, The region facing the second element is provided along the side surface facing the second element, Multiple first structures are provided, The first element-facing region is electrically connected to the third region included in one of the plurality of first structures. The second element-facing region is electrically connected to the third region which is included in another one of the plurality of first structures. The first element region is connectable to one of the first conductive member and the second conductive member included in one of the plurality of first structures. The electronic circuit according to any one of configurations 1 to 14, wherein the second element region is connectable to one of the first conductive member and the second conductive member included in the other one of the plurality of first structures.
[0102] (Composition 17) The first substrate further includes a first intermediate hole including the side surface facing the first element, a second intermediate hole including the side surface facing the second element, At least a portion of either the first intermediate hole or the second intermediate hole is provided between the first element region and the second element region, in the electronic circuit described in configuration 16.
[0103] (Composition 18) First element structure, The second element structure, Furthermore, The first element structure is The first element is a Josephson junction, The first element region connected to the first element Josephson junction, The region opposite the first element, Includes, The second element structure is, The second element Josephson junction, The second element region connected to the aforementioned second element Josephson junction, The region opposite the second element, Includes, The first substrate further includes a side surface of the first element, a side surface facing the first element, a side surface of the second element, and a side surface facing the second element. The side surface of the first element, the side surface opposite the first element, the side surface of the second element, and the side surface opposite the second element intersect the plane, The first element region is provided along the side surface of the first element, The region facing the first element is provided along the side surface facing the first element, The second element region is provided along the side surface of the second element, The region facing the second element is provided along the side surface facing the second element, The first element region is connectable to the first conductive member, The second element region is an electronic circuit according to any one of configurations 1 to 14, which can be coupled with the second conductive member.
[0104] (Composition 19) The electronic circuit described in one of configurations 1 to 18, The second substrate and, A control unit provided on the second substrate, Equipped with, A computing device wherein at least a portion of the second substrate overlaps with the first substrate.
[0105] (Composition 20) The electronic circuit described in configuration 11, Control unit and Equipped with, The control unit is a computing device capable of supplying a signal to the fourth conductive member.
[0106] According to the embodiment, an electronic circuit and a computing device capable of improving characteristics can be provided.
[0107] Embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configurations of each element such as nonlinear elements, Josephson junctions, substrates, conductive members, and control units included in electronic circuits or computing devices are included within the scope of the present invention as long as those skilled in the art can appropriately select from the known scope to implement the present invention in a similar manner and obtain similar effects.
[0108] Combinations of two or more elements from each example, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.
[0109] All electronic circuits and computing devices that a person skilled in the art can design and implement based on the electronic circuits and computing devices described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.
[0110] Within the scope of the concept of this invention, a person skilled in the art would be able to conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of this invention.
[0111] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]
[0112] 10A~10D, 10X, 10Y: First structure, 11C~14C: First to fourth conductive members, 11c, 12c: First and second connection regions, 11d, 12d: First and second recesses, 11s~14s: First to fourth regions, 11sL, 12sL: First and second region lengths, 13sA: Third other region, 13sAL: Third other region length, 13sL: Third region length, 14f: Control conductive film, 20a, 20b: First and second element portions, 21, 22: First and second Josephson junctions, 23: Intermediate Josephson junction, 21i~23i: Insulating layer, 41, 42: First and second element capacitors, 41h~44h: First to fourth intermediate holes, 41s~44s: 1st to 4th element regions, 41sA~44sA: 1st to 4th element opposing regions, 50A, 50B: 1st and 2nd element structures, 50C: 1st nonlinear element, 50r: loop, 51, 52: 1st and 2nd element Josephson junctions, 51G: conductive layer, 52f: 2nd surface conductive film, 61: control conductive member, 70: control unit, 81a, 81b: 1st and 2nd surfaces, 81s, 82s: 1st and 2nd substrates, 82c, 82d: 3rd and 4th surfaces, 110~114: electronic circuit, 210: computing device, C1~C5: 1st to 5th capacitors, CC1, CC2: 1st substrate conductive film, 2nd substrate conductive film, CM: connecting member, CP1: coupler control line, CPE: coupler control electrode, CQ1: Qubit control line, CQE: Qubit control electrode, D1, D2: First and second directions, PA1, PA2, PB1~PB4, QA1, QA2, QB1~QB4: Pad section, RO1: Readout resonator, ROE: Readout resonator electrode, SP: Space, h1~h3: First to third holes, s1~s4: First to fourth sides, s41, s42: First and second element sides, sA3: Third other side, sA41, sA42: First and second element opposing sides
Claims
1. First substrate and, The first structure and Equipped with, The first substrate includes a first surface, a first side surface, a second side surface, a third side surface and a third other side surface, The first side, the second side, the third side, and the third other side intersect with the plane along the first surface. The first structure includes a first nonlinear element, a first conductive member, a second conductive member, and a third conductive member. The first nonlinear element includes a first element portion, a second element portion, and an intermediate Josephson junction provided between the first element portion and the second element portion. The first conductive member includes a first region and a first connection region, the first region being provided along the first side surface, a portion of the first connection region being electrically connected to the first region, and another portion of the first connection region being electrically connected to the first element portion. The second conductive member includes a second region and a second connection region, the second region being provided along the second side surface, a portion of the second connection region being electrically connected to the second region, and another portion of the second connection region being electrically connected to the second element portion. The third conductive member includes a third region and a third other region, the third region is provided along the third side surface, the third other region is provided along the third other side surface, the direction from the first region to the third region is along the plane, and the direction from the second region to the third other region is along the plane, in an electronic circuit.
2. The length of the third region in the first direction is longer than the length of the first region in the first direction of the first region. The first direction is perpendicular to the first plane, The electronic circuit according to claim 1, wherein the length of the third other region in the first direction is longer than the length of the second region in the first direction of the second region.
3. The first substrate further includes a second surface, The direction from the second surface to the first surface is along the first direction, The electronic circuit according to claim 2, wherein the first substrate includes a first recess including the first side surface and a second recess including the second side surface.
4. The first substrate includes a first hole connected to the first surface and the second surface, The third side surface is part of the first hole, The electronic circuit according to claim 3, wherein the third other side surface is another part of the first hole.
5. The first structure further includes a second surface conductive film provided along the second surface, The electronic circuit according to claim 3, wherein the third conductive member is electrically connected to the second surface conductive film.
6. The first nonlinear element further includes a first Josephson junction and a second Josephson junction, One end of the first Josephson junction is electrically connected to the first element portion. The other end of the first Josephson junction is electrically connected to the third region. One end of the second Josephson junction is electrically connected to the second element portion. The electronic circuit according to any one of claims 1 to 5, wherein the other end of the second Josephson junction is electrically connected to the third other region.
7. The first structure further includes a fourth conductive member including a fourth region, The first substrate further includes a fourth side surface, The fourth side intersects the plane, The fourth region is provided along the fourth side surface, the electronic circuit according to claim 1.
8. The fourth lateral position of the fourth region in the second direction from the second region to the first region is located between the first lateral position of the first region in the second direction and the second lateral position of the second region in the second direction. The third lateral position of the third region in the second direction is located between the fourth lateral position and the first lateral position. The electronic circuit according to claim 7, wherein the third other side position of the third other region in the second direction is located between the fourth side position and the second side position.
9. Further comprising the first element structure, The first element structure is The first element Josephson junction and The first element region connected to the first element Josephson junction, A second element region connected to the first element Josephson junction, The region opposite the first element, The region opposite the second element, Includes, The first substrate further includes a first element side surface, a second element side surface, a first element opposing side surface, and a second element opposing side surface. The side surface of the first element, the side surface of the second element, the side surface opposite the first element, and the side surface opposite the second element intersect the plane, The first element region is provided along the side surface of the first element, The second element region is provided along the side surface of the second element, The region facing the first element is provided along the side surface facing the first element, The region facing the second element is provided along the side surface facing the second element, Multiple first structures are provided, The first element-facing region is electrically connected to the third region included in one of the plurality of first structures. The second element-facing region is electrically connected to the third region which is included in another one of the plurality of first structures. The first element region is connectable to one of the first conductive member and the second conductive member included in one of the plurality of first structures. The electronic circuit according to claim 1, wherein the second element region is connectable to one of the first conductive member and the second conductive member included in the other one of the plurality of first structures.
10. The first instability structure and The second element structure, Furthermore, The first element structure is The first element Josephson junction and The first element region connected to the first element Josephson junction, The region opposite the first element, Includes, The second element structure is The second element Josephson junction, The second element region connected to the aforementioned second element Josephson junction, The region opposite the second element, Includes, The first substrate further includes a side surface of the first element, a side surface facing the first element, a side surface of the second element, and a side surface facing the second element. The side surface of the first element, the side surface opposite the first element, the side surface of the second element, and the side surface opposite the second element intersect the plane, The first element region is provided along the side surface of the first element, The region facing the first element is provided along the side surface facing the first element, The second element region is provided along the side surface of the second element, The region facing the second element is provided along the side surface facing the second element, The first element region is connectable to the first conductive member, The electronic circuit according to claim 1, wherein the second element region is connectable to the second conductive member.
11. The electronic circuit described in claim 1, The second substrate and, A control unit provided on the second substrate, Equipped with, A computing device wherein at least a portion of the second substrate overlaps with the first substrate.