High-speed tag disabling circuit

Abstract

A system and method for efficiently resetting data stored in a memory array is described. In various embodiments, an integrated circuit includes a memory for storing data and a processing unit for generating access requests for the data stored in the memory. When an access circuit of the memory array initiates a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value below the threshold voltage of the transistor. Thus, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuit provides reset data on the write bit lines and asserts each of the write word lines of the memory array. To complete the write operation, the access circuit returns the power supply voltage level from below the threshold voltage level to the operating voltage level.

Description

Background Art

[0001] (Description of Related Art) Generally, various semiconductor chips use a memory for storing data and a processing unit for generating an access request for the data stored in the memory. The memory includes a memory array of many bit cells and an access circuit used to access the values stored in the array. An example of a memory array is the tag array of a cache at any one of the multiple levels of a cache memory subsystem. In a semiconductor chip having a plurality of processing units, the demand for the memory increases. A larger amount of memory provides both sufficient storage for each processing unit and more sharing of information across the plurality of processing units. In some designs, the processing unit and the memory are on the same die, such as a system-on-a-chip (SOC). In other designs, the processing unit and the memory are on different dies within the same package, such as a system-on-a-package (SIP).

[0002] Static Random Access Memory (SRAM) is commonly used for the memory array. The memory array is sometimes reset to balance performance and power consumption. Examples of resetting the memory array include invalidating the cache during the transition from the sleep state to the active state, invalidating the cache to push new content to the client, invalidating the cache to change the cache size, etc. Resetting the memory array quickly improves performance. However, when updating a large number of entries simultaneously, the size of the write driver of the access circuit increases significantly. Therefore, there are costs associated with increased power consumption and increased on-die area.

[0003] In view of the above, an efficient method and system for efficiently resetting the data stored in the memory array are desired. [Brief explanation of the drawing]

[0004] [Figure 1] This is a generalized diagram of a memory bit cell. [Figure 2] This is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 3] This is a generalized diagram of a memory array access circuit. [Figure 4] This is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 5] This is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 6] This is a generalized diagram of a memory bank. [Figure 7] This is a generalized diagram of a method for efficiently resetting data stored in a memory array. [Figure 8] This is a generalized diagram of a computing system. [Modes for carrying out the invention]

[0005] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0006] The following description includes numerous specific details to provide a full understanding of the invention. However, those skilled in the art should recognize that the invention can be carried out without these specific details. In some examples, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the invention. Furthermore, for the sake of simplicity and clarity of explanation, it should be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to others.

[0007] A system and method for efficiently resetting data stored in a memory array is contemplated. In various embodiments, the integrated circuit includes a memory for storing data and a processing unit that generates access requests to the data stored in the memory. The memory includes a memory array of many bit cells and an access circuit used to access the values ​​stored in the array. In various embodiments, the memory array is implemented in SRAM. An example of a memory array is a tag array of one of several levels of cache in a cache memory subsystem. The memory array (or array) utilizes memory bit cells arranged as multiple rows and multiple columns.

[0008] Prior to a reset operation, the memory array access circuit generates a power reference voltage level for the array over the power connection used by the memory bit cells in any of the multiple columns. In various embodiments, the p-type devices (transistors) of the back-to-back inverter of the SRAM bit cells receive the power reference voltage level. However, when the access circuit receives an indicator for a reset operation, the access circuit generates a voltage level over the power connection that is below the threshold voltage of the transistors used within the memory bit cells. Thus, the p-type devices are turned off and do not conflict with the write driver during a write operation. In some embodiments, the access circuit generates a ground reference voltage level over the power connection.

[0009] The access circuit also generates a reset value on the write data line. In one embodiment, the reset data value indicates an invalid cache line. When the power connection is updated and write data is provided to the write bit line, the access circuit asserts each of the write word lines of the memory array. Thus, with respect to a particular column of the memory array, each of the multiple rows simultaneously stores the updated data with the reset value on the write data line. In some embodiments, the access circuit simultaneously asserts each of the write word lines corresponding to each of the multiple rows of the memory array. In another embodiment, the access circuit asserts multiple write word lines in stages to reduce voltage droop caused by simultaneous switching of the wide bus. Similarly, if the memory array uses multiple column selection lines, in one embodiment, the access circuit asserts multiple column selection lines simultaneously. In another embodiment, the access circuit asserts multiple column selection lines in stages.

[0010] When the write word line and any column selection line are asserted, the write operation is initiated by the pass gate and n-type device within the SRAM bit cell. However, the write operation does not complete while the p-type device remains disabled. The bit cell's power supply voltage level returns from a reset value, which is below the device threshold voltage level, to an operating value, which is above the device threshold voltage level. The write operation can be completed without the p-type device conflicting with the access circuit's write driver. Therefore, both the latency and power consumption of the write operation during reset are reduced. Once the write operation is complete and the reset operation is finished, the access circuit reverses the above steps to prepare the memory array for access requests generated from the processing unit.

[0011] Referring to Figure 1, a generalized diagram of the memory bit cell 100 is shown. As shown, data storage is provided by the memory bit cell 100, which uses a variation of a six-transistor (6T) static random access memory (SRAM) cell. In other embodiments, a different RAM cell from various types of RAM cells is used. In various embodiments, the memory bit cell 100 is copied many times and arranged in a row and column array for memory. The memory also includes an access circuit, which is not shown here for the sake of clarity. However, a further explanation of the access circuit is provided in the explanation directed to the access circuit 300 (in Figure 3) and the memory bank 600 (in Figure 6). The access circuit uses several components to generate voltage levels on word lines 114, data lines 116 and 118, and the power supply voltage reference VDD 140. Examples of these components are a row decoder, a column decoder, a sense amplifier, and a latch for storing read and write data.

[0012] The memory bit cell 100 utilizes both p-type and n-type MOSFETs (metal-oxide-semiconductor field-effect transistors). As used herein, MOSFETs are also referred to as transistors and devices. The terms “transistor” and “device” are used interchangeably in the following description. An n-type transistor or n-type device is an NMOSFET. Similarly, a p-type transistor or p-type device is a PMOSFET. As used herein, a Boolean logic high level is also referred to as a logic high level. Similarly, a Boolean logic low level is also referred to as a logic low level. In various embodiments, the logic high level is equal to the power reference level, and the logic low level is equal to the ground reference level. As used herein, a circuit node or line is “asserted” if it stores a voltage level that enables a transistor receiving a voltage level, or if that voltage level indicates that operation is enabled. For example, an n-type transistor is enabled if it receives a positive non-zero voltage level on its gate terminal that is at least a threshold voltage above the voltage level on its source terminal.

[0013] As used herein, a circuit node or line is “negated” if it stores a voltage level that disables a transistor receiving that voltage level. An n-type transistor is disabled if it receives a voltage level at its gate terminal that is at least a threshold voltage below the voltage level at its source terminal. Similarly, a p-type transistor is enabled if it receives a voltage level at its gate terminal that is at least a threshold voltage below the voltage level at its source terminal. A p-type transistor is negated if it receives a voltage level at its gate terminal that is at least a threshold voltage above the voltage level at its source terminal.

[0014] The memory bit cell 100 (or bit cell 100) uses a latch element implemented by p-type transistors 102-104 and n-type transistors 106-108. The bit cell 100 also uses a pass gate implemented by n-type transistors 110 and 112. When the pass gates 110 and 112 are enabled by the word line input 114, the latch element accesses the data bit lines 116 and 118. When the transistors 102-108 of the latch element resolve the voltage levels (data values) on the drain terminals, output nodes 120 and 122, the transistors 102-108 consume no power other than leakage current power.

[0015] Data stored by the latching transistors 102-108 is gate-controlled from bit lines 116 and 118 by n-type transistors 110 and 112. The n-type transistors 110 and 112 continue to block stored data from bit lines 116 and 118 until the word line input 114 is enabled by an external access circuit. The external access circuit also precharges bit lines 116 and 118. The latching transistors 102-108 amplify any voltage difference detected between the differential voltages on bit lines 116 and 118, decomposing these voltages into full-swing voltage values. Bit lines 116 and 118 are routed across each column of the array. In some embodiments, bit lines 116 and 118 are also inputs to a sense amplifier (not shown) and a readout latch (not shown). In other embodiments, bit lines 116 and 118 are inputs to dynamic logic.

[0016] Word line 114 is used to enable n-type transistors 110 and 112 (pass gates 110 and 112). Word line 114 is also connected to other 6T RAM cells in the corresponding row of the array and other bit cells. Typically, a row decoder (not shown) asserts a single word line from among multiple word lines at a time. For example, a row decoder receives address information used to identify a single row from among multiple rows of an array. Once identified, the row decoder asserts the corresponding single word line from among multiple word lines. If the address information indicates that word line 114 is the selected word line to be asserted, n-type transistors 110 and 112 in each 6T RAM cell in the row are enabled, providing access to bit lines 116 and 118 to the latching transistors 102-108. However, during a reset operation, multiple word lines are asserted simultaneously. Further details of the reset operation are briefly provided in the following description.

[0017] In read access operation, an external sense amplifier is enabled, an external read latch is enabled, and an external precharge transistor is disabled. Thus, the latching transistors 102-108 can decompose the differential voltage on bit lines 116 and 118 into the total voltage swing value. In write access operation, the column decoder selects a column of the array and, in addition to disabling the external precharge signal, drives voltage levels on bit lines 116 and 118 routed across the entire selected column. Although the memory bit cell 100 is shown as a single-port cell, in other embodiments, the memory bit cell 100 uses a multi-port design to provide parallel access operation for improved performance.

[0018] There are various reasons for resetting a memory array that uses bit cell 100. In some designs, the memory array is a tag array of caches at one of several levels of a cache memory subsystem. Examples of reasons for performing a reset include invalidating the cache during a transition from sleep to active state, invalidating the cache to push new content to a client, invalidating the cache to change the cache size, etc. Prior to the reset operation, the external access circuit generates a power reference voltage VDD140 as a positive non-zero voltage level greater than the transistor threshold voltage level. In various embodiments, each bit cell in at least one of the multiple columns of the array shares VDD140. Bit cell 100 is included in this column. However, when the access circuit receives an indicator for a reset operation, the access circuit generates a voltage level on VDD140 that is less than the transistor threshold voltage level. In some embodiments, the access circuit generates a ground reference voltage level on VDD140, such as VSS 130. Thus, p-type devices 102 and 104 are disabled. By being disabled, the p-type devices 102 and 104 do not conflict with the external write driver during subsequent write operations. In various embodiments, each bit cell in at least one of a plurality of columns containing bit cell 100 has a similar disabled p-type device.

[0019] When the access circuit provides a voltage level on VDD140 that turns off p-type devices 102 and 104, and additionally provides write data on bit lines 116 and 118, the access circuit asserts word line 114 along with each of the other word lines of the multiple rows of the memory array. Once each of the write word lines of the memory array, such as word line 114, is asserted, the write operation begins. For example, the pass gates 110 and 112 of bit cell 10 are enabled. The write operation has begun but does not complete while p-type devices 102 and 104 remain disabled. Later, the access circuit returns VDD140 from a voltage level below the transistor threshold voltage to a voltage level above the transistor threshold voltage. The write operation can be completed without the p-type devices 102 and 104 conflicting with the access circuit's external write driver. In various embodiments, each bit cell in at least one of the multiple columns containing bit cell 100 simultaneously completes the write operation without conflict from the p-type devices. Therefore, both the latency and power consumption of write operations during reset are reduced. Once the write operation is complete and the reset operation is finished, the access circuit reverses the above steps to prepare the memory array for access requests generated by the processing unit.

[0020] Referring to Figure 2, a generalized diagram of method 200 for efficiently resetting data stored in a memory array is shown. For illustrative purposes, the steps in this embodiment (as well as in Figures 4-5 and 7) are shown in order. However, in other embodiments, some steps occur in a different order than those shown, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0021] An array of memory bit cells stores data, and the array is arranged as a plurality of rows and columns (block 202). In various embodiments, the value of the stored data is maintained by a data storage loop within the memory bit cell. Further, the value of the stored data is updated by a write operation. In some embodiments, the memory bit cell includes a pass gate and a feedback inverter (and a feedback tri-state inverter) to implement the data storage loop and to enable updating of the stored value during a write operation. For example, each bit cell uses a variation of a 6 transistor (6T) static random access memory (SRAM) cell. In some embodiments, the memory bit cell uses the pass gate and the feedback inverter of the memory bit cell 100 (of FIG. 1).

[0022] If the memory array access circuit (or access circuit) determines that no reset request has been received (condition block 204: "no"), the control flow of method 200 returns to block 202, where the array continues to store data. However, if the access circuit determines that a reset request has been received (condition block 204: "yes"), the access circuit generates a voltage level that is less than the threshold voltage of the transistors on the power connection used by the memory bit cells of the columns of the array (block 206). By doing so, the p-type devices within the bit cells are disabled.

[0023] The access circuit generates reset data on the write data line (block 208). In one embodiment, the reset data includes invalid bits used to invalidate cache lines. Subsequently, the access circuit asserts the write word lines of each row of the array (block 210). Typically, the access circuit asserts a single write word line during a write operation and continues to provide a voltage level greater than the transistor threshold voltage level on the power connection of the bit cell. However, in the case of a reset operation, the access circuit asserts each write word line during the write operation and provides a voltage level less than the transistor threshold voltage level on the power connection of the bit cell.

[0024] When each of the write word lines of the memory array is asserted, the write operation begins. For example, the pass gates of each bit cell within a particular column are enabled. The write operation does not complete while the p-type devices of the bit cells remain disabled after the write operation has been initiated. Later, the access circuit returns the voltage level on the power connection of the bit cell from a voltage level less than the transistor threshold voltage to a voltage level greater than the transistor threshold voltage (block 212). The write operation can complete without the p-type devices of the bit cells competing with the external write driver of the access circuit. Thus, both the latency and power consumption of the write operation during reset are reduced. When the write operation is complete and the reset operation has ended, the access circuit reverses the above steps to prepare the memory array for an access request generated from the processing unit. For example, the access circuit negates the write word lines of each row of the array (block 214).

[0025] Next, referring to Figure 3, a generalized block diagram of the memory array access circuit 300 is shown. As shown, the memory array access circuit 300 (or access circuit 300) includes a word line decoder 310 and a number of Boolean composite gates 320, 340, 360-362. In some embodiments, the entire external memory array uses the output signals of the access circuit 300. In other embodiments, the memory is divided into multiple memory banks, and a specific memory bank uses the output signals of the access circuit 300.

[0026] The access circuit receives a value asserted on the control signal collapse 330 when a reset operation is being performed. In one embodiment, the collapse signal 330 is used to generate a voltage level below the transistor threshold voltage used by the p-type device of the memory bit cell. In some embodiments, this voltage level is a ground reference voltage level. For example, in one embodiment, when a reset operation is initiated, the collapse signal 330 is asserted with a Boolean high, and the inverter 380 generates a local VDD signal 382 as a Boolean low. The local VDD signal 382 is transmitted to the p-type device of each memory bit cell in a particular column of the memory array.

[0027] The word line decoder 310 receives word line predecode signals 302-304. The number of signals 302-304 is equal to the number of rows in the memory array or memory bank using the access circuit 300. During a typical write operation, the write request address is used to determine which row in the memory array (or memory bank) is selected. One of the word line predecode signals 302-304 is asserted based on the write request address. The word line decoder 310 also receives a word line (WL) clock signal 326 generated by the Boolean composite gate 320 (or gate 320).

[0028] Gate 320 receives a clock signal 322 and an enable signal. In some embodiments, the enable signal 324 indicates that a particular memory bank is being written to. Gate 320 also receives a collapse signal 330. Therefore, based on gate 320 and its Boolean OR function, during a reset operation, the collapse signal 330 overrides the clock signal 332 and the enable signal 324. In one embodiment, during a reset operation, an external predecoder asserts each of the word line predecode signals 302-304. Therefore, the collapse signal 330 causes the WL clock signal 326 to be asserted, resulting in each of the word lines 312-314 being asserted. In another embodiment, the word line decoder 310 directly receives the collapse signal 330, and as a result, when the collapse signal 330 is asserted, the word line decoder 310 asserts each of the word lines 312-314.

[0029] A Boolean composite gate 340 (or gate 340) and inverter 344 generate a BLPCX signal 350, which is used as a bit line precharge signal by the p-type devices of the memory array. These external p-type devices perform precharge operations on the bit lines of a particular column of the memory array. Gate 340 receives a bit line precharge signal 342 from the preceding stage of the control circuit that determines when to enable and disable precharge for write operations. However, the Boolean logic of gate 340 allows a collapse signal 330 to override this bit line precharge signal 342. When the collapse signal 330 is asserted at a high Boolean level, inverter 344 generates a BLPCX signal 350 as a high Boolean level, which disables the p-type devices of the bit line precharge circuit for a particular column of the memory array.

[0030] Boolean composite gates 360-362 are duplicates of the same composite gate. The access circuit 300 includes the same number of Boolean composite gates 360-362 (or composite gates 360-362) as the number of columns used for the same type of data stored in the memory array. For example, instead of using 1024 rows, the memory array uses 256 rows with data arranged horizontally so that 4 columns are used. Thus, 4 columns of selection lines are used. Such an arrangement reduces the capacitive load on the bit lines. Furthermore, multiple columns of the memory array can share a single write driver and a single sense amplifier of the memory array.

[0031] In one embodiment, composite gate 360 ​​receives a clock signal 322, an enable signal 324, a write enable signal 352, and a write column decoding signal 354, which is the output of a decoder that selects which of a plurality of columns is being updated. Gate 362 receives the same input signals. However, during a reset operation, an asserted collapse signal 330 causes each of gates 360-362 to bypass these other input signals and generate asserted values ​​for output signals WRCS370-372. These output signals WRCS370-372 are used by an external memory array as write column selection lines.

[0032] Next, referring to Figure 4, a generalized diagram of method 400 for efficiently resetting data stored in a memory array is shown. The access circuit initiates the reset of an array of memory bit cells arranged as multiple rows and multiple columns (block 402). In a first clock cycle, the access circuit asserts the write word line for each row of the first portion of the multiple rows (block 404). In various embodiments, the access circuit has already performed the aforementioned steps directed to blocks 206 and 208 of method 200 (in Figure 2). For example, the access circuit has already reduced the voltage level received by the p-type device of the bit cells in a particular column of the memory array. For example, the access circuit reduces this voltage level to below the transistor threshold voltage level. Additionally, the access circuit has already generated reset data on the write bit line.

[0033] The access circuit asserts the write word lines for each row of the second portion of the multiple rows in a second clock cycle following the first clock cycle (block 406). Thus, the access circuit asserts the write word lines in stages to reduce the voltage droop caused by the simultaneous switching of the wide bus. The voltage droop is proportional to the equation L di / dt, where L is the parasitic inductance and di / dt is the rate of change of current consumption over time. In one embodiment, the access circuit divides the memory array into two parts and asserts half of the total number of word lines in a first clock cycle and the remaining half of the total number of word lines in a second clock cycle. In such an embodiment, the access circuit uses two clock cycles to assert each of the word lines of the memory array during a reset operation. The access circuit writes the reset data to each memory bit cell in the column (block 408). For example, the access circuit performs the aforementioned steps directed to blocks 210-214 of method 200 (in Figure 2).

[0034] In another embodiment, the access circuit asserts one-quarter of the total number of word lines in a first clock cycle and another quarter of the total number of word lines in a second clock cycle. In such an embodiment, the access circuit uses four clock cycles to assert each of the word lines of the memory array during a reset operation. However, using a conventional mechanism for performing a reset operation, the access circuit updates one row per clock cycle. For example, conventional mechanisms did not reduce the power supply voltage used by the p-type device of the bit cell. Therefore, the p-type device competes with the write driver during a write operation while resetting. Updating a large number of rows simultaneously significantly increases the size of the write driver in the access circuit. Thus, there are costs associated with increased power consumption and increased on-die area. Therefore, conventional mechanisms updated one row per clock cycle. For a memory array with 1024 entries, the reset operation requires 1024 clock cycles. However, using the steps described in at least methods 200 and 400 (Figures 200 and 400), the reset operation requires only 2, 4, or 8 clock cycles. The latency and on-die area of ​​components such as the writing driver are reduced.

[0035] Next, referring to Figure 5, a generalized diagram of method 500 for efficiently resetting data stored in multiple memory bit cells within a column of a memory array is shown. The access circuit initiates the reset of the array of memory bit cells arranged as multiple rows and multiple columns (block 502). The access circuit asserts two or more column select lines (block 504). As previously described, in some designs, instead of using 1024 rows, the memory array uses 256 rows with data arranged horizontally so that 4 columns are used. Thus, 4 column select lines are used. Such an arrangement reduces the capacitive load on the bit lines. Furthermore, multiple columns of a memory array can share a single write driver and a single sense amplifier of the memory array. In such designs, typically, a single column select line is asserted during a write operation. However, here, two or more select lines are asserted during a reset operation. In some embodiments, each of the multiple column select lines is asserted.

[0036] The access circuit disables the precharge of the write bit lines for two or more columns of a plurality of columns (block 506). Furthermore, the access circuit disables the precharge of the bit lines of two or more columns corresponding to the complementary values ​​of the write bit lines of two or more columns. Typically, a single bit line of a single column and its single corresponding complementary bit line have their precharge circuits disabled during the write operation in order to place the write data on these two bit lines of the single column. However, here, the bit lines of two or more columns have corresponding precharge circuits that are disabled during the reset operation in order to place the write data on these bit lines of two or more columns. In some embodiments, the two or more columns include each column of the plurality of columns. The access circuit writes reset data to each memory bit cell of the two or more columns with the corresponding column selection asserted (block 508). In various embodiments, the access circuit performs the aforementioned steps directed to blocks 210-214 of method 200 (in Figure 2) for two or more columns of a plurality of columns.

[0037] Next, referring to Figure 6, a generalized block diagram of memory bank 600 is shown. In various embodiments, the memory is organized into multiple memory banks, and the memory macroblock includes both the left and right banks. In some embodiments, bank 600 is either the left or right bank of the memory macroblock. While “left” and “right” are used to describe the memory banks, other notations such as “upper bank” and “lower bank” may be used. As illustrated, memory bank 600 includes arrays 610A-610B, row decoders 620A-620B, sense amplifiers 630A-630B between arrays 610A-610B, read and write timing control logic 640A-640B, and read and write latches in block 650. Note that in some embodiments, multiple banks are accessed simultaneously in the same clock cycle or the same pipeline stage. Access includes either read access or write access. In such embodiments, a bank address decoder selects the corresponding bank to access.

[0038] In various embodiments, each of the blocks 610A-610B, 620A-620B, 630A-630B, 640A-640B, and 650 within the memory bank 600 is communicatively coupled to another block within the same block. For example, direct connections are used where routing is performed via another block. Alternatively, signal staging is performed in an intermediate block. In various embodiments, each of the arrays 610A-610B includes a plurality of memory bit cells 660 arranged in a tiled form. In various embodiments, the bit cell 660 includes the circuit of bit cell 100 (in Figure 1). Here, rows are aligned vertically, etc., in the illustrated embodiment, with tracks used for routing the word lines of the array. Columns are aligned horizontally, etc., in the illustrated embodiment, with tracks used for routing the bit lines of the array.

[0039] The row decoders and word line drivers in blocks 620A to 620B receive address information corresponding to an access request. For example, each of blocks 620A to 620B receives information provided by the access request address 670. Each of blocks 620A to 620B selects a specific row or entry from among multiple rows in the relevant array of arrays 620A to 620B. In some embodiments, blocks 620A to 620B use the index portion of address 670 to select a given row or entry in the relevant array of arrays 620A to 620B. Each row or entry stores one or more memory lines.

[0040] In the illustrated embodiment, rows or entries in arrays 620A-620B are arranged vertically. However, in other embodiments, horizontal orientation is used for memory line storage. For a write access request, a write latch is located in block 650. The write data is driven into arrays 610A-610B. Timing control circuits 640A-640B update the write latch with new data and set up the write word line driver logic in block 650. The write data is written to a row of bit cells selected by the relevant block from blocks 620A-620B. In some embodiments, a precharge circuit is included in block 650.

[0041] In the case of a read access request, block 650 is used to precharge the read bit lines routed to arrays 610A-610B. Timing circuits in blocks 640A-640B are used to precharge and set up the sense amplifiers in blocks 630A-630B. Timing circuits 640A-640B set up the read word line driver logic. One of the row decoders 620A-620B selects the row from which to read data, and this data is provided on the read bit lines sensed by the sense amplifier. A read latch captures the read data.

[0042] In various embodiments, the row decoders and word line drivers 620A-620B and the column selection control circuit in any of blocks 630A-630B and 650 utilize the functionality of the access circuit 300 (Figure 3) to perform the steps described above with respect to the bit cell 100 (Figure 1) and the access circuit 300 (Figure 3). In other words, the access circuit shown surrounding arrays 610A-610B utilizes the collapse control signal asserted during the reset operation. Thus, the access circuit shown surrounding arrays 610A-610B can generate a power supply voltage level below the transistor threshold voltage and send it to the power connections of each bit cell in a particular column. Additionally, the access circuit shown surrounding arrays 610A-610B can assert each of the word lines during the reset operation. Furthermore, this access circuit of memory bank 600 can assert multiple word lines in groups over multiple clock cycles. Therefore, this access circuit in memory bank 600 allows the p-type device of the bit cell to complete the reset operation without conflicting with the write driver. Power consumption is reduced, and the on-die area of ​​the word driver is also reduced.

[0043] Next, referring to Figure 7, a generalized diagram of method 700 for efficiently resetting data stored in a memory array is shown. The access circuit performs a reset of the array of memory bit cells arranged as multiple rows and multiple columns (block 702). If the access circuit determines that the requested reset write operation is not yet complete (condition block 704: "no"), the control flow of method 700 returns to block 702, where the reset operation continues. However, if the access circuit determines that the requested reset write operation is complete (condition block 704: "yes"), the access circuit negates the write word lines for each row of the first portion of the multiple rows in the first clock cycle (block 706).

[0044] The access circuit negates the write word lines for each row in the second portion of the multiple rows during the second clock cycle following the first clock cycle (block 708). The access circuit negates the column selection lines for two or more columns out of the multiple columns (block 710). The access circuit enables precharging of the write bit lines for two or more columns out of the multiple columns (block 712).

[0045] Referring to Figure 8, one embodiment of the computing system 800 is shown. The computing system 800 includes a processor 810 and memory 830. Interfaces such as the memory controller, bus or communication fabric, one or more phased locked loops (PLLs) and other clock generation circuits, and power management units are not shown for the sake of clarity. In other embodiments, it is understood that the computing system 800 includes one or more other processors of the same or different type as the processor 810, one or more peripheral devices, network interfaces, one or more other memory devices, etc. In some embodiments, the functions of the computing system 800 are integrated on a system on a chip (SoC). In other embodiments, the functions of the computing system 800 are integrated on a peripheral card inserted into a motherboard. The computing system 800 is used in any of various computing devices such as server computers, desktop computers, tablet computers, laptops, smartphones, smartwatches, game consoles, and personal assistant devices.

[0046] The processor 810 includes hardware such as circuits. For example, the processor 810 includes at least one integrated circuit 820 used by the high-speed reset array 822. The integrated circuit 820 uses the high-speed reset array 822 for data storage of various types of data. In various embodiments, the high-speed reset array 822 uses memory bit cells arranged as multiple rows and columns. One or more of the processor 810 and the integrated circuit 820 use the high-speed reset array as a cache at a specific level of multiple levels of the cache memory subsystem. In some embodiments, the high-speed reset array 822 uses one or more of the circuits described above for the bit cell 100 (Figure 1), the access circuit 300 (Figure 3), and the memory bank 600 (Figure 6).

[0047] In various embodiments, the processor 810 includes one or more processing units. In some embodiments, each processing unit includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 810 is a central processing unit (CPU). In another embodiment, the processing cores are compute units, and each compute unit has a highly parallel data microarchitecture having multiple parallel execution lanes and associated data storage buffers. In such embodiments, the processor 810 is a graphics processing unit (GPU), a digital signal processor (DSP), etc.

[0048] In some embodiments, memory 830 includes one or more of the following: a hard disk drive, a solid-state disk, other types of flash memory, a portable solid-state drive, and a tape drive. Memory 830 stores an operating system (OS) 832, one or more applications represented by code 834, and at least source data 836. Memory 830 can also store intermediate and final result data generated by the processor 810 when executing a particular application of code 834. Although a single instance of the operating system 832 and the code 834 and source data 836 are shown, in other embodiments, a different number of these software components are stored in memory 830. The operating system 832 includes instructions for starting the boot-up of the processor 810, assigning tasks to hardware circuits, managing the resources of the computing system 800, and hosting one or more virtual environments.

[0049] Each of the processor 810 and memory 830, like any other hardware components included in the computing system 800, includes an interface unit for communicating with each other. The interface unit includes a queue for handling memory requests and memory responses, and a control circuit for communicating with each other based on a specific communication protocol. The communication protocol determines various parameters such as power performance status which determines the supply voltage level, operating supply voltage and operating clock frequency, data rate, and one or more burst modes.

[0050] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions implementing the method and / or mechanism are transported or stored on a computer-readable medium. Numerous types of media configured to store program instructions are available, including volatile or non-volatile storage devices in the form of hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (PROMs), and random access memory (RAMs). Generally speaking, computer-accessible storage media include any storage media that is accessible by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media (e.g., disks (fixed or removable), tapes, CD-ROMs, or storage media such as DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Ray®s). Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (SRAM), etc.), ROM, and flash memory, as well as non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as the Universal Serial Bus (USB) interface. Other examples of storage media include microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0051] Additionally, in various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII stream format (GDS II). In some cases, the descriptions are read by a synthesis tool that synthesizes the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware, including the system. The netlist can then be arranged and routed to generate a dataset describing the geometric shapes to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to generate semiconductor circuits or circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Additionally, instructions are used for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0052] Although the embodiments described above are explained in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. It is an integrated circuit, An array of memory bit cells for storing data, arranged as multiple rows and multiple columns, It includes an access circuit, The access circuit responds to a reset request, In the first clock cycle, the write word lines of each row in the first portion of the plurality of rows are asserted, and in the second clock cycle, the write word lines of each row in the second portion of the plurality of rows are asserted, wherein the write word lines of each row in the first portion remain asserted in the second clock cycle. In the second clock cycle, reset data is written to each memory bit cell of any of the multiple columns, It is configured to do the following: Integrated circuit.

2. The access circuit is configured to generate a power reference voltage level on the power supply connection used by the memory bit cells of any of the rows. The integrated circuit according to claim 1.

3. The access circuit is configured to simultaneously assert the write word lines of each row in the first portion of the plurality of rows and the write word lines of each row in the second portion of the plurality of rows in response to receiving the reset request. The integrated circuit according to claim 1.

4. Each of the plurality of rows stores a plurality of memory lines, The access circuit is configured to assert two or more column selection lines of two or more memory lines among the plurality of memory lines. The integrated circuit according to claim 1.

5. The access circuit is configured to generate a predetermined voltage level on the power supply connection that is below the threshold voltage level of the transistor used in the memory bit cell, in response to receiving the reset request. The integrated circuit according to claim 2.

6. The access circuit is configured to generate a voltage level on the power supply connection that is higher than the threshold voltage level of the transistor when each of the write word lines of the plurality of rows is asserted. The integrated circuit according to claim 5.

7. The access circuit is configured to negate the write word lines of the first and second parts respectively when the write operation of writing the reset data to each memory bit cell of any of the columns is completed. The integrated circuit according to claim 1.

8. It is a method, Storing data in an array of memory bit cells arranged as multiple rows and multiple columns, Upon receiving a reset request, The access circuit of the array asserts the write word lines of each row in the first portion of the plurality of rows during the first clock cycle. The access circuit asserts the write word lines of each row in the second portion of the plurality of rows during the second clock cycle, and the write word lines of each row in the first portion remain asserted during the second clock cycle. The access circuit includes writing reset data to each memory bit cell of any of the plurality of columns in the second clock cycle, method.

9. The access circuit includes generating a power reference voltage level on the power supply connection used by the memory bit cells of any of the columns before receiving the reset request. The method of claim 8.

10. The access circuit includes simultaneously asserting the write word lines of each row in the first portion of the plurality of rows and the write word lines of each row in the second portion of the plurality of rows in response to receiving the reset request. The method of claim 8.

11. Storing multiple memory lines in each of the multiple rows, The access circuit includes asserting two or more column selection lines of two or more memory lines among the plurality of memory lines, The method of claim 8.

12. The access circuit, upon receiving the reset request, includes generating a predetermined voltage level on the power supply connection that is below the threshold voltage level of the transistor used in the memory bit cell. The method of claim 9.

13. The method includes generating a voltage level on the power supply connection that is higher than the threshold voltage level of the transistor in response to each of the write word lines of the plurality of rows being asserted. The method according to claim 12.

14. The access circuit includes negating the write word lines of the first portion and the second portion, respectively, in response to the completion of the write operation. The method of claim 8.

15. A computing system, A memory configured to store instructions for one or more tasks and source data processed by the one or more tasks, The system comprises an integrated circuit configured to execute the instruction using the source data, The aforementioned integrated circuit is Access circuit and It comprises an array of memory bit cells for storing data, arranged as multiple rows and multiple columns, The access circuit, upon receiving a reset request, In the first clock cycle, assert the write word lines of each row in the first portion of the plurality of rows, In the second clock cycle, the write word lines of each row in the second portion of the plurality of rows are asserted, and the write word lines of each row in the first portion remain asserted during the second clock cycle. In the second clock cycle, reset data is written to each memory bit cell of any of the multiple columns, It is configured to do the following: Computing system.

16. The access circuit is configured to generate a power reference voltage level for the array on the power connections used by the memory bit cells of any of the columns before receiving the reset request. The computing system according to claim 15.

17. The access circuit is configured to simultaneously assert the write word lines of each row in the first portion of the plurality of rows and the write word lines of each row in the second portion of the plurality of rows in response to receiving the reset request. The computing system according to claim 15.

18. Each of the plurality of rows stores a plurality of memory lines, The access circuit is configured to assert two or more column selection lines of two or more memory lines among the plurality of memory lines. The computing system according to claim 15.

19. The access circuit is configured to generate a predetermined voltage level on the power supply connection that is below the threshold voltage level of the transistor used in the memory bit cell, in response to receiving the reset request. The computing system according to claim 16.

20. The access circuit is configured to generate a voltage level on the power supply connection that is higher than the threshold voltage level of the transistor when each of the write word lines of the plurality of rows is asserted. The computing system according to claim 19.

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