Display panel and display device including the same
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- LG DISPLAY CO LTD
- Filing Date
- 2025-07-16
- Publication Date
- 2026-06-17
Smart Images
Figure 0007875354000001 
Figure 0007875354000002 
Figure 0007875354000003
Abstract
Claims
1. It includes multiple data lines, multiple gate lines, multiple power lines, multiple mode selection lines, and multiple subpixels, Each of the aforementioned subpixels is, First light-emitting element, The second light-emitting element, A first drive unit is configured to receive a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals as inputs and to supply current to the first light-emitting element, A second drive unit is configured to receive the aforementioned pixel drive voltage, second pixel data voltage, and a plurality of gate signals, and to supply current to the second light-emitting element. The system includes a shared switch unit configured to supply the first pixel data voltage to the first drive unit and the second pixel data voltage to the second drive unit, The first drive unit is, A first drive transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, configured to drive the first light-emitting element during a first refresh frame period, A first constant voltage node to which the pixel driving voltage is applied, and a first capacitor connected between the first node, A first switch transistor, connected between the first node and the third node, is turned on in response to the gate high voltage of the first scan signal and turned off in response to the gate low voltage of the first scan signal. A second switch transistor is connected between the first node and a third constant voltage node to which an initialization voltage is applied, and is turned on in response to the gate high voltage of the fourth scan signal and turned off in response to the gate low voltage of the fourth scan signal, and A display panel comprising a third switch transistor, which is connected between the third node and the fourth node, and which is turned on in response to the gate low voltage of the second light-emitting signal and turned off in response to the gate high voltage of the second light-emitting signal.
2. A wide-angle lens superimposed on the light-emitting region of the first light-emitting element, and The display panel according to claim 1, further comprising a narrow-viewing-angle lens superimposed on the light-emitting region of the second light-emitting element.
3. The display panel according to claim 1, wherein the first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second constant voltage node to which a cathode voltage is applied.
4. The second drive unit is, A second drive transistor comprising a gate electrode connected to the fifth node, a first electrode connected to the second or eighth node, and a second electrode connected to the sixth node, configured to drive the second light-emitting element during the second refresh frame period, A second capacitor is connected between the first constant voltage node and the fifth node. A fourth switch transistor is connected between the fifth node and the sixth node, and is turned on in response to the gate high voltage of the fifth scan signal and turned off in response to the gate low voltage of the fifth scan signal. A fifth switch transistor is connected between the fifth node and the third constant voltage node, and is turned on in response to the gate high voltage of the sixth scan signal and turned off in response to the gate low voltage of the sixth scan signal, and The system includes a sixth switch transistor, which is connected between the sixth node and the seventh node, and is turned on in response to the gate low voltage of the third light-emitting signal and turned off in response to the gate high voltage of the third light-emitting signal. The display panel according to claim 3, wherein the second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second constant voltage node.
5. The shared switch section is, A seventh switch transistor is connected between the corresponding data line and the second node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. An eighth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A ninth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. A tenth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes an eleventh switch transistor, which is connected between the seventh node and the fourth constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node. The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. During the first refresh frame period, the first pixel data voltage is applied to the data line, and during the second refresh frame period, the second pixel data voltage is applied to the data line. The display panel according to claim 4, wherein the shared switch unit receives the first pixel data voltage and the second pixel data voltage through a single data line.
6. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the eighth node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor, connected between the second node and the eighth node, is turned on in response to the gate low voltage of the first scan signal and turned off in response to the gate high voltage of the first scan signal. A 12th switch transistor is connected between the 4th node and a 4th constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the 3-2 scan signal and turned off in response to the gate high voltage of the 3-2 scan signal, and The system includes a 13th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. When the first switch transistor is turned off, the eleventh switch transistor is turned on, and when the first switch transistor is turned on, the eleventh switch transistor is turned off. The display panel according to claim 4, wherein the shared switch unit receives the first pixel data voltage and the second pixel data voltage through a single data line.
7. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-second signal, and turned off in response to the gate high voltage of the scan signal of the second-second signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 12th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The display panel according to claim 4, wherein the pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage.
8. The display panel according to claim 6 or 7, further comprising a data switch unit configured to apply the first pixel data voltage to the first data line and the park voltage to the second data line during the first refresh frame period, and to apply the second pixel data voltage to the second data line and the park voltage to the first data line during the second refresh frame period.
9. The aforementioned data switch unit is First and second transistors are connected in series between the first input node and the first data line. Third and fourth transistors are connected in series between the second input node and the first data line. Fifth and sixth transistors are connected in series between the first input node and the second data line, and The system includes seventh and eighth transistors connected in series between the second input node and the second data line, The first and seventh transistors are turned on in accordance with the gate-on voltage of the first selection signal and turned off in accordance with the gate-off voltage of the first selection signal. The third and fifth transistors are turned on in response to the gate-on voltage of the second selection signal and turned off in response to the gate-off voltage of the second selection signal. The second and sixth transistors are turned on in response to the gate-on voltage of the third selection signal and turned off in response to the gate-off voltage of the third selection signal. The display panel according to claim 8, wherein the fourth and eighth transistors are turned on in response to the gate-on voltage of the fourth selection signal and turned off in response to the gate-off voltage of the fourth selection signal.
10. A display panel including multiple data lines, multiple gate lines, multiple power lines, and multiple subpixels. A data drive unit configured to supply data voltage to the data line, and Includes a gate drive unit configured to supply a gate signal to the gate line, Each of the aforementioned subpixels is, First light-emitting element, Second light-emitting element, A first drive unit is configured to receive a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals as inputs and to supply current to the first light-emitting element, A second drive unit is configured to receive the aforementioned pixel drive voltage, second pixel data voltage, and a plurality of gate signals, and to supply current to the second light-emitting element. The system includes a shared switch unit configured to supply the first pixel data voltage to the first drive unit and the second pixel data voltage to the second drive unit, The first drive unit is, A first drive transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, configured to drive the first light-emitting element during a first refresh frame period, A first constant voltage node to which the pixel driving voltage is applied, and a first capacitor connected between the first node, A first switch transistor, connected between the first node and the third node, is turned on in response to the gate high voltage of the first scan signal and turned off in response to the gate low voltage of the first scan signal. A second switch transistor is connected between the first node and a third constant voltage node to which an initialization voltage is applied, and is turned on in response to the gate high voltage of the fourth scan signal and turned off in response to the gate low voltage of the fourth scan signal, and A display device comprising a third switch transistor connected between the third node and the fourth node, which is turned on in response to the gate low voltage of the second light-emitting signal and turned off in response to the gate high voltage of the second light-emitting signal.
11. A wide-angle lens superimposed on the light-emitting region of the first light-emitting element, and The display device according to claim 10, further comprising a narrow-viewing-angle lens superimposed on the light-emitting region of the second light-emitting element.
12. The display device according to claim 11, wherein the first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second constant voltage node to which a cathode voltage is applied.
13. The second drive unit is, A second drive transistor comprising a gate electrode connected to the fifth node, a first electrode connected to the second or eighth node, and a second electrode connected to the sixth node, configured to drive the second light-emitting element during the second refresh frame period, A second capacitor is connected between the first constant voltage node and the fifth node. A fourth switch transistor is connected between the fifth node and the sixth node, and is turned on in response to the gate high voltage of the fifth scan signal and turned off in response to the gate low voltage of the fifth scan signal. A fifth switch transistor is connected between the fifth node and the third constant voltage node, and is turned on in response to the gate high voltage of the sixth scan signal and turned off in response to the gate low voltage of the sixth scan signal, and The system includes a sixth switch transistor, which is connected between the sixth node and the seventh node, and is turned on in response to the gate low voltage of the third light-emitting signal and turned off in response to the gate high voltage of the third light-emitting signal. The display device according to claim 12, wherein the second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second constant voltage node.
14. The shared switch section is, A seventh switch transistor is connected between the data line and the second node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. An eighth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A ninth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. A tenth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes an eleventh switch transistor, which is connected between the seventh node and the fourth constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the third-second node, and turned off in response to the gate high voltage of the scan signal of the third-second node, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. The display device according to claim 13, wherein the first pixel data voltage is applied to the data line during the first refresh frame period, and the second pixel data voltage is applied to the data line during the second refresh frame period.
15. The display device according to claim 14, wherein one or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period in which there is no pixel data update.
16. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the eighth node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor, connected between the second node and the eighth node, is turned on in response to the gate low voltage of the first scan signal and turned off in response to the gate high voltage of the first scan signal. A 12th switch transistor is connected between the 4th node and a 4th constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the 3-2 scan signal and turned off in response to the gate high voltage of the 3-2 scan signal, and The system includes a 13th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. The display device according to claim 13, wherein when the first switch transistor is turned off, the eleventh switch transistor is turned on, and when the first switch transistor is turned on, the eleventh switch transistor is turned off.
17. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-second signal, and turned off in response to the gate high voltage of the scan signal of the second-second signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 12th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The display device according to claim 13, wherein the pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage.
18. The display device according to claim 16 or 17, wherein one or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period in which there is no pixel data update.
19. The display device according to claim 16 or 17, further comprising a data switch unit configured to apply the first pixel data voltage to the first data line and the park voltage to the second data line during the first refresh frame period, and to apply the second pixel data voltage to the second data line and the park voltage to the first data line during the second refresh frame period.
20. The aforementioned data switch unit is First and second transistors are connected in series between the first input node and the first data line. Third and fourth transistors are connected in series between the second input node and the first data line. Fifth and sixth transistors are connected in series between the first input node and the second data line, and The system includes seventh and eighth transistors connected in series between the second input node and the second data line, The first and seventh transistors are turned on in accordance with the gate-on voltage of the first selection signal and turned off in accordance with the gate-off voltage of the first selection signal. The third and fifth transistors are turned on in response to the gate-on voltage of the second selection signal and turned off in response to the gate-off voltage of the second selection signal. The second and sixth transistors are turned on in response to the gate-on voltage of the third selection signal and turned off in response to the gate-off voltage of the third selection signal. The display device according to claim 19, wherein the fourth and eighth transistors are turned on in accordance with the gate-on voltage of the fourth selection signal and turned off in accordance with the gate-off voltage of the fourth selection signal.