Method for manufacturing a semiconductor device and a semiconductor device.
The method addresses miniaturization challenges in semiconductor devices by using controlled ion implantation and polymer masks to narrow contact areas, enhancing device performance through reduced resistance and stable threshold voltage.
JP7877668B2Inactive Publication Date: 2026-06-23FUJI ELECTRIC CO LTD
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- FUJI ELECTRIC CO LTD
- Filing Date
- 2021-12-03
- Publication Date
- 2026-06-23
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
To provide a manufacturing method of a semiconductor device and a semiconductor device capable of miniaturizing a mesa width by narrowing the width of a p+ type contact region.SOLUTION: A second conductivity type first semiconductor region 3, a first conductivity type second semiconductor region 4, a trench 6, a gate insulating film 7, a gate electrode 8, and an interlayer insulating film 13 are formed. Next, a contact hole 9 is formed through the interlayer insulating film 13 to reach the first semiconductor region 3. Using a polymer 17 formed here as a mask, ion implantation 19 is performed to form a second conductivity type third semiconductor region 5 on the surface layer of the first semiconductor region 3 exposed on the bottom surface of the contact hole 9, and after ion implantation 19, the polymer 17 is removed. Next, a second conductivity type fourth semiconductor region, a first electrode, and a second electrode are formed.SELECTED DRAWING: Figure 4
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