Liquid dispensing device

Abstract

To provide a liquid discharge device which can improve image quality of an image formed on a medium even if a signal amount propagated by the liquid discharge device increases.SOLUTION: There is provided a liquid discharge device in which a control circuit board that outputs a head control signal for controlling a discharge head to a head circuit board includes a first buffer and a second buffer, a first buffer circuit capable of simultaneously executing writing of first image data included in a base image data signal to the first buffer and reading of second image data included in the base image data signal from the second buffer executes writing of the first image data to the first buffer at a first frequency, executes reading of the first image data from the first buffer at a second frequency higher than the first frequency, executes writing of the second image data to the second buffer at the first frequency, and executes reading of the second image data from the second buffer at the second frequency.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a liquid ejection device.

Background Art

[0002] In a liquid ejection device 1 that forms an image by ejecting a liquid onto a medium, the ejection timing of the liquid ejected onto the medium is controlled by controlling the drive timing of a drive element that ejects the liquid by driving, and a desired image is formed on the medium. In such a liquid ejection device, from the viewpoint of improving the image quality formed on the medium, the number of nozzles of the liquid ejection device has increased, and accordingly, the number of drive elements provided corresponding to the nozzles has also increased. Therefore, the amount of signals propagated in the liquid ejection device has increased.

[0003] In response to the increase in the amount of signals propagated in such a liquid ejection device, Patent Document 1 discloses a technique that enables stable ejection of ink while reducing the possibility of an increase in the signal lines electrically connecting the control unit and the head unit by converting the signals propagated in the liquid ejection device into LVDS signals and then supplying the LVDS signals to the head unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, from the viewpoint of improving the image quality formed on the medium, the number of nozzles of the liquid ejection device and the number of drive elements provided corresponding to the nozzles still continue to increase. Therefore, further improvement in response to the increase in the amount of signals propagated in the liquid ejection device is required.

Means for Solving the Problems

[0006] One embodiment of the liquid dispensing device according to the present invention is: A dispensing head that dispenses liquid by driving a drive element and forms an image on a medium, A head circuit board that controls the discharge head, A control circuit board that outputs a head control signal for controlling the discharge head to the head circuit board, A cable connecting the head circuit board and the control circuit board, Equipped with, The aforementioned control circuit board is A base image data output circuit that outputs a base image data signal which forms the basis of the aforementioned image, A first buffer circuit comprising a first buffer and a second buffer, capable of simultaneously writing the first image data included in the base image data signal to the first buffer and reading the second image data included in the base image data signal from the second buffer, A first buffer control circuit that controls the first buffer circuit, A control signal output circuit that outputs the head control signal including the second image data, It has, The first buffer circuit is, The writing of the first image data to the first buffer is performed at a first frequency, 1. The reading of image data from the first buffer is performed at a second frequency higher than the first frequency. The writing of the second image data to the second buffer is performed at the first frequency, and the reading of the second image data from the second buffer is performed at the second frequency. [Brief explanation of the drawing]

[0007] [Figure 1] This diagram shows the functional configuration of a liquid dispensing device. [Figure 2] This figure shows an example of the signal waveforms for the drive signals COMA and COMB. [Figure 3]This figure shows an example of the signal waveform of the drive signal VOUT. [Figure 4] This is a diagram illustrating the functional configuration of the discharge head. [Figure 5] This figure shows an example of the content decoded by the decoder. [Figure 6] This diagram shows the configuration of the selection circuit corresponding to one unit of the discharge section. [Figure 7] This is a diagram illustrating the operation of the drive signal selection circuit. [Figure 8] This is a diagram illustrating the operation of a liquid dispensing device. [Modes for carrying out the invention]

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for illustrative purposes only. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

[0009] In the following description, an inkjet printer will be used as an example of the liquid ejection device according to the present invention. However, the liquid ejection device 1 is not limited to an inkjet printer, and may also be a colorant ejection device used in the manufacture of color filters for liquid crystal displays, an electrode material ejection device used in the formation of electrodes for organic EL displays, surface-emitting displays, etc., a bio-organic material ejection device used in the manufacture of biochips, etc.

[0010] 1. Functional configuration of the liquid dispensing device Figure 1 shows the functional configuration of the liquid dispensing device 1. As shown in Figure 1, the liquid dispensing device 1 comprises a control circuit board 10, a head circuit board 30, a dispensing head 20, and a cable CB connecting the control circuit board 10 and the head circuit board 30.

[0011] The control circuit board 10 includes a main control circuit 100, a discharge command output circuit 110, a memory control circuit 120, a clock circuit 130, a dual-port RAM 140, a multiplexer 150, and an interface (IF: Interface) circuit 160. In the control circuit board 10, the main control circuit 100, the discharge command output circuit 110, the memory control circuit 120, the clock circuit 130, the dual-port RAM 140, the multiplexer 150, and the interface circuit 160 are mounted on a wiring board not shown. Here, the wiring board included in the control circuit board 10 is not limited to one. That is, the main control circuit 100, the discharge command output circuit 110, the memory control circuit 120, the clock circuit 130, the dual-port RAM 140, the multiplexer 150, and the interface circuit 160 included in the control circuit board 10 may be mounted on one wiring board, or any of them may be mounted on different wiring boards.

[0012] Based on the image data input from an external device such as a host computer not shown, the main control circuit 100 generates and outputs a control signal for controlling each part of the liquid ejection device 1. The main control circuit 100 includes a discharge control circuit 102 and a drive control circuit 104.

[0013] The discharge control circuit 102 generates a signal that serves as a basis for an image to be formed on a medium, and generates a signal for controlling the discharge of liquid such as the discharge timing and discharge amount of the liquid from the discharge head 20 described later. Then, it outputs to the discharge command output circuit 110. Specifically, the discharge control circuit 102 generates a latch signal rLAT and a change signal rCH that define the discharge timing of the liquid, and a print data signal rSI that defines the discharge amount of the liquid, and outputs them to the discharge command output circuit 110. In addition to the latch signal rLAT, the change signal rCH, and the print data signal rSI, the discharge control circuit 102 may output a forced discharge signal for forcibly discharging the liquid from the discharge head 20 and an inspection signal for inspecting the state of the discharge head 20.

[0014] The ejection command output circuit 110 generates an ejection command signal rDI including an ejection command defined by a latch signal rLAT, a change signal rCH, and a print data signal rSI, which are signals serving as the basis for the image to be formed on the medium, and outputs it to the dual-port RAM 140. Details of the ejection command signal rDI will be described later.

[0015] Also, the ejection control circuit 102 generates a memory control signal MC and outputs it to the memory control circuit 120. Based on the input memory control signal MC, the memory control circuit 120 generates memory control signals Ma1 and Ma2 for controlling the writing of data to the dual-port RAM 140 and the reading of data from the dual-port RAM 140, and outputs them to the dual-port RAM 140. That is, the ejection control circuit 102 and the memory control circuit 120 control the dual-port RAM 140.

[0016] The clock circuit 130 generates a clock signal WCK1 and a clock signal RCK1 with a higher frequency than the clock signal WCK1, and outputs them to the dual-port RAM 140.

[0017] The dual-port RAM 140 receives the ejection command signal rDI output by the ejection command output circuit 110, the memory control signals Ma1 and Ma2 output by the memory control circuit 120, and the clock signals WCK1 and RCK1 output by the clock circuit 130.

[0018] Also, the dual-port RAM 140 has storage areas M1 and M2.

[0019] The memory area M1 receives the ejection command signal rDI output by the ejection command output circuit 110 and the memory control signal Ma1 output by the memory control circuit 120. When the memory control signal Ma1 controls the writing of data to the memory area M1, the ejection command signal rDI is written to the memory area M1 according to the clock signal WCK1. When the memory control signal Ma1 controls the reading of data from the memory area M1, the data written to the memory area M1 is read out according to the clock signal RCK1.

[0020] Similarly, the memory area M2 receives the ejection command signal rDI output by the ejection command output circuit 110 and the memory control signal Ma2 output by the memory control circuit 120. When the memory control signal Ma2 controls the writing of data to the memory area M2, the ejection command signal rDI is written to the memory area M2 according to the clock signal WCK1. When the memory control signal Ma2 controls the reading of data from the memory area M2, the data written to the memory area M2 is read out according to the clock signal RCK1.

[0021] In other words, the dual portram 140 writes the eject command signal rDI output by the eject command output circuit 110 to one of the memory areas M1 and M2 at a frequency defined by the clock signal RCK1, and reads it from the other memory area M1 and M2 according to the clock signal WCK1, which is more frequent than the clock signal RCK1. In such a dual portram 140, each of the memory areas M1 and M2 functions as a buffer circuit that temporarily holds the eject command signal rDI, and converts the frequency of the eject command signal rDI from the frequency defined by the clock signal RCK1 to the frequency defined by the clock signal WCK1, which is more frequent than the frequency defined by the clock signal RCK1, and outputs it as the base eject data signal rDpd. It also functions as a frequency conversion circuit.

[0022] Then, the base output data signal rDpd, which includes the data read from memory areas M1 and M2, is output from the dual port 140 to the multiplexer 150.

[0023] In other words, the dual portram 140 includes memory area M1 and memory area M2 that function as buffer circuits, and is capable of simultaneously writing data contained in the eject command signal rDI to memory area M1 and reading data contained in the eject command signal rDI from memory area M2, and is capable of simultaneously reading data contained in the eject command signal rDI from memory area M1 and writing data contained in the eject command signal rDI to memory area M2. In other words, when the memory control circuit 120 outputs a memory control signal Ma1 that controls writing data to memory area M1, it outputs a memory control signal Ma2 that controls reading data to memory area M2, and when the memory control signal Ma1 that controls reading data to memory area M1 is output, it outputs a memory control signal Ma2 that controls writing data to memory area M2.

[0024] The drive control circuit 104 outputs to the multiplexer 150 a waveform selection signal rCs, which selects the signal waveforms of the drive signals COMA and COMB that drive the drive elements of the discharge head 20, and a period signal rPTS, which defines the drive period in the liquid discharge device 1, as signals for controlling the drive of each part of the liquid discharge device 1 in order to form an image on the medium. In other words, the drive control circuit 104 outputs the waveform selection signal rCs and the period signal rPTS, which control the drive of at least one of the discharge head 20 and the head circuit board 30. In addition to the waveform selection signal rCs and the period signal rPTS, the drive control circuit 104 may also output signals for controlling the drive of a motor (not shown) in the liquid discharge device 1 and signals for controlling access to a memory circuit (not shown), as signals for controlling the drive of each part of the liquid discharge device 1.

[0025] The multiplexer 150 generates a head control signal HC1 by multiplexing the base output data signal rDpd, the waveform selection signal rCs, and the periodic signal rPTS, and outputs it to the interface circuit 160. Specifically, the multiplexer 150 selects the periodic signal rPTS as the head control signal HC1. Then, during the period when the dual portram 140 is outputting the base output data signal rDpd, it selects the base output data signal rDpd as the head control signal HC1, and during the period when the dual portram 140 is not outputting the base output data signal rDpd, it selects the waveform selection signal rCs as the head control signal HC1. Such a multiplexer 150 may, for example, operate using the Busy signal, which indicates whether or not the dual portram 140 is outputting the base output data signal rDpd, as the selection control signal.

[0026] Here, the configuration for outputting the head control signal HC1 is not limited to the multiplexer 150, but any configuration that can sequentially select the base output data signal rDpd, the waveform selection signal rCs, and the period signal rPTS, and output a head control signal HC1 that includes the base output data signal rDpd, the waveform selection signal rCs, and the period signal rPTS in serial order is acceptable. Therefore, the control circuit board 10 may have a command queuing circuit instead of the multiplexer 150, or in addition to the multiplexer 150.

[0027] The interface circuit 160 converts the head control signal HC1 output by the multiplexer 150 into a high-speed communication signal HSC and outputs it to the head circuit board 30. In other words, the interface circuit 160 outputs a high-speed communication signal HSC that serially includes the base output data signal rDpd, the waveform selection signal rCs, and the period signal rPTS. This reduces the number of signal lines included in the cable CB connecting the control circuit board 10 and the head circuit board 30. This reduces the risk of skew and crosstalk occurring in the high-speed communication signal HSC.

[0028] Such an interface circuit 160 may convert the head control signal HC1 into an LVDS (low voltage signaling) signal or into a high-speed communication signal HSC such as a PCI Express signal, but it is preferable that the interface circuit 160 converts the head control signal HC1 into an optical high-speed communication signal HSC. By converting the head control signal HC1 into an optical high-speed communication signal HSC, the interface circuit 160 can reduce latency in the high-speed communication signal HSC and further reduce the risk of skew and crosstalk occurring in the high-speed communication signal HSC.

[0029] In other words, the cable CB connecting the control circuit board 10 and the head circuit board 30 is an optical communication cable such as an optical fiber, and the interface circuit 160 converts the high-speed communication signal HSC into an optical signal, thereby reducing latency in the high-speed communication signal HSC and reducing the risk of skew and crosstalk in the high-speed communication signal HSC. As a result, the accuracy of the high-speed communication signal HSC input to the head circuit board 30 is improved.

[0030] The head circuit board 30 includes an ejection control circuit 310, a memory control circuit 320, a clock circuit 330, a dual portram 340, a demultiplexer 350, an interface (IF) circuit 360, a drive waveform selection circuit 52, and a drive signal output circuit 50. The ejection control circuit 310, memory control circuit 320, clock circuit 330, dual portram 340, demultiplexer 350, interface (IF) circuit 360, drive waveform selection circuit 52, and drive signal output circuit 50 are mounted on a wiring board (not shown). The head circuit board 30 is not limited to having only one wiring board. In other words, the ejection control circuit 310, memory control circuit 320, clock circuit 330, dual port 340, demultiplexer 350, interface (IF) circuit 360, drive waveform selection circuit 52, and drive signal output circuit 50 of the head circuit board 30 may be mounted on a single wiring board, or any of them may be mounted on different wiring boards.

[0031] The high-speed communication signal HSC output by the control circuit board 10 is input to the interface circuit 360. The interface circuit 360 reconstructs the input high-speed communication signal HSC to generate a head control signal HC2 corresponding to the head control signal HC1. The interface circuit 360 then inputs the generated head control signal HC2 to the demultiplexer 350.

[0032] The demultiplexer 350 demultiplexes the head control signal HC2, separating it into a base output data signal Dpd, a waveform selection signal Cs, and a periodic signal PTS. The base output data signal Dpd output by the demultiplexer 350 is input to the dual portram 340, the waveform selection signal Cs output by the demultiplexer 350 is input to the drive waveform selection circuit 52, and the periodic signal PTS is input to the memory control circuit 320 and the drive waveform selection circuit 52.

[0033] In other words, the interface circuit 360 and the demultiplexer 350 convert the high-speed communication signal HSC input from the control circuit board 10 into a base output data signal Dpd, a waveform selection signal Cs, and a periodic signal PTS.

[0034] The memory control circuit 320 controls the writing of data to the dual portram 340 and the reading of data from the dual portram 340 based on the input periodic signal PTS. In other words, the memory control circuit 320 controls the dual portram 340. Specifically, the memory control circuit 320 generates memory control signals Ma3 and Ma4 according to the timing defined by the input periodic signal PTS, and outputs them to the dual portram 340.

[0035] The clock circuit 330 generates a clock signal WCK2 and a clock signal RCK2 with a lower frequency than the clock signal WCK2, and outputs them to the dual port 340. The frequency of the clock signal WCK2 output by the clock circuit 330 is approximately equal to the frequency of the clock signal WCK1 output by the clock circuit 130 of the control circuit board 10, and the frequency of the clock signal RCK2 output by the clock circuit 330 is approximately equal to the frequency of the clock signal RCK1 output by the clock circuit 130 of the control circuit board 10. Here, "approximately equal frequencies" does not mean that they are exactly the same, but includes cases where they can be considered approximately identical when errors and variations are taken into account.

[0036] The dual portram 340 receives the base output data signal Dpd from the demultiplexer 350, the memory control signals Ma3 and Ma4 from the memory control circuit 320, and the clock signals WCK2 and RCK2 from the clock circuit 330. The dual portram 340 also has memory areas M3 and M4.

[0037] The memory area M3 receives the base output data signal Dpd output by the demultiplexer 350 and the memory control signal Ma3 output by the memory control circuit 320. When the memory control signal Ma3 controls the writing of data to the memory area M3, the base output data signal Dpd is written to the memory area M3 according to the clock signal WCK2. When the memory control signal Ma3 controls the reading of data from the memory area M3, the data written to the memory area M3 is read out according to the clock signal RCK2.

[0038] Similarly, the memory area M4 receives the base output data signal Dpd output by the demultiplexer 350 and the memory control signal Ma4 output by the memory control circuit 320. When the memory control signal Ma4 controls the writing of data to the memory area M4, the base output data signal Dpd is written to the memory area M4 according to the clock signal WCK2. When the memory control signal Ma4 controls the reading of data from the memory area M4, the data written to the memory area M4 is read out according to the clock signal RCK2.

[0039] Then, the data read from memory areas M3 and M4 is output as a base discharge command signal DI from the dual port 140 to the discharge control circuit 310.

[0040] In other words, the dual portram 340 includes memory area M3 and memory area M4 that function as buffer circuits, and is capable of simultaneously writing data contained in the base output data signal Dpd to memory area M3 and reading data contained in the base output data signal Dpd from memory area M4, and is capable of simultaneously reading data contained in the base output data signal Dpd from memory area M3 and writing data contained in the base output data signal Dpd to memory area M4.

[0041] The discharge control circuit 310 generates a latch signal LAT, a change signal CH, and a print data signal SI, whose logic levels are controlled based on the base discharge command signal DI input from the dual portram 340, and outputs them to the discharge head 20. This defines the timing and amount of liquid discharged from the discharge head 20. In other words, the discharge control circuit 310 controls the operation of the discharge head 20 based on the base discharge command signal DI input from the dual portram 340.

[0042] The drive waveform selection circuit 52 selects the drive of the discharge head 20 based on the waveform selection signal Cs. The waveform selection signal Cs defines the signal waveforms of the drive signals COMA and COMB that drive the element. In other words, the waveform selection signal Cs contains information that defines the signal waveforms of the drive signals COMA and COMB that drive the drive element.

[0043] The drive waveform selection circuit 52 generates a base drive signal dA that defines the signal waveform of drive signal COMA, and a base drive signal dB that defines the signal waveform of drive signal COMB, and outputs them to the drive signal output circuit 50. Such a drive waveform selection circuit 52 may include, for example, a data table in which signal waveforms corresponding to waveform selection signals Cs are stored, and the information of the data table referenced based on the input waveform selection signal Cs may be output as base drive signals dA and dB.

[0044] The drive signal output circuit 50 generates a drive signal COMA by amplifying the signal waveform defined by the input base drive signal dA and outputs it to the discharge head 20, and also generates a drive signal COMB by amplifying the signal waveform defined by the input base drive signal dB and outputs it to the discharge head 20. Specifically, the drive signal output circuit 50 converts the input base drive signal dA into an analog signal by D / A conversion, amplifies the converted analog signal to generate a drive signal COMA and outputs it to the discharge head 20, and also converts the input base drive signal dB into an analog signal by D / A conversion, amplifies the converted analog signal to generate a drive signal COMB and outputs it to the discharge head 20.

[0045] The ejection head 20 receives a latch signal LAT, a change signal CH, a print data signal SI, and drive signals COMA and COMB. At the timings defined by the latch signal LAT and the change signal CH, the ejection head 20 selects or deselects the signal waveforms of the drive signals COMA and COMB based on the print data signal SI, thereby controlling the amount of drive of the drive element that ejects liquid. In other words, the ejection head 20 controls the amount of liquid ejected and the ejection timing by controlling the amount of drive of the drive element based on the latch signal LAT, the change signal CH, the print data signal SI, and the drive signals COMA and COMB. As a result, the ejection head 20 forms the desired image on the medium.

[0046] 2. Functional configuration of the discharge head Here, we will describe the configuration and specific operation of the ejection head 20, which forms a desired image on a medium by ejecting liquid onto the medium. In describing the configuration and operation of the ejection head 20, we will first describe an example of the signal waveforms of the drive signals COMA and COMB that are input to the ejection head 20.

[0047] Figure 2 shows an example of the signal waveforms of the drive signals COMA and COMB. As shown in Figure 2, the drive signal COMA is a signal waveform formed by continuously combining a trapezoidal waveform Adp1, which is placed in the period T1 from when the latch signal LAT rises until when the change signal CH rises, and a trapezoidal waveform Adp2, which is placed in the period T2 from when the change signal CH rises until when the latch signal LAT rises. The trapezoidal waveform Adp1 is a signal waveform that drives the drive element so that a predetermined amount of liquid is discharged, and the trapezoidal waveform Adp2 is a signal waveform that drives the drive element so that a larger amount of liquid than the predetermined amount is discharged. Here, in the following explanation, the amount of liquid discharged when the trapezoidal waveform Adp1 is supplied to the drive element may be referred to as a small amount, and the amount of liquid discharged when the trapezoidal waveform Adp2 is supplied to the drive element may be referred to as a medium amount.

[0048] Furthermore, as shown in Figure 2, the drive signal COMB is a signal waveform formed by combining a trapezoidal waveform Bdp1 placed during period T1 and a trapezoidal waveform Bdp2 placed during period T2. Trapezoidal waveform Bdp1 is a signal waveform that drives the drive element to the extent that no liquid is discharged, and trapezoidal waveform Bdp2 is a signal waveform that drives the drive element so that a predetermined amount of liquid is discharged. The trapezoidal waveform used to drive the drive element to prevent liquid from being discharged is a signal waveform that prevents changes in the viscosity of the liquid by vibrating the liquid near the opening of the nozzle from which the liquid is discharged when the drive element is driven.

[0049] Furthermore, as shown in Figure 2, the voltage values ​​at the start and end timings of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all the same, at voltage Vc. That is, each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is a signal waveform that starts and ends at voltage Vc. The period Ta, consisting of periods T1 and T2, corresponds to the printing period for forming new dots on the medium.

[0050] Note that while Figure 2 illustrates the case where trapezoidal waveform Adp1 and trapezoidal waveform Bdp2 are the same signal waveform, trapezoidal waveform Adp1 and trapezoidal waveform Bdp2 may be different signal waveforms. Furthermore, although the explanation assumes that a small amount of liquid is discharged in both cases where trapezoidal waveform Adp1 and trapezoidal waveform Bdp2 are supplied to the driving element, this is not the only possible scenario.

[0051] Next, we will describe an example of the signal waveform of the drive signal VOUT, which is generated by selecting or deselecting the signal waveforms included in the drive signals COMA and COMB. Figure 3 is a diagram showing an example of the signal waveform of the drive signal VOUT. Figure 3 shows an example of the signal waveform of the drive signal VOUT corresponding to the dot size formed on the medium when the drive signal VOUT is supplied to the drive element, and specifically, an example of the signal waveform of the drive signal VOUT corresponding to the dot size formed on the medium as large dot LD, medium dot MD, small dot SD, and non-recorded ND.

[0052] As shown in Figure 3, the drive signal VOUT when a large dot LD is formed on the medium has a signal waveform that consists of a trapezoidal waveform Adp1 positioned in period T1 and a trapezoidal waveform Adp2 positioned in period T2, in a continuous sequence during period Ta. When this drive signal VOUT is supplied to the drive element, a small amount of liquid and a medium amount of liquid are discharged from the corresponding nozzle. Therefore, during period Ta, the liquids land on the medium and combine, forming a large dot LD on the medium.

[0053] When a medium dot MD is formed on the medium, the drive signal VOUT is a signal waveform that consists of a trapezoidal waveform Adp1 placed in period T1 and a trapezoidal waveform Bdp2 placed in period T2, in a continuous sequence during period Ta. When this drive signal VOUT is supplied to the drive element, a small amount of liquid is discharged twice from the corresponding nozzle. Therefore, during period Ta, each liquid lands on the medium and combines, forming a medium dot MD on the medium.

[0054] When small dots SD are formed on the medium, the drive signal VOUT has a waveform that consists of a trapezoidal waveform Adp1 in period T1 and a constant voltage Vc signal waveform in period T2, in a continuous sequence. When this drive signal VOUT is supplied to the drive element, a small amount of liquid is discharged once from the corresponding nozzle. Therefore, in period Ta, this liquid lands on the medium, forming small dots SD on the medium.

[0055] The drive signal VOUT, which corresponds to a non-recording ND that does not form dots on the medium, has a signal waveform that consists of a trapezoidal waveform Bdp1 placed in period T1 and a constant voltage Vc signal waveform placed in period T2, in a continuous sequence during period Ta. When this drive signal VOUT is supplied to the drive element, only the liquid near the opening of the corresponding nozzle vibrates slightly, and no liquid is discharged. Therefore, during period Ta, the liquid does not land on the medium, and no dots are formed on the medium.

[0056] Here, a constant signal waveform with a voltage Vc in the drive signal VOUT refers to a signal waveform where the voltage Vc immediately preceding a trapezoidal waveform Adp1, Adp2, Bdp1, or Bdp2 is retained, when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, or Bdp2 are selected as the drive signal VOUT. In other words, when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, or Bdp2 are selected as the drive signal VOUT, the immediately preceding voltage Vc is supplied to the drive element as the drive signal VOUT.

[0057] Next, the functional configuration of the discharge head 20 will be described. Figure 4 is a diagram illustrating the functional configuration of the discharge head 20. As shown in Figure 4, the discharge head 20 has a drive signal selection circuit 200 and n discharge units 600.

[0058] The drive signal selection circuit 200 selects or deselects the trapezoidal waveforms Adp1 and Adp2 included in the drive signal COMA and the trapezoidal waveforms Bdp1 and Bdp2 included in the drive signal COMB, thereby generating a drive signal VOUT that corresponds individually to each of the n piezoelectric elements 60 acting as drive elements, and outputs it to the corresponding discharge unit 600.

[0059] As shown in Figure 4, the drive signal selection circuit 200 includes a selection control circuit 210 and n selection circuits 230. The selection control circuit 210 receives the print data signal SI, latch signal LAT, and change signal CH output by the ejection control circuit 310. The selection control circuit 210 also receives a clock signal SCK. Here, the clock signal SCK is a carrier clock for propagating the print data signal SI, and may be output by, for example, an oscillator circuit (not shown), or may be input from the head circuit board 30.

[0060] The selection control circuit 210 is provided with a set of register 212, latch circuit 214, and decoder 216, corresponding to each of the n discharge units 600. In other words, the selection control circuit 210 includes the same number of register 212, latch circuit 214, and decoder 216 sets as there are n discharge units 600.

[0061] The print data signal SI is a 2n-bit signal that serially contains 2 bits of print data [SIH,SIL] for each of the n ejection units 600, for selecting one of the following depending on the dot size formed on the medium: large dot LD, medium dot MD, small dot SD, or no-recording ND. The print data signal SI is held in register 212 for each piece of print data [SIH,SIL] contained in the print data signal SI, corresponding to the n ejection units 600.

[0062] Specifically, in the selection control circuit 210, the registers 212 are connected in cascading order to form an n-stage shift register. The print data [SIH,SIL] input serially as the print data signal SI is sequentially transferred to the subsequent registers 212 according to the clock signal SCK. When the supply of the clock signal SCK stops, the print data [SIH,SIL] corresponding to each of the n ejectors 600 is held in the register 212 corresponding to each of the n ejectors 600. In the following explanation, in order to distinguish the n registers 212 that constitute the shift register, they may be referred to as the 1st stage, 2nd stage, ..., nth stage, in order from the upstream side to the downstream side where the print data signal SI is propagated.

[0063] Each of the n latch circuits 214 is provided in correspondence with each of the n registers 212. Each latch circuit 214 simultaneously latches the print data [SIH,SIL] held in each of the n registers 212 on the rising edge of the latch signal LAT and outputs it to the corresponding decoder 216.

[0064] Figure 5 shows an example of the decoding content in decoder 216. Decoder 216 generates and outputs selection signals S1 and S2 by decoding the print data [SIH,SIL] latched by latch circuit 214 with the content shown in Figure 5. For example, if the input print data [SIH,SIL] is [1,0], decoder 216 outputs the logic level of selection signal S1 as H and L levels for periods T1 and T2 to selection circuit 230, and the logic level of selection signal S2 as L and H levels for periods T1 and T2 to selection circuit 230.

[0065] The selection circuit 230 is provided in correspondence to each of the n discharge units 600. That is, the drive signal selection circuit 200 has the same number of selection circuits 230 as the n discharge units 600. Figure 6 is a diagram showing the configuration of the selection circuit 230 corresponding to one discharge unit 600. As shown in Figure 6, the selection circuit 230 includes inverters 232a, 232b and transfer gates 234a, 234b, which are NOT circuits.

[0066] The selection signal S1 is input to the unmarked positive control terminal of transfer gate 234a, while being logically inverted by inverter 232a and input to the marked negative control terminal of transfer gate 234a. A drive signal COMA is also supplied to the input terminal of transfer gate 234a. The selection signal S2 is input to the unmarked positive control terminal of transfer gate 234b, while being logically inverted by inverter 232b and input to the marked negative control terminal of transfer gate 234b. A drive signal COMB is also supplied to the input terminal of transfer gate 234b. The output terminals of transfer gate 234a and transfer gate 234b are then connected in common. The signal at this common connection terminal is output as the drive signal VOUT.

[0067] Specifically, when the selection signal S1 is at a high level, the input and output terminals of the transfer gate 234a become conductive, and when the selection signal S1 is at a low level, the input and output terminals of the transfer gate 234a become non-conductive. Similarly, when the selection signal S2 is at a high level, the input and output terminals of the transfer gate 234b become conductive, and when the selection signal S2 is at a low level, the input and output terminals of the transfer gate 234b become non-conductive. In other words, the selection circuit 230 switches the conduction state between the input and output terminals of the transfer gates 234a and 234b based on the selection signals S1 and S2, and selects or deselects the signal waveforms of the drive signals COMA and COMB supplied to the input terminals of the transfer gates 234a and 234b, thereby generating the drive signal VOUT at the connection terminal where the output terminals of the transfer gate 234a and the output terminals of the transfer gate 234b are commonly connected.

[0068] The operation of the drive signal selection circuit 200 will be explained using Figure 7. Figure 7 is a diagram illustrating the operation of the drive signal selection circuit 200. The print data [SIH,SIL] included in the print data signal SI is input serially in synchronization with the clock signal SCK. The print data [SIH,SIL] is then sequentially transferred in the registers 212 that constitute the shift register, corresponding to the n ejection units 600, in synchronization with the clock signal SCK. Subsequently, when the supply of the clock signal SCK is stopped, each of the registers 212 holds the print data [SIH,SIL] corresponding to each of the n ejection units 600. The print data [SIH,SIL] included in the print data signal SI is input in the order corresponding to the n, ..., 2, and 1 stages of the ejection units 600 in the registers 212 that constitute the shift register.

[0069] Then, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH,SIL] held in register 212. In 7, LS1, LS2, ..., LSp represent the print data [SIH, SIL] latched by the latch circuit 214 corresponding to the 1st, 2nd, ..., nth stage registers 212.

[0070] The decoder 216 outputs the logic levels of selection signals S1 and S2 in the manner shown in Figure 5, for each of the periods T1 and T2, according to the size of the dots defined in the latched print data [SIH, SIL].

[0071] Specifically, when the input print data [SIH,SIL] is [1,1], the decoder 216 sets the selection signal S1 to H,H level during periods T1 and T2, and the selection signal S2 to L,L level during periods T1 and T2. In this case, the selection circuit 230 selects trapezoidal waveform Adp1 during period T1 and trapezoidal waveform Adp2 during period T2. As a result, a drive signal VOUT corresponding to the large dot LD shown in Figure 3 is generated at the output terminal of the selection circuit 230.

[0072] Furthermore, when the input print data [SIH,SIL] is [1,0], the decoder 216 sets the selection signal S1 to H,L level during periods T1 and T2, and the selection signal S2 to L,H level during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 during period T1 and the trapezoidal waveform Bdp2 during period T2. As a result, a drive signal VOUT corresponding to the middle dot MD shown in Figure 3 is generated at the output terminal of the selection circuit 230.

[0073] Furthermore, when the input print data [SIH,SIL] is [0,1], the decoder 216 sets the selection signal S1 to H,L level during periods T1 and T2, and the selection signal S2 to L,L level during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 during period T1, and does not select either the trapezoidal waveform Adp2 or Bdp2 during period T2. As a result, a drive signal VOUT corresponding to the small dot SD shown in Figure 3 is generated at the output terminal of the selection circuit 230.

[0074] Furthermore, when the input print data [SIH,SIL] is [0,0], the decoder 216 sets the selection signal S1 to L,L level during periods T1 and T2, and the selection signal S2 to H,L level during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Bdp1 during period T1, and does not select either the trapezoidal waveform Adp2 or Bdp2 during period T2. As a result, a drive signal VOUT corresponding to the non-recorded ND shown in Figure 3 is generated at the output terminal of the selection circuit 230.

[0075] As described above, the drive signal selection circuit 200 generates and outputs the drive signal VOUT by selecting the signal waveforms of the drive signal COMA and the drive signal COMB based on the print data signal SI, the clock signal SCK, the latch signal LAT, and the change signal CH. In other words, the print data signal SI, the latch signal LAT, and the change signal CH contain information that defines the driving conditions of the drive element.

[0076] 3. Signal propagation in liquid dispensing devices A specific example of the operation of the liquid dispensing device 1 configured as described above will now be explained. Figure 8 is a diagram illustrating the operation of the liquid dispensing device 1. Figure 8 shows a predetermined operating period Tp, an operating period Tp+1 that follows operating period Tp, and an operating period Tp+2 that follows operating period Tp+1, in the operating period defined by the periodic signal rPTS.

[0077] The operation cycle Tp is started when the drive control circuit 104 outputs periodic data rPp as a periodic signal rPTS. During the operation cycle Tp, the discharge control circuit 102 performs a short H-type operation. The system generates a latch signal rLAT which acts as a bell, a change signal rCH which is at a high level for a short time, and a print data signal rSI which contains print data [SIH,SIL] corresponding to n ejection units 600, and outputs them to the ejection command output circuit 110. The ejection command output circuit 110 generates ejection data rDIp which contains information on the rising edge of the latch signal rLAT, information on the falling edge of the latch signal rLAT, information on the rising edge of the change signal rCH, information on the falling edge of the change signal rCH, and information on the logic level of the print data [SIH,SIL], and outputs it to the dual portram 140 as an ejection command signal rDI.

[0078] As shown in Figure 8, during the operation cycle Tp, the memory control circuit 120 outputs a memory control signal Ma1 that controls the writing of data to the storage area M1, and a memory control signal Ma2 that controls the reading of data from the storage area M2. Therefore, the ejected data rDIp output by the eject command output circuit 110 during the operation cycle Tp is held in the storage area M1 of the dual portram 140 according to the clock signal WCK1. In other words, the ejected data rDIp is written to the storage area M1 at the frequency of the clock signal WCK1.

[0079] The operation cycle Tp+1 begins after the operation cycle Tp when the drive control circuit 104 outputs the periodic data rPp+1 as a periodic signal rPTS. In the operation cycle Tp+1, the ejection control circuit 102 generates a latch signal rLAT that is at a high level for a short time, a change signal rCH that is at a high level for a short time, and a print data signal rSI that contains print data [SIH,SIL] corresponding to the n ejection units 600, and outputs these to the ejection command output circuit 110. The ejection command output circuit 110 generates ejection data rDIp+1 that contains information on the rising edge of the latch signal rLAT, information on the falling edge of the latch signal rLAT, information on the rising edge of the change signal rCH, information on the falling edge of the change signal rCH, and information on the logic level of the print data [SIH,SIL], and outputs this as an ejection command signal rDI to the dual portram 140.

[0080] As shown in Figure 8, during the operation cycle Tp+1, the memory control circuit 120 outputs a memory control signal Ma1 that controls the reading of data from the storage area M1, and a memory control signal Ma2 that controls the writing of data to the storage area M2. Therefore, the ejected data rDIp+1 output by the eject command output circuit 110 during the operation cycle Tp+1 is held in the storage area M2 of the dual portram 140 according to the clock signal WCK1. In other words, the ejected data rDIp+1 is written to the storage area M2 at the frequency of the clock signal WCK1.

[0081] Furthermore, during the operation cycle Tp+1, the ejected data rDIp held in the memory area M1 of the dual portram 140 is read out as the base ejected data signal rDpd according to the clock signal RCK1. In other words, the ejected data rDIp is read out from the memory area M1 at the frequency of the clock signal RCK1.

[0082] The ejection data rDIp read from the dual portram 140 is input to the multiplexer 150. The multiplexer 150 also receives periodic data rPp+1 as a periodic signal rPTS output by the drive control circuit 104, and waveform selection data rCp+1 as a waveform selection signal rCs output by the drive control circuit 104. The multiplexer 150 then generates and outputs a head control signal HC1 by sequentially selecting the ejection data rDIp as the base ejection data signal rDpd, the periodic data rPp+1 as the periodic signal rPTS, and the waveform selection data rCp+1 as the waveform selection signal rCs.

[0083] Specifically, in the operating cycle Tp+1, the multiplexer 150 first selects the period data rPp+1 as the period signal rPTS and outputs it as the head control signal HC1. Subsequently, the multiplexer 150 selects the discharge data rDIp as the base discharge data signal rDpd and outputs it as the head control signal HC1. Then, the multiplexer 150 selects the waveform selection data rCp+1 as the waveform selection signal rCs and outputs it as the head control signal HC1. In other words, in the operating cycle Tp+1, the multiplexer 150 generates and outputs the head control signal HC1 which is included serially in the order of period data rPp+1, discharge data rDIp, and waveform selection data rCp+1. Note that the order of signal selection in the multiplexer 150 is not limited to the above.

[0084] The head control signal HC1 output by the multiplexer 150 is converted into a high-speed communication signal HSC in the interface circuit 160, and then restored to a head control signal HC2 in the interface circuit 360. The head control signal HC2 is input to the demultiplexer 350. The head control signal HC2 is then demultiplexed in the demultiplexer 350, separating it into periodic data Pp+1 corresponding to periodic data rPp+1, discharge data DIp corresponding to discharge data rDIp, and waveform selection data Cp+1 corresponding to waveform selection data rCp+1.

[0085] The periodic signal PTS, which includes periodic data Pp+1, is input to the memory control circuit 320. As a result, during the operating period Tp+1, the memory control circuit 320 outputs a memory control signal Ma3 that controls the reading of data from storage area M3, and a memory control signal Ma4 that controls the writing of data to storage area M4.

[0086] The base ejection data signal Dpd, which includes the ejection data DIp, is input to the dual portram 340. As a result, in the operating cycle Tp+1, the ejection data DIp included in the base ejection data signal Dpd is held in the storage area M4 of the dual portram 140 according to the clock signal WCK2. In other words, the ejection data DIp is written to the storage area M4 at the frequency of the clock signal WCK2.

[0087] The waveform selection signal Cs, which includes the waveform selection data Cp+1, is input to the drive waveform selection circuit 52. The drive waveform selection circuit 52 selects a base drive signal dA for generating the drive signal COMA of the signal waveform defined by the waveform selection data Cp+1, and a base drive signal dB for generating the drive signal COMB of the signal waveform defined by the waveform selection data Cp+1. Then, in the operation cycle T+2 following the operation cycle Tp+1, the drive waveform selection circuit 52 outputs the selected base drive signals dA and dB to the drive signal output circuit 50. As a result, the drive signal output circuit 50 outputs the drive signals COMA and COMB of the signal waveform defined by the base drive signals dA and dB.

[0088] The operation cycle Tp+2 begins after the operation cycle Tp+1 when the drive control circuit 104 outputs the periodic data rPp+2 as a periodic signal rPTS. In the operation cycle Tp+2, the ejection control circuit 102 generates a latch signal rLAT that is at a high level for a short time, a change signal rCH that is at a high level for a short time, and a print data signal rSI that contains print data [SIH,SIL] corresponding to the n ejection units 600, and outputs them to the ejection command output circuit 110. The ejection command output circuit 110 generates ejection data rDIp+2 that contains information on the rising edge of the latch signal rLAT, information on the falling edge of the latch signal rLAT, information on the rising edge of the change signal rCH, information on the falling edge of the change signal rCH, and information on the logic level of the print data [SIH,SIL], and outputs it to the dual portram 140 as an ejection command signal rDI.

[0089] As shown in Figure 8, in the operation cycle Tp+2, the memory control circuit 120 controls the writing of data to the storage area M1 with a memory control signal Ma1, and data from the storage area M2. The device outputs a memory control signal Ma2 that controls the reading of the data. Therefore, the discharge data rDIp+2 output by the discharge command output circuit 110 during the operation cycle Tp+2 is held in the storage area M1 of the dual portram 140 according to the clock signal WCK1. In other words, the discharge data rDIp+2 is written to the storage area M1 at the frequency of the clock signal WCK1.

[0090] Furthermore, during the operation cycle Tp+2, the ejected data rDIp+1 held in the memory area M2 of the dual portram 140 is read out as the base ejected data signal rDpd according to the clock signal RCK1. In other words, the ejected data rDIp+1 is read out from the memory area M2 at the frequency of the clock signal RCK1.

[0091] The ejection data rDIp+1 read from the dual port ram 140 is input to the multiplexer 150. The multiplexer 150 also receives periodic data rPp+2 as a periodic signal rPTS output by the drive control circuit 104, and waveform selection data rCp+2 as a waveform selection signal rCs output by the drive control circuit 104. The multiplexer 150 then generates and outputs a head control signal HC1 by sequentially selecting the ejection data rDIp+1 as the base ejection data signal rDpd, the periodic data rPp+2 as the periodic signal rPTS, and the waveform selection data rCp+2 as the waveform selection signal rCs.

[0092] Specifically, in the operating cycle Tp+2, the multiplexer 150 first selects the periodic data rPp+2 as the periodic signal rPTS and outputs it as the head control signal HC1. Then, the multiplexer 150 selects the discharge data rDIp+1 as the base discharge data signal rDpd and outputs it as the head control signal HC1. After that, the multiplexer 150 selects the waveform selection data rCp+2 as the waveform selection signal rCs and outputs it as the head control signal HC1. In other words, in the operating cycle Tp+2, the multiplexer 150 generates and outputs the head control signal HC1 which is included serially in the order of periodic data rPp+2, discharge data rDIp+1, and waveform selection data rCp+2. Note that the order of signal selection in the multiplexer 150 is not limited to the above.

[0093] The head control signal HC1 output by the multiplexer 150 is converted into a high-speed communication signal HSC in the interface circuit 160, and then restored to a head control signal HC2 in the interface circuit 360. The head control signal HC2 is input to the demultiplexer 350. The head control signal HC2 is then demultiplexed in the demultiplexer 350, separating it into periodic data Pp+2 corresponding to periodic data rPp+2, discharge data DIp+1 corresponding to discharge data rDIp+1, and waveform selection data Cp+2 corresponding to waveform selection data rCp+2.

[0094] The periodic signal PTS, which includes the periodic data Pp+2, is input to the memory control circuit 320. As a result, during the operating period Tp+2, the memory control circuit 320 outputs a memory control signal Ma3 that controls writing data to the storage area M3, and a memory control signal Ma4 that controls reading data from the storage area M4.

[0095] The base ejection data signal Dpd, which includes the ejection data DIp+1, is input to the dual portram 340. As a result, in the operating cycle Tp+2, the ejection data DIp+1 included in the base ejection data signal Dpd is held in the memory area M3 of the dual portram 340 according to the clock signal WCK2. In other words, the ejection data DIp+1 is written to the memory area M3 at the frequency of the clock signal WCK2.

[0096] The waveform selection signal Cs, which includes the waveform selection data Cp+2, is input to the drive waveform selection circuit 52. The drive waveform selection circuit 52 selects a base drive signal dA for generating a drive signal COMA of a signal waveform defined by the waveform selection data Cp+2, and a base drive signal dB for generating a drive signal COMB of a signal waveform defined by the waveform selection data Cp+2. Then, in the operation cycle T+3 that follows the operation cycle Tp+2, the drive waveform selection circuit 52 outputs the selected base drive signals dA and dB to the drive signal output circuit 50. As a result, the drive signal output circuit 50 outputs drive signals COMA and COMB of signal waveforms defined by the base drive signals dA and dB.

[0097] Furthermore, during the operation cycle Tp+2, the ejected data DIp held in the memory area M4 of the dual portram 340 is read out as the base ejection command signal DI according to the clock signal RCK2. In other words, the ejected data rDIp is read out from the memory area M4 at the frequency of the clock signal RCK2.

[0098] The base ejection command signal DI, which includes the read ejection data DIp, is input to the ejection control circuit 310. The ejection control circuit 310 generates a latch signal LAT that rises based on the rising edge information of the latch signal rLAT contained in the ejection data DIp and falls based on the falling edge information of the latch signal rLAT, a change signal CH that rises based on the rising edge information of the change signal rCH and falls based on the falling edge information of the change signal rCH, and a print data signal SI corresponding to the logic level information of the print data [SIH, SIL], and outputs these to the ejection head 20. As a result, the ejection head 20 generates a drive signal VOUT corresponding to each of the n ejection units 600 in the operation shown in Figures 4 to 7 and outputs it to the corresponding ejection unit 600.

[0099] As described above, in the liquid dispensing device 1 of this embodiment, the control circuit board 10 includes a dispensing command output circuit 110 that outputs a dispensing command signal rDI which is the basis of the image, a dual portram 140 which includes a memory area M1 and a memory area M2 and can simultaneously write the dispensing data rDIp+1 included in the dispensing command signal rDI to the memory area M2 and read the dispensing data rDIp included in the dispensing command signal rDI from the memory area M1, a memory control circuit 120 which controls the dual portram 140, and includes the dispensing data rDIp The dual portram 140 has an interface circuit 160 that outputs a high-speed communication signal HSC, and the dual portram 140 performs the writing of discharge data rDIp+1 to the storage area M2 at the frequency of the clock signal WCK1, and the reading of discharge data rDIp+1 from the storage area M2 at the frequency of the clock signal RCK1 which is higher than the frequency of the clock signal WCK1, and the writing of discharge data rDIp to the storage area M1 at the frequency of the clock signal WCK1, and the reading of discharge data rDIp from the storage area M1 at the frequency of the clock signal RCK1.

[0100] Furthermore, the head circuit board 30 includes an interface circuit 360 and a demultiplexer 350 that convert the high-speed communication signal HSC input from the control circuit board 10 into a base ejection data signal Dpd, a dual portram 340 that includes memory areas M3 and M4 and can simultaneously write the ejection data DIp+1 contained in the high-speed communication signal HSC to memory area M3 and read the ejection data rDIp contained in the high-speed communication signal HSC from memory area M4, a memory control circuit 320 that controls the dual portram 340, and a control that controls the ejection head 20 based on the ejection data rDIp. The dual portram 340 has a discharge control circuit 310, and performs the writing of discharge data DIp+1 to the storage area M3 at a frequency of clock signal WCK2 equivalent to the frequency of clock signal RCK1, reads the discharge data DIp+1 from the storage area M3 at a frequency of clock signal RCK2 equivalent to the frequency of clock signal WCK1, writes the discharge data rDIp to the storage area M4 at a frequency of clock signal WCK2 equivalent to the frequency of clock signal RCK1, and reads the discharge data rDIp from the storage area M4 at a frequency of clock signal RCK2 equivalent to the frequency of clock signal WCK1. To do.

[0101] Here, a high-speed communication signal HSC, which includes a latch signal LAT, a change signal CH, and a print data signal SI that control the ejection head 20, is an example of a head control signal; an ejection command signal rDI is an example of a base image data signal; and an ejection command output circuit 110 that outputs the ejection command signal rDI is an example of a base image data output circuit. Furthermore, storage area M2 is an example of a first buffer; storage area M1 is an example of a second buffer; storage area M3 is an example of a third buffer; storage area M4 is an example of a fourth buffer; a dual portram 140 including storage areas M2 and M1 is an example of a first buffer circuit; and a dual portram 340 including storage areas M3 and M4 is an example of a second buffer circuit. Furthermore, a memory control circuit 120 that controls the dual portram 140 is an example of a first buffer control circuit; and a memory control circuit 320 that controls the dual portram 340 is an example of a second buffer control circuit. Furthermore, ejection data rDIp+1 is an example of first image data and first head control data; and ejection data rDIp is an example of second image data and second head control data. Furthermore, a configuration including interface circuit 160 and multiplexer 150 is an example of a control signal output circuit, and a configuration including interface circuit 360 and demultiplexer 350 is an example of a conversion circuit. Also, the frequency of clock signal WCK1 is an example of a first frequency, the frequency of clock signal RCK1 is an example of a second frequency, and the base ejection data signal Dpd is an example of an image data signal. Furthermore, at least one of waveform selection signal rCs and period signal rPTS, which control the driving of at least one of ejection head 20 and head circuit board 30, is an example of a drive control signal, and a drive control circuit 104 that outputs waveform selection signal rCs and period signal rPTS is an example of a drive control signal output circuit.

[0102] 4. Effects In the liquid dispensing device 1 of this embodiment, configured as described above, the dual portram 140 writes the dispensing data rDIp+1 to the storage area M2 at the frequency of the clock signal WCK1, reads the dispensing data rDIp+1 from the storage area M2 at the frequency of the clock signal RCK1 which is higher than the frequency of the clock signal WCK1, writes the dispensing data rDIp to the storage area M1 at the frequency of the clock signal WCK1, and reads the dispensing data rDIp from the storage area M1 at the frequency of the clock signal RCK1. This enables high-speed propagation of signals from the control circuit board 10 to the head circuit board 30 without changing the correlation between the information contained in the dispensing data rDIp and the dispensing data rDIp+1.

[0103] In other words, the risk of discrepancies occurring between the timing defined by the ejection command signal rDI, which is the basis of the image, and the timing in which the head circuit board 30 and the ejection head 20 are controlled, due to signal conversion associated with the increased speed of the signal propagated from the control circuit board 10 to the head circuit board 30, is reduced. As a result, the ejection accuracy of the ink ejected from the ejection head 20 is improved. That is, even if the transmitted signal speed is increased in response to an increase in the number of nozzles in the liquid ejection device 1 and the number of drive elements provided corresponding to the nozzles, the risk of a decrease in the ejection accuracy of the ink ejected from the ejection head 20 is reduced.

[0104] Furthermore, the dual portram 340 provided on the head circuit board 30 writes the ejected data DIp+1 to the storage area M3 at a frequency of clock signal WCK2 equivalent to the frequency of clock signal RCK1, reads the ejected data DIp+1 from the storage area M3 at a frequency of clock signal RCK2 equivalent to the frequency of clock signal WCK1, writes the ejected data rDIp to the storage area M4 at a frequency of clock signal WCK2 equivalent to the frequency of clock signal RCK1, and reads the ejected data rDIp from the storage area M4 at a frequency of clock signal RCK2 equivalent to the frequency of clock signal WCK1. As a result of signal conversion when restoring the signals propagated to the head circuit board 30, the ejected command signal that forms the basis of the image is restored. This also reduces the risk of discrepancies between the timing defined by rDI and the timing controlled by the head circuit board 30 and the ejection head 20. As a result, the ejection accuracy of the ink ejected from the ejection head 20 is further improved. In other words, even if the transmitted signal speed is increased in response to an increase in the number of nozzles in the liquid ejection device 1 and the number of drive elements provided corresponding to the nozzles, the risk of a decrease in the ejection accuracy of the ink ejected from the ejection head 20 is further reduced.

[0105] Furthermore, the dual portram 140 writes the ejected data rDIp+1 to the storage area M2 at the frequency of the clock signal WCK1, reads the ejected data rDIp+1 from the storage area M2 at the frequency of the clock signal RCK1 which is higher than the frequency of the clock signal WCK1, writes the ejected data rDIp to the storage area M1 at the frequency of the clock signal WCK1, and reads the ejected data rDIp from the storage area M1 at the frequency of the clock signal RCK1, thereby converting the ejected command signal rDI into a high-frequency signal. The multiplexer 150 then uses the bandwidth secured by the conversion of the ejected command signal rDI into a high-frequency signal to propagate signals that control the driving of at least one of the ejected head 20 and the head circuit board 30, such as the waveform selection signal rCs and the periodic signal rPTS, thereby reducing the number of signal lines in the cable CB connecting the control circuit board 10 and the head circuit board 30. This reduces the risk of skew and crosstalk occurring in the high-speed communication signal HSC.

[0106] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0107] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0108] The following conclusions can be drawn from the embodiments described above.

[0109] One embodiment of a liquid dispensing device is: A dispensing head that dispenses liquid by driving a drive element and forms an image on a medium, A head circuit board that controls the discharge head, A control circuit board that outputs a head control signal for controlling the discharge head to the head circuit board, A cable connecting the head circuit board and the control circuit board, Equipped with, The aforementioned control circuit board is A base image data output circuit that outputs a base image data signal which forms the basis of the aforementioned image, A first buffer circuit comprising a first buffer and a second buffer, capable of simultaneously writing the first image data included in the base image data signal to the first buffer and reading the second image data included in the base image data signal from the second buffer, A first buffer control circuit that controls the first buffer circuit, A control signal output circuit that outputs the head control signal including the second image data, It has, The first buffer circuit is, The first image data is written to the first buffer at a first frequency, and the first image data is read from the first buffer at a second frequency higher than the first frequency. The writing of the second image data to the second buffer is performed at the first frequency, and the reading of the second image data from the second buffer is performed at the second frequency.

[0110] This liquid ejection device enables the first buffer circuit to write the first image data to the first buffer at a first frequency, read the first image data from the first buffer at a second frequency higher than the first frequency, write the second image data to the second buffer at a first frequency, and read the second image data from the second buffer at a second frequency. This allows for faster propagation of signals between the control circuit board and the head circuit board without changing the timing correlation defined by the base image data signal generated by the control circuit board. As a result, the risk of variations between the timing defined by the base image data signal and the timing controlled by the head circuit board and the ejection head is reduced, improving the ejection accuracy of the ink ejected from the ejection head. In other words, even when the propagated signal speed is increased in response to an increase in the number of drive elements, the risk of a decrease in the ejection accuracy of the ink ejected from the ejection head is reduced.

[0111] Furthermore, because the first buffer circuit can simultaneously write the first image data included in the base image data signal to the first buffer and read the second image data included in the base image data signal from the second buffer, it is possible to further increase the speed of signals propagated between the control circuit board and the head circuit board.

[0112] In one embodiment of the liquid dispensing device, The first image data may include information defining the driving conditions of the driving element.

[0113] In one embodiment of the liquid dispensing device, The control circuit board has a drive control signal output circuit that outputs a drive control signal that controls the driving of at least one of the ejection head and the head circuit board. The control signal output circuit may output the head control signal which includes the second image data and the drive control signal in serial.

[0114] This liquid ejection device allows for the serial propagation of drive control signals using the bandwidth secured by the increased speed of signals propagated between the control circuit board and the head circuit board. As a result, the number of signal lines in the cable can be reduced, and the risk of skew and electrical crosstalk between signals propagated through the cable is reduced, thereby improving the ejection accuracy of the ink ejected from the ejection head.

[0115] In one embodiment of the liquid dispensing device, The aforementioned control signal output circuit includes a multiplexer, The control signal output circuit may output the head control signal by multiplexing the second image data and the drive control signal with the multiplexer.

[0116] This liquid ejection device allows for the serial propagation of drive control signals using the bandwidth secured by the increased speed of signals propagated between the control circuit board and the head circuit board. As a result, the number of signal lines in the cable can be reduced, and the risk of skew and electrical crosstalk between signals propagated through the cable is reduced, thereby improving the ejection accuracy of the ink ejected from the ejection head.

[0117] In one embodiment of the liquid dispensing device, The drive control signal may include information that defines the signal waveform of the drive signal that drives the drive element.

[0118] In one embodiment of the liquid dispensing device, The drive control signal may include information defining the drive cycle of at least one of the ejection head and the head circuit board.

[0119] In one embodiment of the liquid dispensing device, The cable may be an optical communication cable, and the head control signal may be an optical signal.

[0120] This liquid ejection device reduces the risk of skew and electrical crosstalk between signals propagated through cables, resulting in improved ink ejection accuracy from the ejection head.

[0121] In one embodiment of the liquid dispensing device, The head circuit board is A conversion circuit that converts the head control signal input from the control circuit board into an image data signal, A second buffer circuit, which includes a third buffer and a fourth buffer, is capable of simultaneously writing first head control data included in the head control signal to the third buffer and reading second head control data included in the head control signal from the fourth buffer, A second buffer control circuit that controls the second buffer circuit, A discharge control circuit controls the discharge head based on the second head control data, It has, The second buffer circuit is, The first head control data is written to the third buffer at the second frequency, and the first head control data is read from the third buffer at the first frequency. The writing of the second head control data to the fourth buffer may be performed at the second frequency, and the reading of the second head control data from the fourth buffer may be performed at the first frequency.

[0122] According to this liquid ejection device, the second buffer circuit writes the first head control data to the third buffer at the second frequency, reads the first head control data from the third buffer at the first frequency, writes the second head control data to the fourth buffer at the second frequency, and reads the second head control data from the fourth buffer at the first frequency. As a result, the head circuit board can also reconstruct signals based on the base image data signal without changing the timing correlation. Consequently, the risk of discrepancies between the timing defined by the base image data signal and the timing controlled by the head circuit board and ejection head is further reduced, and the ejection accuracy of the ink ejected from the ejection head is further improved. In other words, even when the propagation speed is increased in response to an increase in the number of drive elements, the risk of a decrease in the ejection accuracy of the ink ejected from the ejection head is further reduced. [Explanation of symbols]

[0123] 1…Liquid dispensing device, 10…Control circuit board, 20…Dispensing head, 30…Head circuit board, 50…Drive signal output circuit, 52…Drive waveform selection circuit, 60…Piezoelectric element, 100…Main control circuit, 102…Dispensing control circuit, 104…Drive control circuit, 110…Dispensing command output circuit 120...Memory control circuit, 130...Clock circuit, 140...Dual port, 150...Multiplexer, 160...Interface circuit, 200...Drive signal selection circuit, 210...Selection control circuit, 212...Register, 214...Latch circuit, 216...Decoder, 230...Selection circuit, 232a,232b...Inverter, 234a,234b...Transfer gate, 310...Discharge control circuit, 320...Memory control circuit, 330...Clock circuit, 340...Dual port, 350...Demultiplexer, 360...Interface circuit, 600...Discharge unit, CB...Cable, M1,M2,M3,M4...Memory area

Claims

1. A dispensing head that dispenses liquid by driving a drive element and forms an image on a medium, A head circuit board that controls the discharge head, A control circuit board that outputs a head control signal for controlling the discharge head to the head circuit board, A cable connecting the head circuit board and the control circuit board, Equipped with, The aforementioned control circuit board is A base image data output circuit that outputs a base image data signal which forms the basis of the aforementioned image, A first buffer circuit comprising a first buffer and a second buffer, capable of simultaneously writing the first image data included in the base image data signal to the first buffer and reading the second image data included in the base image data signal from the second buffer, A first buffer control circuit that controls the first buffer circuit, A control signal output circuit that outputs the head control signal including the second image data, It has, The first buffer circuit is, The first image data is written to the first buffer at a first frequency, and the first image data is read from the first buffer at a second frequency higher than the first frequency. The writing of the second image data to the second buffer is performed at the first frequency, and the reading of the second image data from the second buffer is performed at the second frequency. The first image data includes information defining the driving conditions of the driving element, A liquid dispensing device characterized by the following features.

2. The control circuit board has a drive control signal output circuit that outputs a drive control signal that controls the driving of at least one of the ejection head and the head circuit board. The control signal output circuit outputs the head control signal which includes the second image data and the drive control signal in serial. The liquid dispensing device according to feature 1.

3. The aforementioned control signal output circuit includes a multiplexer, The multiplexer multiplexes the second image data and the drive control signal, causing the control signal output circuit to output the head control signal. The liquid dispensing device according to feature 2.

4. The drive control signal includes information defining the signal waveform of the drive signal that drives the drive element. The liquid dispensing device according to claim 2 or 3.

5. The drive control signal includes information defining the drive cycle of at least one of the ejection head and the head circuit board. A liquid dispensing device according to any one of claims 2 to 4.

6. The cable is an optical communication cable, and the head control signal is an optical signal. A liquid dispensing device according to any one of claims 1 to 5.

7. The head circuit board is A conversion circuit that converts the head control signal input from the control circuit board into an image data signal, A second buffer circuit comprising a third buffer and a fourth buffer, capable of simultaneously writing first head control data included in the head control signal to the third buffer and reading second head control data included in the head control signal from the fourth buffer, A second buffer control circuit that controls the second buffer circuit, Based on the second head control data, a discharge control circuit controls the discharge head, It has, The second buffer circuit is, The first head control data is written to the third buffer at the second frequency, and the first head control data is read from the third buffer at the first frequency. The writing of the second head control data to the fourth buffer is performed at the second frequency, and the reading of the second head control data from the fourth buffer is performed at the first frequency. A liquid dispensing device according to any one of claims 1 to 6.

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