Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

To provide a nitride semiconductor device and a method for manufacturing the nitride semiconductor device with which it is possible to suppress the decrease of field effect transistor characteristics.SOLUTION: The P-type impurity region that a field effect transistor of the nitride semiconductor device includes has a peak position at a location separate from an interface with a gate insulating film, where the concentration of P-type impurities is at the maximum. In the vertical direction of the interface, the distance from the interface to the peak position is 200 nm to 1500 nm inclusive. The concentration of the P-type impurities at the peak position is 5×1018 cm-3 or greater. The concentration of the P-type impurities in the interface of the impurity region is 1×1016 cm-3 to 3×1018 cm-3 inclusive. The impurity region has a flexion point between the interface and the peak position where the concentration of the P-type impurities stops increasing and begins to decrease toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurities at the flexion point is the concentration of the P-type impurities or lower at the peak position by at least 3×1018 cm-3.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device.

Background Art

[0002] When manufacturing a vertical MOSFET using gallium nitride (GaN), a technique is known in which Mg is ion-implanted into a GaN layer and heat-treated to form a P-type impurity region (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an N-type vertical MOSFET using GaN, in order to increase the breakdown voltage, it is necessary to provide a high-concentration P-type (hereinafter also referred to as P+) region at a deep position from the surface of the GaN layer. When forming the P+ type region by the ion implantation method, heat treatment is required to activate the P-type impurity after ion implantation. Due to this heat treatment, part of the P-type impurity diffuses from the deep position of the GaN layer to the surface side. When the concentration of the P-type impurity becomes unintentionally high on the surface of the GaN layer and in its vicinity, the characteristics may deteriorate, for example, the threshold voltage of the vertical MOSFET may become higher than necessary.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide a nitride semiconductor device and a method for manufacturing the nitride semiconductor device capable of suppressing deterioration of the characteristics of a field effect transistor.

Means for Solving the Problems

[0006] To solve the above problems, a nitride semiconductor device according to one aspect of the present invention comprises a gallium nitride layer having a first main surface and a second main surface located opposite the first main surface, and a field-effect transistor provided on the gallium nitride layer. The field-effect transistor comprises a gate insulating film provided on the first main surface side of the gallium nitride layer, and a P-type impurity region provided on the gallium nitride layer and in contact with the gate insulating film. The impurity region has a peak position (maximum point) where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the vertical direction perpendicular to the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of P-type impurities at the peak position is 5 × 10⁻¹⁶ 18 cm -3 That is all. The concentration of the P-type impurity at the interface in the impurity region is 1 × 10⁻⁶ 16 cm -3 The above 3 x 10 18 cm -3 The following applies: The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing toward the interface to decreasing toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10⁻⁶ 18 cm -3 The concentration value of the P-type impurity at the peak position is less than or equal to the above value.

[0007] A method for manufacturing a nitride semiconductor device according to an aspect of the present invention includes a step of ion-implanting a P-type impurity into a preset region of the gallium nitride layer from the first main surface side of the gallium nitride layer, a step of ion-implanting an inert element into the region from the first main surface side, and a step of heat-treating the gallium nitride layer into which the P-type impurity and the inert element are ion-implanted to activate the P-type impurity, thereby forming a P-type impurity region in the gallium nitride layer, and a step of forming a gate insulating film on the first main surface side of the gallium nitride layer in which the impurity region is formed. In the step of ion-implanting the P-type impurity, in a vertical direction perpendicular to the interface between the impurity region and the gate insulating film, a position from 200 nm to 1500 nm from the interface becomes the peak position of the ion implantation amount of the P-type impurity, and the concentration of the P-type impurity at the peak position of the ion implantation amount of the P-type impurity is 5×10 18 cm -3 or more after the heat treatment, and the P-type impurity is ion-implanted.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device capable of suppressing deterioration of characteristics of a field effect transistor.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. [Figure 3] FIG. 3 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to Embodiment 1 of the present invention. [Figure 4] FIG. 4 is an enlarged cross-sectional view showing the vertical MOSFET shown in FIG. 2. [Figure 5A] FIG. 5A is a cross-sectional view showing the manufacturing method of the vertical MOSFET according to Embodiment 1 of the present invention in the order of steps. [Figure 5B]Figure 5B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 1 of the present invention in order of steps. [Figure 5C] Figure 5C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 1 of the present invention in order of steps. [Figure 5D] Figure 5D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 1 of the present invention in order of steps. [Figure 5E] Figure 5E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 1 of the present invention in order of steps. [Figure 6] Figure 6 is a graph showing the distribution of Mg concentration in the depth direction of a GaN substrate according to an embodiment of the present invention. [Figure 7] Figure 7 is a graph showing the distribution of Mg concentration in the depth direction of a GaN substrate according to a comparative example of the present invention. [Figure 8] Figure 8 is a cross-sectional view showing a modified example 1 of the vertical MOSFET according to Embodiment 1 of the present invention. [Figure 9] Figure 9 is a plan view showing a modified example 2 of the vertical MOSFET according to Embodiment 1 of the present invention. [Figure 10] Figure 10 is a plan view showing an example of the configuration of a GaN semiconductor device according to Embodiment 2 of the present invention. [Figure 11] Figure 11 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device according to Embodiment 2 of the present invention. [Figure 12A] Figure 12A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 12B] Figure 12B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 12C] Figure 12C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 12D] Figure 12D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 12E]Figure 12E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 12F] Figure 12F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 2 of the present invention in order of steps. [Figure 13] Figure 13 is a plan view showing a modified example of a GaN semiconductor device according to Embodiment 2 of the present invention. [Modes for carrying out the invention]

[0010] Embodiments of the present invention are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0011] In the following explanation, the terms X-axis, Y-axis, and Z-axis may be used to describe directions. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10. The X-axis and Y-axis directions are also called the horizontal directions. The Z-axis direction is the normal direction to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other.

[0012] In the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0013] In the following explanation, the + and - symbols attached to P and N, which indicate the conductivity type of a semiconductor region, mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same P, this does not mean that the impurity concentrations of those regions are exactly the same.

[0014] <Embodiment 1> (Example configuration) Figure 1 is a plan view showing an example configuration of a gallium nitride (GaN) semiconductor device 100 (an example of a "nitride semiconductor device" of the present invention) according to Embodiment 1 of the present invention. Figures 2 and 3 are cross-sectional views showing an example configuration of the GaN semiconductor device 100 according to Embodiment 1 of the present invention. Figure 2 shows a cross-section obtained by cutting the plan view of Figure 1 along the line X1-X'1 parallel to the X axis. Figure 3 shows a cross-section obtained by cutting the plan view of Figure 1 along the line X2-X'2 parallel to the X axis. Figure 4 is an enlarged cross-sectional view showing the vertical MOSFET 1 shown in Figure 2. Note that in Figure 1, the gate electrode 44 and source electrode 54 shown in Figures 2 to 4 are omitted from the illustration.

[0015] The GaN semiconductor device 100 shown in Figures 1 to 4 is a power device. As shown in Figures 1 to 3, the GaN semiconductor device 100 is provided with a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1. The vertical MOSFETs 1 are an example of the "field-effect transistor" of the present invention. For example, the plurality of vertical MOSFETs 1 are repeatedly provided in one direction (for example, in the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and these unit structures are arranged in a line in one direction (for example, in the X-axis direction).

[0016] As shown in Figures 2 to 4, the vertical MOSFET 1 is a planar gate type MOSFET and has a gallium nitride substrate (an example of the "gallium nitride layer" of the present invention; hereinafter referred to as GaN substrate) 10, a gate insulating film 42, a gate electrode 44 provided on the gate insulating film 42, a source electrode 54 and a drain electrode 56.

[0017] The GaN substrate 10 (an example of the "gallium nitride layer" of the present invention) is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a surface 10a (an example of the "first main surface" of the present invention) and a back surface 10b (an example of the "second main surface" of the present invention) located on the opposite side of surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1 × 10⁻¹⁶ 7 cm -2 This is a low-dislocation self-supporting GaN substrate with a dislocation count of less than [value missing].

[0018] The N-type impurities (donor elements) contained in the GaN substrate 10 include at least one of silicon (Si) and oxygen (O). In addition, the P-type impurities (acceptor elements) contained in the GaN substrate 10 include at least one of magnesium (Mg) and beryllium (Be).

[0019] Because the GaN substrate 10 is a low-dislocation self-supporting GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, during the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0020] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N type, and the GaN layer may be N type or N- type.

[0021] In vertical MOSFET 1, the semiconductor material is GaN, but the semiconductor material may also contain one or more elements such as aluminum (Al) and indium (In). The semiconductor material may also be a mixed crystal semiconductor containing trace amounts of Al and In, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0022] The GaN substrate 10 is provided with a drift region 22, a P-type impurity region 23, a P++-type contact region 25, and an N+-type source region 26. The impurity region 23, the contact region 25, and the source region 26 are regions in which impurities are ion-implanted to a predetermined depth from the surface 10a of the GaN substrate 10, and the impurities are activated by heat treatment. For example, the impurity region 23 and the contact region 25 contain Mg as a P-type impurity. The drift region 22 and the source region 26 contain, for example, Si as an N-type impurity.

[0023] The P-type impurity region 23 is, for example, a P-type well region and includes a P+-type region 231 with a high Mg concentration (an example of the "concentration of P-type impurities" in this invention), a P--type region 233 with a lower Mg concentration than the P+-type region 231, a P-type region 232 with a lower Mg concentration than the P+-type region 231 and a higher Mg concentration than the P--type region 233, and a P---type region 234 with a lower Mg concentration than the P--type region 233.

[0024] The P+ type region 231 includes the peak position P1 where the Mg concentration is maximum. The P type region 232 includes the local peak position P2 where the Mg concentration is locally maximum. From the interface IF between the impurity region 23 and the gate insulating film 42 toward the peak position P1, the P-- type region 234, P type region 232, P- type region 233, and P+ type region 231 are arranged in this order. Since the vertical MOSFET 1 is a planar gate type, the above interface IF is parallel to the surface 10a of the GaN substrate 10.

[0025] Furthermore, the contact region 25 is a P++ type region. The concentration of P-type impurities is higher in the contact region 25 than in the impurity region 23. For example, the concentration of Mg in the impurity region 23 is 1 × 10⁻⁶ 16 cm -3 That concludes the explanation. The concentration of Mg in the contact area 25 is 5 × 10⁻⁶. 18 cm -3 The above 2 x 10 20 cm -3 The following applies:

[0026] The drift region 22 is an N-type region, and the source region 26 is an N+-type region. The source region 26 has a higher concentration of N-type impurities than the drift region 22. For example, the concentration of N-type impurities in the drift region 22 is the same as the concentration of N-type impurities in the GaN substrate 10. In this case, N-type impurities do not need to be ion-implanted in the drift region 22. The source region 26 is located on the surface side of the impurity region 23. The source region 26 is formed when Si is ion-implanted on the surface side of the impurity region 23 and activated by heat treatment.

[0027] As shown in Figures 2 to 4, the upper part of the source region 26 is exposed to the surface 10a of the GaN substrate 10. The bottom and first side of the source region 26 are in contact with the impurity region 23. Also, as shown in Figures 2 and 4, the second side of the source region 26 is in contact with the impurity region 23 and the contact region 25. The first side of the source region 26 is located on the Rch side of the region where the channel of the vertical MOSFET 1 is formed (hereinafter referred to as the channel region). The second side of the source region 26 is located on the opposite side of the first side in the X-axis direction.

[0028] For example, the first and second sides of the source region 26 are in contact with the P-- type region 234 of the impurity region 23 in a direction parallel to the interface IF. The channel of the vertical MOSFET 1 is formed in the P-- type region 234 adjacent to the first side of the source region 26. In addition, the bottom of the source region 26 and the bottom of the contact region 25 are in contact with the P-- type region 232 of the impurity region 23.

[0029] Furthermore, the P+ type region 231 is in contact with the drift region 22. This reduces charge concentration on the gate insulating film 42 and the P-- type region 234, thereby increasing the breakdown voltage of the vertical MOSFET 1.

[0030] The impurity region 23 and the source region 26 have a stripe shape extending in the Y-axis direction when viewed from above. The contact region 25 is arranged at regular intervals in the X-axis direction and the Y-axis direction, for example.

[0031] As shown in Figure 4, the upper part (hereinafter referred to as the upper region) 221 of the drift region 22 is exposed to the surface 10a of the GaN substrate 10. The upper region 221 is in contact with the gate insulating film 42 on the surface 10a. The upper region 221 is X It is located between a pair of impurity regions 23 that face each other in the axial direction. The upper region 221 may also be called the JFET region.

[0032] The lower part of the drift region 22 (hereinafter referred to as the lower region) 222 is in contact with the bottom of the impurity region 23. The lower region 222 is located between the upper region 221 and the drain electrode 56, and between the impurity region 23 and the drain electrode 56. The lower region 222 may be provided continuously in the Y-axis direction between multiple vertical MOSFETs 1 (i.e., multiple unit structures) that are repeated in the Y-axis direction.

[0033] The drift region 22 functions as a current path between the drain electrode 56 and the channel region Rch. The upper region (JFET region) 221 of the drift region 22 may have a higher N-type concentration than the lower region 222, for example, by ion implantation of N-type impurities. For example, the JFET region 221 may be N-type. This makes it possible to reduce the on-resistance of the vertical MOSFET 1.

[0034] The contact region 25 is in contact with the impurity region 23 and has the function of fixing the potential of the impurity region 23 to the potential of the source electrode 54 (for example, ground potential). The contact region 25 also functions as a hole extraction path when the gate is off.

[0035] The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film). The gate insulating film 42 is provided, for example, on a flat surface 10a.

[0036] The gate electrode 44 is located above the channel region Rch via a gate insulating film 42. In the vertical MOSFET 1, the gate electrode 44 is a planar type located on a flat gate insulating film 42. The gate electrode 44 is formed of impurity-doped polysilicon.

[0037] The source electrode 54 is provided on the surface 10a of the GaN substrate 10. The source electrode 54 is in contact with a part of the source region 26 and the contact region 25. The source electrode 54 may also be provided on the gate electrode 44 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 44 so that the gate electrode 44 and the source electrode 54 are not electrically connected.

[0038] The source electrode 54 is made of, for example, an alloy of Al or Al-Si. The source electrode 54 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer. The drain electrode 56 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the back surface 10b. The drain electrode 56 is made of the same material as the source electrode 54.

[0039] In the vertical MOSFET 1, when a potential greater than or equal to a threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the channel region Rch. With the inversion layer formed in the channel region Rch, if a predetermined high potential is applied to the drain electrode 56 and a low potential (e.g., ground potential) is applied to the source electrode 54, current flows from the drain electrode 56 to the source electrode 54. Conversely, when a potential lower than the threshold voltage is applied to the gate electrode 44, an inversion layer is not formed in the channel region Rch, and the current is interrupted. As a result, the vertical MOSFET 1 can switch the current between the drain electrode 56 and the source electrode 54.

[0040] (Manufacturing method) Next, a method for manufacturing a vertical MOSFET 1 according to Embodiment 1 of the present invention will be described. Figures 5A to 5E are cross-sectional views showing the manufacturing method for a vertical MOSFET 1 according to Embodiment 1 of the present invention in order of steps. The vertical MOSFET 1 is manufactured using various manufacturing equipment such as an ion implantation apparatus, a heat treatment apparatus, a film deposition apparatus, an exposure apparatus, and an etching apparatus.

[0041] As shown in Figure 5A, the manufacturing apparatus ion-implants Mg as a P-type impurity into the region 23' of the GaN substrate 10 where a P-type impurity region 23 (see Figure 4) is planned to be formed (hereinafter referred to as the P-type formation region) 23', from the surface 10a side of the GaN substrate 10. The P-type formation region 23' is an example of a "pre-set region" in the present invention.

[0042] For example, the manufacturing apparatus forms a mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the P-type formation region 23' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M1 is formed.

[0043] In the Mg ion implantation process shown in Figure 5A, the Mg implantation energy (acceleration voltage) and dose are set such that the peak position P1, where the amount of Mg ion implanted is maximum, is at a distance d1 from the surface 10a of the GaN substrate 10 in the vertical direction perpendicular to the surface 10a (for example, the Z-axis direction), and the Mg concentration at the peak position P1 is a predetermined value. The distance d1 from the surface 10a of the GaN substrate 10 to the peak position P1 is between 200 nm and 1500 nm, and as an example, between 500 nm and 1500 nm. The predetermined value mentioned above is 5 × 10⁻¹⁰ after the heat treatment for Mg activation (see Figure 5C below). 18 cm -3 The above is preferable to 8 × 10 18 cm -3 That is all. far1×10 19 cm -3 That's all.

[0044] The Mg ion implantation process shown in Figure 5A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0045] Furthermore, in the process shown in Figure 5A, before or after the Mg ion implantation process, the manufacturing apparatus ion implants an inert element (for example, at least one of nitrogen (N) and argon (Ar)) into the P-type formation region 23' from the surface 10a side of the GaN substrate 10. For example, the manufacturing apparatus ion implants N as an inert element into the P-type formation region 23' from the surface 10a side of the GaN substrate 10. In this N ion implantation process, the implantation energy (acceleration voltage) for N is set so that the peak position of the N ion implantation amount coincides with the peak position P1 of the Mg ion implantation amount in the direction perpendicular to the surface 10a of the GaN substrate 10 (for example, the Z-axis direction). The N ion implantation creates vacancies in the Mg implantation region (the region between the surface 10a of the GaN substrate 10 and the peak position P1 of Mg).

[0046] In addition, during the N ion implantation process, the N implantation energy (acceleration voltage) may be set such that the peak position of the N ion implantation amount in the direction perpendicular to the surface 10a of the GaN substrate 10 (for example, in the Z-axis direction) is between the surface 10a of the GaN substrate 10 (i.e., the position that becomes the interface IF described above) and the peak position P1 of the Mg ion implantation amount.

[0047] The amount of N ion implanted is between 0.1 and 10 times the amount of Mg ion implanted. For example, the implantation energy and dose of N may be set such that the peak position of the N ion implantation coincides with the peak position P1 of the Mg ion implantation, and the amount of N ion implanted at peak position P1 is the same as the amount of Mg ion implantation (i.e., 1 times).

[0048] Similar to the Mg ion implantation process, the N ion implantation process may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0049] In the process shown in Figure 5A, after Mg and N are successively ion-implanted, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

[0050] Next, as shown in Figure 5B, the manufacturing apparatus ion-implants Si as an N-type impurity into the region 26' of the GaN substrate 10 where the N-type source region 26 (see Figure 4) is to be formed (hereinafter referred to as the source formation region). For example, the manufacturing apparatus forms a mask M2 on the GaN substrate 10. The mask M2 is an SiO2 film or a photoresist. The mask M2 has a shape that opens above the source formation region 26' and covers the top of other regions. The manufacturing apparatus ion-implants an N-type impurity (e.g., silicon (Si) or oxygen (O)) into the GaN substrate 10 on which the mask M2 is formed. After ion implantation, the manufacturing apparatus removes the mask M2 from the GaN substrate 10.

[0051] Furthermore, before or after the ion implantation step of N-type impurities into the source formation region 26', the manufacturing apparatus ion implants Mg as a P-type impurity into the region of the GaN substrate 10 where the contact region 25 (see Figures 1 and 3) is to be formed (hereinafter referred to as the contact formation region). For example, the manufacturing apparatus forms a mask (not shown) on the GaN substrate 10. This mask is an SiO2 film or a photoresist. This mask has a shape that opens above the contact formation region and covers above other regions. The manufacturing apparatus ion implants Mg into the GaN substrate 10 on which this mask is formed.

[0052] Next, as shown in Figure 5C, the manufacturing apparatus forms an insulating protective film 61 on the surface 10a of the GaN substrate 10. The protective film 61 has the function of preventing nitrogen atoms from being released from the GaN substrate 10 during heat treatment. Nitrogen vacancies are formed at the locations where nitrogen atoms are released from the GaN substrate 10. Since nitrogen vacancies can function as donor-type defects, the expression of P-type properties may be inhibited. To prevent this, the manufacturing apparatus provides a protective film 61 on the GaN substrate 10.

[0053] The protective film 61 preferably has high heat resistance, good adhesion to the GaN substrate 10, prevents impurities from diffusing from the protective film 61 to the GaN substrate 10, and is selectively removable from the GaN substrate 10. The protective film 61 is an aluminum nitride (AlN) film, an SiO2 film, or a silicon nitride (SiN) film. The protective film 61 may be a laminated film containing at least one of the AlN film, SiO2 film, and SiN film. In addition, an insulating film serving as a base for the protective film 61 may be provided between the GaN substrate 10 and the protective film 61. An example of the insulating film serving as the base is an SiO2 film.

[0054] Next, the manufacturing apparatus applies a heat treatment to the GaN substrate 10 covered with the protective film 61, with a maximum temperature of 800°C to 2000°C. This heat treatment is, for example, a rapid heating treatment. This heat treatment activates the P-type impurities (e.g., Mg) and N-type impurities (e.g., Si or O) introduced into the GaN substrate 10. As a result, as shown in Figure 5C, a P-type impurity region 23, an N+-type source region 26, and a P++-type contact region 25 (see Figures 1 and 3) are formed on the GaN substrate 10, and a drift region 22 is defined. Furthermore, this heat treatment can recover to some extent defects in the GaN substrate 10 caused by ion implantation. After the heat treatment, the manufacturing apparatus removes the protective film 61 from the GaN substrate 10.

[0055] In the heat treatment process for activation shown in Figure 5C, Mg diffuses along the vacancies formed by N ion implantation, and Mg is also trapped in these vacancies (vacancy-guided diffusion). During the heat treatment for activation, a Mg trapping region is formed by vacancies between the Mg peak position P1 and the surface 10a of the GaN substrate 10, thus suppressing the diffusion of Mg from the Mg implantation peak position P1 to the surface 10a of the GaN substrate 10.

[0056] Next, as shown in Figure 5D, the manufacturing apparatus forms a gate insulating film 42 on the GaN substrate 10. Then, as shown in Figure 5E, the manufacturing apparatus forms a gate electrode 44, a source electrode 54, and a drain electrode 56 (see Figure 4). Through these steps, the vertical MOSFET 1 shown in Figures 1 to 4 is completed.

[0057] (Experimental results) The experimental results regarding the distribution of Mg concentration in the depth direction of the GaN layer are shown below. Figure 6 is a graph showing the distribution of Mg concentration in the depth direction of a GaN substrate according to an embodiment of the present invention. Figure 7 is a graph showing the distribution of Mg concentration in the depth direction of a GaN substrate according to a comparative example of the present invention. The horizontal axis in Figures 6 and 7 represents the depth (nm) from the surface of the GaN layer. The vertical axis in Figures 6 and 7 represents the Mg concentration (cm-3) in the GaN layer.

[0058] In the example shown in Figure 6, Mg ion implantation was performed with an acceleration voltage of 700 keV (single-stage implantation) and a Mg dose of 4.2 × 10⁻⁶ 14 cm -2 The procedure is carried out under the following conditions, and N ion implantation is performed with an acceleration voltage of 580 keV (single-stage implantation) and a dose of N of 3 × 10⁻¹⁶. 14 cm -2 The experiment was conducted under the specified conditions. The Mg concentration in the depth direction of the GaN substrate was measured using SIMS (Secondary Ion Mass Spectrometry) both before and after the heat treatment for activation.

[0059] In the comparative example shown in Figure 7, Mg ion implantation was performed under the same conditions as in the example, while N ion implantation was not performed. The Mg concentration in the depth direction of the GaN substrate was measured by SIMS before and after the heat treatment for activation.

[0060] As shown in Figures 6 and 7, it was found that in the examples and comparative examples, the heat treatment described above tended to cause Mg to diffuse towards the surface side of the GaN layer. However, in the examples, after the heat treatment, a local peak position P2 appeared between the surface of the GaN substrate and the peak position P1 of the Mg ion implantation where the Mg concentration was maximum, resulting in a local peak position P2 of Mg being locally maximum. It is thought that the local peak position P2 of Mg is formed when vacancies formed by N ion implantation cluster during the heat treatment, and Mg is trapped in that region.

[0061] In this example, Mg is trapped between the surface of the GaN substrate and the peak position P1. As a result, it was found that in this example, the Mg concentration on the surface of the GaN substrate and the Mg concentration at the peak position P1 can be maintained at concentrations close to those at the time of Mg ion implantation (i.e., before heat treatment).

[0062] In contrast, in the comparative example, N ion implantation is not performed, and no vacancies are formed due to N ion implantation. Therefore, as shown in Figure 7, the local peak position P2 of Mg, as in the example, is not formed in the comparative example. It was found that the Mg ion-implanted in the GaN substrate diffuses vigorously to the surface side of the GaN substrate by heat treatment, and the Mg concentration on the surface of the GaN substrate becomes high after heat treatment.

[0063] High Mg concentration on and near the surface of a GaN substrate can raise the threshold voltage of an N-type vertical MOSFET, potentially degrading its performance. For example, a threshold voltage of 3V or higher is required for a vertical MOSFET to operate normally off, but a higher threshold voltage reduces mobility. There is a trade-off between the threshold voltage and mobility. A decrease in mobility is undesirable from a vertical MOSFET's performance standpoint.

[0064] Furthermore, in the comparative example, the Mg concentration at peak position P1', where the Mg concentration is maximum after Mg ion implantation, also tended to decrease after heat treatment. As can be seen by comparing Figures 6 and 7, this tendency was more pronounced in the comparative example than in the example. A large decrease in Mg concentration at peak position P'1 reduces the width of the depletion layer extending from the P+-type region including peak position P'1 to the N-type GaN substrate, which may lead to a decrease in the breakdown voltage of the vertical MOSFET.

[0065] (Effects of the embodiment) As described above, the GaN semiconductor device 100 according to Embodiment 1 of the present invention comprises a GaN substrate 10 and a planar gate type vertical MOSFET 1 provided on the GaN substrate 10. The GaN substrate 10 has a surface 10a and a back surface 10b located on the opposite side of the surface 10a. The vertical MOSFET 1 comprises a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10 and a P-type impurity region 23 provided on the GaN substrate 10 and in contact with the gate insulating film 42.

[0066] The P-type impurity region 23 is, for example, a P-type well region, and has a peak position P1 at a location away from the interface IF between the impurity region 23 and the gate insulating film 42 where the concentration of P-type impurities (e.g., Mg) is maximum. In the vertical direction (e.g., the Z-axis direction) perpendicular to the interface IF between the impurity region 23 and the gate insulating film 42, the distance d1 from the interface IF to the peak position P1 is between 200 nm and 1500 nm. The Mg concentration at the peak position P1 is 5 × 10⁻¹⁴ 18 cm -3 That concludes the explanation. The Mg concentration at interface IF in impurity region 23 is 1 × 10⁻⁶. 16 cm -3 The above 3 x 10 18 cm -3 The following applies:

[0067] Furthermore, the impurity region 23 has inflection points between the interface IF and the peak position P1, at positions away from both the interface IF and the peak position P1, where the Mg concentration changes from increasing to decreasing toward the interface IF, or where the rate of decrease toward the interface IF increases. These inflection points are the starting points where the Mg concentration decreases sharply toward the interface IF. These inflection points are, for example, local peak positions P2 where the Mg concentration is locally maximum. The Mg concentration at the local peak position P2, which is an inflection point, is 3 × 10⁻⁶. 18 cm -3 The above values ​​are below the Mg concentration value at peak position P1.

[0068] The local peak position P2 is formed when Mg is trapped in vacancies during the heat treatment to activate Mg. The local peak position P2 is a convex region in which the Mg profile is inflected, as shown in Figure 6, for example. The formation of the local peak position P2 suppresses Mg diffusion toward the surface 10a side of the GaN substrate 10, and the Mg concentration at and near the interface IF between the surface 10a of the GaN substrate 10 and the gate insulating film 42 is kept low. This makes it possible to suppress, for example, an unintended increase in the threshold value or an unintended decrease in mobility of the N-type vertical MOSFET 1, and makes it easier to control these values ​​within an appropriate range. As a result, it is possible to provide a vertical MOSFET 1 with suppressed performance degradation.

[0069] Furthermore, the Mg concentration at the peak position P1 of the GaN substrate 10 is 5 × 10⁻⁶. 18 cm -3 The above is preferable to 8 × 10 18 cm -3 That is all. far1×10 19 cm -3 This concludes the explanation. This makes it possible to provide a vertical MOSFET 1 with a high voltage resistance.

[0070] A method for manufacturing a GaN semiconductor device 100 according to Embodiment 1 of the present invention comprises the steps of: ion implanting Mg into a predetermined region (for example, a P-type formation region 23') of the GaN substrate 10 from the surface 10a side of the GaN substrate 10; ion implanting N into the P-type formation region 23' from the surface 10a side of the GaN substrate 10; heat treating the GaN substrate 10 in which Mg and N have been ion-implanted to activate the Mg and form a P-type impurity region 23 in the GaN substrate 10; and forming a gate insulating film 42 on the surface 10a side of the GaN substrate 10 in which the P-type impurity region 23 has been formed. In the step of ion implanting Mg, in the vertical direction (for example, the Z-axis) perpendicular to the interface IF between the impurity region 23 and the gate insulating film 42, the peak position P1 of the Mg ion implantation amount is at a position between 200 nm and 1500 nm from the interface IF, and the Mg concentration after heat treatment at the peak position P1 is 5 × 10⁻¹⁰ 18 cm -3 Mg is ion-implanted to achieve the above result.

[0071] According to this method, by ion implanting N from the surface 10a side of the GaN substrate 10, a large number of vacancies can be introduced into the GaN substrate 10. During the heat treatment to activate Mg, these vacancies cluster between the surface 10a of the GaN substrate 10 and the peak position P1, capturing Mg. As a result, as shown in Figure 6, for example, a local peak position P2 can be formed between the surface 10a of the GaN substrate 10 and the peak position P1, where the Mg concentration is locally maximum.

[0072] During heat treatment, Mg is captured at the local peak position P2, thus suppressing Mg diffusion from the local peak position P2 to the surface 10a of the GaN substrate 10. This allows the Mg concentration on the surface 10a of the GaN substrate 10 to be maintained at a concentration close to that at the time of ion implantation (i.e., before heat treatment). This makes it easy to control the threshold and mobility of the N-type vertical MOSFET 1 within an appropriate range, making it possible to provide a vertical MOSFET 1 with suppressed performance degradation.

[0073] Furthermore, as shown in Figure 6, for example, the Mg concentration at the peak position P1 of the GaN substrate 10 can be maintained at a concentration close to that at the time of Mg ion implantation (i.e., before heat treatment). This makes it possible to widen the width of the depletion layer extending from the P+ type region 231 including the peak position P1 to the drift region 22, thereby providing a vertical MOSFET 1 with a high breakdown voltage.

[0074] (modified version) (1) Variation 1 In the above embodiment, for example, as shown in Figure 4, a configuration was shown in which the P-type region 232, which is part of the P-type impurity region 23, is in contact with the bottom of the source region 26. However, in Embodiment 1 of the present invention, the positional relationship between the P-type region 232 and the source region 26 is not limited to this.

[0075] Figure 8 is a cross-sectional view showing a modified example 1 of the vertical MOSFET 1 according to Embodiment 1 of the present invention. As shown in Figure 8, in the vertical MOSFET 1 according to Embodiment 1, the P-type region 232 may be in contact with the side of the source region 26, rather than the bottom. Even with this configuration, a local peak position P2 exists between the P+-type region 231 and the interface IF. As a result, Modified Example 1 achieves the same effects as the Embodiment.

[0076] (2) Modification example 2 In the above embodiment, as shown in Figure 1, a configuration was shown in which multiple contact regions 25 are arranged in a line along the X-axis in a plan view. However, in Embodiment 1 of the present invention, the arrangement of the contact regions 25 is not limited to this.

[0077] Figure 9 is a plan view showing a modified example 2 of the vertical MOSFET 1 according to Embodiment 1 of the present invention. As shown in Figure 9, in the vertical MOSFET 1 according to Embodiment 1, the multiple contact regions 25 may be arranged in a line along the X-axis direction with alternating misalignments in the Y-axis direction. That is, one contact region 25 and the other contact region 25 adjacent to each other across the N-type JFET region 211 may be arranged to face each other in a direction tilted with respect to the X-axis direction in a plan view. Even with such a configuration, the source electrode 54 can be ohmic connected to the impurity region 23 via the contact region 25. Modified example 2 has the same effects as the above embodiment.

[0078] (Embodiment 2) In the above-described Embodiment 1, the vertical MOSFET 1 was described as having a planar gate structure. However, in embodiments of the present invention, the vertical MOSFET is not limited to a planar gate structure. In embodiments of the present invention, the vertical MOSFET may be a trench gate type in which the gate electrode is arranged in a trench provided in a GaN substrate via a gate insulating film.

[0079] (Example configuration) Figure 10 is a plan view showing an example configuration of a GaN semiconductor device 100A (an example of the "nitride semiconductor device" of the present invention) according to Embodiment 2 of the present invention. Figure 11 is a cross-sectional view showing an example configuration of a GaN semiconductor device 100A according to Embodiment 2 of the present invention. Figure 11 shows a cross-section obtained by cutting the plan view of Figure 10 along the line X3-X'3 parallel to the X axis.

[0080] The GaN semiconductor device 100A shown in Figures 10 and 11 is a power device. The GaN semiconductor device 100A is provided with vertical MOSFETs 1A (an example of the "field-effect transistor" of the present invention). Multiple vertical MOSFETs 1A are repeatedly provided in one direction (for example, in the X-axis direction). One vertical MOSFET 1A is a repeating unit structure, and these unit structures are arranged in a line in one direction (for example, in the X-axis direction).

[0081] The vertical MOSFET 1A is a trench-gate type MOSFET and has a trench H provided in the gallium nitride substrate 10. The trench H opens to the surface 10a side of the GaN substrate 10. The bottom surface of the trench H reaches an N-type drift region 22. A gate electrode 44 is located within this trench H via a gate insulating film 42. The channel of the vertical MOSFET 1A is formed in a P--type region 234 along the side surface of the trench H.

[0082] In the vertical MOSFET 1A, the P+ type region 231 is provided in the depth direction (for example, in the Z-axis direction) from the surface 10a side of the GaN substrate 10. For example, the P+ type region 231 is formed to a deeper position from the surface 10a of the GaN substrate 10 compared to the trench H. The P+ type region 231 can alleviate charge concentration in the gate insulating film 42 and the P-- type region 234 at the bottom of the trench H, thereby increasing the breakdown voltage of the vertical MOSFET 1A.

[0083] Furthermore, in the vertical MOSFET 1A, the P+-type region 231 partially faces the surface 10a of the GaN substrate 10 and is in contact with the source electrode 54. As a result, the potential of the impurity region 23, which includes the P+-type region 231, is fixed at the potential of the source electrode 54 (for example, the ground potential).

[0084] (Manufacturing method) Next, a method for manufacturing a vertical MOSFET 1 according to Embodiment 2 of the present invention will be described. Figures 12A to 12F are cross-sectional views showing the manufacturing method of a vertical MOSFET 1A according to Embodiment 2 of the present invention in order of steps.

[0085] As shown in Figure 12A, the manufacturing apparatus ion-implants Mg as a P-type impurity into the region 23' of the GaN substrate 10 where a P-type impurity region 23 (see Figure 11) is to be formed (i.e., the P-type formation region) 23', from the surface 10a side of the GaN substrate 10.

[0086] Next, as shown in Figure 12B, the manufacturing apparatus forms a mask M11 on the surface 10a of the GaN substrate 10. The mask M11 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M11 has a shape that opens above the region 231' where the P+ type region 231 is to be formed (hereinafter referred to as the P+ type formation region) and covers the other regions. In the X-axis direction, if the distance from the region H' where the trench H is to be formed (hereinafter referred to as the trench formation region) to the mask M11 is d11, then d11 is between 200 nm and 1500 nm, and as an example, between 500 nm and 1500 nm.

[0087] Next, the manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M11 is formed. In this ion implantation process, for example, the Mg implantation energy (acceleration voltage) and dose are set so that the Mg concentration in the area exposed from the mask M11 in the P-type formation region 23' is a predetermined value. The predetermined value is 5 × 10⁻¹⁰ after the heat treatment for Mg activation (see Figure 12D described later). 18 cm -3 The above is preferable to 8 × 10 18 cm -3 That is all. far1×10 19 cm -3 That concludes the explanation. The Mg ion implantation process may be carried out as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0088] Furthermore, in the process shown in Figure 12B, before or after the Mg ion implantation process, the manufacturing apparatus ion implants an inert element (for example, nitrogen (N) or argon (Ar)) into the GaN substrate 10 on which the mask M11 is formed. For example, the manufacturing apparatus ion implants N as an inert element into the P-type formation region 23' from the surface 10a side of the GaN substrate 10.

[0089] In this nitrogen (N) ion implantation process, the N implantation energy (acceleration voltage) and dose may be set to produce a profile similar to that of the magnesium (Mg) ion implantation process. Furthermore, similar to the Mg ion implantation process, the N ion implantation process may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. The N ion implantation amount is, for example, between 0.1 and 10 times the Mg ion implantation amount.

[0090] In the process shown in Figure 12B, after Mg and N are successively ion-implanted, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

[0091] Next, as shown in Figure 12C, the manufacturing apparatus ion-implants Si as an N-type impurity into the region 26' of the GaN substrate 10 where the N-type source region 26 (see Figure 11) is to be formed (i.e., the source formation region).

[0092] Next, as shown in Figure 12D, the manufacturing apparatus forms a protective film 61 on the surface 10a of the GaN substrate 10. Then, the manufacturing apparatus applies a heat treatment to the GaN substrate 10 covered with the protective film 61 at a maximum temperature of 800°C to 2000°C. This heat treatment is, for example, a rapid heating treatment. This heat treatment activates the P-type impurities (e.g., Mg) and N-type impurities (e.g., Si or O) introduced into the GaN substrate 10, forming a P-type impurity region 23 and an N+-type source region 26 in the GaN substrate 10, and defining a drift region 22. This heat treatment also allows for some degree of recovery of defects caused by ion implantation in the GaN substrate 10. After the heat treatment, the manufacturing apparatus removes the protective film 61 from the GaN substrate 10.

[0093] Next, as shown in Figure 12E, the manufacturing apparatus etches the GaN substrate 10 from the surface 10a side to form a trench H. Then, as shown in Figure 12F, the manufacturing apparatus sequentially forms the gate insulating film 42 and the gate electrode 44 within the trench. The manufacturing apparatus also forms the source electrode 54 (see Figure 11) and the drain electrode 56 (see Figure 11). Through these processes, the vertical MOSFET 1A shown in Figures 10 and 11 is completed.

[0094] (Effects of Embodiment 2) As described above, the GaN semiconductor device 100A according to Embodiment 2 of the present invention comprises a GaN substrate 10 and a trench gate type vertical MOSFET 1A provided on the GaN substrate 10. In the trench-gate vertical MOSFET 1A, the side of the trench H becomes the interface IF between the impurity region 23 and the gate insulating film 42. The vertical MOSFET 1A has a peak position P1 where the Mg concentration is maximum, located away from this interface IF in the X-axis direction. In the vertical direction perpendicular to the interface IF (i.e., the X-axis direction), the distance d11 from the interface IF to the peak position P1 is between 200 nm and 1500 nm. The Mg concentration at the peak position P1 is 5 × 10⁻¹⁰ 18 cm -3 That concludes the explanation. The Mg concentration at interface IF in impurity region 23 is 1 × 10⁻⁶. 16 cm -3 The above 3 x 10 18 cm -3 The following applies:

[0095] Furthermore, the impurity region 23 has a local peak position P2 located between the interface IF and peak position P1, and at positions away from both the interface IF and peak position P1, where the Mg concentration is locally maximum. The local peak position P2 is a convex region where the Mg profile is inflected, as shown in Figure 6, for example. The Mg concentration at the local peak position P2 is 3 × 10⁻⁶. 18 cm -3 The above values ​​are below the Mg concentration value at peak position P1.

[0096] In the GaN semiconductor device 100A, a local peak position P2 exists between the side surface of the trench H and the peak position P1 where the Mg concentration is maximum. The local peak position P2 is formed when Mg is trapped in vacancies during the heat treatment to activate Mg. The formation of the local peak position P2 suppresses Mg diffusion to the side surface of the trench H, and the Mg concentration at the interface IF and its vicinity is kept low. As a result, similar to Embodiment 1, it becomes easy to control the threshold and mobility of the vertical MOSFET 1A within an appropriate range, making it possible to provide a vertical MOSFET 1A with suppressed performance degradation.

[0097] Furthermore, in the GaN semiconductor device 100A, the Mg concentration in the P+-type region 231 can be maintained at a concentration close to that at the time of Mg ion implantation (i.e., before heat treatment). This allows for a wider depletion layer extending from the P+-type region 231 to the drift region 22, making it possible to provide a vertical MOSFET 1A with a high breakdown voltage.

[0098] (modified version) Figure 13 is a plan view showing a modified example of the GaN semiconductor device 100A according to Embodiment 2 of the present invention. As shown in Figure 13, in the P+ type region 231, the regions facing the surface 10a of the GaN substrate 10 (i.e., the regions in contact with the source electrode 54) may be arranged in a line along the X-axis in a plan view. Even in this configuration, the same effects as those of Embodiment 2 shown in Figures 10 and 11 are achieved.

[0099] <Other Embodiments> As described above, the present invention has been described by embodiments and modifications, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure. Of course, the present invention includes various embodiments and the like that are not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the embodiments and modifications described above. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist. The technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable from the above description.

[0100] Furthermore, the present invention can also take the following configuration. (1) A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10 18 cm -3 That's all. The concentration of the P-type impurity at the interface of the impurity region is 1 × 10 16 cm -3 The above 3 x 10 18 cm -3 The following: The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing towards the interface to decreasing, or the rate of decrease towards the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10 18 cm -3 The above describes a nitride semiconductor device in which the concentration value of the P-type impurity at the peak position is less than or equal to the above value. (2) The nitride semiconductor device according to (1), wherein the inflection point is a local peak position where the concentration of the P-type impurity is locally maximum. (3) The nitride semiconductor device according to (1) or (2), wherein the P-type impurity comprises at least one of Mg and Be. (4) The concentration of the P-type impurity at the aforementioned peak position is 8 × 10 18 cm -3 The nitride semiconductor device described in any one of the above items (1) to (3). (5) The nitride semiconductor device according to any one of (1) to (4) above, wherein the gate insulating film is an SiO2 film. (6) The aforementioned impurity region is, The P+ type region is characterized by a high concentration of the aforementioned P-type impurities, The P-type region is one in which the concentration of the P-type impurity is lower than that of the P+-type region, A P-type region in which the concentration of the P-type impurity is lower than that of the P+-type region and higher than that of the P--type region, The region has a P--type region in which the concentration of the P-type impurity is lower than that of the P-type region, The P+ type region includes the peak position, The P-type region includes the inflection point, A nitride semiconductor device according to any one of (1) to (5), wherein the P--type region, the P-type region, the P-type region, and the P+-type region are arranged in this order from the interface toward the peak position. (7) The gallium nitride layer further comprises an N-type source region, The nitride semiconductor device according to (6), wherein the source region is in contact with the P-- type region in a direction parallel to the interface. (8) The nitride semiconductor device according to (7), wherein the impurity region is interposed between the source region and the second main surface of the gallium nitride layer. (9) The nitride semiconductor device according to any one of (1) to (8), wherein the interface is parallel to the first main surface of the gallium nitride layer. (10) The nitride semiconductor device according to any one of (1) to (9), wherein the field-effect transistor is a planar gate type vertical MOSFET in which a gate electrode is disposed on the first main surface via the gate insulating film. (11) The gallium nitride layer has trenches provided from the first main surface toward the second main surface, The nitride semiconductor device according to any one of (1) to (9), wherein the field-effect transistor is a trench-gate type vertical MOSFET in which a gate electrode is arranged in the trench via the gate insulating film. (12) A step of ion implanting P-type impurities into a predetermined region of the gallium nitride layer from the first main surface side of the gallium nitride layer, A step of ion implanting an inert element into the region from the first main surface side, A step of subjecting the gallium nitride layer, which has been ion-implanted with the P-type impurities and the inert element, to heat treatment to activate the P-type impurities and form a P-type impurity region in the gallium nitride layer, The process includes forming a gate insulating film on the first main surface side of the gallium nitride layer on which the impurity region is formed, In the process of ion implanting the P-type impurity, In a vertical direction intersecting the interface between the impurity region and the gate insulating film, the peak position of the ion implantation amount of the P-type impurity is at a position between 200 nm and 1500 nm from the interface, and The concentration of the P-type impurity at the peak position of the ion implantation amount of the P-type impurity is 5 × 10 after the heat treatment. 18 cm -3 A method for manufacturing a nitride semiconductor device, wherein the P-type impurity is ion-implanted as described above. (13) In the process of ion implanting the aforementioned inert element, A method for manufacturing a nitride semiconductor device according to (12), wherein the inert element is ion-implanted such that the peak position of the ion implantation amount of the inert element in the vertical direction coincides with the peak position of the ion implantation amount of the P-type impurity. (14) In the process of ion implanting the aforementioned inert element, The method for manufacturing a nitride semiconductor device according to (12), wherein the inert element is ion-implanted such that the peak position of the ion implantation amount of the inert element in the vertical direction is between the interface and the peak position of the ion implantation amount of the P-type impurity. (15) The method for manufacturing a nitride semiconductor device according to any one of (12) to (14), wherein the inert element comprises at least one of N and Ar. (16) The method for manufacturing a nitride semiconductor device according to any one of (12) to (15), wherein the maximum temperature of the heat treatment is 800°C or more and 2000°C or less. [Explanation of Symbols]

[0101] 1. 1A Vertical MOSFET 10 GaN substrates 10a surface 10b back side 22 Drift region 23´ P-type formation area 23 Impurity region 25 Contact area 26' Source formation region 26 Source Area 26 Source formation region 42 Gate insulating film 44 gate 54 Source electrodes 56 Drain electrode 61 Protective film 100, 100A GaN semiconductor device 221 Upper area (JFET area) 222 Lower area 231´ P+ type formation area 231 P+ type region 232 P-type region 233 P-type region 234 P--type region d1, d11 distance H Trench formation region H Trench IF interface M1, M2, M11 Masks P1', P1, P2 Local peak locations Rch channel region

Claims

1. A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10 １８ cm －３ That's all. The concentration of the P-type impurity at the interface in the impurity region is 1 × 10 １６ cm －３ The above 3 x 10 １８ cm －３ The following: The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing towards the interface to decreasing. The concentration of the P-type impurity at the inflection point is 3 × 10 １８ cm －３ The above describes a nitride semiconductor device in which the concentration value of the P-type impurity at the peak position is less than or equal to the above value.

2. A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10¹⁸ cm⁻³ or greater. The concentration of the P-type impurity at the interface in the impurity region is between 1 × 10¹⁶ cm⁻³ and 3 × 10¹⁸ cm⁻³. The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing toward the interface to decreasing toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10¹⁸ cm⁻³ or more, and less than or equal to the concentration value of the P-type impurity at the peak position. The inflection point is a local peak position where the concentration of the P-type impurity is locally maximum, in a nitride semiconductor device.

3. The nitride semiconductor device according to claim 1, wherein the P-type impurity comprises at least one of Mg and Be.

4. A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10¹⁸ cm⁻³ or greater. The concentration of the P-type impurity at the interface in the impurity region is between 1 × 10¹⁶ cm⁻³ and 3 × 10¹⁸ cm⁻³. The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing toward the interface to decreasing toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10¹⁸ cm⁻³ or more, and less than or equal to the concentration value of the P-type impurity at the peak position. The concentration of the P-type impurity at the peak position is 8×10 １８ cm －３ or more. A nitride semiconductor device.

5. The gate insulating film is SiO ２ A nitride semiconductor device according to claim 1, wherein the film is a film.

6. A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10¹⁸ cm⁻³ or greater. The concentration of the P-type impurity at the interface in the impurity region is between 1 × 10¹⁶ cm⁻³ and 3 × 10¹⁸ cm⁻³. The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing toward the interface to decreasing toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10¹⁸ cm⁻³ or more, and less than or equal to the concentration value of the P-type impurity at the peak position. The aforementioned impurity region is, The P+ type region is characterized by a high concentration of the aforementioned P-type impurities, A P-type region in which the concentration of the P-type impurity is lower than that of the P+-type region, A P-type region in which the concentration of the P-type impurity is lower than that of the P+-type region and higher than that of the P--type region, The region has a P-- type region in which the concentration of the P- type impurity is lower than that of the P- type region. The P+ type region includes the peak position, The P-type region includes the inflection point, A nitride semiconductor device in which the P-- type region, the P- type region, the P- type region, and the P+ type region are arranged in this order from the interface toward the peak position.

7. The gallium nitride layer further comprises an N-type source region, The nitride semiconductor device according to claim 6, wherein the source region is in contact with the P-- type region in a direction parallel to the interface.

8. The nitride semiconductor device according to claim 7, wherein the impurity region is interposed between the source region and the second main surface of the gallium nitride layer.

9. The nitride semiconductor device according to claim 1, wherein the interface is parallel to the first main surface of the gallium nitride layer.

10. The nitride semiconductor device according to claim 1, wherein the field-effect transistor is a planar gate type vertical MOSFET in which a gate electrode is arranged on the first main surface via the gate insulating film.

11. A gallium nitride layer having a first main surface and a second main surface located on the opposite side of the first main surface, The gallium nitride layer comprises a field-effect transistor, The aforementioned field-effect transistor is A gate insulating film provided on the first main surface side of the gallium nitride layer, The gallium nitride layer comprises a P-type impurity region provided in contact with the gate insulating film, The impurity region has a peak position where the concentration of P-type impurities is maximum, located away from the interface between the impurity region and the gate insulating film. In the perpendicular direction intersecting the interface, the distance from the interface to the peak position is 200 nm or more and 1500 nm or less. The concentration of the P-type impurity at the aforementioned peak position is 5 × 10¹⁸ cm⁻³ or greater. The concentration of the P-type impurity at the interface in the impurity region is between 1 × 10¹⁶ cm⁻³ and 3 × 10¹⁸ cm⁻³. The impurity region further has an inflection point between the interface and the peak position, at a position away from the interface and the peak position, where the concentration of the P-type impurity changes from increasing toward the interface to decreasing toward the interface, or the rate of decrease toward the interface increases. The concentration of the P-type impurity at the inflection point is 3 × 10¹⁸ cm⁻³ or more, and less than or equal to the concentration value of the P-type impurity at the peak position. The gallium nitride layer has trenches provided from the first main surface toward the second main surface, The field-effect transistor is a trench-gate type vertical MOSFET in which a gate electrode is arranged in the trench via the gate insulating film, wherein the nitride semiconductor device is a nitride semiconductor device.

12. A step of ion implanting P-type impurities into a predetermined region of the gallium nitride layer from the first main surface side of the gallium nitride layer, A step of ion implanting an inert element into the region from the first main surface side, A step of subjecting the gallium nitride layer, which has been ion-implanted with the P-type impurities and the inert element, to heat treatment to activate the P-type impurities and form a P-type impurity region in the gallium nitride layer, The process includes forming a gate insulating film on the first main surface side of the gallium nitride layer on which the impurity region is formed, In the process of ion implanting the aforementioned P-type impurity, In a vertical direction intersecting the interface between the impurity region and the gate insulating film, the peak position of the ion implantation amount of the P-type impurity is at a position between 200 nm and 1500 nm from the interface, and The concentration of the P-type impurity at the peak position of the ion implantation amount of the P-type impurity is 5 × 10 after the heat treatment. １８ cm －３ A method for manufacturing a nitride semiconductor device, wherein the P-type impurity is ion-implanted as described above.

13. In the process of ion implanting the aforementioned inert element, The method for manufacturing a nitride semiconductor device according to claim 12, wherein the inert element is ion-implanted such that the peak position of the ion implantation amount of the inert element in the vertical direction coincides with the peak position of the ion implantation amount of the P-type impurity.

14. In the process of ion implanting the aforementioned inert element, A method for manufacturing a nitride semiconductor device according to claim 12, wherein the inert element is ion-implanted such that the peak position of the ion implantation amount of the inert element in the vertical direction is between the interface and the peak position of the ion implantation amount of the P-type impurity.

15. The method for manufacturing a nitride semiconductor device according to claim 12, wherein the inert element includes at least one of N and Ar.

16. The method for manufacturing a nitride semiconductor device according to claim 12, wherein the maximum temperature of the heat treatment is 800°C or more and 2000°C or less.

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